80 lines
4.3 KiB
C
80 lines
4.3 KiB
C
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/****************************************************************************
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* arch/risc-v/src/rp23xx-rv/hardware/rp23xx_hstx_ctrl.h
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_HSTX_CTRL_H
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#define __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_HSTX_CTRL_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include "hardware/rp23xx_memorymap.h"
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Register offsets *********************************************************/
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#define RP23XX_HSTX_CTRL_CSR_OFFSET 0x00000000
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#define RP23XX_HSTX_CTRL_BIT_OFFSET(n) ((n) * 4 + 0x000004)
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#define RP23XX_HSTX_CTRL_EXPAND_SHIFT_OFFSET 0x00000024
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#define RP23XX_HSTX_CTRL_EXPAND_TMDS_OFFSET 0x00000028
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/* Register definitions *****************************************************/
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#define RP23XX_HSTX_CTRL_CSR (RP23XX_HSTX_CTRL_BASE + RP23XX_HSTX_CTRL_CSR_OFFSET)
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#define RP23XX_HSTX_CTRL_BIT(n) (RP23XX_HSTX_CTRL_BASE + RP23XX_HSTX_CTRL_BIT_OFFSET(n))
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#define RP23XX_HSTX_CTRL_EXPAND_SHIFT (RP23XX_HSTX_CTRL_BASE + RP23XX_HSTX_CTRL_EXPAND_SHIFT_OFFSET)
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#define RP23XX_HSTX_CTRL_EXPAND_TMDS (RP23XX_HSTX_CTRL_BASE + RP23XX_HSTX_CTRL_EXPAND_TMDS_OFFSET)
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/* Register bit definitions *************************************************/
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#define RP23XX_HSTX_CTRL_CSR_MASK (0xff1f1f73)
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#define RP23XX_HSTX_CTRL_CSR_CLKDIV_MASK (0xf0000000)
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#define RP23XX_HSTX_CTRL_CSR_CLKPHASE_MASK (0x0f000000)
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#define RP23XX_HSTX_CTRL_CSR_N_SHIFTS_MASK (0x001f0000)
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#define RP23XX_HSTX_CTRL_CSR_SHIFT_MASK (0x00001f00)
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#define RP23XX_HSTX_CTRL_CSR_COUPLED_SEL_MASK (0x00000060)
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#define RP23XX_HSTX_CTRL_CSR_COUPLED_MODE (1 << 4)
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#define RP23XX_HSTX_CTRL_CSR_EXPAND_EN (1 << 1)
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#define RP23XX_HSTX_CTRL_CSR_EN (1 << 0)
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#define RP23XX_HSTX_CTRL_BIT_MASK (0x00031f1f)
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#define RP23XX_HSTX_CTRL_BIT_CLK_MASK (1 << 25)
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#define RP23XX_HSTX_CTRL_BIT_INV_MASK (1 << 24)
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#define RP23XX_HSTX_CTRL_BIT_SEL_N_MASK (0x00001f00)
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#define RP23XX_HSTX_CTRL_BIT_SEL_P_MASK (0x0000001f)
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#define RP23XX_HSTX_CTRL_EXPAND_SHIFT_MASK (0x1f1f1f1f)
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#define RP23XX_HSTX_CTRL_EXPAND_SHIFT_ENC_N_SHIFTS_MASK (0x1f000000)
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#define RP23XX_HSTX_CTRL_EXPAND_SHIFT_ENC_SHIFT_MASK (0x001f0000)
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#define RP23XX_HSTX_CTRL_EXPAND_SHIFT_RAW_N_SHIFTS_MASK (0x00001f00)
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#define RP23XX_HSTX_CTRL_EXPAND_SHIFT_RAW_SHIFT_MASK (0x0000001f)
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#define RP23XX_HSTX_CTRL_EXPAND_TMDS_MASK (0x00ffffff)
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#define RP23XX_HSTX_CTRL_EXPAND_TMDS_L2_NBITS_MASK (0x00e00000)
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#define RP23XX_HSTX_CTRL_EXPAND_TMDS_L2_ROT_MASK (0x001f0000)
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#define RP23XX_HSTX_CTRL_EXPAND_TMDS_L1_NBITS_MASK (0x0000e000)
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#define RP23XX_HSTX_CTRL_EXPAND_TMDS_L1_ROT_MASK (0x00001f00)
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#define RP23XX_HSTX_CTRL_EXPAND_TMDS_L0_NBITS_MASK (0x000000e0)
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#define RP23XX_HSTX_CTRL_EXPAND_TMDS_L0_ROT_MASK (0x0000001f)
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#endif /* __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_HSTX_CTRL_H */
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