296 lines
9.1 KiB
C
296 lines
9.1 KiB
C
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/****************************************************************************
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* arch/arm/src/armv7/arm_addrenv.c
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*
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* Copyright (C) 2014 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <string.h>
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#include <errno.h>
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#include <debug.h>
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#include <nuttx/pgalloc.h>
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#include <arch/irq.h>
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#include "cache.h"
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#include "mmu.h"
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#include "pginline.h"
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#include "addrenv.h"
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#ifdef CONFIG_ARCH_ADDRENV
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/****************************************************************************
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* Private Data
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****************************************************************************/
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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/****************************************************************************
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* Name: set_l2_entry
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*
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* Description:
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* Set the L2 table entry as part of the initialization of the L2 Page
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* table.
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*
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****************************************************************************/
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void set_l2_entry(FAR uint32_t *l2table, uintptr_t paddr, uintptr_t vaddr,
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uint32_t mmuflags)
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{
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uint32_t index;
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/* The table divides a 1Mb address space up into 256 entries, each
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* corresponding to 4Kb of address space. The page table index is
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* related to the offset from the beginning of 1Mb region.
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*/
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index = (vaddr & 0x000ff000) >> 12;
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/* Save the table entry */
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l2table[index] = (paddr | mmuflags);
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}
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/****************************************************************************
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* Name: arm_addrenv_create_region
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*
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* Description:
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* Create one memory region.
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*
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* Returned Value:
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* On success, the number of pages allocated is returned. Otherwise, a
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* negated errno value is returned.
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*
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****************************************************************************/
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int arm_addrenv_create_region(FAR uintptr_t **list, unsigned int listlen,
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uintptr_t vaddr, size_t regionsize,
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uint32_t mmuflags)
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{
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irqstate_t flags;
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uintptr_t paddr;
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FAR uint32_t *l2table;
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#ifndef CONFIG_ARCH_PGPOOL_MAPPING
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uint32_t l1save;
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#endif
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size_t nmapped;
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unsigned int npages;
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unsigned int i;
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unsigned int j;
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bvdbg("listlen=%d vaddr=%08lx regionsize=%ld, mmuflags=%08x\n",
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listlen, (unsigned long)vaddr, (unsigned long)regionsize,
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(unsigned int)mmuflags);
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/* Verify that we are configured with enough virtual address space to
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* support this memory region.
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*
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* npages pages correspondes to (npages << MM_PGSHIFT) bytes
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* listlen sections corresponds to (listlen << 20) bytes
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*/
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npages = MM_NPAGES(regionsize);
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if (npages > (listlen << (20 - MM_PGSHIFT)))
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{
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bdbg("ERROR: npages=%u listlen=%u\n", npages, listlen);
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return -E2BIG;
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}
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/* Back the allocation up with physical pages and set up the level mapping
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* (which of course does nothing until the L2 page table is hooked into
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* the L1 page table).
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*/
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nmapped = 0;
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for (i = 0; i < npages; i += ENTRIES_PER_L2TABLE)
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{
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/* Allocate one physical page for the L2 page table */
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paddr = mm_pgalloc(1);
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if (!paddr)
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{
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return -ENOMEM;
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}
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DEBUGASSERT(MM_ISALIGNED(paddr));
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list[i] = (FAR uintptr_t *)paddr;
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flags = irqsave();
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#ifdef CONFIG_ARCH_PGPOOL_MAPPING
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/* Get the virtual address corresponding to the physical page address */
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l2table = (FAR uint32_t *)arm_pgvaddr(paddr);
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#else
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/* Temporarily map the page into the virtual address space */
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l1save = mmu_l1_getentry(ARCH_SCRATCH_VBASE);
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mmu_l1_setentry(paddr & ~SECTION_MASK, ARCH_SCRATCH_VBASE, MMU_MEMFLAGS);
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l2table = (FAR uint32_t *)(ARCH_SCRATCH_VBASE | (paddr & SECTION_MASK));
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#endif
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/* Initialize the page table */
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memset(l2table, 0, ENTRIES_PER_L2TABLE * sizeof(uint32_t));
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/* Back up L2 entries with physical memory */
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for (j = 0; j < ENTRIES_PER_L2TABLE && nmapped < regionsize; j++)
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{
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/* Allocate one physical page for region data */
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paddr = mm_pgalloc(1);
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if (!paddr)
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{
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#ifndef CONFIG_ARCH_PGPOOL_MAPPING
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mmu_l1_restore(ARCH_SCRATCH_VBASE, l1save);
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#endif
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irqrestore(flags);
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return -ENOMEM;
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}
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/* Map the .text region virtual address to this physical address */
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set_l2_entry(l2table, paddr, vaddr, mmuflags);
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nmapped += MM_PGSIZE;
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vaddr += MM_PGSIZE;
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}
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/* Make sure that the initialized L2 table is flushed to physical
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* memory.
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*/
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arch_flush_dcache((uintptr_t)l2table,
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(uintptr_t)l2table +
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ENTRIES_PER_L2TABLE * sizeof(uint32_t));
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#ifndef CONFIG_ARCH_PGPOOL_MAPPING
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/* Restore the scratch section L1 page table entry */
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mmu_l1_restore(ARCH_SCRATCH_VBASE, l1save);
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#endif
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irqrestore(flags);
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}
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return npages;
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}
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/****************************************************************************
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* Name: arm_addrenv_destroy_region
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*
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* Description:
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* Destroy one memory region.
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*
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****************************************************************************/
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void arm_addrenv_destroy_region(FAR uintptr_t **list, unsigned int listlen,
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uintptr_t vaddr)
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{
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irqstate_t flags;
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uintptr_t paddr;
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FAR uint32_t *l2table;
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#ifndef CONFIG_ARCH_PGPOOL_MAPPING
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uint32_t l1save;
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#endif
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int i;
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int j;
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bvdbg("listlen=%d vaddr=%08lx\n", listlen, (unsigned long)vaddr);
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for (i = 0; i < listlen; vaddr += SECTION_SIZE, list++, i++)
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{
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/* Unhook the L2 page table from the L1 page table */
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mmu_l1_clrentry(vaddr);
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/* Has this page table been allocated? */
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paddr = (uintptr_t)list[i];
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if (paddr != 0)
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{
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flags = irqsave();
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#ifdef CONFIG_ARCH_PGPOOL_MAPPING
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/* Get the virtual address corresponding to the physical page address */
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l2table = (FAR uint32_t *)arm_pgvaddr(paddr);
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#else
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/* Temporarily map the page into the virtual address space */
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l1save = mmu_l1_getentry(ARCH_SCRATCH_VBASE);
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mmu_l1_setentry(paddr & ~SECTION_MASK, ARCH_SCRATCH_VBASE, MMU_MEMFLAGS);
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l2table = (FAR uint32_t *)(ARCH_SCRATCH_VBASE | (paddr & SECTION_MASK));
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#endif
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/* Return the allocated pages to the page allocator */
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for (j = 0; j < ENTRIES_PER_L2TABLE; j++)
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{
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paddr = *l2table++;
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if (paddr != 0)
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{
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paddr &= PTE_SMALL_PADDR_MASK;
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mm_pgfree(paddr, 1);
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}
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}
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#ifndef CONFIG_ARCH_PGPOOL_MAPPING
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/* Restore the scratch section L1 page table entry */
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mmu_l1_restore(ARCH_SCRATCH_VBASE, l1save);
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#endif
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irqrestore(flags);
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/* And free the L2 page table itself */
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mm_pgfree((uintptr_t)list[i], 1);
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}
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}
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}
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#endif /* CONFIG_ARCH_ADDRENV */
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