arch/arm/src/armv7-m/arm_vectors.c : Add the address alignment.
Add the address alignment to keep the constraint of ARMv7-M architecture same as RAM vector. ARMv7-M architecture describes the vector table address alignment as following. The Vector table must be naturally aligned to a power of two whose alignment value is greater than or equal to (Number of Exceptions supported x 4), with a minimum alignment of 128 bytes. I wonder why the implementation of arm_vectors.c does not follow this constraint of address alignment about ARMv7-M architecture. Although RAM vector is taken care about it. I think, as the result it was done by linker script on each board. At our system, NuttX will be started by bootloader. To fix the address of entry point(__start) I set the address of entry point to beginning of binary, so the beginning of binary is not a vector table. At this case, keeping the address alignment constraint of arm_vectors.c is needed.
This commit is contained in:
Takuya Miyashita
Xiang Xiao
parent
4178f3ede4
commit
072890c1bf
3 changed files with 49 additions and 47 deletions
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@ -43,45 +43,6 @@
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* Pre-processor Definitions
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****************************************************************************/
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/* Vector Table Offset Register (VECTAB). This mask seems to vary among
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* ARMv7-M implementations. It may need to be redefined in some
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* architecture-specific header file. By default, the base address of the
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* new vector table must be aligned to the size of the vector table extended
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* to the next larger power of 2.
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*/
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#ifndef NVIC_VECTAB_TBLOFF_MASK
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# if ARMV7M_VECTAB_SIZE > 512
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# define NVIC_VECTAB_TBLOFF_MASK (0xfffff000)
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# elif ARMV7M_VECTAB_SIZE > 256
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# define NVIC_VECTAB_TBLOFF_MASK (0xfffff800)
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# elif ARMV7M_VECTAB_SIZE > 128
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# define NVIC_VECTAB_TBLOFF_MASK (0xfffffc00)
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# elif ARMV7M_VECTAB_SIZE > 64
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# define NVIC_VECTAB_TBLOFF_MASK (0xfffffe00)
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# elif ARMV7M_VECTAB_SIZE > 32
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# define NVIC_VECTAB_TBLOFF_MASK (0xffffff00)
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# else
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# define NVIC_VECTAB_TBLOFF_MASK (0xffffff80)
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# endif
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#endif
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/* Alignment ****************************************************************/
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/* Per the ARMv7M Architecture reference manual, the NVIC vector table
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* requires 7-bit address alignment (i.e, bits 0-6 of the address of the
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* vector table must be zero). In this case alignment to a 128 byte address
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* boundary is sufficient.
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*
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* Some parts, such as the LPC17xx/LPC40xx family, require alignment to a 256
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* byte address boundary. Any other unusual alignment requirements for the
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* vector can be specified for a given architecture be redefining
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* NVIC_VECTAB_TBLOFF_MASK in the chip-specific chip.h header file for the
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* appropriate mask.
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*/
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#define RAMVEC_ALIGN ((~NVIC_VECTAB_TBLOFF_MASK & 0xffff) + 1)
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/****************************************************************************
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* Public Data
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****************************************************************************/
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@ -99,7 +60,7 @@
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*/
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up_vector_t g_ram_vectors[ARMV7M_VECTAB_SIZE]
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locate_data(".ram_vectors") aligned_data(RAMVEC_ALIGN);
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locate_data(".ram_vectors") aligned_data(VECTOR_ALIGN);
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/****************************************************************************
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* Public Functions
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@ -40,6 +40,7 @@
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#include "chip.h"
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#include "arm_internal.h"
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#include "ram_vectors.h"
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/****************************************************************************
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* Pre-processor Definitions
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@ -47,10 +48,6 @@
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#define IDLE_STACK (_ebss + CONFIG_IDLETHREAD_STACKSIZE)
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#ifndef ARMV7M_PERIPHERAL_INTERRUPTS
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# error ARMV7M_PERIPHERAL_INTERRUPTS must be defined to the number of I/O interrupts to be supported
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#endif
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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@ -76,7 +73,8 @@ extern void exception_common(void);
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* Note that the [ ... ] designated initializer is a GCC extension.
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*/
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const void * const _vectors[] locate_data(".vectors") =
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const void * const _vectors[] locate_data(".vectors")
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aligned_data(VECTOR_ALIGN) =
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{
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/* Initial stack */
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@ -31,12 +31,14 @@
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#include "arm_internal.h"
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#include "chip.h"
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#ifdef CONFIG_ARCH_RAMVECTORS
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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#ifndef ARMV7M_PERIPHERAL_INTERRUPTS
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# error ARMV7M_PERIPHERAL_INTERRUPTS must be defined to the number of I/O interrupts to be supported
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#endif
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/* This is the size of the vector table (in 4-byte entries). This size
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* includes the (1) the peripheral interrupts, (2) space for 15 Cortex-M
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* exceptions, and (3) IDLE stack pointer which lies at the beginning of the
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@ -45,6 +47,47 @@
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#define ARMV7M_VECTAB_SIZE (ARMV7M_PERIPHERAL_INTERRUPTS + 16)
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/* Vector Table Offset Register (VECTAB). This mask seems to vary among
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* ARMv7-M implementations. It may need to be redefined in some
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* architecture-specific header file. By default, the base address of the
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* new vector table must be aligned to the size of the vector table extended
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* to the next larger power of 2.
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*/
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#ifndef NVIC_VECTAB_TBLOFF_MASK
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# if ARMV7M_VECTAB_SIZE > 512
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# define NVIC_VECTAB_TBLOFF_MASK (0xfffff000)
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# elif ARMV7M_VECTAB_SIZE > 256
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# define NVIC_VECTAB_TBLOFF_MASK (0xfffff800)
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# elif ARMV7M_VECTAB_SIZE > 128
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# define NVIC_VECTAB_TBLOFF_MASK (0xfffffc00)
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# elif ARMV7M_VECTAB_SIZE > 64
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# define NVIC_VECTAB_TBLOFF_MASK (0xfffffe00)
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# elif ARMV7M_VECTAB_SIZE > 32
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# define NVIC_VECTAB_TBLOFF_MASK (0xffffff00)
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# else
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# define NVIC_VECTAB_TBLOFF_MASK (0xffffff80)
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# endif
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#endif
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/* Alignment ****************************************************************/
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/* Per the ARMv7M Architecture reference manual, the NVIC vector table
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* requires 7-bit address alignment (i.e, bits 0-6 of the address of the
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* vector table must be zero). In this case alignment to a 128 byte address
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* boundary is sufficient.
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*
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* Some parts, such as the LPC17xx/LPC40xx family, require alignment to a 256
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* byte address boundary. Any other unusual alignment requirements for the
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* vector can be specified for a given architecture be redefining
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* NVIC_VECTAB_TBLOFF_MASK in the chip-specific chip.h header file for the
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* appropriate mask.
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*/
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#define VECTOR_ALIGN ((~NVIC_VECTAB_TBLOFF_MASK & 0xffff) + 1)
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#ifdef CONFIG_ARCH_RAMVECTORS
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/****************************************************************************
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* Public Data
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****************************************************************************/
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