From 080f9ede45d4b611b4516b03431fa91e0779a1a2 Mon Sep 17 00:00:00 2001 From: Ville Juven Date: Wed, 4 Sep 2024 12:25:47 +0300 Subject: [PATCH] arm64_mmu.c: Fix kernel L1 page table size The kernel L1 page table must be at least 1 page --- arch/arm64/src/common/arm64_mmu.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/arch/arm64/src/common/arm64_mmu.c b/arch/arm64/src/common/arm64_mmu.c index a2572850a1..bd1283a637 100644 --- a/arch/arm64/src/common/arm64_mmu.c +++ b/arch/arm64/src/common/arm64_mmu.c @@ -131,6 +131,14 @@ #define NUM_BASE_LEVEL_ENTRIES GET_NUM_BASE_LEVEL_ENTRIES( \ CONFIG_ARM64_VA_BITS) +#ifdef CONFIG_BUILD_KERNEL +#define BASE_XLAT_TABLE_SIZE XLAT_TABLE_ENTRIES +#define BASE_XLAT_TABLE_ALIGN PAGE_SIZE +#else +#define BASE_XLAT_TABLE_SIZE NUM_BASE_LEVEL_ENTRIES +#define BASE_XLAT_TABLE_ALIGN NUM_BASE_LEVEL_ENTRIES * sizeof(uint64_t) +#endif + #if (CONFIG_ARM64_PA_BITS == 48) #define TCR_PS_BITS TCR_PS_BITS_256TB #elif (CONFIG_ARM64_PA_BITS == 44) @@ -149,8 +157,8 @@ * Private Data ****************************************************************************/ -static uint64_t base_xlat_table[NUM_BASE_LEVEL_ENTRIES] aligned_data( - NUM_BASE_LEVEL_ENTRIES * sizeof(uint64_t)); +static uint64_t base_xlat_table[BASE_XLAT_TABLE_SIZE] +aligned_data(BASE_XLAT_TABLE_ALIGN); static uint64_t xlat_tables[CONFIG_MAX_XLAT_TABLES][XLAT_TABLE_ENTRIES] aligned_data(XLAT_TABLE_ENTRIES * sizeof(uint64_t));