From 0cb9ae021b190ba5a2bd73998230ec710b7c2b7c Mon Sep 17 00:00:00 2001 From: patacongo Date: Tue, 20 Dec 2011 21:16:39 +0000 Subject: [PATCH] Update M25P driver per feedback from Mohammed Elwakeel git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@4207 42af7a65-404d-4744-a932-0658087f49c3 --- ChangeLog | 3 ++ arch/arm/src/stm32/stm32_pwm.c | 2 +- configs/ea3131/pgnsh/defconfig | 5 ++ configs/stm3240g-eval/README.txt | 9 ++-- configs/stm3240g-eval/include/board.h | 7 +-- configs/stm3240g-eval/src/stm3240g-internal.h | 7 +-- drivers/mtd/m25px.c | 52 ++++++++++++++----- 7 files changed, 61 insertions(+), 24 deletions(-) diff --git a/ChangeLog b/ChangeLog index 69f6febf0d..061be118e3 100644 --- a/ChangeLog +++ b/ChangeLog @@ -2283,5 +2283,8 @@ by Laurent Latil. Theses changes also include support for the STM32F103VCT6. * arch/configs/stm3240g-eval/src/up_pwm.c: Add hooks needed to use the new apps/examples/pwm test of the STM32 PWM driver. + * drivers/mtd/mp25x.c: Add ability to use different SPI modes and different + manufacturers codes. Fix a error in the wait for not busy (submitted by + Mohammad Elwakeel. diff --git a/arch/arm/src/stm32/stm32_pwm.c b/arch/arm/src/stm32/stm32_pwm.c index 35524226c0..99d2e310ce 100644 --- a/arch/arm/src/stm32/stm32_pwm.c +++ b/arch/arm/src/stm32/stm32_pwm.c @@ -724,7 +724,7 @@ static int pwm_start(FAR struct pwm_lowerhalf_s *dev, FAR const struct pwm_info_ cr2 = pwm_getreg(priv, STM32_GTIM_CR2_OFFSET); ccmr1 = pwm_getreg(priv, STM32_GTIM_CCMR1_OFFSET); - ccmr2 = pwm_getreg(priv, STM32_GTIM_CCMR1_OFFSET); + ccmr2 = pwm_getreg(priv, STM32_GTIM_CCMR2_OFFSET); /* Reset the Output Compare Mode Bits and set the select output compare mode */ diff --git a/configs/ea3131/pgnsh/defconfig b/configs/ea3131/pgnsh/defconfig index 252a64c092..d6643a3f3c 100644 --- a/configs/ea3131/pgnsh/defconfig +++ b/configs/ea3131/pgnsh/defconfig @@ -176,6 +176,11 @@ CONFIG_UART_BITS=8 CONFIG_UART_PARITY=0 CONFIG_UART_2STOP=0 +# +# MP25x Configuration +# +CONFIG_MP25P_SPIMODE=3 + # # General build options # diff --git a/configs/stm3240g-eval/README.txt b/configs/stm3240g-eval/README.txt index 746d0e5eca..a7e49a73a3 100755 --- a/configs/stm3240g-eval/README.txt +++ b/configs/stm3240g-eval/README.txt @@ -207,9 +207,10 @@ events as follows: PWM === -The STM3240G-Eval has no real on-board PWM devices, but the board can be configured to output -a pulse train using TIM4 CH2. This pin is used by FSMC is connect to CN5 just for this -purpose: +The STM3240G-Eval has no real on-board PWM devices, but the board can be +configured to output a pulse train using TIM4 CH2. This pin is used by +FSMC is but is also connected to the Motor Control Connector (CN5) just +for this purpose: PD13 FSMC_A18 / MC_TIM4_CH2 pin 33 (EnB) @@ -217,7 +218,7 @@ FSMC must be disabled in this case! PD13 is available at: Daughterboard Extension Connector, CN3, pin 32 - available TFT LCD Connector, CN19, pin 17 -- not available without removing the LCD. - Motor Control Connector CN15, pin 33 -- no available unless to connect SB14. + Motor Control Connector CN15, pin 33 -- not available unless you bridge SB14. STM3240G-EVAL-specific Configuration Options ============================================ diff --git a/configs/stm3240g-eval/include/board.h b/configs/stm3240g-eval/include/board.h index 046691dd9f..0f6f2fca10 100755 --- a/configs/stm3240g-eval/include/board.h +++ b/configs/stm3240g-eval/include/board.h @@ -285,8 +285,9 @@ /* PWM * - * The STM3240G-Eval has no real on-board PWM devices, but the board can be configured to output - * a pulse train using TIM4 CH2. This pin is used by FSMC is connect to CN5 just for this + * The STM3240G-Eval has no real on-board PWM devices, but the board can be + * configured to output a pulse train using TIM4 CH2. This pin is used by FSMC is + * but is also connected to the Motor Control Connector (CN5) just for this * purpose: * * PD13 FSMC_A18 / MC_TIM4_CH2 pin 33 (EnB) @@ -295,7 +296,7 @@ * * Daughterboard Extension Connector, CN3, pin 32 - available * TFT LCD Connector, CN19, pin 17 -- not available without removing the LCD. - * Motor Control Connector CN15, pin 33 -- no available unless to connect SB14. + * Motor Control Connector CN15, pin 33 -- not available unless you bridge SB14. */ #define GPIO_TIM4_CH2 GPIO_TIM4_CH2_2 diff --git a/configs/stm3240g-eval/src/stm3240g-internal.h b/configs/stm3240g-eval/src/stm3240g-internal.h index 0ccdaf40a3..fb4ce466b8 100644 --- a/configs/stm3240g-eval/src/stm3240g-internal.h +++ b/configs/stm3240g-eval/src/stm3240g-internal.h @@ -86,8 +86,9 @@ /* PWM * - * The STM3240G-Eval has no real on-board PWM devices, but the board can be configured to output - * a pulse train using TIM4 CH2. This pin is used by FSMC is connect to CN5 just for this + * The STM3240G-Eval has no real on-board PWM devices, but the board can be + * configured to output a pulse train using TIM4 CH2. This pin is used by FSMC is + * but is also connected to the Motor Control Connector (CN5) just for this * purpose: * * PD13 FSMC_A18 / MC_TIM4_CH2 pin 33 (EnB) @@ -96,7 +97,7 @@ * * Daughterboard Extension Connector, CN3, pin 32 - available * TFT LCD Connector, CN19, pin 17 -- not available without removing the LCD. - * Motor Control Connector CN15, pin 33 -- no available unless to connect SB14. + * Motor Control Connector CN15, pin 33 -- not available unless you bridge SB14. */ #define STM3240G_EVAL_PWMTIMER 4 diff --git a/drivers/mtd/m25px.c b/drivers/mtd/m25px.c index 69962a7b62..cfdb1ea971 100644 --- a/drivers/mtd/m25px.c +++ b/drivers/mtd/m25px.c @@ -55,10 +55,28 @@ /************************************************************************************ * Pre-processor Definitions ************************************************************************************/ +/* Configuration ********************************************************************/ +/* Per the data sheet, MP25P10 parts can be driven with either SPI mode 0 (CPOL=0 and + * CPHA=0) or mode 3 (CPOL=1 and CPHA=1). But I have heard that other devices can + * operated in mode 0 or 1. So you may need to specify CONFIG_MP25P_SPIMODE to + * select the best mode for your device. If CONFIG_MP25P_SPIMODE is not defined, + * mode 0 will be used. + */ +#ifndef CONFIG_MP25P_SPIMODE +# define CONFIG_MP25P_SPIMODE SPIDEV_MODE0 +#endif + +/* Various manufacturers may have produced the parts */ + +#ifndef CONFIG_MP25P_MANUFACTURER +# define CONFIG_MP25P_MANUFACTURER 0x20 +#endif + +/* M25P Registers *******************************************************************/ /* Indentification register values */ -#define M25P_MANUFACTURER 0x20 +#define M25P_MANUFACTURER CONFIG_MP25P_MANUFACTURER #define M25P_MEMORY_TYPE 0x20 #define M25P_M25P1_CAPACITY 0x11 /* 1 M-bit */ #define M25P_M25P64_CAPACITY 0x17 /* 64 M-bit */ @@ -204,7 +222,7 @@ static void m25p_lock(FAR struct spi_dev_s *dev) * state. */ - SPI_SETMODE(dev, SPIDEV_MODE3); + SPI_SETMODE(dev, CONFIG_MP25P_SPIMODE); SPI_SETBITS(dev, 8); (void)SPI_SETFREQUENCY(dev, 20000000); } @@ -299,27 +317,35 @@ static void m25p_waitwritecomplete(struct m25p_dev_s *priv) { uint8_t status; - /* Select this FLASH part */ - - SPI_SELECT(priv->dev, SPIDEV_FLASH, true); - - /* Send "Read Status Register (RDSR)" command */ - - (void)SPI_SEND(priv->dev, M25P_RDSR); - /* Loop as long as the memory is busy with a write cycle */ do { + /* Select this FLASH part */ + + SPI_SELECT(priv->dev, SPIDEV_FLASH, true); + + /* Send "Read Status Register (RDSR)" command */ + + (void)SPI_SEND(priv->dev, M25P_RDSR); + /* Send a dummy byte to generate the clock needed to shift out the status */ status = SPI_SEND(priv->dev, M25P_DUMMY); + + /* Deselect the FLASH */ + + SPI_SELECT(priv->dev, SPIDEV_FLASH, false); + + if ((status & M25P_SR_WIP) != 0) + { + m25p_unlock(priv->dev); + usleep(1000); + m25p_lock(priv->dev); + } } while ((status & M25P_SR_WIP) != 0); - /* Deselect the FLASH */ - - SPI_SELECT(priv->dev, SPIDEV_FLASH, false); fvdbg("Complete\n"); }