arch/arm/src/stm32f7/stm32_serial.c: This adds the ability to invert and swap RX/TX on STM32F7 UARTs. I added the TIOCGINVERT as well to reserve the IOCTL number, but did not implement it. This is the same as for TIOCGSINGLEWIRE.
This commit is contained in:
Beat Küng
Gregory Nutt
parent
118d0f8f1f
commit
1395938260
3 changed files with 138 additions and 6 deletions
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@ -1977,6 +1977,22 @@ config STM32F7_USART_SINGLEWIRE
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Enable single wire UART support. The option enables support for the
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TIOCSSINGLEWIRE ioctl in the STM32F7 serial driver.
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config STM32F7_USART_INVERT
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bool "Signal Invert Support"
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default n
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depends on STM32F7_USART
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---help---
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Enable signal inversion UART support. The option enables support for the
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TIOCSINVERT ioctl in the STM32F7 serial driver.
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config STM32F7_USART_SWAP
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bool "Swap RX/TX pins support"
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default n
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depends on STM32F7_USART
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---help---
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Enable RX/TX pin swapping support. The option enables support for the
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TIOCSSWAP ioctl in the STM32F7 serial driver.
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if PM
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config STM32F7_PM_SERIAL_ACTIVITY
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@ -74,7 +74,9 @@
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Some sanity checks *******************************************************/
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/* Total number of possible serial devices */
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#define STM32_NSERIAL (STM32F7_NUSART + STM32F7_NUART)
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@ -1258,12 +1260,13 @@ static void up_set_format(struct uart_dev_s *dev)
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/* Get the original state of UE */
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cr1 = up_serialin(priv, STM32_USART_CR1_OFFSET);
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cr1 = up_serialin(priv, STM32_USART_CR1_OFFSET);
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cr1_ue = cr1 & USART_CR1_UE;
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cr1 &= ~USART_CR1_UE;
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cr1 &= ~USART_CR1_UE;
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/* Disable UE as the format bits and baud rate registers can not be
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* updated while UE = 1 */
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* updated while UE = 1
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*/
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up_serialout(priv, STM32_USART_CR1_OFFSET, cr1);
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@ -1354,7 +1357,7 @@ static void up_set_format(struct uart_dev_s *dev)
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/* Configure STOP bits */
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regval = up_serialin(priv, STM32_USART_CR2_OFFSET);
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regval = up_serialin(priv, STM32_USART_CR2_OFFSET);
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regval &= ~(USART_CR2_STOP_MASK);
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if (priv->stopbits2)
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@ -1683,6 +1686,7 @@ static int up_setup(struct uart_dev_s *dev)
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#endif
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/* Configure CR2 */
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/* Clear STOP, CLKEN, CPOL, CPHA, LBCL, and interrupt enable bits */
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regval = up_serialin(priv, STM32_USART_CR2_OFFSET);
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@ -1699,6 +1703,7 @@ static int up_setup(struct uart_dev_s *dev)
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up_serialout(priv, STM32_USART_CR2_OFFSET, regval);
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/* Configure CR1 */
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/* Clear TE, REm and all interrupt enable bits */
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regval = up_serialin(priv, STM32_USART_CR1_OFFSET);
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@ -1707,6 +1712,7 @@ static int up_setup(struct uart_dev_s *dev)
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up_serialout(priv, STM32_USART_CR1_OFFSET, regval);
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/* Configure CR3 */
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/* Clear CTSE, RTSE, and all interrupt enable bits */
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regval = up_serialin(priv, STM32_USART_CR3_OFFSET);
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@ -2148,6 +2154,99 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg)
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break;
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#endif
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#ifdef CONFIG_STM32F7_USART_INVERT
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case TIOCSINVERT:
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{
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uint32_t cr1;
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uint32_t cr1_ue;
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irqstate_t flags;
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flags = enter_critical_section();
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/* Get the original state of UE */
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cr1 = up_serialin(priv, STM32_USART_CR1_OFFSET);
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cr1_ue = cr1 & USART_CR1_UE;
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cr1 &= ~USART_CR1_UE;
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/* Disable UE, {R,T}XINV can only be written when UE=0 */
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up_serialout(priv, STM32_USART_CR1_OFFSET, cr1);
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/* Enable/disable signal inversion. */
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uint32_t cr = up_serialin(priv, STM32_USART_CR2_OFFSET);
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if (arg & SER_INVERT_ENABLED_RX)
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{
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cr |= USART_CR2_RXINV;
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}
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else
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{
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cr &= ~USART_CR2_RXINV;
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}
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if (arg & SER_INVERT_ENABLED_TX)
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{
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cr |= USART_CR2_TXINV;
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}
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else
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{
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cr &= ~USART_CR2_TXINV;
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}
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up_serialout(priv, STM32_USART_CR2_OFFSET, cr);
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/* Re-enable UE if appropriate */
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up_serialout(priv, STM32_USART_CR1_OFFSET, cr1 | cr1_ue);
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leave_critical_section(flags);
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}
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break;
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#endif
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#ifdef CONFIG_STM32F7_USART_SWAP
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case TIOCSSWAP:
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{
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uint32_t cr1;
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uint32_t cr1_ue;
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irqstate_t flags;
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flags = enter_critical_section();
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/* Get the original state of UE */
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cr1 = up_serialin(priv, STM32_USART_CR1_OFFSET);
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cr1_ue = cr1 & USART_CR1_UE;
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cr1 &= ~USART_CR1_UE;
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/* Disable UE, SWAP can only be written when UE=0 */
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up_serialout(priv, STM32_USART_CR1_OFFSET, cr1);
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/* Enable/disable Swap mode. */
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uint32_t cr = up_serialin(priv, STM32_USART_CR2_OFFSET);
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if (arg == SER_SWAP_ENABLED)
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{
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cr |= USART_CR2_SWAP;
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}
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else
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{
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cr &= ~USART_CR2_SWAP;
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}
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up_serialout(priv, STM32_USART_CR2_OFFSET, cr);
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/* Re-enable UE if appropriate */
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up_serialout(priv, STM32_USART_CR1_OFFSET, cr1 | cr1_ue);
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leave_critical_section(flags);
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}
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break;
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#endif
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#ifdef CONFIG_SERIAL_TERMIOS
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case TCGETS:
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{
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@ -2258,9 +2357,10 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg)
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up_txint(dev, false);
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/* Configure TX as a GPIO output pin and Send a break signal*/
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/* Configure TX as a GPIO output pin and Send a break signal */
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tx_break = GPIO_OUTPUT | (~(GPIO_MODE_MASK|GPIO_OUTPUT_SET) & priv->tx_gpio);
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tx_break = GPIO_OUTPUT |
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(~(GPIO_MODE_MASK | GPIO_OUTPUT_SET) & priv->tx_gpio);
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stm32_configgpio(tx_break);
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leave_critical_section(flags);
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@ -2998,6 +3098,7 @@ static int up_pm_prepare(struct pm_callback_s *cb, int domain,
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default:
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/* Should not get here */
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break;
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}
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@ -190,6 +190,21 @@
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#define TIOCSERGSTRUCT _TIOC(0x0032) /* Get device TTY structure */
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/* Inversion Support */
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#define TIOCSINVERT _TIOC(0x0033) /* Set Singal Inversion */
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#define TIOCGINVERT _TIOC(0x0034) /* Get Singal Inversion */
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#define SER_INVERT_ENABLED_RX (1 << 0) /* Enable/disable signal inversion for RX */
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#define SER_INVERT_ENABLED_TX (1 << 1) /* Enable/disable signal inversion for TX */
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/* RX/TX Swap Support */
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#define TIOCSSWAP _TIOC(0x0035) /* Set RX/TX Swap */
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#define TIOCGSWAP _TIOC(0x0036) /* Get RX/TX Swap */
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#define SER_SWAP_ENABLED (1 << 0) /* Enable/disable RX/TX swap */
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/********************************************************************************************
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* Public Type Definitions
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********************************************************************************************/
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