arch/arm/src/max326xx/chip: Add SPI register definition header file.
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Gregory Nutt
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arch/arm/src/max326xx/chip/max32660_spi.h
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arch/arm/src/max326xx/chip/max32660_spi.h
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/************************************************************************************
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* arch/arm/src/max326xx/chip/max326_spi.h
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*
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* Copyright (C) 2018 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __ARCH_ARM_SRC_MAX326XX_CHIP_MAX326_SPI_H
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#define __ARCH_ARM_SRC_MAX326XX_CHIP_MAX326_SPI_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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#include "chip/max326_memorymap.h"
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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/* Register Offsets *****************************************************************/
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#define MAX326_SPI_DATA_OFFSET 0x0000 /* SPI FIFO Data Register */
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#define MAX326_SPI_CTRL0_OFFSET 0x0004 /* SPI Master Signals Control Register */
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#define MAX326_SPI_CTRL1_OFFSET 0x0008 /* SPI Transmit Packet Size Register */
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#define MAX326_SPI_CTRL2_OFFSET 0x000c /* SPI Static Configuration Register */
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#define MAX326_SPI_SSTIME_OFFSET 0x0010 /* SPI Slave Select Timing Register */
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#define MAX326_SPI_CLKCFG_OFFSET 0x0014 /* SPI Master Clock Configuration Register */
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#define MAX326_SPI_DMA_OFFSET 0x001c /* SPI DMA Control Register */
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#define MAX326_SPI_INTFL_OFFSET 0x0020 /* SPI Interrupt Status Flags Register */
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#define MAX326_SPI_INTEN_OFFSET 0x0024 /* SPI Interrupt Enable Register */
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#define MAX326_SPI_WAKEFL_OFFSET 0x0028 /* SPI Wakeup Status Flags Register */
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#define MAX326_SPI_WAKEEN_OFFSET 0x002c /* SPI Wakeup Enable Register */
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#define MAX326_SPI_STAT_OFFSET 0x0030 /* SPI Active Status Register */
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/* Register Addresses ***************************************************************/
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#define MAX326_SPI0_DATA (MAX326_SPI0_BASE + MAX326_SPI_DATA_OFFSET)
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#define MAX326_SPI0_CTRL0 (MAX326_SPI0_BASE + MAX326_SPI_CTRL0_OFFSET)
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#define MAX326_SPI0_CTRL1 (MAX326_SPI0_BASE + MAX326_SPI_CTRL1_OFFSET)
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#define MAX326_SPI0_CTRL2 (MAX326_SPI0_BASE + MAX326_SPI_CTRL2_OFFSET)
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#define MAX326_SPI0_SSTIME (MAX326_SPI0_BASE + MAX326_SPI_SSTIME_OFFSET)
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#define MAX326_SPI0_CLKCFG (MAX326_SPI0_BASE + MAX326_SPI_CLKCFG_OFFSET)
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#define MAX326_SPI0_DMA (MAX326_SPI0_BASE + MAX326_SPI_DMA_OFFSET)
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#define MAX326_SPI0_INTFL (MAX326_SPI0_BASE + MAX326_SPI_INTFL_OFFSET)
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#define MAX326_SPI0_INTEN (MAX326_SPI0_BASE + MAX326_SPI_INTEN_OFFSET)
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#define MAX326_SPI0_WAKEFL (MAX326_SPI0_BASE + MAX326_SPI_WAKEFL_OFFSET)
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#define MAX326_SPI0_WAKEEN (MAX326_SPI0_BASE + MAX326_SPI_WAKEEN_OFFSET)
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#define MAX326_SPI0_STAT (MAX326_SPI0_BASE + MAX326_SPI_STAT_OFFSET)
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/* Register Bit-field Definitions ***************************************************/
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/* SPI FIFO Data Register (SPI data up to 32-bits wide) */
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/* SPI Master Signals Control Register */
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#define SPI_CTRL0_SPIEN (1 << 0 ) /* Bit 0: SPI Enable/Disable */
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#define SPI_CTRL0_MMEN (1 << 1) /* Bit 1: SPI Master Mode Enable */
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#define SPI_CTRL0_SSIO (1 << 4) /* Bit 4: Slave Select Output (master) */
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#define SPI_CTRL0_START (1 << 5) /* Bit 5: Start Data Transmission (master) */
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#define SPI_CTRL0_SSCTRL (1 << 8) /* Bit 8: Slave Select Control (master) */
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#define SPI_CTRL0_SSSEL(n) (1 << ((n) + 16)) /* Bits 16-19: Slave Select n
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* Enable, n=0 */
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/* SPI Transmit Packet Size Register */
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#define SPI_CTRL1_TXNUMCH_SHIFT (0) /* Bits 0-15: Number of Transmit Characters */
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#define SPI_CTRL1_TXNUMCH_MASK (0xffff << SPI_CTRL1_TXNUMCH_SHIFT)
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# define SPI_CTRL1_TXNUMCH(n) ((uint32_t)(n) << SPI_CTRL1_TXNUMCH_SHIFT)
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#define SPI_CTRL1_RXNUMCH_SHIFT (16) /* Bits 16-31: Number of Receive Characters */
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#define SPI_CTRL1_RXNUMCH_MASK (0xffff << SPI_CTRL1_RXNUMCH_SHIFT)
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# define SPI_CTRL1_RXNUMCH(n) ((uint32_t)(n) << SPI_CTRL1_RXNUMCH_SHIFT)
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/* SPI Static Configuration Register */
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#define SPI_CTRL2_CLKPHA (1 << 0) /* Bit 0: Clock Phase */
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#define SPI_CTRL2_CLKPOL (1 << 1) /* Bit 1: Clock Polarity */
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#define SPI_CTRL2_NUMBITS_SHIFT (8) /* Bits 8-11: Number of Bits per Character */
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#define SPI_CTRL2_NUMBITS_MASK (15 << SPI_CTRL2_NUMBITS_SHIFT)
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# define SPI_CTRL2_NUMBITS_(n) ((uint32_t)(n) << SPI_CTRL2_NUMBITS_SHIFT)
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#define SPI_CTRL2_DATWIDTH_SHIFT (12) /* Bits 12-13: SPI Data Width */
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#define SPI_CTRL2_DATWIDTH_MASK (3 << SPI_CTRL2_DATWIDTH_SHIFT)
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# define SPI_CTRL2_DATWIDTH_SINGLE (0 << SPI_CTRL2_DATWIDTH_SHIFT) /* MOSI */
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# define SPI_CTRL2_DATWIDTH_DUAL (1 << SPI_CTRL2_DATWIDTH_SHIFT) /* MOSI/MISO */
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#define SPI_CTRL2_3WIRE (1 << 15) /* Bit 15: Three-Wire Mode Enable */
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#define SPI_CTRL2_SSPOL (1 << 16) /* Bit 16: Slave Select Polarity */
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/* SPI Slave Select Timing Register */
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#define SPI_SSTIME_SSACT1_SHIFT (0) /* Bits 0-7: Slave Select Active to First
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* SCLK */
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#define SPI_SSTIME_SSACT1_MASK (0xff << SPI_SSTIME_SSACT1_SHIFT)
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# define SPI_SSTIME_SSACT1(n) ((uint32_t)((n) & 0xff) << SPI_SSTIME_SSACT1_SHIFT)
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#define SPI_SSTIME_SSACT2_SHIFT (8) /* Bits 8-15: Slave Select Active After Last
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* SCLK */
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#define SPI_SSTIME_SSACT2_MASK (0xff << SPI_SSTIME_SSACT2_SHIFT)
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# define SPI_SSTIME_SSACT2(n) ((uint32_t)((n) & 0xff) << SPI_SSTIME_SSACT2_SHIFT)
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#define SPI_SSTIME_SSINACT_SHIFT (16) /* Bits 16-23: SS Inactive Clock Delay */
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#define SPI_SSTIME_SSINACT_MASK (0xff << SPI_SSTIME_SSINACT_SHIFT)
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# define SPI_SSTIME_SSINACT(n) ((uint32_t)((n) & 0xff) << SPI_SSTIME_SSINACT_SHIFT)
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/* SPI Master Clock Configuration Register */
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#define SPI_CLKCFG_LO_SHIFT (0) /* Bits 0-7: SCLK Low Clock Cycles Control */
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#define SPI_CLKCFG_LO_MASK (0xff << SPI_CLKCFG_LO_SHIFT)
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# define SPI_CLKCFG_LO(n) ((uint32_t)(n) << SPI_CLKCFG_LO_SHIFT)
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#define SPI_CLKCFG_HI_SHIFT (8) /* Bits 8-15: SCLK Hi Clock Cycles Control */
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#define SPI_CLKCFG_HI_MASK (0xff << SPI_CLKCFG_HI_SHIFT)
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# define SPI_CLKCFG_HI_DISABLE (0 << SPI_CLKCFG_HI_SHIFT)
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# define SPI_CLKCFG_HI(n) ((uint32_t)(n) << SPI_CLKCFG_HI_SHIFT)
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#define SPI_CLKCFG_SCALE_SHIFT (16) /* Bits 16-19: System Clock to SPI Clock
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* Scale Factor */
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#define SPI_CLKCFG_SCALE_MASK (0xff << SPI_CLKCFG_SCALE_SHIFT)
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# define SPI_CLKCFG_SCALE_DISABLE (0 << SPI_CLKCFG_SCALE_SHIFT)
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# define SPI_CLKCFG_SCALE(n) ((uint32_t)(n) << SPI_CLKCFG_SCALE_SHIFT)
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/* SPI DMA Control Register */
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#define SPI_DMA_TXFIFOLVL_SHIFT (0) /* Bits 0-4: TX FIFO Threshold Level */
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#define SPI_DMA_TXFIFOLVL_MASK (0x1f << SPI_DMA_TXFIFOLVL_SHIFT)
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# define SPI_DMA_TXFIFOLVL(n) ((uint32_t)(n) << SPI_DMA_TXFIFOLVL_SHIFT)
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#define SPI_DMA_TXFIFOEN (1 << 6) /* Bit 6: TX FIFO Enabled */
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#define SPI_DMA_TXFIFOCLR (1 << 7) /* Bit 7: Clear the TX FIFO */
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#define SPI_DMA_TXFIFOCNT_SHIFT (8) /* Bits 8-13: Number of Bytes in the TX
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* FIFO */
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#define SPI_DMA_TXFIFOCNT_MASK (0x3f << SPI_DMA_TXFIFOCNT_SHIFT)
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#define SPI_DMA_TXDMAEN (1 << 15) /* Bit 15: TX DMA Enable */
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#define SPI_DMA_RXFIFOLVL_SHIFT (16) /* Bits 16-20: RX FIFO Threshold Level */
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#define SPI_DMA_RXFIFOLVL_MASK (0x1f << SPI_DMA_RXFIFOLVL_SHIFT)
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# define SPI_DMA_RXFIFOLVL(n) ((uint32_t)(n) << SPI_DMA_RXFIFOLVL_SHIFT)
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#define SPI_DMA_RXFIFOEN (1 << 22) /* Bit 22: RX FIFO Enabled */
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#define SPI_DMA_RXFIFOCLR (1 << 23) /* Bit 23: Clear the RX FIFO */
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#define SPI_DMA_RXFIFOCNT_SHIFT (24) /* Bits 24-29: Number of Bytes in the RX
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* FIFO */
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#define SPI_DMA_RXFIFOCNT_MASK (0x3f << SPI_DMA_RXFIFOCNT_SHIFT)
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#define SPI_DMA_RXDMAEN (1 << 31) /* Bit 31: RX DMA Enable */
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/* SPI Interrupt Status Flags Register and SPI Interrupt Enable Register */
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#define SPI_INT_TXLEVEL (1 << 0) /* Bit 0: TX FIFO Threshold Level Crossed */
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#define SPI_INT_TXEMPTY (1 << 1) /* Bit 1: TX FIFO Empty */
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#define SPI_INT_RXLEVEL (1 << 2) /* Bit 2: RX FIFO Threshold Level Crossed */
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#define SPI_INT_RXFULL (1 << 3) /* Bit 3: RX FIFO Full */
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#define SPI_INT_SSA (1 << 4) /* Bit 4: Slave Select Asserted */
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#define SPI_INT_SSD (1 << 5) /* Bit 5: Slave Select Deasserted */
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#define SPI_INT_FAULT (1 << 8) /* Bit 8: Multi-Master Fault Interrupt */
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#define SPI_INT_ABORT (1 << 9) /* Bit 9: Slave Mode Transaction Abort
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* Detected */
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#define SPI_INT_MDONE (1 << 11) /* Bit 11: Master Data Transmission
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* Complete */
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#define SPI_INT_TXOVR (1 << 12) /* Bit 12: TX FIFO Overrun */
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#define SPI_INT_TXUND (1 << 13) /* Bit 13: TX FIFO Underrun */
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#define SPI_INT_RXOVR (1 << 14) /* Bit 14: RX FIFO Overrun */
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#define SPI_INT_RXUND (1 << 15) /* Bit 15: RX FIFO Underrun */
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/* SPI Wakeup Status Flags Register and SPI Wakeup Enable Register */
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#define SPI_WAKE_TXLEVEL (1 << 0) /* Bit 0: Wake on TX FIFO Threshold Level
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* Crossed */
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#define SPI_WAKE_TXEMPTY (1 << 1) /* Bit 1: Wake on TX FIFO Empty */
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#define SPI_WAKE_RXLEVEL (1 << 2) /* Bit 2: Wake on RX FIFO Threshold Level
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* Crossed */
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#define SPI_WAKE_RXFULL (1 << 3) /* Bit 3: Wake on RX FIFO Full */
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/* SPI Active Status Register */
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#define SPI_STAT_BUSY (1 << 0) /* Bit 0: SPI Active Status */
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#endif /* __ARCH_ARM_SRC_MAX326XX_CHIP_MAX326_SPI_H */
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