boards/xtensa/esp32s3: Move some .bss sections to the external RAM

This commit moves some internal libraries' .bss sections to the
external PSRAM chip, freeing internal memory for other usages. Note
that it is necessary to update `esp32s3-devkit:python` defconfig
otherwise it would fail to build.

Signed-off-by: Tiago Medicci Serrano <tiago.medicci@espressif.com>

arch/xtensa/src/esp32s3/esp32s3_spiram.c

@@ -123,8 +123,10 @@ static struct smp_call_data_s g_call_data =
 SMP_CALL_INITIALIZER(pause_cpu_handler, NULL);
 #endif
 
+#ifdef CONFIG_XTENSA_EXTMEM_BSS
 extern uint8_t _ext_ram_bss_start;
 extern uint8_t _ext_ram_bss_end;
+#endif
 
 /****************************************************************************
  * ROM Function Prototypes
@@ -397,7 +399,7 @@ int IRAM_ATTR esp_spiram_init_cache(void)
   uint32_t mapped_vaddr_size;
   uint32_t target_mapped_vaddr_start;
   uint32_t target_mapped_vaddr_end;
-  uint32_t ext_bss_size;
+  uint32_t ext_bss_size = 0;
 
   int ret = psram_get_available_size(&psram_size);
   if (ret != OK)
@@ -478,8 +480,10 @@ int IRAM_ATTR esp_spiram_init_cache(void)
 
   cache_resume_dcache(0);
 
+#ifdef CONFIG_XTENSA_EXTMEM_BSS
   ext_bss_size = ((intptr_t)&_ext_ram_bss_end -
                   (intptr_t)&_ext_ram_bss_start);
+#endif
 
   g_allocable_vaddr_start = g_mapped_vaddr_start + ext_bss_size;
   g_allocable_vaddr_end = g_mapped_vaddr_start + g_mapped_size -

arch/xtensa/src/esp32s3/esp32s3_start.c

@@ -163,6 +163,11 @@ extern uint8_t _instruction_reserved_end[];
 extern uint8_t _rodata_reserved_start[];
 extern uint8_t _rodata_reserved_end[];
 
+#ifdef CONFIG_XTENSA_EXTMEM_BSS
+extern uintptr_t _ext_ram_bss_start;
+extern uintptr_t _ext_ram_bss_end;
+#endif
+
 /* Address of the CPU0 IDLE thread */
 
 uint32_t g_idlestack[IDLETHREAD_STACKWORDS]
@@ -417,6 +422,11 @@ noinstrument_function void noreturn_function IRAM_ATTR __esp32s3_start(void)
     }
 #endif
 
+#ifdef CONFIG_XTENSA_EXTMEM_BSS
+  memset(&_ext_ram_bss_start, 0,
+         (&_ext_ram_bss_end - &_ext_ram_bss_start) * sizeof(uintptr_t));
+#endif
+
   /* Setup the syscall table needed by the ROM code */
 
   esp_setup_syscall_table();

boards/xtensa/esp32s3/common/scripts/esp32s3_sections.ld

@@ -303,8 +303,12 @@ SECTIONS
     . = ALIGN(8);
     _bss_start = ABSOLUTE(.);
     _sbss = ABSOLUTE(.);
-
+#ifdef CONFIG_XTENSA_EXTMEM_BSS
+    *(EXCLUDE_FILE(*libnet80211.a *libpp.a *libpython3.13.a) .bss EXCLUDE_FILE(*libnet80211.a *libpp.a *libpython3.13.a) .bss.*)
+    *(EXCLUDE_FILE(*libnet80211.a *libpp.a *libpython3.13.a) .bss EXCLUDE_FILE(*libnet80211.a *libpp.a *libpython3.13.a) COMMON)
+#else
     *(.bss .bss.*)
+#endif
     *(COMMON)
     *(.dynsbss)
     *(.sbss)
@@ -602,6 +606,7 @@ SECTIONS
    * Because to `extern_ram_seg` and `drom0_0_seg` are on the same bus
    */
 
+#ifdef CONFIG_XTENSA_EXTMEM_BSS
   .ext_ram.dummy (NOLOAD):
   {
     . = ORIGIN(extern_ram_seg);
@@ -615,12 +620,18 @@ SECTIONS
   {
     _ext_ram_bss_start = ABSOLUTE(.);
 
+    *(.extmem.bss .extmem.bss.*)
     *(.ext_ram.bss .ext_ram.bss.*)
+    *libpp.a:(.bss .bss.*)
+    *libpp.a:(COMMON)
+    *libnet80211.a:(.bss .bss.*)
+    *libnet80211.a:(COMMON)
     *libpython3.13.a:(*.PyRuntime)
-
+    *libpython3.13.a:(.bss .bss.*)
     . = ALIGN(4);
     _ext_ram_bss_end = ABSOLUTE(.);
   } > extern_ram_seg
+#endif
 
   .rtc.text :
   {

boards/xtensa/esp32s3/common/scripts/flat_memory.ld

@@ -189,11 +189,13 @@ MEMORY
    * A dummy section is used to avoid overlap. See `.ext_ram.dummy` in `esp32s3_sections.ld
    */
 
-#ifdef CONFIG_ESP32S3_APP_FORMAT_MCUBOOT
+#ifdef CONFIG_XTENSA_EXTMEM_BSS
+#  ifdef CONFIG_ESP32S3_APP_FORMAT_MCUBOOT
   extern_ram_seg(RWX) :               org = 0x3c000000 + ORIGIN(ROM),
                                       len = 0x2000000 - ORIGIN(ROM)
-#else
+#  else
   extern_ram_seg(RWX) :               org = 0x3c000020 , len = 0x2000000-0x20
+#  endif
 #endif
 }
 

boards/xtensa/esp32s3/esp32s3-devkit/configs/python/defconfig

@@ -118,3 +118,4 @@ CONFIG_WIRELESS_WAPI_CMDTOOL=y
 CONFIG_WIRELESS_WAPI_STACKSIZE=4096
 CONFIG_WS2812=y
 CONFIG_WS2812_NON_SPI_DRIVER=y
+CONFIG_XTENSA_EXTMEM_BSS=y