From 20ddbd7368d5d098ea059cf1a148bf8dc3526f46 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 20 Apr 2017 11:08:23 -0600 Subject: [PATCH] STM32F0: Add support for HSI48 --- arch/arm/src/stm32f0/Kconfig | 10 +- arch/arm/src/stm32f0/Make.defs | 4 + arch/arm/src/stm32f0/chip/stm32f0_rcc.h | 64 +++++-- arch/arm/src/stm32f0/chip/stm32f0_usbdev.h | 6 +- arch/arm/src/stm32f0/stm32f0_hsi48.c | 183 +++++++++++++++++++++ arch/arm/src/stm32f0/stm32f0_hsi48.h | 109 ++++++++++++ arch/arm/src/stm32f0/stm32f0_rcc.h | 4 +- 7 files changed, 360 insertions(+), 20 deletions(-) create mode 100644 arch/arm/src/stm32f0/stm32f0_hsi48.c create mode 100644 arch/arm/src/stm32f0/stm32f0_hsi48.h diff --git a/arch/arm/src/stm32f0/Kconfig b/arch/arm/src/stm32f0/Kconfig index 746d9e40ec..a330dda624 100644 --- a/arch/arm/src/stm32f0/Kconfig +++ b/arch/arm/src/stm32f0/Kconfig @@ -466,6 +466,7 @@ config STM32F0_STM32F07X config STM32F0_STM32F09X bool default n + select STM32F0_HAVE_HSI48 config STM32F0_VALUELINE bool @@ -528,6 +529,7 @@ config STM32F0_LOWVOLTLINE config STM32F0_USBLINE bool default n + select STM32F0_HAVE_HSI48 select STM32F0_HAVE_USART3 select STM32F0_HAVE_USART4 select STM32F0_HAVE_TIM1 @@ -576,6 +578,10 @@ config STM32F0_HAVE_CCM bool default n +config STM32F0_HAVE_HSI48 + bool + default n + config STM32F0_HAVE_USBDEV bool default n @@ -588,10 +594,6 @@ config STM32F0_HAVE_HRTIM1 bool default n -config STM32F0_HAVE_LTDC - bool - default n - config STM32F0_HAVE_USART3 bool default n diff --git a/arch/arm/src/stm32f0/Make.defs b/arch/arm/src/stm32f0/Make.defs index ada01348f7..3aadfbfaae 100644 --- a/arch/arm/src/stm32f0/Make.defs +++ b/arch/arm/src/stm32f0/Make.defs @@ -87,6 +87,10 @@ ifeq ($(CONFIG_ARCH_IRQPRIO),y) CHIP_CSRCS += stm32f0_irqprio.c endif +ifeq ($(CONFIG_STM32F0_HAVE_HSI48),y) +CHIP_CSRCS += stm32f0_hsi48.c +endif + ifeq ($(CONFIG_STM32F0_SPI0),y) CHIP_CSRCS += stm32f0_spi.c else diff --git a/arch/arm/src/stm32f0/chip/stm32f0_rcc.h b/arch/arm/src/stm32f0/chip/stm32f0_rcc.h index 613020b830..89464aa682 100644 --- a/arch/arm/src/stm32f0/chip/stm32f0_rcc.h +++ b/arch/arm/src/stm32f0/chip/stm32f0_rcc.h @@ -55,6 +55,8 @@ #define STM32F0_RCC_CSR_OFFSET 0x0024 /* Control/status register */ #define STM32F0_RCC_AHBRSTR_OFFSET 0x0028 /* AHB Reset register */ #define STM32F0_RCC_CFGR2_OFFSET 0x002c /* Clock configuration register 2 */ +#define STM32F0_RCC_CFGR3_OFFSET 0x0030 /* Clock configuration register 3 */ +#define STM32F0_RCC_CR2_OFFSET 0x0034 /* Clock control register 2 */ /* Register Addresses ***************************************************************/ @@ -70,6 +72,8 @@ #define STM32F0_RCC_CSR (STM32F0_RCC_BASE+STM32F0_RCC_CSR_OFFSET) #define STM32F0_RCC_AHBRSTR (STM32F0_RCC_BASE+STM32F0_RCC_AHBRSTR_OFFSET) #define STM32F0_RCC_CFGR2 (STM32F0_RCC_BASE+STM32F0_RCC_CFGR2_OFFSET) +#define STM32F0_RCC_CFGR3 (STM32F0_RCC_BASE+STM32F0_RCC_CFGR3_OFFSET) +#define STM32F0_RCC_CR2 (STM32F0_RCC_BASE+STM32F0_RCC_CR2_OFFSET) /* Register Bitfield Definitions ****************************************************/ @@ -149,16 +153,18 @@ /* Bit 22-23: Reserved */ #define RCC_CFGR_MCO_SHIFT (24) /* Bits 27-24: Microcontroller Clock Output */ #define RCC_CFGR_MCO_MASK (15 << RCC_CFGR_MCO_SHIFT) -# define RCC_CFGR_NOCLK (0 << RCC_CFGR_MCO_SHIFT) /* 0000: No clock */ -# define RCC_CFGR_HSI14 (1 << RCC_CFGR_MCO_SHIFT) /* 0001: Internal RC 14MHz oscillator */ -# define RCC_CFGR_LSI (2 << RCC_CFGR_MCO_SHIFT) /* 0010: Internal Low Speed (LSI) oscillator */ -# define RCC_CFGR_LSE (2 << RCC_CFGR_MCO_SHIFT) /* 0011: External Low Speed (LSE) oscillator */ -# define RCC_CFGR_SYSCLK (4 << RCC_CFGR_MCO_SHIFT) /* 0100: System clock selected */ -# define RCC_CFGR_INTCLK (5 << RCC_CFGR_MCO_SHIFT) /* 0101: Internal 8 MHz RC oscillator clock selected */ -# define RCC_CFGR_EXTCLK (6 << RCC_CFGR_MCO_SHIFT) /* 0110: External 4-32 MHz oscillator clock selected */ -# define RCC_CFGR_PLLCLKd2 (7 << RCC_CFGR_MCO_SHIFT) /* 0111: PLL clock selected (divided by 1 or 2 depending on PLLNODIV */ -# define RCC_CFGR_PLL2CLK (8 << RCC_CFGR_MCO_SHIFT) /* 1000: Internal RC 48MHz (HSI48) oscillator */ -#define RCC_CFGR_MCOPRE_SHIFT (28) /* Bits 28-30: Microcontroller Clock Output Prescaler, not available on STM32F05x */ +# define RCC_CFGR_NOCLK (0 << RCC_CFGR_MCO_SHIFT) /* 0000: No clock */ +# define RCC_CFGR_HSI14 (1 << RCC_CFGR_MCO_SHIFT) /* 0001: Internal RC 14MHz oscillator */ +# define RCC_CFGR_LSI (2 << RCC_CFGR_MCO_SHIFT) /* 0010: Internal Low Speed (LSI) oscillator */ +# define RCC_CFGR_LSE (2 << RCC_CFGR_MCO_SHIFT) /* 0011: External Low Speed (LSE) oscillator */ +# define RCC_CFGR_SYSCLK (4 << RCC_CFGR_MCO_SHIFT) /* 0100: System clock selected */ +# define RCC_CFGR_INTCLK (5 << RCC_CFGR_MCO_SHIFT) /* 0101: Internal 8 MHz RC oscillator clock selected */ +# define RCC_CFGR_EXTCLK (6 << RCC_CFGR_MCO_SHIFT) /* 0110: External 4-32 MHz oscillator clock selected */ +# define RCC_CFGR_PLLCLKd2 (7 << RCC_CFGR_MCO_SHIFT) /* 0111: PLL clock selected (divided by 1 or 2 + * depending on PLLNODIV) */ +# define RCC_CFGR_PLL2CLK (8 << RCC_CFGR_MCO_SHIFT) /* 1000: Internal RC 48MHz (HSI48) oscillator */ +#define RCC_CFGR_MCOPRE_SHIFT (28) /* Bits 28-30: Microcontroller Clock Output Prescaler, + * not available on STM32F05x */ #define RCC_CFGR_MCOPRE_MASK (3 << RCC_CFGR_MCOPRE_SHIFT) # define RCC_CFGR_MCOPRE_div1 (0 << RCC_CFGR_MCOPRE_SHIFT) /* 000: MCO is divided by 1 */ # define RCC_CFGR_MCOPRE_div2 (1 << RCC_CFGR_MCOPRE_SHIFT) /* 001: MCO is divided by 2 */ @@ -345,4 +351,42 @@ # define RCC_CFGR2_PREDIV1d15 (14 << RCC_CFGR2_PREDIV1_SHIFT) # define RCC_CFGR2_PREDIV1d16 (15 << RCC_CFGR2_PREDIV1_SHIFT) +/* Clock configuration register 3 */ + +#define RCC_CFGR3_USART1SW_SHIFT (0) /* Bits 0-1: USART1 clock source selection */ +#define RCC_CFGR3_USART1SW_MASK (3 << RCC_CFGR3_USART1SW_SHIFT) +# define RCC_CFGR3_USART1SW_PCLK (0 << RCC_CFGR3_USART1SW_SHIFT) /* PCLK is USART1 clock source */ +# define RCC_CFGR3_USART1SW_SYSCLK (1 << RCC_CFGR3_USART1SW_SHIFT) /* SYSCLK is USART1 clock */ +# define RCC_CFGR3_USART1SW_LSE (2 << RCC_CFGR3_USART1SW_SHIFT) /* LSE is USART1 clock */ +# define RCC_CFGR3_USART1SW_HSI (3 << RCC_CFGR3_USART1SW_SHIFT) /* HSI is USART1 clock */ +#define RCC_CFGR3_CECSW (1 << 6) /* Bit 6: HDMI CEC clock source selection */ +#define RCC_CFGR3_USBSW (1 << 7) /* Bit 7: USB clock source selection */ +#define RCC_CFGR3_ADCSW (1 << 8) /* Bit 8: ADC clock source selection */ +#define RCC_CFGR3_USART2SW_SHIFT (16) /* Bits 16-17: USART2 clock source selection */ +#define RCC_CFGR3_USART2SW_MASK (3 << RCC_CFGR3_USART2SW_SHIFT) +# define RCC_CFGR3_USART2SW_PCLK (0 << RCC_CFGR3_USART2SW_SHIFT) /* PCLK is USART2 clock source */ +# define RCC_CFGR3_USART2SW_SYSCLK (1 << RCC_CFGR3_USART2SW_SHIFT) /* SYSCLK is USART2 clock */ +# define RCC_CFGR3_USART2SW_LSE (2 << RCC_CFGR3_USART2SW_SHIFT) /* LSE is USART2 clock */ +# define RCC_CFGR3_USART2SW_HSI (3 << RCC_CFGR3_USART2SW_SHIFT) /* HSI is USART2 clock */ +#define RCC_CFGR3_USART3SW_SHIFT (18) /* Bits 18-19: USART3 clock source selection */ +#define RCC_CFGR3_USART3SW_MASK (3 << RCC_CFGR3_USART3SW_SHIFT) +# define RCC_CFGR3_USART3SW_PCLK (0 << RCC_CFGR3_USART3SW_SHIFT) /* PCLK is USART3 clock source */ +# define RCC_CFGR3_USART3SW_SYSCLK (1 << RCC_CFGR3_USART3SW_SHIFT) /* SYSCLK is USART3 clock */ +# define RCC_CFGR3_USART3SW_LSE (2 << RCC_CFGR3_USART3SW_SHIFT) /* LSE is USART3 clock */ +# define RCC_CFGR3_USART3SW_HSI (3 << RCC_CFGR3_USART3SW_SHIFT) /* HSI is USART3 clock */ + +/* Clock control register 2 */ + +#define RCC_CR2_HSI14ON (1 << 0) /* Bit 0: HSI14 clock enable */ +#define RCC_CR2_HSI14RDY (1 << 1) /* Bit 1: HSI14 clock ready flag */ +#define RCC_CR2_HSI14DIS (1 << 2) /* Bit 2: HSI14 clock request from ADC disable */ +#define RCC_CR2_HSI14TRIM_SHIFT (3) /* Bits 3-7: HSI14 clock trimming */ +#define RCC_CR2_HSI14TRIM_MASK (31 << RCC_CR2_HSI14TRIM_SHIFT) +#define RCC_CR2_HSI14CAL_SHIFT (8) /* Bits 8-15: HSI14 clock calibration */ +#define RCC_CR2_HSI14CAL_MASK (0xff << RCC_CR2_HSI14CAL_SHIFT) +#define RCC_CR2_HSI48ON (1 << 16) /* Bit 16: HSI48 clock enable */ +#define RCC_CR2_HSI48RDY (1 << 17) /* Bit 17: HSI48 clock ready flag */ +#define RCC_CR2_HSI48CAL_SHIFT (24) /* Bits 24-31: HSI48 factory clock calibration */ +#define RCC_CR2_HSI48CAL_MASK (0xff << RCC_CR2_HSI48CAL_SHIFT) + #endif /* __ARCH_ARM_SRC_STM32F0_CHIP_STM32F0_RCC_H */ diff --git a/arch/arm/src/stm32f0/chip/stm32f0_usbdev.h b/arch/arm/src/stm32f0/chip/stm32f0_usbdev.h index 2c48f1809e..dabcc37fc5 100644 --- a/arch/arm/src/stm32f0/chip/stm32f0_usbdev.h +++ b/arch/arm/src/stm32f0/chip/stm32f0_usbdev.h @@ -108,10 +108,8 @@ #define STM32_USB_FNR (STM32_USB_BASE+STM32_USB_FNR_OFFSET) #define STM32_USB_DADDR (STM32_USB_BASE+STM32_USB_DADDR_OFFSET) #define STM32_USB_BTABLE (STM32_USB_BASE+STM32_USB_BTABLE_OFFSET) -#define STM32_USB_LPMCSR_OFFSET 0x0054 /* LPM control and status register (16-bits) */ -#define STM32_USB_LPMCSR_OFFSET 0x0054 /* LPM control and status register (16-bits) */ -#define STM32_USB_BCDR_OFFSET 0x0058 /* Battery charging detector (16-bits) */ -#define STM32_USB_BCDR_OFFSET 0x0058 /* Battery charging detector (16-bits) */ +#define STM32_USB_LPMCSR (STM32_USB_BASE+STM32_USB_LPMCSR_OFFSET) +#define STM32_USB_BCDR (STM32_USB_BASE+STM32_USB_BCDR_OFFSET) /* Buffer Descriptor Table (Relatative to BTABLE address) */ diff --git a/arch/arm/src/stm32f0/stm32f0_hsi48.c b/arch/arm/src/stm32f0/stm32f0_hsi48.c new file mode 100644 index 0000000000..73c46e5f63 --- /dev/null +++ b/arch/arm/src/stm32f0/stm32f0_hsi48.c @@ -0,0 +1,183 @@ +/**************************************************************************** + * arch/arm/src/stm32f0/stm32f0_hsi48.c + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "up_arch.h" +#include "chip.h" +#include "chip/stm32f0_rcc.h" +#include "chip/stm32f0_crs.h" + +#include "stm32f0_hsi48.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32f0_enable_hsi48 + * + * Description: + * On STM32F04x, STM32F07x and STM32F09x devices only, the HSI48 clock + * signal is generated from an internal 48 MHz RC oscillator and can be + * used directly as a system clock or divided and be used as PLL input. + * + * The internal 48MHz RC oscillator is mainly dedicated to provide a high + * precision clock to the USB peripheral by means of a special Clock + * Recovery System (CRS) circuitry, which could use the USB SOF signal or + * the LSE or an external signal to automatically adjust the oscillator + * frequency on-fly, in a very small steps. This oscillator can also be + * used as a system clock source when the system is in run mode; it will + * be disabled as soon as the system enters in Stop or Standby mode. When + * the CRS is not used, the HSI48 RC oscillator runs on its default + * frequency which is subject to manufacturing process variations. + * + * Input Parameters: + * Identifies the syncrhonization source for the HSI48. When used as the + * USB source clock, this must be set to SYNCSRC_USB. + * + * Returned Value: + * None + * + ****************************************************************************/ + +void stm32f0_enable_hsi48(enum syncsrc_e syncsrc) +{ + uint32_t regval; + + /* Enable the HSI48 clock. + * + * The HSI48 RC can be switched on and off using the HSI48ON bit in the + * Clock control register (RCC_CR). + * + * The USB clock may be derived from either the PLL clock or from the + * HSI48 clock. This oscillator will be also automatically enabled (by + * hardware forcing HSI48ON bit to one) as soon as it is chosen as a clock + * source for the USB and the peripheral is + * enabled. + */ + + regval = getreg32(STM32F0_RCC_CR2); + regval |= RCC_CR2_HSI48ON; + putreg32(regval, STM32F0_RCC_CR2); + + if (syncsrc == SYNCSRC_USB) + { + /* Select the HSI48 as the USB clock source */ + + regval = getreg32(STM32F0_RCC_CFGR3); + regval &= ~RCC_CFGR3_USBSW; + putreg32(regval, STM32F0_RCC_CFGR3); + } + + /* Wait for the HSI48 clock to stabilize */ + + while ((getreg32(STM32F0_RCC_CR2) & RCC_CR2_HSI48RDY) == 0); + + + /* The CRS synchronization (SYNC) source, selectable through the CRS_CFGR + * register, can be the signal from the external CRS_SYNC pin, the LSE + * clock or the USB SOF signal. + */ + + regval = getreg32(STM32F0_CRS_CFGR); + regval &= ~CRS_CFGR_SYNCSRC_MASK; + + switch (syncsrc) + { + default: + case SYNCSRC_GPIO: /* GPIO selected as SYNC signal source */ + regval |= CRS_CFGR_SYNCSRC_GPIO; + break; + + case SYNCSRC_LSE: /* LSE selected as SYNC signal source */ + regval |= CRS_CFGR_SYNCSRC_LSE; + break; + + case SYNCSRC_USB: /* USB SOF selected as SYNC signal source */ + regval |= CRS_CFGR_SYNCSRC_USBSOF; + break; + } + + putreg32(regval, STM32F0_CRS_CFGR); + + /* Set the AUTOTRIMEN bit the the CRS_CR register to enables the automatic + * hardware adjustment of TRIM bits according to the measured frequency + * error between the selected SYNC event. + */ + + regval = getreg32(STM32F0_CRS_CR); + regval |= CRS_CR_AUTOTRIMEN; + putreg32(regval, STM32F0_CRS_CR); +} + +/**************************************************************************** + * Name: stm32f0_disable_hsi48 + * + * Description: + * Disable the HSI48 clock. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void stm32f0_disable_hsi48(void) +{ + uint32_t regval; + + /* Disable the HSI48 clock */ + + regval = getreg32(STM32F0_RCC_CR2); + regval &= ~RCC_CR2_HSI48ON; + putreg32(regval, STM32F0_RCC_CR2); + + /* Set other registers to the default settings. */ + + regval = getreg32(STM32F0_CRS_CFGR); + regval &= ~CRS_CFGR_SYNCSRC_MASK; + putreg32(regval, STM32F0_CRS_CFGR); + + regval = getreg32(STM32F0_CRS_CR); + regval &= ~CRS_CR_AUTOTRIMEN; + putreg32(regval, STM32F0_CRS_CR); +} diff --git a/arch/arm/src/stm32f0/stm32f0_hsi48.h b/arch/arm/src/stm32f0/stm32f0_hsi48.h new file mode 100644 index 0000000000..d299db13e1 --- /dev/null +++ b/arch/arm/src/stm32f0/stm32f0_hsi48.h @@ -0,0 +1,109 @@ +/************************************************************************************ + * arch/arm/src/stm32f0/stm32f0_rcc.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * Alan Carvalho de Assis + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32F0_STM32F0_HSI48_H +#define __ARCH_ARM_SRC_STM32F0_STM32F0_HSI48_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#ifdef CONFIG_STM32F0_HAVE_HSI48 + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +enum syncsrc_e +{ + SYNCSRC_GPIO = 0, /* GPIO selected as SYNC signal source */ + SYNCSRC_LSE, /* LSE selected as SYNC signal source */ + SYNCSRC_USB, /* USB SOF selected as SYNC signal source */ +}; + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/**************************************************************************** + * Name: stm32f0_enable_hsi48 + * + * Description: + * On STM32F04x, STM32F07x and STM32F09x devices only, the HSI48 clock + * signal is generated from an internal 48 MHz RC oscillator and can be + * used directly as a system clock or divided and be used as PLL input. + * + * The internal 48MHz RC oscillator is mainly dedicated to provide a high + * precision clock to the USB peripheral by means of a special Clock + * Recovery System (CRS) circuitry, which could use the USB SOF signal or + * the LSE or an external signal to automatically adjust the oscillator + * frequency on-fly, in a very small steps. This oscillator can also be + * used as a system clock source when the system is in run mode; it will + * be disabled as soon as the system enters in Stop or Standby mode. When + * the CRS is not used, the HSI48 RC oscillator runs on its default + * frequency which is subject to manufacturing process variations. + * + * Input Parameters: + * Identifies the syncrhonization source for the HSI48. When used as the + * USB source clock, this must be set to SYNCSRC_USB. + * + * Returned Value: + * None + * + ****************************************************************************/ + +void stm32f0_enable_hsi48(enum syncsrc_e syncsrc); + +/**************************************************************************** + * Name: stm32f0_disable_hsi48 + * + * Description: + * Disable the HSI48 clock. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void stm32f0_disable_hsi48(void); + +#endif /* CONFIG_STM32F0_HAVE_HSI48 */ +#endif /* __ARCH_ARM_SRC_STM32F0_STM32F0_HSI48_H */ diff --git a/arch/arm/src/stm32f0/stm32f0_rcc.h b/arch/arm/src/stm32f0/stm32f0_rcc.h index ca8f537059..e23484ae43 100644 --- a/arch/arm/src/stm32f0/stm32f0_rcc.h +++ b/arch/arm/src/stm32f0/stm32f0_rcc.h @@ -34,8 +34,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0_STM32F0_RRC_H -#define __ARCH_ARM_SRC_STM32F0_STM32F0_RRC_H +#ifndef __ARCH_ARM_SRC_STM32F0_STM32F0_RCC_H +#define __ARCH_ARM_SRC_STM32F0_STM32F0_RCC_H /************************************************************************************ * Included Files