arch/arm/src/stm32f0l0g0: add FLASH support for STM32C0
Add FLASH support for STM32C0 based on STM32G0 FLASH driver. FLASH support is identical for these two, except that the STM32G0 can support dual bank, which is not available in the STM32C0. Signed-off-by: raiden00pl <raiden00@railab.me>
This commit is contained in:
raiden00pl
Xiang Xiao
parent
92159bbdba
commit
251b19272f
4 changed files with 180 additions and 19 deletions
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@ -909,166 +909,207 @@ config ARCH_CHIP_STM32L073RZ
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config ARCH_CHIP_STM32C051D8
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bool "STM32C051D8"
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select ARCH_CHIP_STM32C051XX
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select STM32F0L0G0_FLASH_CONFIG_8
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config ARCH_CHIP_STM32C051F6
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bool "STM32C051F6"
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select ARCH_CHIP_STM32C051XX
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select STM32F0L0G0_FLASH_CONFIG_6
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config ARCH_CHIP_STM32C051F8
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bool "STM32C051F8"
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select ARCH_CHIP_STM32C051XX
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select STM32F0L0G0_FLASH_CONFIG_8
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config ARCH_CHIP_STM32C051G6
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bool "STM32C051G6"
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select ARCH_CHIP_STM32C051XX
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select STM32F0L0G0_FLASH_CONFIG_6
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config ARCH_CHIP_STM32C051G8
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bool "STM32C051G8"
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select ARCH_CHIP_STM32C051XX
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select STM32F0L0G0_FLASH_CONFIG_8
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config ARCH_CHIP_STM32C051K6
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bool "STM32C051K6"
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select ARCH_CHIP_STM32C051XX
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select STM32F0L0G0_FLASH_CONFIG_6
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config ARCH_CHIP_STM32C051K8
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bool "STM32C051K8"
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select ARCH_CHIP_STM32C051XX
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select STM32F0L0G0_FLASH_CONFIG_8
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config ARCH_CHIP_STM32C051C6
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bool "STM32C051C6"
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select ARCH_CHIP_STM32C051XX
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select STM32F0L0G0_FLASH_CONFIG_6
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config ARCH_CHIP_STM32C051C8
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bool "STM32C051C8"
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select ARCH_CHIP_STM32C051XX
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select STM32F0L0G0_FLASH_CONFIG_8
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config ARCH_CHIP_STM32C071F8
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bool "STM32C071F8"
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select ARCH_CHIP_STM32C071XX
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select STM32F0L0G0_FLASH_CONFIG_8
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config ARCH_CHIP_STM32C071FB
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bool "STM32C071FB"
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select ARCH_CHIP_STM32C071XX
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select STM32F0L0G0_FLASH_CONFIG_B
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config ARCH_CHIP_STM32C071G8
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bool "STM32C071G8"
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select ARCH_CHIP_STM32C071XX
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select STM32F0L0G0_FLASH_CONFIG_8
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config ARCH_CHIP_STM32C071GB
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bool "STM32C071GB"
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select ARCH_CHIP_STM32C071XX
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select STM32F0L0G0_FLASH_CONFIG_B
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config ARCH_CHIP_STM32C071K8
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bool "STM32C071K8"
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select ARCH_CHIP_STM32C071XX
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select STM32F0L0G0_FLASH_CONFIG_8
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config ARCH_CHIP_STM32C071KB
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bool "STM32C071KB"
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select ARCH_CHIP_STM32C071XX
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select STM32F0L0G0_FLASH_CONFIG_B
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config ARCH_CHIP_STM32C071C8
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bool "STM32C071C8"
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select ARCH_CHIP_STM32C071XX
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select STM32F0L0G0_FLASH_CONFIG_8
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config ARCH_CHIP_STM32C071CB
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bool "STM32C071CB"
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select ARCH_CHIP_STM32C071XX
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select STM32F0L0G0_FLASH_CONFIG_B
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config ARCH_CHIP_STM32C071R8
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bool "STM32C071R8"
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select ARCH_CHIP_STM32C071XX
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select STM32F0L0G0_FLASH_CONFIG_8
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config ARCH_CHIP_STM32C071RB
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bool "STM32C071RB"
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select ARCH_CHIP_STM32C071XX
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select STM32F0L0G0_FLASH_CONFIG_B
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config ARCH_CHIP_STM32C091FB
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bool "STM32C091FB"
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select ARCH_CHIP_STM32C091XX
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select STM32F0L0G0_FLASH_CONFIG_B
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config ARCH_CHIP_STM32C091FC
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bool "STM32C091FC"
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select ARCH_CHIP_STM32C091XX
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select STM32F0L0G0_FLASH_CONFIG_C
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config ARCH_CHIP_STM32C091EC
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bool "STM32C091EC"
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select ARCH_CHIP_STM32C091XX
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select STM32F0L0G0_FLASH_CONFIG_C
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config ARCH_CHIP_STM32C091GB
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bool "STM32C091GB"
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select ARCH_CHIP_STM32C091XX
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select STM32F0L0G0_FLASH_CONFIG_B
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config ARCH_CHIP_STM32C091GC
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bool "STM32C091GC"
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select ARCH_CHIP_STM32C091XX
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select STM32F0L0G0_FLASH_CONFIG_C
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config ARCH_CHIP_STM32C091KB
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bool "STM32C091KB"
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select ARCH_CHIP_STM32C091XX
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select STM32F0L0G0_FLASH_CONFIG_B
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config ARCH_CHIP_STM32C091KC
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bool "STM32C091KC"
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select ARCH_CHIP_STM32C091XX
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select STM32F0L0G0_FLASH_CONFIG_C
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config ARCH_CHIP_STM32C091CB
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bool "STM32C091CB"
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select ARCH_CHIP_STM32C091XX
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select STM32F0L0G0_FLASH_CONFIG_B
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config ARCH_CHIP_STM32C091CC
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bool "STM32C091CC"
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select ARCH_CHIP_STM32C091XX
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select STM32F0L0G0_FLASH_CONFIG_C
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config ARCH_CHIP_STM32C091RB
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bool "STM32C091RB"
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select ARCH_CHIP_STM32C091XX
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select STM32F0L0G0_FLASH_CONFIG_B
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config ARCH_CHIP_STM32C091RC
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bool "STM32C091RC"
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select ARCH_CHIP_STM32C091XX
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select STM32F0L0G0_FLASH_CONFIG_C
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config ARCH_CHIP_STM32C092FB
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bool "STM32C092FB"
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select ARCH_CHIP_STM32C092XX
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select STM32F0L0G0_FLASH_CONFIG_B
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config ARCH_CHIP_STM32C092FC
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bool "STM32C092FC"
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select ARCH_CHIP_STM32C092XX
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select STM32F0L0G0_FLASH_CONFIG_C
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config ARCH_CHIP_STM32C092EC
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bool "STM32C092EC"
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select ARCH_CHIP_STM32C092XX
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select STM32F0L0G0_FLASH_CONFIG_C
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config ARCH_CHIP_STM32C092GB
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bool "STM32C092GB"
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select ARCH_CHIP_STM32C092XX
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select STM32F0L0G0_FLASH_CONFIG_B
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config ARCH_CHIP_STM32C092GC
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bool "STM32C092GC"
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select ARCH_CHIP_STM32C092XX
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select STM32F0L0G0_FLASH_CONFIG_C
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config ARCH_CHIP_STM32C092KB
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bool "STM32C092KB"
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select ARCH_CHIP_STM32C092XX
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select STM32F0L0G0_FLASH_CONFIG_B
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config ARCH_CHIP_STM32C092KC
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bool "STM32C092KC"
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select ARCH_CHIP_STM32C092XX
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select STM32F0L0G0_FLASH_CONFIG_C
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config ARCH_CHIP_STM32C092CB
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bool "STM32C092CB"
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select ARCH_CHIP_STM32C092XX
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select STM32F0L0G0_FLASH_CONFIG_B
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config ARCH_CHIP_STM32C092CC
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bool "STM32C092CC"
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select ARCH_CHIP_STM32C092XX
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select STM32F0L0G0_FLASH_CONFIG_C
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config ARCH_CHIP_STM32C092RB
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bool "STM32C092RB"
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select ARCH_CHIP_STM32C092XX
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select STM32F0L0G0_FLASH_CONFIG_B
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config ARCH_CHIP_STM32C092RC
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bool "STM32C092RC"
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select ARCH_CHIP_STM32C092XX
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select STM32F0L0G0_FLASH_CONFIG_C
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endchoice # ST STM32F0/L0/G0/C0 Chip Selection
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@ -1210,6 +1251,7 @@ config STM32F0L0G0_STM32G0
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select STM32F0L0G0_HAVE_TIM16
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select STM32F0L0G0_HAVE_TIM17
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select STM32F0L0G0_HAVE_I2C2
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select ARCH_HAVE_PROGMEM
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config STM32F0L0G0_STM32L0
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bool
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@ -1235,6 +1277,7 @@ config STM32F0L0G0_STM32C0
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select STM32F0L0G0_HAVE_TIM14
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select STM32F0L0G0_HAVE_TIM16
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select STM32F0L0G0_HAVE_TIM17
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select ARCH_HAVE_PROGMEM
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config STM32F0L0G0_STM32F03X
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bool
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@ -87,6 +87,119 @@
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#define FLASH_ACR_DBGSWEN (1 << 18) /* Bit 18: Debug access software enable */
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/* Bits 19-31: Reserved */
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/* TODO */
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/* Flash Status Register (SR) */
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#define FLASH_SR_EOP (1) /* Bit 0: End of operation */
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#define FLASH_SR_OPERR (1 << 1) /* Bit 1: Operation error */
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/* Bit 2: Reserved */
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#define FLASH_SR_PROGERR (1 << 3) /* Bit 3: Programming error */
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#define FLASH_SR_WRPERR (1 << 4) /* Bit 4: Write protection error */
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#define FLASH_SR_PGAERR (1 << 5) /* Bit 5: Programming alignment error */
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#define FLASH_SR_SIZERR (1 << 6) /* Bit 6: Size error */
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#define FLASH_SR_PGSERR (1 << 7) /* Bit 7: Programming sequence error */
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#define FLASH_SR_MISSERR (1 << 8) /* Bit 8: Fast programming data miss error */
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#define FLASH_SR_FASTERR (1 << 9) /* Bit 9: Fast programming error */
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/* Bits 10-13: Reserved */
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#define FLASH_SR_RDERR (1 << 14) /* Bit 14: PCROP read error */
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#define FLASH_SR_OPTVERR (1 << 15) /* Bit 15: Option and engineering bits loading validity error */
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#define FLASH_SR_BSY1 (1 << 16) /* Bit 16: Busy */
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/* Bit 17: Reserved */
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#define FLASH_SR_CFGBSY (1 << 18) /* Bit 18: Programming or erase configuration busy */
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/* Bits 19-31: Reserved */
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/* Flash Control Register (CR) */
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#define FLASH_CR_PG (1) /* Bit 0: Flash memory programming enable */
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#define FLASH_CR_PER (1 << 1) /* Bit 1: Page erase enable */
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#define FLASH_CR_MER1 (1 << 2) /* Bit 2: Mass erase */
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#define FLASH_CR_PNB_SHIFT (3) /* Bits 3-9: Page number selection */
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#define FLASH_CR_PNB_MASK (0x7f << FLASH_CR_PNB_SHIFT)
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# define FLASH_CR_PNB(n) ((n) << FLASH_CR_PNB_SHIFT)
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#define FLASH_CR_STRT (1 << 16) /* Bit 16: Start erase operation */
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#define FLASH_CR_OPTSTRT (1 << 17) /* Bit 17: Start of modification of option bytes */
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#define FLASH_CR_FSTPG (1 << 18) /* Bit 18: Fast programming enable */
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/* Bits 19-23: Reserved */
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#define FLASH_CR_EOPIE (1 << 24) /* Bit 24: End-of-operation interrupt enable */
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#define FLASH_CR_ERRIE (1 << 25) /* Bit 25: Error interrupt enable */
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#define FLASH_CR_RDERRIE (1 << 26) /* Bit 26: PCROP read error interrupt enable */
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#define FLASH_CR_OBL_LAUNCH (1 << 27) /* Bit 27: Option byte load launch */
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#define FLASH_CR_SEC_PROT (1 << 28) /* Bit 28: Securable memory area protection enable */
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/* Bit 29: Reserved */
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#define FLASH_CR_OPTLOCK (1 << 30) /* Bit 30: Options Lock */
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#define FLASH_CR_LOCK (1 << 31) /* Bit 31: FLASH_CR Lock */
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/* Flash Option Register (OPTR) */
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#define FLASH_OPTR_RDP_SHIFT (0)
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#define FLASH_OPTR_RDP_MASK (0xff << FLASH_OPTR_RDP_SHIFT)
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#define FLASH_OPTR_BOR_EN (1 << 8) /* Brown out reset enable */
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#define FLASH_OPTR_BORR_LEV_SHIFT (9) /* BOR threshold at rising Vdd supply */
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#define FLASH_OPTR_BORR_LEV_MASK (0x3 << FLASH_OPTR_BORR_LEV_SHIFT)
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#define FLASH_OPTR_BORF_LEV_SHIFT (11) /* BOR thresholda t falling Vdd supply */
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#define FLASH_OPTR_BORF_LEV_MASK (0x3 << FLASH_OPTR_BORF_LEV_SHIFT)
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#define FLASH_OPTR_NRST_STOP (1 << 13)
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#define FLASH_OPTR_NRST_STDBY (1 << 14)
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#define FLASH_OPTR_NRSTS_SHDW (1 << 15)
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#define FLASH_OPTR_IDWG_SW (1 << 16) /* Bit 16: Independent watchdog selection */
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#define FLASH_OPTR_IDWG_STOP (1 << 17) /* Bit 17: Independent watchdog counter freeze in stop mode */
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#define FLASH_OPTR_IDWG_STDBY (1 << 18) /* Bit 18: Independent watchdog counter freeze in Standby mode */
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#define FLASH_OPTR_WWDG_SW (1 << 19) /* Bit 19: Window watchdog selection */
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/* Bit 20: Reserved */
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#define FLASH_OPTR_HSE_NOT_REMAPPED (1 << 21) /* Bit 21: HSE remapping enable/disable */
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#define FLASH_OPTR_RAM_PARITY_CHECK (1 << 22) /* Bit 22: SRAM parity check control */
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#define FLASH_OPTR_SECURE_MUXING_EN (1 << 23) /* Bit 23: Multiple-bonding security */
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/* Bit 23: Reserved */
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#define FLASH_OPTR_NBOOT_SEL (1 << 24) /* Bit 24: BOOT0 signal source selection */
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#define FLASH_OPTR_NBOOT1 (1 << 25) /* Bit 25: NBOOT1 boot configuration */
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#define FLASH_OPTR_NBOOT0 (1 << 26) /* Bit 26: NBOOT0 option bit */
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#define FLASH_OPTR_NRST_MODE_SHIFT (27) /* Bits 27-28: PF2-NRST pin configuration */
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#define FLASH_OPTR_NRST_MODE_MASK (0x3 << FLASH_OPTR_NRST_MODE_SHIFT)
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#define FLASH_OPTR_IRHEN (1 << 29) /* Bit 29: Internal reset holder enable */
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#define FLASH_OPTR_FDCAN_BLCK_SHIFT (30) /* Bits 30-31: FDCAN bootloader clock source */
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#define FLASH_OPTR_FDCAN_BLCK_MASK (0x3 << FLASH_OPTR_FDCAN_BLCK_SHIFT)
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/* Flash PCROP area A start address register (PCROP1ASR) */
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#define FLASH_PCROP1ASR_STRT_SHIFT (0)
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#define FLASH_PCROP1ASR_STRT_MASK (0x1ff << FLASH_PCROP1ASR_STRT_SHIFT)
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/* Flash PCROP area A end address register (PCROP1AER) */
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#define FLASH_PCROP1AER_PCROP1A_END_SHIFT (0)
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#define FLASH_PCROP1AER_PCROP1A_END_MASK (0x1ff << FLASH_PCROP1AER_PCROP1A_END_SHIFT)
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#define FLASH_PCROP1AER_PCROP_RDP (1 << 31)
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/* Flash WRP area A address register (WRP1AR) */
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#define FLASH_WRP1AR_WRP1A_STRT_SHIFT (0)
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#define FLASH_WRP1AR_WRP1A_STRT_MASK (0x7f << FLASH_WRP1AR_WRP1A_STRT_SHIFT)
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#define FLASH_WRP1AR_WRP1A_END_SHIFT (16)
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#define FLASH_WRP1AR_WRP1A_END_MASK (0x7f << FLASH_WRP1AR_WRP1A_END_SHIFT)
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/* Flash WRP area B address register (WRP1BR) */
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#define FLASH_WRP1BR_WRP1B_STRT_SHIFT (0)
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#define FLASH_WRP1BR_WRP1B_STRT_MASK (0x7f << FLASH_WRP1BR_WRP1B_STRT_SHIFT)
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#define FLASH_WRP1BR_WRP1B_END_SHIFT (16)
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#define FLASH_WRP1BR_WRP1B_END_MASK (0x7f << FLASH_WRP1BR_WRP1B_END_SHIFT)
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/* Flash PCROP area B start address register (PCROP1BSR) */
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#define FLASH_PCROP1BSR_PCROP1B_STRT_SHIFT (0)
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#define FLASH_PCROP1BSR_PCROP1B_STRT_MASK (0x1ff << FLASH_PCROP1BSR_PCROP1B_STRT_SHIFT)
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/* Flash PCROP area B end address register (PCROP1BER) */
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#define FLASH_PCROP1BER_PCROP1B_END_SHIFT (0)
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#define FLASH_PCROP1BER_PCROP1B_END_MASK (0x1ff << FLASH_PCROP1BER_PCROP1B_END_SHIFT)
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/* Flash Security register (SECR) */
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#define FLASH_SECR_SEC_SIZE_SHIFT (0) /* Bits 0-7: Securable memory area size */
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#define FLASH_SECR_SEC_SIZE_MASK (0xff << FLASH_SECR_SEC_SIZE_SHIFT)
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/* Bits 8-15: Reserved */
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#define FLASH_SECR_BOOT_LOCK (1 << 16) /* Bit 16: Used to force boot from user area */
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/* Bits 20-31: Reserved */
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#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32C0_FLASH_H */
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@ -26,8 +26,8 @@
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#include <nuttx/config.h>
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#if defined(CONFIG_STM32F0L0G0_STM32G0)
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# include "stm32g0_flash.c"
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#if defined(CONFIG_STM32F0L0G0_STM32G0) || defined(CONFIG_STM32F0L0G0_STM32C0)
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# include "stm32g0c0_flash.c"
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#else
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# error "Flash driver unsupported on selected chip."
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#endif
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@ -1,5 +1,5 @@
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/****************************************************************************
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* arch/arm/src/stm32f0l0g0/stm32g0_flash.c
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* arch/arm/src/stm32f0l0g0/stm32g0c0_flash.c
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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@ -107,20 +107,26 @@
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# define FLASH_NBLOCKS 64
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#elif defined(CONFIG_STM32F0L0G0_FLASH_CONFIG_C)
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# define FLASH_NBLOCKS 128
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# ifdef CONFIG_ARCH_CHIP_STM32G0
|
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# define FLASH_DUAL_BANK 1
|
||||
# define FLASH_BANK2_BASE 0x08020000
|
||||
# endif
|
||||
#elif defined(CONFIG_STM32F0L0G0_FLASH_CONFIG_E)
|
||||
# define FLASH_NBLOCKS 256
|
||||
# ifdef CONFIG_ARCH_CHIP_STM32G0
|
||||
# define FLASH_DUAL_BANK 1
|
||||
# define FLASH_BANK2_BASE 0x08040000
|
||||
# endif
|
||||
#else
|
||||
# error "Invalid flash configuration defined"
|
||||
#endif
|
||||
|
||||
#ifdef FLASH_DUAL_BANK
|
||||
# define FLASH_BANKSIZE (FLASH_NBLOCKS * FLASH_BLOCK_SIZE / 2)
|
||||
# define FLASH_SR_BSY (FLASH_SR_BSY1 | FLASH_SR_BSY2)
|
||||
#else
|
||||
# define FLASH_BANKSIZE (FLASH_NBLOCKS * FLASH_BLOCK_SIZE)
|
||||
# define FLASH_SR_BSY (FLASH_SR_BSY1)
|
||||
#endif
|
||||
|
||||
/* Dual bank G0B1 MCUs have a non-linear mapping of block number between
|
||||
|
|
@ -301,8 +307,7 @@ static int flash_wait_for_operation(void)
|
|||
|
||||
for (i = 0; i < FLASH_TIMEOUT; i += 10)
|
||||
{
|
||||
if (!(getreg32(STM32_FLASH_SR) &
|
||||
(FLASH_SR_CFGBSY | FLASH_SR_BSY1 | FLASH_SR_BSY2)))
|
||||
if (!(getreg32(STM32_FLASH_SR) & (FLASH_SR_CFGBSY | FLASH_SR_BSY)))
|
||||
{
|
||||
timeout = false;
|
||||
break;
|
||||
|
|
@ -852,7 +857,7 @@ ssize_t up_progmem_write(size_t addr, const void *buf, size_t count)
|
|||
goto exit_with_unlock;
|
||||
}
|
||||
|
||||
/* Future improvements may add ECC checking here. */
|
||||
/* Future improvements may add ECC checking here (STM32G0 only). */
|
||||
}
|
||||
|
||||
modifyreg32(STM32_FLASH_CR, FLASH_CR_PG, 0);
|
||||
|
|
@ -877,7 +882,7 @@ exit_with_unlock:
|
|||
break;
|
||||
}
|
||||
|
||||
/* Future improvements may add ECC checking here. */
|
||||
/* Future improvements may add ECC checking here (STM32G0 only). */
|
||||
}
|
||||
|
||||
modifyreg32(STM32_FLASH_SR, 0, FLASH_SR_CLEAR_ERROR_FLAGS);
|
||||
Loading…
Add table
Reference in a new issue