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board/tricore: rename tc397 chip board name

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"tc397" is a chip name which is not appropriate to act as a board name.
 the board supported here is actually "a2g-tc397-5v-tft".
 The correct definition is : tricore is arch name, tc3xx is arch family
 name, tc397 is chip name and the borad name is a2g-tc397-5v-tft
This commit is contained in:
wangchengdong 2025-08-25 13:35:13 +08:00 • committed by Xiang Xiao
parent 9b8c8bdd7b
commit 28206007e0
29 changed files with 360 additions and 188 deletions
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12
Documentation/platforms/tricore/tc397/boards/kit_a2g_tc397_tft/index.rst
View file

@ -1,14 +1,14 @@
================= =================
KIT_A2G_TC397_TFT A2G_TC397_5V_TFT
================= =================
This page file describes the contents of the build configurations available This page file describes the contents of the build configurations available
for the NuttX TriCore port. for the NuttX TriCore port.
Infineon’s AURIX™- TC3xx `KIT_A2G_TC397_TFT <https://www.infineon.com/cms/en/product/evaluation-boards/kit_a2g_tc397_5v_tft>`__ Board Infineon’s AURIX™- TC3xx `A2G_TC397_5V_TFT <https://www.infineon.com/cms/en/product/evaluation-boards/kit_a2g_tc397_5v_tft>`__ Board
===================================================================================================================================== =====================================================================================================================================
This port should work on KIT_A2G_TC397_TFT with a proper CPU. This port should work on A2G_TC397_5V_TFT with a proper CPU.
The mandatory CPU features are: The mandatory CPU features are:
* System Timer (STM) * System Timer (STM)
@ -26,17 +26,17 @@ Configurations
Common Configuration Notes Common Configuration Notes
-------------------------- --------------------------
1. Each Tricore TC397 configuration is maintained in a sub-directory 1. Each A2G_TC397_5V_TFT configuration is maintained in a sub-directory
and can be selected as follow:: and can be selected as follow::
tools/configure.sh tc397:<subdir> tools/configure.sh a2g-tc397-5v-tft:<subdir>
Where ``<subdir>`` is one of the configuration sub-directories described in Where ``<subdir>`` is one of the configuration sub-directories described in
the following paragraph. the following paragraph.
NuttX Shell:: NuttX Shell::
tools/configure.sh tc397:nsh tools/configure.sh a2g-tc397-5v-tft:nsh
2. These configurations use the mconf-based configuration tool. To 2. These configurations use the mconf-based configuration tool. To
change a configurations using that tool, you should: change a configurations using that tool, you should:

5
arch/tricore/Kconfig
View file

@ -34,7 +34,7 @@ config ARCH_FAMILY
config ARCH_CHIP config ARCH_CHIP
string string
default "tc3xx" if ARCH_CHIP_TC397 default "tc397" if ARCH_CHIP_TC397
config ARCH_CHIP_TC397 config ARCH_CHIP_TC397
bool "AURIX Family TC397" bool "AURIX Family TC397"
@ -47,4 +47,7 @@ config ARCH_CHIP_TC397
if ARCH_TC3XX if ARCH_TC3XX
source "arch/tricore/src/tc3xx/Kconfig" source "arch/tricore/src/tc3xx/Kconfig"
endif endif
if ARCH_TC397
source "arch/tricore/src/tc397/Kconfig"
endif
endif # ARCH_TRICORE endif # ARCH_TRICORE

4
arch/tricore/include/irq.h
View file

@ -44,6 +44,10 @@
#include <arch/chip/irq.h> #include <arch/chip/irq.h>
#if defined(CONFIG_ARCH_TC3XX)
# include <arch/tc3xx/irq.h>
#endif
/**************************************************************************** /****************************************************************************
* Pre-processor Prototypes * Pre-processor Prototypes
****************************************************************************/ ****************************************************************************/

48
arch/tricore/include/tc397/chip.h Normal file
View file

@ -0,0 +1,48 @@
/****************************************************************************
* arch/tricore/include/tc397/chip.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_TRICORE_INCLUDE_TC397_CHIP_H
#define __ARCH_TRICORE_INCLUDE_TC397_CHIP_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
/****************************************************************************
* Pre-processor Prototypes
****************************************************************************/
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* __ARCH_TRICORE_INCLUDE_TC397_CHIP_H */

69
arch/tricore/include/tc397/irq.h Normal file
View file

@ -0,0 +1,69 @@
/****************************************************************************
* arch/tricore/include/tc397/irq.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* This file should never be included directly but, rather,
* only indirectly through nuttx/irq.h
*/
#ifndef __ARCH_TRICORE_INCLUDE_TC397_IRQ_H
#define __ARCH_TRICORE_INCLUDE_TC397_IRQ_H
/****************************************************************************
* Included Files
****************************************************************************/
/****************************************************************************
* Pre-processor Prototypes
****************************************************************************/
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Inline functions
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#ifndef __ASSEMBLY__
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif
#endif /* __ARCH_TRICORE_INCLUDE_TC397_IRQ_H */

2
arch/tricore/src/CMakeLists.txt
View file

@ -19,7 +19,7 @@
# the License. # the License.
# #
# ############################################################################## # ##############################################################################
add_subdirectory(${ARCH_SUBDIR})
add_subdirectory(${NUTTX_CHIP_ABS_DIR} EXCLUDE_FROM_ALL exclude_chip) add_subdirectory(${NUTTX_CHIP_ABS_DIR} EXCLUDE_FROM_ALL exclude_chip)
add_subdirectory(common) add_subdirectory(common)

1
arch/tricore/src/Makefile
View file

@ -25,6 +25,7 @@ include chip/Make.defs
ifeq ($(CONFIG_ARCH_TC3XX),y) ifeq ($(CONFIG_ARCH_TC3XX),y)
ARCH_SUBDIR = tc3xx ARCH_SUBDIR = tc3xx
include $(ARCH_SUBDIR)/Make.defs
endif endif
ARCH_SRCDIR = $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src ARCH_SRCDIR = $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src

3
arch/tricore/src/tc397/.gitignore vendored Normal file
View file

@ -0,0 +1,3 @@
/*_unpack
/tc397
/*tar.gz

37
arch/tricore/src/tc397/CMakeLists.txt Normal file
View file

@ -0,0 +1,37 @@
# ##############################################################################
# arch/tricore/src/tc3xx/CMakeLists.txt
#
# SPDX-License-Identifier: Apache-2.0
#
# Licensed to the Apache Software Foundation (ASF) under one or more contributor
# license agreements. See the NOTICE file distributed with this work for
# additional information regarding copyright ownership. The ASF licenses this
# file to you under the Apache License, Version 2.0 (the "License"); you may not
# use this file except in compliance with the License. You may obtain a copy of
# the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
# License for the specific language governing permissions and limitations under
# the License.
#
# ##############################################################################
if(CONFIG_ARCH_CHIP_TC397)
if(NOT EXISTS ${CMAKE_CURRENT_LIST_DIR}/tc397)
FetchContent_Declare(
tc397
URL https://github.com/wangchdo/tc397_sdk/archive/refs/heads/master.tar.gz
SOURCE_DIR ${CMAKE_CURRENT_LIST_DIR}/tc397 BINARY_DIR
${CMAKE_BINARY_DIR}/arch/${CONFIG_ARCH}/src/${CONFIG_ARCH_CHIP}/tc397)
FetchContent_GetProperties(tc397)
if(NOT tc397_POPULATED)
FetchContent_Populate(tc397)
endif()
endif()
add_subdirectory(tc397)
endif()

2
boards/tricore/tc3xx/tc397/Kconfig → arch/tricore/src/tc397/Kconfig
View file

@ -3,5 +3,3 @@
# see the file kconfig-language.txt in the NuttX tools repository. # see the file kconfig-language.txt in the NuttX tools repository.
# #
if ARCH_BOARD_TC397
endif

49
arch/tricore/src/tc397/Make.defs Normal file
View file

@ -0,0 +1,49 @@
############################################################################
# arch/tricore/src/tc397/Make.defs
#
# SPDX-License-Identifier: Apache-2.0
#
# Licensed to the Apache Software Foundation (ASF) under one or more
# contributor license agreements. See the NOTICE file distributed with
# this work for additional information regarding copyright ownership. The
# ASF licenses this file to you under the Apache License, Version 2.0 (the
# "License"); you may not use this file except in compliance with the
# License. You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
# License for the specific language governing permissions and limitations
# under the License.
#
############################################################################
ifeq ($(CONFIG_ARCH_CHIP_TC397),y)
-include tc397/tc397/Make.defs
endif
TC397_UNPACK = tc397
TC397_COMMIT = master
TC397_URL = https://github.com/wangchdo/tc397_sdk/archive/refs/heads
TC397_TARBALL = tc397/$(TC397_UNPACK).tar.gz
TC397_DIR = tc397_sdk-master
$(TC397_TARBALL):
$(call DOWNLOAD,$(TC397_URL),$(TC397_COMMIT).tar.gz,$(TC397_TARBALL))
tc397/.tc397_unpack: $(TC397_TARBALL)
$(Q) echo "Unpacking: TC397"
$(Q) tar xzf $(TC397_TARBALL) -C tc397
$(Q) mv tc397/$(TC397_DIR) tc397/$(TC397_UNPACK)
$(Q) touch tc397/.tc397_unpack
ifeq ($(wildcard tc397/$(TC397_UNPACK)/.git),)
context:: tc397/.tc397_unpack
distclean::
$(call DELFILE, tc397/.tc397_unpack)
$(call DELFILE, $(TC397_TARBALL))
$(call DELDIR, tc397/$(TC397_UNPACK))
endif

8
arch/tricore/src/tc3xx/chip.h → arch/tricore/src/tc397/chip.h
View file

@ -1,5 +1,5 @@
/**************************************************************************** /****************************************************************************
* arch/tricore/src/tc3xx/chip.h * arch/tricore/src/tc397/chip.h
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
* *
@ -20,11 +20,11 @@
* *
****************************************************************************/ ****************************************************************************/
#ifndef __ARCH_TRICORE_SRC_TC3XX_CHIP_H #ifndef __ARCH_TRICORE_SRC_TC397_CHIP_H
#define __ARCH_TRICORE_SRC_TC3XX_CHIP_H #define __ARCH_TRICORE_SRC_TC397_CHIP_H
/**************************************************************************** /****************************************************************************
* Included Files * Included Files
****************************************************************************/ ****************************************************************************/
#endif /* __ARCH_TRICORE_SRC_TC3XX_CHIP_H */ #endif /* __ARCH_TRICORE_SRC_TC397_CHIP_H */

30
arch/tricore/src/tc3xx/CMakeLists.txt
View file

@ -24,28 +24,10 @@ set(SRCS tc3xx_timerisr.c tc3xx_serial.c)
target_sources(arch PRIVATE ${SRCS}) target_sources(arch PRIVATE ${SRCS})
if(CONFIG_ARCH_CHIP_TC397) if(CONFIG_TRICORE_TOOLCHAIN_TASKING)
nuttx_add_kernel_library(c_fpu)
if(NOT EXISTS ${CMAKE_CURRENT_LIST_DIR}/tc397) target_sources(c_fpu PRIVATE tc3xx_libc.c)
FetchContent_Declare( target_link_options(
tc397 nuttx PRIVATE
URL https://github.com/anchao/tc397_sdk/archive/refs/heads/master.tar.gz --library-directory=${CMAKE_BINARY_DIR}/arch/tricore/src/exclude_chip)
SOURCE_DIR ${CMAKE_CURRENT_LIST_DIR}/tc397 BINARY_DIR
${CMAKE_BINARY_DIR}/arch/${CONFIG_ARCH}/src/${CONFIG_ARCH_CHIP}/tc397)
FetchContent_GetProperties(tc397)
if(NOT tc397_POPULATED)
FetchContent_Populate(tc397)
endif()
endif()
add_subdirectory(tc397)
if(CONFIG_TRICORE_TOOLCHAIN_TASKING)
nuttx_add_kernel_library(c_fpu)
target_sources(c_fpu PRIVATE tc3xx_libc.c)
target_link_options(
nuttx PRIVATE
--library-directory=${CMAKE_BINARY_DIR}/arch/tricore/src/exclude_chip)
endif()
endif() endif()

29
arch/tricore/src/tc3xx/Make.defs
View file

@ -20,10 +20,6 @@
# #
############################################################################ ############################################################################
ifeq ($(CONFIG_ARCH_CHIP_TC397),y)
-include tc3xx/tc397/Make.defs
endif
CHIP_CSRCS += tc3xx_timerisr.c CHIP_CSRCS += tc3xx_timerisr.c
CHIP_CSRCS += tc3xx_serial.c CHIP_CSRCS += tc3xx_serial.c
@ -52,28 +48,3 @@ EXTRA_LIBS += libos$(LIBEXT)
endif endif
LIBPATHS += $(CURDIR) LIBPATHS += $(CURDIR)
TC397_UNPACK = tc397
TC397_COMMIT = master
TC397_URL = https://github.com/anchao/tc397_sdk/archive/refs/heads
TC397_TARBALL = tc3xx/$(TC397_UNPACK).tar.gz
TC397_DIR = tc397_sdk-master
$(TC397_TARBALL):
$(call DOWNLOAD,$(TC397_URL),$(TC397_COMMIT).tar.gz,$(TC397_TARBALL))
tc3xx/.tc397_unpack: $(TC397_TARBALL)
$(Q) echo "Unpacking: TC397"
$(Q) tar xzf $(TC397_TARBALL) -C tc3xx
$(Q) mv tc3xx/$(TC397_DIR) tc3xx/$(TC397_UNPACK)
$(Q) touch tc3xx/.tc397_unpack
ifeq ($(wildcard tc3xx/$(TC397_UNPACK)/.git),)
context:: .tc397_unpack
distclean::
$(call DELFILE, tc3xx/.tc397_unpack)
$(call DELFILE, $(TC397_TARBALL))
$(call DELDIR, tc3xx/$(TC397_UNPACK))
endif

8
boards/Kconfig
View file

@ -2331,7 +2331,7 @@ config ARCH_BOARD_SABRE_6QUAD
This options selects support for NuttX on the NXP/Freescale Sabre This options selects support for NuttX on the NXP/Freescale Sabre
board featuring the iMX 6Quad CPU. board featuring the iMX 6Quad CPU.
config ARCH_BOARD_TC397 config ARCH_BOARD_A2G_TC397_5V_TFT
bool "Infineon's AURIX TC397 board: KIT_A2G_TC397_5V_TFT" bool "Infineon's AURIX TC397 board: KIT_A2G_TC397_5V_TFT"
depends on ARCH_CHIP_TC397 depends on ARCH_CHIP_TC397
---help--- ---help---
@ -3724,7 +3724,7 @@ config ARCH_BOARD
default "milkv_duos" if ARCH_BOARD_SG2000_MILKV_DUOS default "milkv_duos" if ARCH_BOARD_SG2000_MILKV_DUOS
default "starpro64" if ARCH_BOARD_EIC7700X_STARPRO64 default "starpro64" if ARCH_BOARD_EIC7700X_STARPRO64
default "sabre-6quad" if ARCH_BOARD_SABRE_6QUAD default "sabre-6quad" if ARCH_BOARD_SABRE_6QUAD
default "tc397" if ARCH_BOARD_TC397 default "a2g-tc397-5v-tft" if ARCH_BOARD_A2G_TC397_5V_TFT
default "qemu-armv7a" if ARCH_BOARD_QEMU_ARMV7A default "qemu-armv7a" if ARCH_BOARD_QEMU_ARMV7A
default "qemu-armv7r" if ARCH_BOARD_QEMU_ARMV7R default "qemu-armv7r" if ARCH_BOARD_QEMU_ARMV7R
default "qemu-armv8a" if ARCH_BOARD_QEMU_ARMV8A default "qemu-armv8a" if ARCH_BOARD_QEMU_ARMV8A
@ -3939,8 +3939,8 @@ endif
if ARCH_BOARD_SABRE_6QUAD if ARCH_BOARD_SABRE_6QUAD
source "boards/arm/imx6/sabre-6quad/Kconfig" source "boards/arm/imx6/sabre-6quad/Kconfig"
endif endif
if ARCH_BOARD_TC397 if ARCH_BOARD_A2G_TC397_5V_TFT
source "boards/tricore/tc3xx/tc397/Kconfig" source "boards/tricore/tc397/a2g-tc397-5v-tft/Kconfig"
endif endif
if ARCH_BOARD_MPS2_AN500 if ARCH_BOARD_MPS2_AN500
source "boards/arm/mps/mps2-an500/Kconfig" source "boards/arm/mps/mps2-an500/Kconfig"

2
boards/tricore/tc3xx/tc397/CMakeLists.txt → boards/tricore/tc397/a2g-tc397-5v-tft/CMakeLists.txt
View file

@ -1,5 +1,5 @@
# ############################################################################## # ##############################################################################
# boards/tricore/tc3xx/tc397/CMakeLists.txt # boards/tricore/tc397/a2g-tc397-5v-tft/CMakeLists.txt
# #
# SPDX-License-Identifier: Apache-2.0 # SPDX-License-Identifier: Apache-2.0
# #

7
boards/tricore/tc397/a2g-tc397-5v-tft/Kconfig Normal file
View file

@ -0,0 +1,7 @@
#
# For a description of the syntax of this configuration file,
# see the file kconfig-language.txt in the NuttX tools repository.
#
if ARCH_BOARD_A2G_TC397_5V_TFT
endif

6
boards/tricore/tc3xx/tc397/configs/nsh/defconfig → boards/tricore/tc397/a2g-tc397-5v-tft/configs/nsh/defconfig
View file

@ -7,9 +7,9 @@
# #
# CONFIG_NSH_CMDOPT_HEXDUMP is not set # CONFIG_NSH_CMDOPT_HEXDUMP is not set
CONFIG_ARCH="tricore" CONFIG_ARCH="tricore"
CONFIG_ARCH_BOARD="tc397" CONFIG_ARCH_BOARD="a2g-tc397-5v-tft"
CONFIG_ARCH_BOARD_TC397=y CONFIG_ARCH_BOARD_A2G_TC397_5V_TFT=y
CONFIG_ARCH_CHIP="tc3xx" CONFIG_ARCH_CHIP="tc397"
CONFIG_ARCH_CHIP_TC397=y CONFIG_ARCH_CHIP_TC397=y
CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_INTERRUPTSTACK=2048
CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_STACKDUMP=y

8
boards/tricore/tc3xx/tc397/include/board.h → boards/tricore/tc397/a2g-tc397-5v-tft/include/board.h
View file

@ -1,5 +1,5 @@
/**************************************************************************** /****************************************************************************
* boards/tricore/tc3xx/tc397/include/board.h * boards/tricore/tc397/a2g-tc397-5v-tft/include/board.h
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
* *
@ -20,8 +20,8 @@
* *
****************************************************************************/ ****************************************************************************/
#ifndef __BOARDS_TRICORE_TC3XX_TC397_INCLUDE_BOARD_H #ifndef __BOARDS_TRICORE_TC397_A2G_TC397_5V_TFT_INCLUDE_BOARD_H
#define __BOARDS_TRICORE_TC3XX_TC397_INCLUDE_BOARD_H #define __BOARDS_TRICORE_TC397_A2G_TC397_5V_TFT_INCLUDE_BOARD_H
/**************************************************************************** /****************************************************************************
* Included Files * Included Files
@ -37,4 +37,4 @@
* Public Functions Definitions * Public Functions Definitions
****************************************************************************/ ****************************************************************************/
#endif /* __BOARDS_TRICORE_TC3XX_TC397_INCLUDE_BOARD_H */ #endif /* __BOARDS_TRICORE_TC397_A2G_TC397_5V_TFT_INCLUDE_BOARD_H */

8
boards/tricore/tc3xx/tc397/include/board_memorymap.h → boards/tricore/tc397/a2g-tc397-5v-tft/include/board_memorymap.h
View file

@ -1,5 +1,5 @@
/**************************************************************************** /****************************************************************************
* boards/tricore/tc3xx/tc397/include/board_memorymap.h * boards/tricore/tc397/a2g-tc397-5v-tft/include/board_memorymap.h
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
* *
@ -20,8 +20,8 @@
* *
****************************************************************************/ ****************************************************************************/
#ifndef __BOARDS_TRICORE_TC3XX_TC397_INCLUDE_BOARD_MEMORYMAP_H #ifndef __BOARDS_TRICORE_TC397_A2G_TC397_5V_TFT_INCLUDE_BOARD_MEMORYMAP_H
#define __BOARDS_TRICORE_TC3XX_TC397_INCLUDE_BOARD_MEMORYMAP_H #define __BOARDS_TRICORE_TC397_A2G_TC397_5V_TFT_INCLUDE_BOARD_MEMORYMAP_H
/**************************************************************************** /****************************************************************************
* Included Files * Included Files
@ -58,4 +58,4 @@ extern "C"
#endif #endif
#endif /* __ASSEMBLY__ */ #endif /* __ASSEMBLY__ */
#endif /* __BOARDS_TRICORE_TC3XX_TC397_INCLUDE_BOARD_MEMORYMAP_H */ #endif /* __BOARDS_TRICORE_TC397_A2G_TC397_5V_TFT_INCLUDE_BOARD_MEMORYMAP_H */

188
boards/tricore/tc3xx/tc397/scripts/Lcf_Gnuc_Tricore_Tc.lsl → boards/tricore/tc397/a2g-tc397-5v-tft/scripts/Lcf_Gnuc_Tricore_Tc.lsl
View file

@ -1,5 +1,5 @@
/**************************************************************************** /****************************************************************************
* boards/tricore/tc3xx/tc397/scripts/Lcf_Gnuc_Tricore_Tc.lsl * boards/tricore/tc397/a2g-tc397-5v-tft/scripts/Lcf_Gnuc_Tricore_Tc.lsl
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
* *
@ -146,72 +146,72 @@ MEMORY
dsram5_local (w!xp): org = 0xd0000000, len = 96K dsram5_local (w!xp): org = 0xd0000000, len = 96K
dsram5 (w!xp): org = 0x10000000, len = 96K dsram5 (w!xp): org = 0x10000000, len = 96K
psram5 (w!xp): org = 0x10100000, len = 64K psram5 (w!xp): org = 0x10100000, len = 64K
dsram4_local (w!xp): org = 0xd0000000, len = 96K dsram4_local (w!xp): org = 0xd0000000, len = 96K
dsram4 (w!xp): org = 0x30000000, len = 96K dsram4 (w!xp): org = 0x30000000, len = 96K
psram4 (w!xp): org = 0x30100000, len = 64K psram4 (w!xp): org = 0x30100000, len = 64K
dsram3_local (w!xp): org = 0xd0000000, len = 96K dsram3_local (w!xp): org = 0xd0000000, len = 96K
dsram3 (w!xp): org = 0x40000000, len = 96K dsram3 (w!xp): org = 0x40000000, len = 96K
psram3 (w!xp): org = 0x40100000, len = 64K psram3 (w!xp): org = 0x40100000, len = 64K
dsram2_local (w!xp): org = 0xd0000000, len = 96K dsram2_local (w!xp): org = 0xd0000000, len = 96K
dsram2 (w!xp): org = 0x50000000, len = 96K dsram2 (w!xp): org = 0x50000000, len = 96K
psram2 (w!xp): org = 0x50100000, len = 64K psram2 (w!xp): org = 0x50100000, len = 64K
dsram1_local (w!xp): org = 0xd0000000, len = 240K dsram1_local (w!xp): org = 0xd0000000, len = 240K
dsram1 (w!xp): org = 0x60000000, len = 240K dsram1 (w!xp): org = 0x60000000, len = 240K
psram1 (w!xp): org = 0x60100000, len = 64K psram1 (w!xp): org = 0x60100000, len = 64K
dsram0_local (w!xp): org = 0xd0000000, len = 240K dsram0_local (w!xp): org = 0xd0000000, len = 240K
dsram0 (w!xp): org = 0x70000000, len = 240K dsram0 (w!xp): org = 0x70000000, len = 240K
psram0 (w!xp): org = 0x70100000, len = 64K psram0 (w!xp): org = 0x70100000, len = 64K
psram_local (w!xp): org = 0xc0000000, len = 64K psram_local (w!xp): org = 0xc0000000, len = 64K
pfls0 (rx!p): org = 0x80000000, len = 3M pfls0 (rx!p): org = 0x80000000, len = 3M
pfls0_nc (rx!p): org = 0xa0000000, len = 3M pfls0_nc (rx!p): org = 0xa0000000, len = 3M
pfls1 (rx!p): org = 0x80300000, len = 3M pfls1 (rx!p): org = 0x80300000, len = 3M
pfls1_nc (rx!p): org = 0xa0300000, len = 3M pfls1_nc (rx!p): org = 0xa0300000, len = 3M
pfls2 (rx!p): org = 0x80600000, len = 3M pfls2 (rx!p): org = 0x80600000, len = 3M
pfls2_nc (rx!p): org = 0xa0600000, len = 3M pfls2_nc (rx!p): org = 0xa0600000, len = 3M
pfls3 (rx!p): org = 0x80900000, len = 3M pfls3 (rx!p): org = 0x80900000, len = 3M
pfls3_nc (rx!p): org = 0xa0900000, len = 3M pfls3_nc (rx!p): org = 0xa0900000, len = 3M
pfls4 (rx!p): org = 0x80c00000, len = 3M pfls4 (rx!p): org = 0x80c00000, len = 3M
pfls4_nc (rx!p): org = 0xa0c00000, len = 3M pfls4_nc (rx!p): org = 0xa0c00000, len = 3M
pfls5 (rx!p): org = 0x80f00000, len = 1M pfls5 (rx!p): org = 0x80f00000, len = 1M
pfls5_nc (rx!p): org = 0xa0f00000, len = 1M pfls5_nc (rx!p): org = 0xa0f00000, len = 1M
dfls0 (rx!p): org = 0xaf000000, len = 1M dfls0 (rx!p): org = 0xaf000000, len = 1M
ucb (rx!p): org = 0xaf400000, len = 24K ucb (rx!p): org = 0xaf400000, len = 24K
cpu0_dlmu (w!xp): org = 0x90000000, len = 64K cpu0_dlmu (w!xp): org = 0x90000000, len = 64K
cpu0_dlmu_nc (w!xp): org = 0xb0000000, len = 64K cpu0_dlmu_nc (w!xp): org = 0xb0000000, len = 64K
cpu1_dlmu (w!xp): org = 0x90010000, len = 64K cpu1_dlmu (w!xp): org = 0x90010000, len = 64K
cpu1_dlmu_nc (w!xp): org = 0xb0010000, len = 64K cpu1_dlmu_nc (w!xp): org = 0xb0010000, len = 64K
cpu2_dlmu (w!xp): org = 0x90020000, len = 64K cpu2_dlmu (w!xp): org = 0x90020000, len = 64K
cpu2_dlmu_nc (w!xp): org = 0xb0020000, len = 64K cpu2_dlmu_nc (w!xp): org = 0xb0020000, len = 64K
cpu3_dlmu (w!xp): org = 0x90030000, len = 64K cpu3_dlmu (w!xp): org = 0x90030000, len = 64K
cpu3_dlmu_nc (w!xp): org = 0xb0030000, len = 64K cpu3_dlmu_nc (w!xp): org = 0xb0030000, len = 64K
lmuram (w!xp): org = 0x90040000, len = 768K lmuram (w!xp): org = 0x90040000, len = 768K
lmuram_nc (w!xp): org = 0xb0040000, len = 768K lmuram_nc (w!xp): org = 0xb0040000, len = 768K
cpu4_dlmu (w!xp): org = 0x90100000, len = 64K cpu4_dlmu (w!xp): org = 0x90100000, len = 64K
cpu4_dlmu_nc (w!xp): org = 0xb0100000, len = 64K cpu4_dlmu_nc (w!xp): org = 0xb0100000, len = 64K
cpu5_dlmu (w!xp): org = 0x90110000, len = 64K cpu5_dlmu (w!xp): org = 0x90110000, len = 64K
cpu5_dlmu_nc (w!xp): org = 0xb0110000, len = 64K cpu5_dlmu_nc (w!xp): org = 0xb0110000, len = 64K
edmem (w!xp): org = 0x99000000, len = 4M edmem (w!xp): org = 0x99000000, len = 4M
edmem_nc (w!xp): org = 0xb9000000, len = 4M edmem_nc (w!xp): org = 0xb9000000, len = 4M
} }
@ -272,79 +272,79 @@ REGION_ALIAS( default_rom , pfls5)
{ {
CORE_SEC(.ustack) (LCF_DSPR5_START + LCF_USTACK5_OFFSET): CORE_SEC(.ustack) (LCF_DSPR5_START + LCF_USTACK5_OFFSET):
{ PROVIDE(__USTACK5_END = .); . = . + LCF_USTACK5_SIZE; PROVIDE(__USTACK5 = .); } { PROVIDE(__USTACK5_END = .); . = . + LCF_USTACK5_SIZE; PROVIDE(__USTACK5 = .); }
CORE_SEC(.istack) (LCF_DSPR5_START + LCF_ISTACK5_OFFSET): CORE_SEC(.istack) (LCF_DSPR5_START + LCF_ISTACK5_OFFSET):
{ PROVIDE(__ISTACK5_END = .); . = . + LCF_ISTACK5_SIZE; PROVIDE(__ISTACK5 = .); } { PROVIDE(__ISTACK5_END = .); . = . + LCF_ISTACK5_SIZE; PROVIDE(__ISTACK5 = .); }
CORE_SEC(.csa) (LCF_DSPR5_START + LCF_CSA5_OFFSET): CORE_SEC(.csa) (LCF_DSPR5_START + LCF_CSA5_OFFSET):
{ PROVIDE(__CSA5 = .); . = . + LCF_CSA5_SIZE; PROVIDE(__CSA5_END = .); } { PROVIDE(__CSA5 = .); . = . + LCF_CSA5_SIZE; PROVIDE(__CSA5_END = .); }
} }
CORE_ID = CPU4; CORE_ID = CPU4;
SECTIONS SECTIONS
{ {
CORE_SEC(.ustack) (LCF_DSPR4_START + LCF_USTACK4_OFFSET): CORE_SEC(.ustack) (LCF_DSPR4_START + LCF_USTACK4_OFFSET):
{ PROVIDE(__USTACK4_END = .); . = . + LCF_USTACK4_SIZE; PROVIDE(__USTACK4 = .); } { PROVIDE(__USTACK4_END = .); . = . + LCF_USTACK4_SIZE; PROVIDE(__USTACK4 = .); }
CORE_SEC(.istack) (LCF_DSPR4_START + LCF_ISTACK4_OFFSET): CORE_SEC(.istack) (LCF_DSPR4_START + LCF_ISTACK4_OFFSET):
{ PROVIDE(__ISTACK4_END = .); . = . + LCF_ISTACK4_SIZE; PROVIDE(__ISTACK4 = .); } { PROVIDE(__ISTACK4_END = .); . = . + LCF_ISTACK4_SIZE; PROVIDE(__ISTACK4 = .); }
CORE_SEC(.csa) (LCF_DSPR4_START + LCF_CSA4_OFFSET): CORE_SEC(.csa) (LCF_DSPR4_START + LCF_CSA4_OFFSET):
{ PROVIDE(__CSA4 = .); . = . + LCF_CSA4_SIZE; PROVIDE(__CSA4_END = .); } { PROVIDE(__CSA4 = .); . = . + LCF_CSA4_SIZE; PROVIDE(__CSA4_END = .); }
} }
CORE_ID = CPU3; CORE_ID = CPU3;
SECTIONS SECTIONS
{ {
CORE_SEC(.ustack) (LCF_DSPR3_START + LCF_USTACK3_OFFSET): CORE_SEC(.ustack) (LCF_DSPR3_START + LCF_USTACK3_OFFSET):
{ PROVIDE(__USTACK3_END = .); . = . + LCF_USTACK3_SIZE; PROVIDE(__USTACK3 = .); } { PROVIDE(__USTACK3_END = .); . = . + LCF_USTACK3_SIZE; PROVIDE(__USTACK3 = .); }
CORE_SEC(.istack) (LCF_DSPR3_START + LCF_ISTACK3_OFFSET): CORE_SEC(.istack) (LCF_DSPR3_START + LCF_ISTACK3_OFFSET):
{ PROVIDE(__ISTACK3_END = .); . = . + LCF_ISTACK3_SIZE; PROVIDE(__ISTACK3 = .); } { PROVIDE(__ISTACK3_END = .); . = . + LCF_ISTACK3_SIZE; PROVIDE(__ISTACK3 = .); }
CORE_SEC(.csa) (LCF_DSPR3_START + LCF_CSA3_OFFSET): CORE_SEC(.csa) (LCF_DSPR3_START + LCF_CSA3_OFFSET):
{ PROVIDE(__CSA3 = .); . = . + LCF_CSA3_SIZE; PROVIDE(__CSA3_END = .); } { PROVIDE(__CSA3 = .); . = . + LCF_CSA3_SIZE; PROVIDE(__CSA3_END = .); }
} }
CORE_ID = CPU2; CORE_ID = CPU2;
SECTIONS SECTIONS
{ {
CORE_SEC(.ustack) (LCF_DSPR2_START + LCF_USTACK2_OFFSET): CORE_SEC(.ustack) (LCF_DSPR2_START + LCF_USTACK2_OFFSET):
{ PROVIDE(__USTACK2_END = .); . = . + LCF_USTACK2_SIZE; PROVIDE(__USTACK2 = .); } { PROVIDE(__USTACK2_END = .); . = . + LCF_USTACK2_SIZE; PROVIDE(__USTACK2 = .); }
CORE_SEC(.istack) (LCF_DSPR2_START + LCF_ISTACK2_OFFSET): CORE_SEC(.istack) (LCF_DSPR2_START + LCF_ISTACK2_OFFSET):
{ PROVIDE(__ISTACK2_END = .); . = . + LCF_ISTACK2_SIZE; PROVIDE(__ISTACK2 = .); } { PROVIDE(__ISTACK2_END = .); . = . + LCF_ISTACK2_SIZE; PROVIDE(__ISTACK2 = .); }
CORE_SEC(.csa) (LCF_DSPR2_START + LCF_CSA2_OFFSET): CORE_SEC(.csa) (LCF_DSPR2_START + LCF_CSA2_OFFSET):
{ PROVIDE(__CSA2 = .); . = . + LCF_CSA2_SIZE; PROVIDE(__CSA2_END = .); } { PROVIDE(__CSA2 = .); . = . + LCF_CSA2_SIZE; PROVIDE(__CSA2_END = .); }
} }
CORE_ID = CPU1; CORE_ID = CPU1;
SECTIONS SECTIONS
{ {
CORE_SEC(.ustack) (LCF_DSPR1_START + LCF_USTACK1_OFFSET): CORE_SEC(.ustack) (LCF_DSPR1_START + LCF_USTACK1_OFFSET):
{ PROVIDE(__USTACK1_END = .); . = . + LCF_USTACK1_SIZE; PROVIDE(__USTACK1 = .); } { PROVIDE(__USTACK1_END = .); . = . + LCF_USTACK1_SIZE; PROVIDE(__USTACK1 = .); }
CORE_SEC(.istack) (LCF_DSPR1_START + LCF_ISTACK1_OFFSET): CORE_SEC(.istack) (LCF_DSPR1_START + LCF_ISTACK1_OFFSET):
{ PROVIDE(__ISTACK1_END = .); . = . + LCF_ISTACK1_SIZE; PROVIDE(__ISTACK1 = .); } { PROVIDE(__ISTACK1_END = .); . = . + LCF_ISTACK1_SIZE; PROVIDE(__ISTACK1 = .); }
CORE_SEC(.csa) (LCF_DSPR1_START + LCF_CSA1_OFFSET): CORE_SEC(.csa) (LCF_DSPR1_START + LCF_CSA1_OFFSET):
{ PROVIDE(__CSA1 = .); . = . + LCF_CSA1_SIZE; PROVIDE(__CSA1_END = .); } { PROVIDE(__CSA1 = .); . = . + LCF_CSA1_SIZE; PROVIDE(__CSA1_END = .); }
} }
CORE_ID = CPU0; CORE_ID = CPU0;
SECTIONS SECTIONS
{ {
CORE_SEC(.ustack) (LCF_DSPR0_START + LCF_USTACK0_OFFSET): CORE_SEC(.ustack) (LCF_DSPR0_START + LCF_USTACK0_OFFSET):
{ PROVIDE(__USTACK0_END = .); . = . + LCF_USTACK0_SIZE; PROVIDE(__USTACK0 = .); } { PROVIDE(__USTACK0_END = .); . = . + LCF_USTACK0_SIZE; PROVIDE(__USTACK0 = .); }
CORE_SEC(.istack) (LCF_DSPR0_START + LCF_ISTACK0_OFFSET): CORE_SEC(.istack) (LCF_DSPR0_START + LCF_ISTACK0_OFFSET):
{ PROVIDE(__ISTACK0_END = .); . = . + LCF_ISTACK0_SIZE; PROVIDE(__ISTACK0 = .); } { PROVIDE(__ISTACK0_END = .); . = . + LCF_ISTACK0_SIZE; PROVIDE(__ISTACK0 = .); }
CORE_SEC(.csa) (LCF_DSPR0_START + LCF_CSA0_OFFSET): CORE_SEC(.csa) (LCF_DSPR0_START + LCF_CSA0_OFFSET):
{ PROVIDE(__CSA0 = .); . = . + LCF_CSA0_SIZE; PROVIDE(__CSA0_END = .); } { PROVIDE(__CSA0 = .); . = . + LCF_CSA0_SIZE; PROVIDE(__CSA0_END = .); }
} }
/*Fixed memory Allocations for _START*/ /*Fixed memory Allocations for _START*/
CORE_ID = GLOBAL ; CORE_ID = GLOBAL ;
SECTIONS SECTIONS
@ -359,7 +359,7 @@ REGION_ALIAS( default_rom , pfls5)
PROVIDE(__ENABLE_INDIVIDUAL_C_INIT_CPU4 = 0); PROVIDE(__ENABLE_INDIVIDUAL_C_INIT_CPU4 = 0);
PROVIDE(__ENABLE_INDIVIDUAL_C_INIT_CPU5 = 0); PROVIDE(__ENABLE_INDIVIDUAL_C_INIT_CPU5 = 0);
} }
/*Fixed memory Allocations for Trap Vector Table*/ /*Fixed memory Allocations for Trap Vector Table*/
CORE_ID = GLOBAL; CORE_ID = GLOBAL;
SECTIONS SECTIONS
@ -371,7 +371,7 @@ REGION_ALIAS( default_rom , pfls5)
.traptab_tc4 (LCF_TRAPVEC4_START) : { PROVIDE(__TRAPTAB_CPU4 = .); KEEP (*(.traptab_cpu4)); } > pfls4 .traptab_tc4 (LCF_TRAPVEC4_START) : { PROVIDE(__TRAPTAB_CPU4 = .); KEEP (*(.traptab_cpu4)); } > pfls4
.traptab_tc5 (LCF_TRAPVEC5_START) : { PROVIDE(__TRAPTAB_CPU5 = .); KEEP (*(.traptab_cpu5)); } > pfls5 .traptab_tc5 (LCF_TRAPVEC5_START) : { PROVIDE(__TRAPTAB_CPU5 = .); KEEP (*(.traptab_cpu5)); } > pfls5
} }
/*Fixed memory Allocations for _START1 to 5*/ /*Fixed memory Allocations for _START1 to 5*/
CORE_ID = GLOBAL ; CORE_ID = GLOBAL ;
SECTIONS SECTIONS
@ -387,7 +387,7 @@ REGION_ALIAS( default_rom , pfls5)
PROVIDE(__START4 = LCF_STARTPTR_NC_CPU4); PROVIDE(__START4 = LCF_STARTPTR_NC_CPU4);
PROVIDE(__START5 = LCF_STARTPTR_NC_CPU5); PROVIDE(__START5 = LCF_STARTPTR_NC_CPU5);
} }
/*Fixed memory Allocations for Interrupt Vector Table*/ /*Fixed memory Allocations for Interrupt Vector Table*/
SECTIONS SECTIONS
{ {
@ -1949,7 +1949,7 @@ REGION_ALIAS( default_rom , pfls5)
.inttab_tc5_0FE (__INTTAB_CPU5 + 0x1FC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_254)); } .inttab_tc5_0FE (__INTTAB_CPU5 + 0x1FC0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_254)); }
.inttab_tc5_0FF (__INTTAB_CPU5 + 0x1FE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_255)); } .inttab_tc5_0FF (__INTTAB_CPU5 + 0x1FE0) : { . = ALIGN(8) ; KEEP (*(.intvec_tc5_255)); }
} }
/*Fixed memory Allocations for BMHD*/ /*Fixed memory Allocations for BMHD*/
CORE_ID = GLOBAL; CORE_ID = GLOBAL;
SECTIONS SECTIONS
@ -1964,7 +1964,7 @@ REGION_ALIAS( default_rom , pfls5)
.bmhd_2_copy (0xaf401400) : FLAGS(arl) { KEEP (*(.bmhd_2_copy)); } > ucb .bmhd_2_copy (0xaf401400) : FLAGS(arl) { KEEP (*(.bmhd_2_copy)); } > ucb
.bmhd_3_copy (0xaf401600) : FLAGS(arl) { KEEP (*(.bmhd_3_copy)); } > ucb .bmhd_3_copy (0xaf401600) : FLAGS(arl) { KEEP (*(.bmhd_3_copy)); } > ucb
} }
/*Near Abbsolute Addressable Data Sections*/ /*Near Abbsolute Addressable Data Sections*/
/*Near Absolute Data, selectable with patterns and user defined sections*/ /*Near Absolute Data, selectable with patterns and user defined sections*/
CORE_ID = CPU5; CORE_ID = CPU5;
@ -1978,7 +1978,7 @@ REGION_ALIAS( default_rom , pfls5)
*(.zdata_cpu5.*) *(.zdata_cpu5.*)
. = ALIGN(2); . = ALIGN(2);
} > dsram5 AT> pfls0 } > dsram5 AT> pfls0
CORE_SEC(.zbss) (NOLOAD): FLAGS(awz) CORE_SEC(.zbss) (NOLOAD): FLAGS(awz)
{ {
*Ifx_Ssw_Tc5.* (.zbss) *Ifx_Ssw_Tc5.* (.zbss)
@ -1998,7 +1998,7 @@ REGION_ALIAS( default_rom , pfls5)
*(.zdata_cpu4.*) *(.zdata_cpu4.*)
. = ALIGN(2); . = ALIGN(2);
} > dsram4 AT> pfls0 } > dsram4 AT> pfls0
CORE_SEC(.zbss) (NOLOAD): FLAGS(awz) CORE_SEC(.zbss) (NOLOAD): FLAGS(awz)
{ {
*Ifx_Ssw_Tc4.* (.zbss) *Ifx_Ssw_Tc4.* (.zbss)
@ -2009,7 +2009,7 @@ REGION_ALIAS( default_rom , pfls5)
} }
CORE_ID = CPU3; CORE_ID = CPU3;
SECTIONS SECTIONS
{ {
CORE_SEC(.zdata) (LCF_DSPR3_START): FLAGS(awzl) CORE_SEC(.zdata) (LCF_DSPR3_START): FLAGS(awzl)
{ {
*Ifx_Ssw_Tc3.* (.zdata) *Ifx_Ssw_Tc3.* (.zdata)
@ -2018,7 +2018,7 @@ REGION_ALIAS( default_rom , pfls5)
*(.zdata_cpu3.*) *(.zdata_cpu3.*)
. = ALIGN(2); . = ALIGN(2);
} > dsram3 AT> pfls0 } > dsram3 AT> pfls0
CORE_SEC(.zbss) (NOLOAD): FLAGS(awz) CORE_SEC(.zbss) (NOLOAD): FLAGS(awz)
{ {
*Ifx_Ssw_Tc3.* (.zbss) *Ifx_Ssw_Tc3.* (.zbss)
@ -2038,7 +2038,7 @@ REGION_ALIAS( default_rom , pfls5)
*(.zdata_cpu2.*) *(.zdata_cpu2.*)
. = ALIGN(2); . = ALIGN(2);
} > dsram2 AT> pfls0 } > dsram2 AT> pfls0
CORE_SEC(.zbss) (NOLOAD): FLAGS(awz) CORE_SEC(.zbss) (NOLOAD): FLAGS(awz)
{ {
*Ifx_Ssw_Tc2.* (.zbss) *Ifx_Ssw_Tc2.* (.zbss)
@ -2058,7 +2058,7 @@ REGION_ALIAS( default_rom , pfls5)
*(.zdata_cpu1.*) *(.zdata_cpu1.*)
. = ALIGN(2); . = ALIGN(2);
} > dsram1 AT> pfls0 } > dsram1 AT> pfls0
CORE_SEC(.zbss) (NOLOAD): FLAGS(awz) CORE_SEC(.zbss) (NOLOAD): FLAGS(awz)
{ {
*Ifx_Ssw_Tc1.* (.zbss) *Ifx_Ssw_Tc1.* (.zbss)
@ -2078,7 +2078,7 @@ REGION_ALIAS( default_rom , pfls5)
*(.zdata_cpu0.*) *(.zdata_cpu0.*)
. = ALIGN(2); . = ALIGN(2);
} > dsram0 AT> pfls0 } > dsram0 AT> pfls0
CORE_SEC(.zbss) (NOLOAD): FLAGS(awz) CORE_SEC(.zbss) (NOLOAD): FLAGS(awz)
{ {
*Ifx_Ssw_Tc0.* (.zbss) *Ifx_Ssw_Tc0.* (.zbss)
@ -2087,11 +2087,11 @@ REGION_ALIAS( default_rom , pfls5)
*(.zbss_cpu0.*) *(.zbss_cpu0.*)
} > dsram0 } > dsram0
} }
/*Near Absolute Data, selectable by toolchain*/ /*Near Absolute Data, selectable by toolchain*/
CORE_ID = GLOBAL; CORE_ID = GLOBAL;
SECTIONS SECTIONS
{ {
CORE_SEC(.zdata_powerOn) : FLAGS(awzl) CORE_SEC(.zdata_powerOn) : FLAGS(awzl)
{ {
*(.zdata.dsprPowerOnInit.cpu0.32bit) *(.zdata.dsprPowerOnInit.cpu0.32bit)
@ -2099,7 +2099,7 @@ REGION_ALIAS( default_rom , pfls5)
*(.zdata.dsprPowerOnInit.cpu0.8bit) *(.zdata.dsprPowerOnInit.cpu0.8bit)
. = ALIGN(2); . = ALIGN(2);
} > default_ram AT> pfls0 } > default_ram AT> pfls0
CORE_SEC(.zdata) : FLAGS(awzl) CORE_SEC(.zdata) : FLAGS(awzl)
{ {
*(.zdata.dsprInit.cpu0.32bit) *(.zdata.dsprInit.cpu0.32bit)
@ -2110,21 +2110,21 @@ REGION_ALIAS( default_rom , pfls5)
*(.gnu.linkonce.z.*) *(.gnu.linkonce.z.*)
. = ALIGN(2); . = ALIGN(2);
} > default_ram AT> pfls0 } > default_ram AT> pfls0
CORE_SEC(.zbss_powerOn) (NOLOAD) : FLAGS(awz) CORE_SEC(.zbss_powerOn) (NOLOAD) : FLAGS(awz)
{ {
*(.zbss.dsprPowerOnClear.cpu0.32bit) *(.zbss.dsprPowerOnClear.cpu0.32bit)
*(.zbss.dsprPowerOnClear.cpu0.16bit) *(.zbss.dsprPowerOnClear.cpu0.16bit)
*(.zbss.dsprPowerOnClear.cpu0.8bit) *(.zbss.dsprPowerOnClear.cpu0.8bit)
} > default_ram } > default_ram
CORE_SEC(.zbss_noClear) (NOLOAD) : FLAGS(awz) CORE_SEC(.zbss_noClear) (NOLOAD) : FLAGS(awz)
{ {
*(.zbss.dsprNoInit.cpu0.32bit) *(.zbss.dsprNoInit.cpu0.32bit)
*(.zbss.dsprNoInit.cpu0.16bit) *(.zbss.dsprNoInit.cpu0.16bit)
*(.zbss.dsprNoInit.cpu0.8bit) *(.zbss.dsprNoInit.cpu0.8bit)
} > default_ram } > default_ram
CORE_SEC(.zbss) (NOLOAD) : FLAGS(awz) CORE_SEC(.zbss) (NOLOAD) : FLAGS(awz)
{ {
*(.zbss.dsprClearOnInit.cpu0.32bit) *(.zbss.dsprClearOnInit.cpu0.32bit)
@ -2148,14 +2148,14 @@ REGION_ALIAS( default_rom , pfls5)
*(.zlmudata.*) *(.zlmudata.*)
. = ALIGN(2); . = ALIGN(2);
} > cpu0_dlmu AT> pfls0 } > cpu0_dlmu AT> pfls0
CORE_SEC(.zbss) (NOLOAD) : FLAGS(awz) CORE_SEC(.zbss) (NOLOAD) : FLAGS(awz)
{ {
*(.zlmubss) *(.zlmubss)
*(.zlmubss.*) *(.zlmubss.*)
} > cpu0_dlmu } > cpu0_dlmu
} }
/*Near Absolute Const, selectable with patterns and user defined sections*/ /*Near Absolute Const, selectable with patterns and user defined sections*/
CORE_ID = GLOBAL; CORE_ID = GLOBAL;
SECTIONS SECTIONS
@ -2167,7 +2167,7 @@ REGION_ALIAS( default_rom , pfls5)
*(.zrodata_cpu?) *(.zrodata_cpu?)
} > pfls0 } > pfls0
} }
/*Near Absolute Const, selectable by toolchain*/ /*Near Absolute Const, selectable by toolchain*/
CORE_ID = GLOBAL; CORE_ID = GLOBAL;
SECTIONS SECTIONS
@ -2232,13 +2232,13 @@ SECTIONS
*(.a9sdata.*) *(.a9sdata.*)
. = ALIGN(2); . = ALIGN(2);
} > lmuram AT> pfls0 } > lmuram AT> pfls0
CORE_SEC(.sbss4) : CORE_SEC(.sbss4) :
{ {
*(.a9sbss) *(.a9sbss)
*(.a9sbss.*) *(.a9sbss.*)
} > lmuram } > lmuram
_SMALL_DATA4_ = SIZEOF(CORE_SEC(.sdata4)) ? ADDR(CORE_SEC(.sdata4)) : (ADDR(CORE_SEC(.sdata4)) & 0xF0000000) + 32k ; _SMALL_DATA4_ = SIZEOF(CORE_SEC(.sdata4)) ? ADDR(CORE_SEC(.sdata4)) : (ADDR(CORE_SEC(.sdata4)) & 0xF0000000) + 32k ;
__A9_MEM = _SMALL_DATA4_; __A9_MEM = _SMALL_DATA4_;
@ -2248,7 +2248,7 @@ SECTIONS
*(.rodata_a8) *(.rodata_a8)
*(.rodata_a8.*) *(.rodata_a8.*)
} > default_rom } > default_rom
_SMALL_DATA3_ = SIZEOF(CORE_SEC(.sdata3)) ? ADDR(CORE_SEC(.sdata3)) : (ADDR(CORE_SEC(.sdata3)) & 0xF0000000) + 32k ; _SMALL_DATA3_ = SIZEOF(CORE_SEC(.sdata3)) ? ADDR(CORE_SEC(.sdata3)) : (ADDR(CORE_SEC(.sdata3)) & 0xF0000000) + 32k ;
__A8_MEM = _SMALL_DATA3_; __A8_MEM = _SMALL_DATA3_;
} }
@ -2267,7 +2267,7 @@ SECTIONS
*(.data_cpu5.*) *(.data_cpu5.*)
. = ALIGN(2); . = ALIGN(2);
} > dsram5 AT> pfls0 } > dsram5 AT> pfls0
CORE_SEC(.bss) (NOLOAD): FLAGS(aw) CORE_SEC(.bss) (NOLOAD): FLAGS(aw)
{ {
*Ifx_Ssw_Tc5.* (.bss) *Ifx_Ssw_Tc5.* (.bss)
@ -2275,7 +2275,7 @@ SECTIONS
*(.bss_cpu5) *(.bss_cpu5)
*(.bss_cpu5.*) *(.bss_cpu5.*)
} > dsram5 } > dsram5
/*DLMU5 Sections*/ /*DLMU5 Sections*/
CORE_SEC(.lmudata) : FLAGS(awl) CORE_SEC(.lmudata) : FLAGS(awl)
{ {
@ -2283,10 +2283,10 @@ SECTIONS
*(.lmudata_cpu5.*) *(.lmudata_cpu5.*)
. = ALIGN(2); . = ALIGN(2);
} > cpu5_dlmu AT> pfls0 } > cpu5_dlmu AT> pfls0
CORE_SEC(.lmubss) : FLAGS(aw) CORE_SEC(.lmubss) : FLAGS(aw)
{ {
*(.lmubss_cpu5) *(.lmubss_cpu5)
*(.lmubss_cpu5.*) *(.lmubss_cpu5.*)
} > cpu5_dlmu } > cpu5_dlmu
} }
@ -2302,7 +2302,7 @@ SECTIONS
*(.data_cpu4.*) *(.data_cpu4.*)
. = ALIGN(2); . = ALIGN(2);
} > dsram4 AT> pfls0 } > dsram4 AT> pfls0
CORE_SEC(.bss) (NOLOAD): FLAGS(aw) CORE_SEC(.bss) (NOLOAD): FLAGS(aw)
{ {
*Ifx_Ssw_Tc4.* (.bss) *Ifx_Ssw_Tc4.* (.bss)
@ -2310,7 +2310,7 @@ SECTIONS
*(.bss_cpu4) *(.bss_cpu4)
*(.bss_cpu4.*) *(.bss_cpu4.*)
} > dsram4 } > dsram4
/*DLMU4 Sections*/ /*DLMU4 Sections*/
CORE_SEC(.lmudata) : FLAGS(awl) CORE_SEC(.lmudata) : FLAGS(awl)
{ {
@ -2318,7 +2318,7 @@ SECTIONS
*(.lmudata_cpu4.*) *(.lmudata_cpu4.*)
. = ALIGN(2); . = ALIGN(2);
} > cpu4_dlmu AT> pfls0 } > cpu4_dlmu AT> pfls0
CORE_SEC(.lmubss) : FLAGS(aw) CORE_SEC(.lmubss) : FLAGS(aw)
{ {
*(.lmubss_cpu4) *(.lmubss_cpu4)
@ -2337,7 +2337,7 @@ SECTIONS
*(.data_cpu3.*) *(.data_cpu3.*)
. = ALIGN(2); . = ALIGN(2);
} > dsram3 AT> pfls0 } > dsram3 AT> pfls0
CORE_SEC(.bss) (NOLOAD): FLAGS(aw) CORE_SEC(.bss) (NOLOAD): FLAGS(aw)
{ {
*Ifx_Ssw_Tc3.* (.bss) *Ifx_Ssw_Tc3.* (.bss)
@ -2345,7 +2345,7 @@ SECTIONS
*(.bss_cpu3) *(.bss_cpu3)
*(.bss_cpu3.*) *(.bss_cpu3.*)
} > dsram3 } > dsram3
/*DLMU3 Sections*/ /*DLMU3 Sections*/
CORE_SEC(.lmudata) : FLAGS(awl) CORE_SEC(.lmudata) : FLAGS(awl)
{ {
@ -2353,7 +2353,7 @@ SECTIONS
*(.lmudata_cpu3.*) *(.lmudata_cpu3.*)
. = ALIGN(2); . = ALIGN(2);
} > cpu3_dlmu AT> pfls0 } > cpu3_dlmu AT> pfls0
CORE_SEC(.lmubss) : FLAGS(aw) CORE_SEC(.lmubss) : FLAGS(aw)
{ {
*(.lmubss_cpu3) *(.lmubss_cpu3)
@ -2372,7 +2372,7 @@ SECTIONS
*(.data_cpu2.*) *(.data_cpu2.*)
. = ALIGN(2); . = ALIGN(2);
} > dsram2 AT> pfls0 } > dsram2 AT> pfls0
CORE_SEC(.bss) (NOLOAD): FLAGS(aw) CORE_SEC(.bss) (NOLOAD): FLAGS(aw)
{ {
*Ifx_Ssw_Tc2.* (.bss) *Ifx_Ssw_Tc2.* (.bss)
@ -2380,7 +2380,7 @@ SECTIONS
*(.bss_cpu2) *(.bss_cpu2)
*(.bss_cpu2.*) *(.bss_cpu2.*)
} > dsram2 } > dsram2
/*DLMU2 Sections*/ /*DLMU2 Sections*/
CORE_SEC(.lmudata) : FLAGS(awl) CORE_SEC(.lmudata) : FLAGS(awl)
{ {
@ -2388,7 +2388,7 @@ SECTIONS
*(.lmudata_cpu2.*) *(.lmudata_cpu2.*)
. = ALIGN(2); . = ALIGN(2);
} > cpu2_dlmu AT> pfls0 } > cpu2_dlmu AT> pfls0
CORE_SEC(.lmubss) : FLAGS(aw) CORE_SEC(.lmubss) : FLAGS(aw)
{ {
*(.lmubss_cpu2) *(.lmubss_cpu2)
@ -2407,7 +2407,7 @@ SECTIONS
*(.data_cpu1.*) *(.data_cpu1.*)
. = ALIGN(2); . = ALIGN(2);
} > dsram1 AT> pfls0 } > dsram1 AT> pfls0
CORE_SEC(.bss) (NOLOAD): FLAGS(aw) CORE_SEC(.bss) (NOLOAD): FLAGS(aw)
{ {
*Ifx_Ssw_Tc1.* (.bss) *Ifx_Ssw_Tc1.* (.bss)
@ -2415,7 +2415,7 @@ SECTIONS
*(.bss_cpu1) *(.bss_cpu1)
*(.bss_cpu1.*) *(.bss_cpu1.*)
} > dsram1 } > dsram1
/*DLMU1 Sections*/ /*DLMU1 Sections*/
CORE_SEC(.lmudata) : FLAGS(awl) CORE_SEC(.lmudata) : FLAGS(awl)
{ {
@ -2423,7 +2423,7 @@ SECTIONS
*(.lmudata_cpu1.*) *(.lmudata_cpu1.*)
. = ALIGN(2); . = ALIGN(2);
} > cpu1_dlmu AT> pfls0 } > cpu1_dlmu AT> pfls0
CORE_SEC(.lmubss) : FLAGS(aw) CORE_SEC(.lmubss) : FLAGS(aw)
{ {
*(.lmubss_cpu1) *(.lmubss_cpu1)
@ -2442,7 +2442,7 @@ SECTIONS
*(.data_cpu0.*) *(.data_cpu0.*)
. = ALIGN(2); . = ALIGN(2);
} > dsram0 AT> pfls0 } > dsram0 AT> pfls0
CORE_SEC(.bss) (NOLOAD): FLAGS(aw) CORE_SEC(.bss) (NOLOAD): FLAGS(aw)
{ {
*Ifx_Ssw_Tc0.* (.bss) *Ifx_Ssw_Tc0.* (.bss)
@ -2450,7 +2450,7 @@ SECTIONS
*(.bss_cpu0) *(.bss_cpu0)
*(.bss_cpu0.*) *(.bss_cpu0.*)
} > dsram0 } > dsram0
/*DLMU0 Sections*/ /*DLMU0 Sections*/
CORE_SEC(.lmudata) : FLAGS(awl) CORE_SEC(.lmudata) : FLAGS(awl)
{ {
@ -2458,7 +2458,7 @@ SECTIONS
*(.lmudata_cpu0.*) *(.lmudata_cpu0.*)
. = ALIGN(2); . = ALIGN(2);
} > cpu0_dlmu AT> pfls0 } > cpu0_dlmu AT> pfls0
CORE_SEC(.lmubss) : FLAGS(aw) CORE_SEC(.lmubss) : FLAGS(aw)
{ {
*(.lmubss_cpu0) *(.lmubss_cpu0)
@ -2476,7 +2476,7 @@ SECTIONS
*(.bss.farDsprNoInit.cpu0.16bit) *(.bss.farDsprNoInit.cpu0.16bit)
*(.bss.farDsprNoInit.cpu0.8bit) *(.bss.farDsprNoInit.cpu0.8bit)
} > default_ram } > default_ram
CORE_SEC(.data) : FLAGS(awl) CORE_SEC(.data) : FLAGS(awl)
{ {
*(.data.farDsprInit.cpu0.32bit) *(.data.farDsprInit.cpu0.32bit)
@ -2487,7 +2487,7 @@ SECTIONS
*(.gnu.linkonce.d.*) *(.gnu.linkonce.d.*)
. = ALIGN(2); . = ALIGN(2);
} > default_ram AT> pfls0 } > default_ram AT> pfls0
CORE_SEC(.bss) (NOLOAD) : FLAGS(aw) CORE_SEC(.bss) (NOLOAD) : FLAGS(aw)
{ {
*(.bss.farDsprClearOnInit.cpu0.32bit) *(.bss.farDsprClearOnInit.cpu0.32bit)
@ -2497,7 +2497,7 @@ SECTIONS
*(.bss.*) *(.bss.*)
*(.gnu.linkonce.b.*) *(.gnu.linkonce.b.*)
} > default_ram } > default_ram
.heap : FLAGS(aw) .heap : FLAGS(aw)
{ {
. = ALIGN(4); . = ALIGN(4);
@ -2505,14 +2505,14 @@ SECTIONS
. += LCF_HEAP_SIZE; . += LCF_HEAP_SIZE;
__HEAP_END = .; __HEAP_END = .;
} > default_ram } > default_ram
CORE_SEC(.lmudata) : FLAGS(awl) CORE_SEC(.lmudata) : FLAGS(awl)
{ {
*(.lmudata) *(.lmudata)
*(.lmudata.*) *(.lmudata.*)
. = ALIGN(2); . = ALIGN(2);
} > lmuram AT> pfls0 } > lmuram AT> pfls0
CORE_SEC(.lmubss) : FLAGS(aw) CORE_SEC(.lmubss) : FLAGS(aw)
{ {
*(.lmubss) *(.lmubss)
@ -2690,7 +2690,7 @@ SECTIONS
*(.text_cpu0) *(.text_cpu0)
*(.text_cpu0.*) *(.text_cpu0.*)
} > pfls0 } > pfls0
/* /*
* Code executed before calling main extra section for C++ constructor init * Code executed before calling main extra section for C++ constructor init
* -------------------------Start----------------------------------------- * -------------------------Start-----------------------------------------
@ -2702,9 +2702,9 @@ SECTIONS
KEEP(*(.init*)) KEEP(*(.init*))
PROVIDE(__init_end = .); PROVIDE(__init_end = .);
. = ALIGN(8); . = ALIGN(8);
} > pfls0 } > pfls0
.fini : .fini :
{ {
PROVIDE(__fini_start = .); PROVIDE(__fini_start = .);
@ -2713,7 +2713,7 @@ SECTIONS
PROVIDE(__fini_end = .); PROVIDE(__fini_end = .);
. = ALIGN(8); . = ALIGN(8);
} > pfls0 } > pfls0
/* /*
* Code executed before calling main extra section for C++ constructor init * Code executed before calling main extra section for C++ constructor init
* -------------------------End----------------------------------------- * -------------------------End-----------------------------------------

2
boards/tricore/tc3xx/tc397/scripts/Lcf_Tasking_Tricore_Tc.lsl → boards/tricore/tc397/a2g-tc397-5v-tft/scripts/Lcf_Tasking_Tricore_Tc.lsl
View file

@ -1,5 +1,5 @@
/**************************************************************************** /****************************************************************************
* boards/tricore/tc3xx/tc397/scripts/Lcf_Tasking_Tricore_Tc.lsl * boards/tricore/tc397/a2g-tc397-5v-tft/scripts/Lcf_Tasking_Tricore_Tc.lsl
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
* *

2
boards/tricore/tc3xx/tc397/scripts/Make.defs → boards/tricore/tc397/a2g-tc397-5v-tft/scripts/Make.defs
View file

@ -1,5 +1,5 @@
############################################################################ ############################################################################
# boards/tricore/tc3xx/tc397/scripts/Make.defs # boards/tricore/tc397/a2g-tc397-5v-tft/scripts/Make.defs
# #
# SPDX-License-Identifier: Apache-2.0 # SPDX-License-Identifier: Apache-2.0
# #

2
boards/tricore/tc3xx/tc397/src/CMakeLists.txt → boards/tricore/tc397/a2g-tc397-5v-tft/src/CMakeLists.txt
View file

@ -1,5 +1,5 @@
# ############################################################################## # ##############################################################################
# boards/tricore/tc3xx/tc397/src/CMakeLists.txt # boards/tricore/tc397/a2g-tc397-5v-tft/src/CMakeLists.txt
# #
# SPDX-License-Identifier: Apache-2.0 # SPDX-License-Identifier: Apache-2.0
# #

2
boards/tricore/tc3xx/tc397/src/Makefile → boards/tricore/tc397/a2g-tc397-5v-tft/src/Makefile
View file

@ -1,5 +1,5 @@
############################################################################ ############################################################################
# boards/tricore/tc3xx/tc397/src/Makefile # boards/tricore/tc397/a2g-tc397-5v-tft/src/Makefile
# #
# SPDX-License-Identifier: Apache-2.0 # SPDX-License-Identifier: Apache-2.0
# #

8
boards/tricore/tc3xx/tc397/src/tc397.h → boards/tricore/tc397/a2g-tc397-5v-tft/src/tc397.h
View file

@ -1,5 +1,5 @@
/**************************************************************************** /****************************************************************************
* boards/tricore/tc3xx/tc397/src/tc397.h * boards/tricore/tc397/a2g-tc397-5v-tft/src/tc397.h
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
* *
@ -20,8 +20,8 @@
* *
****************************************************************************/ ****************************************************************************/
#ifndef __BOARDS_TRICORE_TC3XX_TC397_SRC_TC397_H #ifndef __BOARDS_TRICORE_TC397_A2G_TC397_5V_TFT_SRC_TC397_H
#define __BOARDS_TRICORE_TC3XX_TC397_SRC_TC397_H #define __BOARDS_TRICORE_TC397_A2G_TC397_5V_TFT_SRC_TC397_H
/**************************************************************************** /****************************************************************************
* Included Files * Included Files
@ -62,4 +62,4 @@ int tc397_bringup(void);
#endif #endif
#endif /* __ASSEMBLY__ */ #endif /* __ASSEMBLY__ */
#endif /* __BOARDS_TRICORE_TC3XX_TC397_SRC_TC397_H */ #endif /* __BOARDS_TRICORE_TC397_A2G_TC397_5V_TFT_SRC_TC397_H */

2
boards/tricore/tc3xx/tc397/src/tc397_appinit.c → boards/tricore/tc397/a2g-tc397-5v-tft/src/tc397_appinit.c
View file

@ -1,5 +1,5 @@
/**************************************************************************** /****************************************************************************
* boards/tricore/tc3xx/tc397/src/tc397_appinit.c * boards/tricore/tc397/a2g-tc397-5v-tft/src/tc397_appinit.c
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
* *

2
boards/tricore/tc3xx/tc397/src/tc397_boardinit.c → boards/tricore/tc397/a2g-tc397-5v-tft/src/tc397_boardinit.c
View file

@ -1,5 +1,5 @@
/**************************************************************************** /****************************************************************************
* boards/tricore/tc3xx/tc397/src/tc397_boardinit.c * boards/tricore/tc397/a2g-tc397-5v-tft/src/tc397_boardinit.c
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
* *

2
boards/tricore/tc3xx/tc397/src/tc397_bringup.c → boards/tricore/tc397/a2g-tc397-5v-tft/src/tc397_bringup.c
View file

@ -1,5 +1,5 @@
/**************************************************************************** /****************************************************************************
* boards/tricore/tc3xx/tc397/src/tc397_bringup.c * boards/tricore/tc397/a2g-tc397-5v-tft/src/tc397_bringup.c
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
* *