diff --git a/configs/Kconfig b/configs/Kconfig index 156e1d3225..b6bd245944 100644 --- a/configs/Kconfig +++ b/configs/Kconfig @@ -910,7 +910,7 @@ config ARCH_BOARD_TEENSY_20 config ARCH_BOARD_TEENSY_3X bool "PJRC Teensy++ 3.1 board" - depends on ARCH_CHIP_MK20DX256VLH7 + depends on ARCH_CHIP_MK20DX256VLH7 || ARCH_CHIP_MK20DX128VLH5 select ARCH_HAVE_LEDS ---help--- This is the port of NuttX to the PJRC Teensy++ 2.0 board. This board is @@ -929,7 +929,7 @@ config ARCH_BOARD_TEENSY_3X This board configuration can also be used with the older Teensy-3.0. The Teensy-3.0 has the same schematic (although some pins are not used on the Teensy-3.0). the primary difference is that the Teensy 3.0 has a - MK30DX128VLH5 with slightly less capability. + MK20DX128VLH5 with slightly less capability. config ARCH_BOARD_TEENSY_LC bool "Teensy LC" diff --git a/configs/sam4s-xplained-pro/Kconfig b/configs/sam4s-xplained-pro/Kconfig index b3f327cf94..e867199956 100644 --- a/configs/sam4s-xplained-pro/Kconfig +++ b/configs/sam4s-xplained-pro/Kconfig @@ -20,5 +20,4 @@ config SAM4S_XPLAINED_PRO_CPULOAD_TIMER_DEVPATH default "/dev/tc0" depends on TIMER && SCHED_CPULOAD && SCHED_CPULOAD_EXTCLK - endif diff --git a/configs/teensy-3.x/Kconfig b/configs/teensy-3.x/Kconfig index ae2bf31307..9f4275d690 100644 --- a/configs/teensy-3.x/Kconfig +++ b/configs/teensy-3.x/Kconfig @@ -2,3 +2,11 @@ # For a description of the syntax of this configuration file, # see misc/tools/kconfig-language.txt. # + +if ARCH_BOARD_TEENSY_3X + +config TEENSY_3X_OVERCLOCK + bool "Overclock" + default n + +endif diff --git a/configs/teensy-3.x/README.txt b/configs/teensy-3.x/README.txt index 94b320b4e8..d9279161c3 100644 --- a/configs/teensy-3.x/README.txt +++ b/configs/teensy-3.x/README.txt @@ -13,17 +13,17 @@ README This board configuration can also be used with the older Teensy-3.0. The Teensy-3.0 has the same schematic (although some pins are not used on the Teensy-3.0). The primary difference is that the Teensy 3.0 has a - MK30DX128VLH5 with slightly less capability. There are many difference - between the MK30DX256VLH7 and the MK30DX128VLH5 but the basic differences + MK20DX128VLH5 with slightly less capability. There are many difference + between the MK30DX256VLH7 and the MK20DX128VLH5 but the basic differences that effect how you configure NuttX are: --------------- -------------- -------------- --------------------------- Feature Teensy 3.0 Teensy 3.1 CONFIGURATION --------------- -------------- -------------- --------------------------- Processor - Core MK20DX128VLH5 MK20DX256VLH7 CONFIG_ARCH_CHIP_xyz + Core MK20DX128VLH5 MK20DX256VLH7 CONFIG_ARCH_CHIP_MK20DX128VLH5 Rated Speed 48 MHz 72 MHz Settings in include/board.h - Overclockable 96 MHz 96 MHz Settings in include/board.h + Overclockable 96 MHz 96 MHz CONFIG_TEENSY_3X_OVERCLOCK Flash Memory 128 KB 256 KB See scripts/flash.ld SRAM 16 KB 64 KB See scripts/flash.ld and set CONFIG_RAM_SIZE=??? diff --git a/configs/teensy-3.x/include/board.h b/configs/teensy-3.x/include/board.h index 2a3cbb94b0..79ae4151f6 100644 --- a/configs/teensy-3.x/include/board.h +++ b/configs/teensy-3.x/include/board.h @@ -61,75 +61,73 @@ * produce a 2MHz reference clock to the PLL. The rated speed is 72MHz, but can * be overclocked at 96MHz * + * 48MHz (rated 50MHz) + * + * PLL Input frequency: PLLIN = REFCLK/PRDIV = 16MHz/1 = 16MHz + * PLL Output frequency: PLLOUT = PLLIN*VDIV = 8Mhz*3 = 72MHz + * MCG Frequency: PLLOUT = 48MHz + * * 72MHz * * PLL Input frequency: PLLIN = REFCLK/PRDIV = 16MHz/2 = 8MHz * PLL Output frequency: PLLOUT = PLLIN*VDIV = 8Mhz*9 = 72MHz - * MCG Frequency: PLLOUT = 96MHz + * MCG Frequency: PLLOUT = 72MHz * - * 96MHz + * 96MHz (Overclocked) * PLL Input frequency: PLLIN = REFCLK/PRDIV = 16MHz/1 = 16MHz * PLL Output frequency: PLLOUT = PLLIN*VDIV = 16Mhz*6 = 96MHz * MCG Frequency: PLLOUT = 96MHz */ -#define BOARD_PRDIV 2 /* PLL External Reference Divider */ -#define BOARD_VDIV 24 /* PLL VCO Divider (frequency multiplier) */ +#if defiend(CONFIG_TEENSY_3X_OVERCLOCK) +/* PLL Configuration */ + +# define BOARD_PRDIV 1 /* PLL External Reference Divider */ +# define BOARD_VDIV 6 /* PLL VCO Divider (frequency multiplier) */ + +/* SIM CLKDIV1 dividers */ + +# define BOARD_OUTDIV1 1 /* Core = MCG, 96MHz */ +# define BOARD_OUTDIV2 2 /* Bus = MCG/2, 48MHz */ +# define BOARD_OUTDIV3 2 /* FlexBus = MCG/2, 48MHz */ +# define BOARD_OUTDIV4 4 /* Flash clock = MCG/4, 24MHz */ + +#elif defined(CONFIG_ARCH_CHIP_MK20DX256VLH7) + +/* PLL Configuration */ + +# define BOARD_PRDIV 2 /* PLL External Reference Divider */ +# define BOARD_VDIV 9 /* PLL VCO Divider (frequency multiplier) */ + +/* SIM CLKDIV1 dividers */ + +# define BOARD_OUTDIV1 1 /* Core = MCG, 72MHz */ +# define BOARD_OUTDIV2 2 /* Bus = MCG/2, 36MHz */ +# define BOARD_OUTDIV3 2 /* FlexBus = MCG/2, 36MHz */ +# define BOARD_OUTDIV4 3 /* Flash clock = MCG/3, 72MHz */ + +#elif defined(CONFIG_ARCH_CHIP_MK20DX128VLH5) +/* PLL Configuration */ + +# define BOARD_PRDIV 1 /* PLL External Reference Divider */ +# define BOARD_VDIV 3 /* PLL VCO Divider (frequency multiplier) */ + +/* SIM CLKDIV1 dividers */ + +# define BOARD_OUTDIV1 1 /* Core = MCG, 48MHz */ +# define BOARD_OUTDIV2 1 /* Bus = MCG/1, 48MHz */ +# define BOARD_OUTDIV3 1 /* FlexBus = MCG/1, 48MHz */ +# define BOARD_OUTDIV4 2 /* Flash clock = MCG/2, 24MHz */ +#endif #define BOARD_PLLIN_FREQ (BOARD_EXTAL_FREQ / BOARD_PRDIV) #define BOARD_PLLOUT_FREQ (BOARD_PLLIN_FREQ * BOARD_VDIV) #define BOARD_MCG_FREQ BOARD_PLLOUT_FREQ -/* SIM CLKDIV1 dividers */ - -#define BOARD_OUTDIV1 1 /* Core = MCG, 96MHz */ -#define BOARD_OUTDIV2 2 /* Bus = MCG/2, 48MHz */ -#define BOARD_OUTDIV3 2 /* FlexBus = MCG/2, 48MHz */ -#define BOARD_OUTDIV4 4 /* Flash clock = MCG/4, 24MHz */ - -#define BOARD_CORECLK_FREQ (BOARD_MCG_FREQ / BOARD_OUTDIV1) -#define BOARD_BUS_FREQ (BOARD_MCG_FREQ / BOARD_OUTDIV2) -#define BOARD_FLEXBUS_FREQ (BOARD_MCG_FREQ / BOARD_OUTDIV3) -#define BOARD_FLASHCLK_FREQ (BOARD_MCG_FREQ / BOARD_OUTDIV4) - -/* SDHC clocking ********************************************************************/ - -/* SDCLK configurations corresponding to various modes of operation. Formula is: - * - * SDCLK frequency = (base clock) / (prescaler * divisor) - * - * The SDHC module is always configure configured so that the core clock is the base - * clock. - */ - -/* Identification mode: 400KHz = 96MHz / ( 16 * 15) */ - -#define BOARD_SDHC_IDMODE_PRESCALER SDHC_SYSCTL_SDCLKFS_DIV16 -#define BOARD_SDHC_IDMODE_DIVISOR SDHC_SYSCTL_DVS_DIV(15) - -/* MMC normal mode: 16MHz = 96MHz / (2 * 3) */ - -#define BOARD_SDHC_MMCMODE_PRESCALER SDHC_SYSCTL_SDCLKFS_DIV2 -#define BOARD_SDHC_MMCMODE_DIVISOR SDHC_SYSCTL_DVS_DIV(3) - -/* SD normal mode (1-bit): 16MHz = 96MHz / (2 * 3) */ - -#define BOARD_SDHC_SD1MODE_PRESCALER SDHC_SYSCTL_SDCLKFS_DIV2 -#define BOARD_SDHC_SD1MODE_DIVISOR SDHC_SYSCTL_DVS_DIV(3) - -/* SD normal mode (4-bit): 24MHz = 96MHz / (2 * 2) (with DMA) - * SD normal mode (4-bit): 16MHz = 96MHz / (2 * 3) (no DMA) - */ - -#ifdef CONFIG_SDIO_DMA -# define BOARD_SDHC_SD4MODE_PRESCALER SDHC_SYSCTL_SDCLKFS_DIV2 -# define BOARD_SDHC_SD4MODE_DIVISOR SDHC_SYSCTL_DVS_DIV(2) -#else -//# define BOARD_SDHC_SD4MODE_PRESCALER SDHC_SYSCTL_SDCLKFS_DIV2 -//# define BOARD_SDHC_SD4MODE_DIVISOR SDHC_SYSCTL_DVS_DIV(3) -# define BOARD_SDHC_SD4MODE_PRESCALER SDHC_SYSCTL_SDCLKFS_DIV16 -# define BOARD_SDHC_SD4MODE_DIVISOR SDHC_SYSCTL_DVS_DIV(15) -#endif +#define BOARD_CORECLK_FREQ (BOARD_MCG_FREQ / BOARD_OUTDIV1) +#define BOARD_BUS_FREQ (BOARD_MCG_FREQ / BOARD_OUTDIV2) +#define BOARD_FLEXBUS_FREQ (BOARD_MCG_FREQ / BOARD_OUTDIV3) +#define BOARD_FLASHCLK_FREQ (BOARD_MCG_FREQ / BOARD_OUTDIV4) /* LED definitions ******************************************************************/ /* A single LED is available driven by PTC5. The LED is grounded so bringing PTC5 diff --git a/configs/teensy-3.x/nsh/defconfig b/configs/teensy-3.x/nsh/defconfig index 01afcab87f..b76d8e2f12 100644 --- a/configs/teensy-3.x/nsh/defconfig +++ b/configs/teensy-3.x/nsh/defconfig @@ -135,6 +135,14 @@ CONFIG_ARMV7M_TOOLCHAIN_GNU_EABIW=y # # Kinetis Configuration Options # +# CONFIG_ARCH_CHIP_MK20DN32VLH5 is not set +# CONFIG_ARCH_CHIP_MK20DX32VLH5 is not set +# CONFIG_ARCH_CHIP_MK20DN64VLH5 is not set +# CONFIG_ARCH_CHIP_MK20DX64VLH5 is not set +# CONFIG_ARCH_CHIP_MK20DN128VLH5 is not set +# CONFIG_ARCH_CHIP_MK20DX128VLH5 is not set +# CONFIG_ARCH_CHIP_MK20DX64VLH7 is not set +# CONFIG_ARCH_CHIP_MK20DX128VLH7 is not set CONFIG_ARCH_CHIP_MK20DX256VLH7=y # CONFIG_ARCH_CHIP_MK40N512VLQ100 is not set # CONFIG_ARCH_CHIP_MK40N512VMD100 is not set @@ -278,6 +286,7 @@ CONFIG_NSH_MMCSDMINOR=0 # # Board-Specific Options # +# CONFIG_TEENSY_3X_OVERCLOCK is not set # CONFIG_LIB_BOARDCTL is not set #