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arch/stm32h7: add RPTUN support

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This commit is contained in:
raiden00pl 2023-08-21 09:47:09 +02:00 • committed by Xiang Xiao
parent a6c25f657d
commit 2fffd7dad6
10 changed files with 701 additions and 39 deletions
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10
arch/arm/src/stm32h7/CMakeLists.txt
View file

@ -45,6 +45,10 @@ if(CONFIG_STM32H7_HSEM)
list(APPEND SRCS stm32_hsem.c)
endif()
if(CONFIG_RPTUN)
list(APPEND SRCS stm32_rptun.c)
endif()
if(CONFIG_SCHED_TICKLESS)
list(APPEND SRCS stm32_tickless.c)
else()
@ -55,8 +59,12 @@ if(CONFIG_STM32H7_ONESHOT)
list(APPEND SRCS stm32_oneshot.c stm32_oneshot_lowerhalf.c)
endif()
if(CONFIG_ARM_MPU)
list(APPEND SRCS stm32_mpuinit.c)
endif()
if(CONFIG_BUILD_PROTECTED)
list(APPEND SRCS stm32_userspace.c stm32_mpuinit.c)
list(APPEND SRCS stm32_userspace.c)
endif()
if(CONFIG_ARMV7M_DTCM)

5
arch/arm/src/stm32h7/Kconfig
View file

@ -522,13 +522,13 @@ endif
config STM32H7_CORTEXM7_FLASH_SIZE
int "Flash reserved for M7 core"
default 1048576 if STM32_CORTEXM4_ENABLED || ARCH_CHIP_STM32H7_CORTEXM4
default 1048576 if STM32H7_CORTEXM4_ENABLED || ARCH_CHIP_STM32H7_CORTEXM4
default 2097152
config STM32H7_CORTEXM7_SHMEM
bool
select ARM_MPU if ARCH_CHIP_STM32H7_CORTEXM7
default y if STM32H7_CORTEXM4_ENABLED
default y if STM32H7_CORTEXM4_ENABLED || ARCH_CHIP_STM32H7_CORTEXM4
default n
config STM32H7_SHMEM_SRAM3
@ -2156,6 +2156,7 @@ config STM32H7_CUSTOM_CLOCKCONFIG
config STM32H7_SRAM4EXCLUDE
bool "Exclude SRAM4 from the heap"
default y if RPTUN
default n
---help---
Exclude SRAM4 from the HEAP in order to use this 64 KB region

10
arch/arm/src/stm32h7/Make.defs
View file

@ -37,6 +37,10 @@ ifeq ($(CONFIG_STM32H7_HSEM),y)
CHIP_CSRCS += stm32_hsem.c
endif
ifeq ($(CONFIG_RPTUN),y)
CHIP_CSRCS += stm32_rptun.c
endif
# Required STM32H7 files
CHIP_CSRCS += stm32_allocateheap.c stm32_exti_gpio.c stm32_gpio.c stm32_irq.c
@ -53,8 +57,12 @@ ifeq ($(CONFIG_STM32H7_ONESHOT),y)
CHIP_CSRCS += stm32_oneshot.c stm32_oneshot_lowerhalf.c
endif
ifeq ($(CONFIG_ARM_MPU),y)
CHIP_CSRCS += stm32_mpuinit.c
endif
ifeq ($(CONFIG_BUILD_PROTECTED),y)
CHIP_CSRCS += stm32_userspace.c stm32_mpuinit.c
CHIP_CSRCS += stm32_userspace.c
endif
ifeq ($(CONFIG_ARMV7M_DTCM),y)

4
arch/arm/src/stm32h7/stm32_allocateheap.c
View file

@ -57,7 +57,7 @@
#if defined(CONFIG_ARCH_CHIP_STM32H7_CORTEXM7) && \
!defined(CONFIG_STM32H7_CORTEXM4_ENABLED)
/* Configuration for M7 core and M4 core support disabled */
/* Configuration for M7 core when M4 core support disabled */
/* At startup the kernel will invoke arm_addregion() so that platform code
* may register available memories for use as part of system heap.
@ -117,7 +117,7 @@
#elif defined(CONFIG_ARCH_CHIP_STM32H7_CORTEXM7) && \
defined(CONFIG_STM32H7_CORTEXM4_ENABLED)
/* Configuration for M7 core and M4 core support enabled */
/* Configuration for M7 core when M4 core support enabled */
# define SRAM_START STM32_AXISRAM_BASE
# define SRAM_END (SRAM_START + STM32H7_SRAM_SIZE)

43
arch/arm/src/stm32h7/stm32_mpuinit.c
View file

@ -27,12 +27,28 @@
#include <assert.h>
#include <sys/param.h>
#include <nuttx/userspace.h>
#ifdef CONFIG_BUILD_PROTECTED
# include <nuttx/userspace.h>
#endif
#include "mpu.h"
#include "hardware/stm32_memorymap.h"
#include "stm32_mpuinit.h"
#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_ARM_MPU)
#ifdef CONFIG_ARM_MPU
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#ifdef CONFIG_RPTUN
# ifdef CONFIG_STM32H7_SHMEM_SRAM3
# define STM32_SHMEM_BASE STM32_SRAM3_BASE
# define STM32_SHMEM_SIZE STM32H7_SRAM3_SIZE
# else
# error missing shmem MPU configuration
# endif
#endif
/****************************************************************************
* Public Functions
@ -42,18 +58,25 @@
* Name: stm32_mpuinitialize
*
* Description:
* Configure the MPU to permit user-space access to only restricted SAM3U
* resources.
* Configure the MPU.
*
* If PROTECTED build:
* - permit user-space access to only restricted STM32 resources.
*
* If RPTUN:
* - configure shared memory as non-cacheable
*
****************************************************************************/
void stm32_mpuinitialize(void)
{
#ifdef CONFIG_BUILD_PROTECTED
uintptr_t datastart = MIN(USERSPACE->us_datastart, USERSPACE->us_bssstart);
uintptr_t dataend = MAX(USERSPACE->us_dataend, USERSPACE->us_bssend);
DEBUGASSERT(USERSPACE->us_textend >= USERSPACE->us_textstart &&
dataend >= datastart);
#endif
/* Show MPU information */
@ -63,18 +86,27 @@ void stm32_mpuinitialize(void)
mpu_reset();
#ifdef CONFIG_BUILD_PROTECTED
/* Configure user flash and SRAM space */
mpu_user_flash(USERSPACE->us_textstart,
USERSPACE->us_textend - USERSPACE->us_textstart);
mpu_user_intsram(datastart, dataend - datastart);
#endif
#ifdef CONFIG_RPTUN
/* Configure shared memory as non-cacheable */
mpu_priv_shmem((uintptr_t)STM32_SHMEM_BASE, STM32_SHMEM_SIZE);
#endif
/* Then enable the MPU */
mpu_control(true, false, true);
}
#ifdef CONFIG_BUILD_PROTECTED
/****************************************************************************
* Name: stm32_mpu_uheap
*
@ -89,5 +121,6 @@ void stm32_mpu_uheap(uintptr_t start, size_t size)
{
mpu_user_intsram(start, size);
}
#endif
#endif /* CONFIG_BUILD_PROTECTED && CONFIG_ARM_MPU */
#endif /* CONFIG_ARM_MPU */

26
arch/arm/src/stm32h7/stm32_mpuinit.h
View file

@ -22,7 +22,6 @@
#define __ARCH_ARM_SRC_STM32H7_STM32_MPUINIT_H
/****************************************************************************
* Name: stm32_mpuinitialize
* Included Files
****************************************************************************/
@ -31,28 +30,8 @@
#include <sys/types.h>
#include <stdint.h>
/****************************************************************************
* Name: stm32_mpuinitialize
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Name: stm32_mpuinitialize
* Public Types
****************************************************************************/
/****************************************************************************
* Name: stm32_mpuinitialize
* Inline Functions
****************************************************************************/
#ifndef __ASSEMBLY__
/****************************************************************************
* Name: stm32_mpuinitialize
* Public Data
****************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
@ -70,12 +49,11 @@ extern "C"
* Name: stm32_mpuinitialize
*
* Description:
* Configure the MPU to permit user-space access to only unrestricted
* STM32H7 resources.
* Configure the MPU.
*
****************************************************************************/
#ifdef CONFIG_BUILD_PROTECTED
#ifdef CONFIG_ARM_MPU
void stm32_mpuinitialize(void);
#else
# define stm32_mpuinitialize()

568
arch/arm/src/stm32h7/stm32_rptun.c Normal file
View file

@ -0,0 +1,568 @@
/****************************************************************************
* arch/arm/src/stm32h7/stm32_rptun.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <debug.h>
#include <nuttx/nuttx.h>
#include <nuttx/kthread.h>
#include <nuttx/rptun/rptun.h>
#include <nuttx/semaphore.h>
#include "arm_internal.h"
#include "stm32_hsem.h"
#include "stm32_dualcore.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#ifdef CONFIG_ARCH_CHIP_STM32H7_CORTEXM7
# if defined(CONFIG_ARMV7M_DCACHE) && !defined(CONFIG_OPENAMP_CACHE)
# error CONFIG_OPENAMP_CACHE must be set
# endif
# if defined(CONFIG_ARMV7M_DCACHE) && !defined(CONFIG_ARM_MPU)
# erro CONFIG_ARM_MPU must be enabled
# endif
#endif
/* Vring configuration parameters */
#define VRINGS (2) /* Number of vrings */
#define VRING_ALIGN (8) /* Vring alignment */
#define VRING_NR (8) /* Number of descriptors */
#define VRING_SIZE (512) /* Size of one descriptor */
#ifdef CONFIG_STM32H7_SHMEM_SRAM3
/* Use 32kB of the SRAM3 as a shared memory */
# define VRING_SHMEM STM32_SRAM3_BASE
#else
# error missing shmem SRAM configuration
#endif
#define VRING0_NOTIFYID (RSC_NOTIFY_ID_ANY) /* Vring0 id */
#define VRING1_NOTIFYID (RSC_NOTIFY_ID_ANY) /* Vring1 id */
/* HSEM configuration */
/* 0 reserved for synchronisation */
#define RPTUN_HSEM_CHAN_MASTER_RX (1) /* RX for master is ready */
#define RPTUN_HSEM_CHAN_SLAVE_RX (2) /* RX for slave is ready */
#define RPTUN_HSEM_CHAN_SLAVE_RESET (3)
#define RPTUN_HSEM_CHAN_SLAVE_PANIC (4)
/****************************************************************************
* Private Types
****************************************************************************/
/* STM32 rptun sharred memory */
struct stm32_rptun_shmem_s
{
volatile uintptr_t base;
struct rptun_rsc_s rsc;
};
/* STM32 rptun device */
struct stm32_rptun_dev_s
{
struct rptun_dev_s rptun;
rptun_callback_t callback;
void *arg;
bool master;
struct stm32_rptun_shmem_s *shmem;
char cpuname[RPMSG_NAME_SIZE + 1];
char shmemname[RPMSG_NAME_SIZE + 1];
};
/****************************************************************************
* Private Function Prototypes
****************************************************************************/
static const char *stm32_rptun_get_cpuname(struct rptun_dev_s *dev);
static const char *stm32_rptun_get_firmware(struct rptun_dev_s *dev);
static const struct rptun_addrenv_s *
stm32_rptun_get_addrenv(struct rptun_dev_s *dev);
static struct rptun_rsc_s *
stm32_rptun_get_resource(struct rptun_dev_s *dev);
static bool stm32_rptun_is_autostart(struct rptun_dev_s *dev);
static bool stm32_rptun_is_master(struct rptun_dev_s *dev);
static int stm32_rptun_start(struct rptun_dev_s *dev);
static int stm32_rptun_stop(struct rptun_dev_s *dev);
static int stm32_rptun_notify(struct rptun_dev_s *dev, uint32_t vqid);
static int stm32_rptun_register_callback(struct rptun_dev_s *dev,
rptun_callback_t callback,
void *arg);
#ifdef CONFIG_ARCH_CHIP_STM32H7_CORTEXM7
static void stm32_rptun_reset(struct rptun_dev_s *dev, int value);
static void stm32_rptun_panic(struct rptun_dev_s *dev);
#endif
/****************************************************************************
* Private Data
****************************************************************************/
static const struct rptun_ops_s g_stm32_rptun_ops =
{
.get_cpuname = stm32_rptun_get_cpuname,
.get_firmware = stm32_rptun_get_firmware,
.get_addrenv = stm32_rptun_get_addrenv,
.get_resource = stm32_rptun_get_resource,
.is_autostart = stm32_rptun_is_autostart,
.is_master = stm32_rptun_is_master,
.start = stm32_rptun_start,
.stop = stm32_rptun_stop,
.notify = stm32_rptun_notify,
.register_callback = stm32_rptun_register_callback,
#ifdef CONFIG_ARCH_CHIP_STM32H7_CORTEXM7
.reset = stm32_rptun_reset,
.panic = stm32_rptun_panic
#endif
};
#ifdef CONFIG_ARCH_CHIP_STM32H7_CORTEXM7
/* Allocate shared memory on the CM7 core side */
static struct stm32_rptun_shmem_s g_shmem __attribute__((section(".shmem")));
#endif
struct stm32_rptun_dev_s g_rptun_dev;
static sem_t g_stm32_rx_sig = SEM_INITIALIZER(0);
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: stm32_rptun_get_cpuname
****************************************************************************/
static const char *stm32_rptun_get_cpuname(struct rptun_dev_s *dev)
{
struct stm32_rptun_dev_s *priv = container_of(dev,
struct stm32_rptun_dev_s, rptun);
return priv->cpuname;
}
/****************************************************************************
* Name: stm32_rptun_get_firmware
****************************************************************************/
static const char *stm32_rptun_get_firmware(struct rptun_dev_s *dev)
{
return NULL;
}
/****************************************************************************
* Name: stm32_rptun_get_addrenv
****************************************************************************/
static const struct rptun_addrenv_s *
stm32_rptun_get_addrenv(struct rptun_dev_s *dev)
{
return NULL;
}
/****************************************************************************
* Name: stm32_rptun_get_resource
****************************************************************************/
static struct rptun_rsc_s *
stm32_rptun_get_resource(struct rptun_dev_s *dev)
{
struct stm32_rptun_dev_s *priv = container_of(dev,
struct stm32_rptun_dev_s, rptun);
struct rptun_rsc_s *rsc;
if (priv->shmem != NULL)
{
return &priv->shmem->rsc;
}
#ifdef CONFIG_ARCH_CHIP_STM32H7_CORTEXM7
priv->shmem = &g_shmem;
#else
priv->shmem = (struct stm32_rptun_shmem_s *)VRING_SHMEM;
#endif
if (priv->master)
{
/* Perform initial setup */
rsc = &priv->shmem->rsc;
rsc->rsc_tbl_hdr.ver = 1;
rsc->rsc_tbl_hdr.num = 1;
rsc->rsc_tbl_hdr.reserved[0] = 0;
rsc->rsc_tbl_hdr.reserved[1] = 0;
rsc->offset[0] = offsetof(struct rptun_rsc_s,
rpmsg_vdev);
rsc->rpmsg_vdev.type = RSC_VDEV;
rsc->rpmsg_vdev.id = VIRTIO_ID_RPMSG;
rsc->rpmsg_vdev.dfeatures = 1 << VIRTIO_RPMSG_F_NS
| 1 << VIRTIO_RPMSG_F_ACK
| 1 << VIRTIO_RPMSG_F_BUFSZ;
rsc->rpmsg_vdev.config_len = sizeof(struct fw_rsc_config);
rsc->rpmsg_vdev.num_of_vrings = VRINGS;
rsc->rpmsg_vring0.align = VRING_ALIGN;
rsc->rpmsg_vring0.num = VRING_NR;
rsc->rpmsg_vring0.notifyid = VRING0_NOTIFYID;
rsc->rpmsg_vring1.align = VRING_ALIGN;
rsc->rpmsg_vring1.num = VRING_NR;
rsc->rpmsg_vring1.notifyid = VRING1_NOTIFYID;
rsc->config.r2h_buf_size = VRING_SIZE;
rsc->config.h2r_buf_size = VRING_SIZE;
priv->shmem->base = (uintptr_t)priv->shmem;
}
else
{
/* TODO: use HSEM */
while (priv->shmem->base == 0)
{
usleep(100);
}
}
return &priv->shmem->rsc;
}
/****************************************************************************
* Name: stm32_rptun_is_autostart
****************************************************************************/
static bool stm32_rptun_is_autostart(struct rptun_dev_s *dev)
{
return true;
}
/****************************************************************************
* Name: stm32_rptun_is_master
****************************************************************************/
static bool stm32_rptun_is_master(struct rptun_dev_s *dev)
{
struct stm32_rptun_dev_s *priv = container_of(dev,
struct stm32_rptun_dev_s, rptun);
return priv->master;
}
/****************************************************************************
* Name: stm32_rptun_start
****************************************************************************/
static int stm32_rptun_start(struct rptun_dev_s *dev)
{
return 0;
}
/****************************************************************************
* Name: stm32_rptun_stop
****************************************************************************/
static int stm32_rptun_stop(struct rptun_dev_s *dev)
{
return 0;
}
/****************************************************************************
* Name: stm32_rptun_notify
****************************************************************************/
static int stm32_rptun_notify(struct rptun_dev_s *dev, uint32_t vqid)
{
#ifdef CONFIG_ARCH_CHIP_STM32H7_CORTEXM7
/* Notify slave that RX is ready */
stm32_hsem_signal(RPTUN_HSEM_CHAN_SLAVE_RX);
#else
/* Notify master that RX is ready */
stm32_hsem_signal(RPTUN_HSEM_CHAN_MASTER_RX);
#endif
return 0;
}
/****************************************************************************
* Name: stm32_rptun_register_callback
****************************************************************************/
static int stm32_rptun_register_callback(struct rptun_dev_s *dev,
rptun_callback_t callback,
void *arg)
{
struct stm32_rptun_dev_s *priv = container_of(dev,
struct stm32_rptun_dev_s, rptun);
priv->callback = callback;
priv->arg = arg;
return 0;
}
#ifdef CONFIG_ARCH_CHIP_STM32H7_CORTEXM7
/****************************************************************************
* Name: stm32_rptun_reset
****************************************************************************/
static void stm32_rptun_reset(struct rptun_dev_s *dev, int value)
{
if (value == 0)
{
/* Soft reset */
stm32_hsem_signal(RPTUN_HSEM_CHAN_SLAVE_RESET);
}
}
/****************************************************************************
* Name: stm32_rptun_panic
****************************************************************************/
static void stm32_rptun_panic(struct rptun_dev_s *dev)
{
stm32_hsem_signal(RPTUN_HSEM_CHAN_SLAVE_PANIC);
}
#endif
#ifdef CONFIG_ARCH_CHIP_STM32H7_CORTEXM7
/****************************************************************************
* Name: stm32_hsem_master_callback
****************************************************************************/
static void stm32_hsem_master_callback(uint8_t id, void *arg)
{
_info("Rptun HSEM master %d\n", id);
switch (id)
{
case RPTUN_HSEM_CHAN_MASTER_RX:
{
nxsem_post(&g_stm32_rx_sig);
break;
}
default:
{
DEBUGASSERT(0);
}
}
}
/****************************************************************************
* Name: stm32_rptun_hsem_cm7
****************************************************************************/
static void stm32_rptun_hsem_cm7(struct stm32_rptun_dev_s *dev)
{
DEBUGASSERT(dev);
stm32_hsem_subscribe(RPTUN_HSEM_CHAN_MASTER_RX,
stm32_hsem_master_callback,
dev);
}
#else
/****************************************************************************
* Name: stm32_hsem_slave_callback
****************************************************************************/
static void stm32_hsem_slave_callback(uint8_t id, void *arg)
{
_info("Rptun HSEM slave %d\n", id);
switch (id)
{
case RPTUN_HSEM_CHAN_SLAVE_RX:
{
nxsem_post(&g_stm32_rx_sig);
break;
}
case RPTUN_HSEM_CHAN_SLAVE_RESET:
{
/* REVISIT: It's not possible to reset a single core.
* What can we do here ?
*/
break;
}
case RPTUN_HSEM_CHAN_SLAVE_PANIC:
{
PANIC();
}
default:
{
DEBUGASSERT(0);
}
}
}
/****************************************************************************
* Name: stm32_rptun_hsem_cm4
****************************************************************************/
static void stm32_rptun_hsem_cm4(struct stm32_rptun_dev_s *dev)
{
DEBUGASSERT(dev);
stm32_hsem_subscribe(RPTUN_HSEM_CHAN_SLAVE_RX,
stm32_hsem_slave_callback,
dev);
stm32_hsem_subscribe(RPTUN_HSEM_CHAN_SLAVE_RESET,
stm32_hsem_slave_callback,
dev);
stm32_hsem_subscribe(RPTUN_HSEM_CHAN_SLAVE_PANIC,
stm32_hsem_slave_callback,
dev);
}
#endif
/****************************************************************************
* Name: stm32_rptun_thread
****************************************************************************/
static int stm32_rptun_thread(int argc, char *argv[])
{
struct stm32_rptun_dev_s *dev = &g_rptun_dev;
while (1)
{
if (dev->callback != NULL)
{
dev->callback(dev->arg, RPTUN_NOTIFY_ALL);
}
nxsem_wait(&g_stm32_rx_sig);
}
return 0;
}
/****************************************************************************
* Public Functions
****************************************************************************/
int stm32_rptun_init(const char *shmemname, const char *cpuname)
{
struct stm32_rptun_dev_s *dev = &g_rptun_dev;
int ret = OK;
/* Initialize HSEM */
stm32_hsem_init();
#ifdef CONFIG_ARCH_CHIP_STM32H7_CORTEXM7
/* The CM7 core always master */
memset(&g_shmem, 0, sizeof(struct stm32_rptun_shmem_s));
dev->master = true;
#else
dev->master = false;
#endif
/* Configure HSEM */
#ifdef CONFIG_ARCH_CHIP_STM32H7_CORTEXM7
stm32_rptun_hsem_cm7(dev);
#else
stm32_rptun_hsem_cm4(dev);
#endif
/* Configure device */
dev->rptun.ops = &g_stm32_rptun_ops;
strncpy(dev->cpuname, cpuname, RPMSG_NAME_SIZE);
strncpy(dev->shmemname, shmemname, RPMSG_NAME_SIZE);
ret = rptun_initialize(&dev->rptun);
if (ret < 0)
{
_err("ERROR: rptun_initialize failed %d!\n", ret);
goto errout;
}
/* Create rptun RX thread */
ret = kthread_create("stm32-rptun", CONFIG_RPTUN_PRIORITY,
CONFIG_RPTUN_STACKSIZE, stm32_rptun_thread, NULL);
if (ret < 0)
{
_err("ERROR: kthread_create failed %d\n", ret);
}
errout:
return ret;
}
/****************************************************************************
* Name: up_addrenv_va_to_pa
*
* Description:
* This is needed by openamp/libmetal/lib/system/nuttx/io.c:78. The
* physical memory is mapped as virtual.
*
* Input Parameters:
* va_
*
* Returned Value:
* va
*
****************************************************************************/
uintptr_t up_addrenv_va_to_pa(void *va)
{
return (uintptr_t)va;
}
/****************************************************************************
* Name: up_addrenv_pa_to_va
*
* Description:
* This is needed by openamp/libmetal/lib/system/nuttx/io.c. The
* physical memory is mapped as virtual.
*
* Input Parameters:
* pa
*
* Returned Value:
* pa
*
****************************************************************************/
void *up_addrenv_pa_to_va(uintptr_t pa)
{
return (void *)pa;
}

61
arch/arm/src/stm32h7/stm32_rptun.h Normal file
View file

@ -0,0 +1,61 @@
/****************************************************************************
* arch/arm/src/stm32h7/stm32_rptun.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32H7_STM32_RPTUN_H
#define __ARCH_ARM_SRC_STM32H7_STM32_RPTUN_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#ifndef __ASSEMBLY__
/****************************************************************************
* Public Data
****************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: stm32_rptun_init
****************************************************************************/
int stm32_rptun_init(const char *shmemname, const char *cpuname);
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_STM32H7_STM32_RPTUN_H */

9
arch/arm/src/stm32h7/stm32_start.c
View file

@ -36,6 +36,9 @@
#include "barriers.h"
#include "nvic.h"
#include "mpu.h"
#ifdef CONFIG_ARM_MPU
# include "stm32_mpuinit.h"
#endif
#include "stm32_rcc.h"
#include "stm32_userspace.h"
@ -282,6 +285,12 @@ void __start(void)
#ifdef CONFIG_BUILD_PROTECTED
stm32_userspace();
#endif
#ifdef CONFIG_ARM_MPU
/* Configure the MPU */
stm32_mpuinitialize();
#endif
showprogress('E');
/* Then start NuttX */

4
arch/arm/src/stm32h7/stm32_userspace.c
View file

@ -87,10 +87,6 @@ void stm32_userspace(void)
{
*dest++ = *src++;
}
/* Configure the MPU to permit user-space access to its FLASH and RAM */
stm32_mpuinitialize();
}
#endif /* CONFIG_BUILD_PROTECTED */