From 31f691e9edce0105aa7fc3482b6cce0686e41dfa Mon Sep 17 00:00:00 2001 From: Jari Nippula Date: Wed, 12 Feb 2025 09:42:02 +0200 Subject: [PATCH] arch/risc-v/src/mpfs/mpfs_coremmc: MPFS_FPGA_FIC0_CLK defined as config value --- arch/risc-v/src/mpfs/Kconfig | 6 ++++++ arch/risc-v/src/mpfs/mpfs_coremmc.c | 2 +- 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/arch/risc-v/src/mpfs/Kconfig b/arch/risc-v/src/mpfs/Kconfig index 442a098da3..a364ba7859 100644 --- a/arch/risc-v/src/mpfs/Kconfig +++ b/arch/risc-v/src/mpfs/Kconfig @@ -397,6 +397,12 @@ config MPFS_COREMMC_WRCOMPLETE_IRQNUM design, select CONFIG_MMCSD_SDIOWAIT_WRCOMPLETE and configure the correct IRQ line here. +config MPFS_FPGA_FIC0_CLK_FREQ + int "FIC0 clk freq" + default 125000000 + ---help--- + Frequency of FPGA FIC0 clock. + config MPFS_IHC_CLIENT bool "IHC slave" depends on RPTUN && !MPFS_BOOTLOADER diff --git a/arch/risc-v/src/mpfs/mpfs_coremmc.c b/arch/risc-v/src/mpfs/mpfs_coremmc.c index 276a510097..d8d260d080 100644 --- a/arch/risc-v/src/mpfs/mpfs_coremmc.c +++ b/arch/risc-v/src/mpfs/mpfs_coremmc.c @@ -125,7 +125,7 @@ /* Clocks and timing */ -#define MPFS_FPGA_FIC0_CLK (125000000) +#define MPFS_FPGA_FIC0_CLK (CONFIG_MPFS_FPGA_FIC0_CLK_FREQ) #define COREMMC_CMDTIMEOUT (100000) #define COREMMC_LONGTIMEOUT (100000000)