From 381d3fe64f4da2b09f12bd8f0cd2d1f07d86b3d3 Mon Sep 17 00:00:00 2001 From: Ramin Seyed-Moussavi Date: Sun, 9 Feb 2025 17:19:54 +0100 Subject: [PATCH] arch/arm/max326xx: add max32690 icc updates Add updates for MAX32690 Instruction Cache Controller to enhance device support in NuttX architecture. --- arch/arm/src/max326xx/Make.defs | 7 +- arch/arm/src/max326xx/hardware/max326_icc.h | 18 ++- .../max326_icc.c => max32660/max32660_icc.c} | 6 +- arch/arm/src/max326xx/max32690/max32690_icc.c | 127 ++++++++++++++++++ 4 files changed, 151 insertions(+), 7 deletions(-) rename arch/arm/src/max326xx/{common/max326_icc.c => max32660/max32660_icc.c} (95%) create mode 100644 arch/arm/src/max326xx/max32690/max32690_icc.c diff --git a/arch/arm/src/max326xx/Make.defs b/arch/arm/src/max326xx/Make.defs index 4eefa10b01..764248a996 100644 --- a/arch/arm/src/max326xx/Make.defs +++ b/arch/arm/src/max326xx/Make.defs @@ -29,7 +29,12 @@ include armv7-m/Make.defs CHIP_CSRCS = max326_start.c max326_irq.c max326_clrpend.c ifeq ($(CONFIG_MAX326XX_ICC),y) -CHIP_CSRCS += max326_icc.c +ifeq ($(CONFIG_ARCH_FAMILY_MAX32660),y) + CHIP_CSRCS += max32660_icc.c +endif +ifeq ($(CONFIG_ARCH_FAMILY_MAX32690),y) + CHIP_CSRCS += max32690_icc.c +endif endif ifeq ($(CONFIG_RTC_DRIVER),y) diff --git a/arch/arm/src/max326xx/hardware/max326_icc.h b/arch/arm/src/max326xx/hardware/max326_icc.h index fad7c927f4..9a517d80f9 100644 --- a/arch/arm/src/max326xx/hardware/max326_icc.h +++ b/arch/arm/src/max326xx/hardware/max326_icc.h @@ -43,10 +43,20 @@ /* Register Addresses *******************************************************/ -#define MAX326_ICC_ID (MAX326_ICC_BASE + MAX326_ICC_ID_OFFSET) -#define MAX326_ICC_MEMCFG (MAX326_ICC_BASE + MAX326_ICC_MEMCFG_OFFSET) -#define MAX326_ICC_CTRLSTAT (MAX326_ICC_BASE + MAX326_ICC_CTRLSTAT_OFFSET) -#define MAX326_ICC_INVDTALL (MAX326_ICC_BASE + MAX326_ICC_INVDTALL_OFFSET) +/* The MAX32690 has two ICC controllers because it includes a + * second integrated RISC-V core. + */ +#if defined(CONFIG_ARCH_FAMILY_MAX32690) + #define MAX326_ICC0_ID (MAX326_ICC0_BASE + MAX326_ICC_ID_OFFSET) + #define MAX326_ICC0_MEMCFG (MAX326_ICC0_BASE + MAX326_ICC_MEMCFG_OFFSET) + #define MAX326_ICC0_CTRLSTAT (MAX326_ICC0_BASE + MAX326_ICC_CTRLSTAT_OFFSET) + #define MAX326_ICC0_INVDTALL (MAX326_ICC0_BASE + MAX326_ICC_INVDTALL_OFFSET) +#else + #define MAX326_ICC_ID (MAX326_ICC_BASE + MAX326_ICC_ID_OFFSET) + #define MAX326_ICC_MEMCFG (MAX326_ICC_BASE + MAX326_ICC_MEMCFG_OFFSET) + #define MAX326_ICC_CTRLSTAT (MAX326_ICC_BASE + MAX326_ICC_CTRLSTAT_OFFSET) + #define MAX326_ICC_INVDTALL (MAX326_ICC_BASE + MAX326_ICC_INVDTALL_OFFSET) +#endif /* Register Bit-field Definitions *******************************************/ diff --git a/arch/arm/src/max326xx/common/max326_icc.c b/arch/arm/src/max326xx/max32660/max32660_icc.c similarity index 95% rename from arch/arm/src/max326xx/common/max326_icc.c rename to arch/arm/src/max326xx/max32660/max32660_icc.c index dd9e540f73..4f78ddc867 100644 --- a/arch/arm/src/max326xx/common/max326_icc.c +++ b/arch/arm/src/max326xx/max32660/max32660_icc.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/max326xx/common/max326_icc.c + * arch/arm/src/max326xx/max32660/max32660_icc.c * * SPDX-License-Identifier: Apache-2.0 * @@ -57,11 +57,13 @@ void max326_icc_enable(bool enable) max326_icc_enableclk(); + putreg32(1, MAX326_ICC_INVDTALL); + /* Enable the cache and wait for it to become ready */ + putreg32(ICC_CTRLSTAT_ENABLE, MAX326_ICC_CTRLSTAT); do { - putreg32(ICC_CTRLSTAT_ENABLE, MAX326_ICC_CTRLSTAT); regval = getreg32(MAX326_ICC_CTRLSTAT); } while ((regval & ICC_CTRLSTAT_READY) == 0); diff --git a/arch/arm/src/max326xx/max32690/max32690_icc.c b/arch/arm/src/max326xx/max32690/max32690_icc.c new file mode 100644 index 0000000000..3dd6cc1ffd --- /dev/null +++ b/arch/arm/src/max326xx/max32690/max32690_icc.c @@ -0,0 +1,127 @@ +/**************************************************************************** + * arch/arm/src/max326xx/max32690/max32690_icc.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include "arm_internal.h" +#include "hardware/max326_icc.h" +#include "max326_periphclks.h" +#include "max326_icc.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: max326_icc_enable + * + * Description: + * Enables or disables the instruction cache. + * The MAX32690 actually has two cache controllers. + * Support for the RISC-V core will be added later. + * + ****************************************************************************/ + +void max326_icc_enable(bool enable) +{ + uint32_t regval; + + if (enable) + { + /* Enable ICC peripheral clocking */ + + max326_syscache_enableclk(); + + putreg32(1, MAX326_ICC0_INVDTALL); + + /* Enable the cache and wait for it to become ready */ + + putreg32(ICC_CTRLSTAT_ENABLE, MAX326_ICC0_CTRLSTAT); + do + { + regval = getreg32(MAX326_ICC0_CTRLSTAT); + } + while ((regval & ICC_CTRLSTAT_READY) == 0); + } + else + { + /* Disable the cache */ + + putreg32(0, MAX326_ICC0_CTRLSTAT); + + /* Disable clocking to the ICC peripheral */ + + max326_syscache_disableclk(); + } +} + +/**************************************************************************** + * Name: max326_icc_invalidate + * + * Description: + * Invalidate the instruction cache + * + ****************************************************************************/ + +void max326_icc_invalidate(void) +{ + /* Any write to the INVDTALL register will invalidate the entire cache. */ + + putreg32(1, MAX326_ICC0_INVDTALL); + + /* Wait for the cache to become ready again */ + + while ((getreg32(MAX326_ICC0_CTRLSTAT) & ICC_CTRLSTAT_READY) == 0) + { + } +} + +/**************************************************************************** + * Name: up_addrenv_coherent + * + * Description: + * Flush D-Cache and invalidate I-Cache in preparation for a change in + * address environments. This should immediately precede a call to + * up_addrenv_select(); + * + * Input Parameters: + * addrenv - Describes the address environment to be made coherent. + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_ADDRENV +int up_addrenv_coherent(const arch_addrenv_t *addrenv) +{ + max326_icc_invalidate(); +} +#endif