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stm32: fix IWDG and WWDG debug mode stop for STM32L15XX

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This commit is contained in:
Juha Niskanen 2017-04-03 07:45:09 -06:00 • committed by Gregory Nutt
parent ee4a8336ce
commit 3a6bd901e4
2 changed files with 11 additions and 11 deletions
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12
arch/arm/src/stm32/stm32_iwdg.c
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@ -634,8 +634,8 @@ static int stm32_settimeout(FAR struct watchdog_lowerhalf_s *lower,
* Name: stm32_iwdginitialize
*
* Description:
* Initialize the IWDG watchdog time. The watchdog timer is initialized and
* registers as 'devpath. The initial state of the watchdog time is
* Initialize the IWDG watchdog timer. The watchdog timer is initialized and
* registers as 'devpath'. The initial state of the watchdog timer is
* disabled.
*
* Input Parameters:
@ -665,7 +665,7 @@ void stm32_iwdginitialize(FAR const char *devpath, uint32_t lsifreq)
priv->started = false;
/* Make sure that the LSI oscillator is enabled. NOTE: The LSI oscillator
* is enabled here but is not disabled by this file (because this file does
* is enabled here but is not disabled by this file, because this file does
* not know the global usage of the oscillator. Any clock management
* logic (say, as part of a power management scheme) needs handle other
* LSI controls outside of this file.
@ -685,9 +685,9 @@ void stm32_iwdginitialize(FAR const char *devpath, uint32_t lsifreq)
(void)watchdog_register(devpath, (FAR struct watchdog_lowerhalf_s *)priv);
/* When the microcontroller enters debug mode (Cortex™-M4F core halted),
/* When the microcontroller enters debug mode (Cortex-M4F core halted),
* the IWDG counter either continues to work normally or stops, depending
* on DBG_WIDG_STOP configuration bit in DBG module.
* on DBG_IWDG_STOP configuration bit in DBG module.
*/
#if defined(CONFIG_STM32_JTAG_FULL_ENABLE) || \
@ -695,7 +695,7 @@ void stm32_iwdginitialize(FAR const char *devpath, uint32_t lsifreq)
defined(CONFIG_STM32_JTAG_SW_ENABLE)
{
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F30XX) || \
defined(CONFIG_STM32_STM32F40XX)
defined(CONFIG_STM32_STM32F40XX) || defined(CONFIG_STM32_STM32L15XX)
uint32_t cr = getreg32(STM32_DBGMCU_APB1_FZ);
cr |= DBGMCU_APB1_IWDGSTOP;
putreg32(cr, STM32_DBGMCU_APB1_FZ);

10
arch/arm/src/stm32/stm32_wwdg.c
View file

@ -734,8 +734,8 @@ static int stm32_ioctl(FAR struct watchdog_lowerhalf_s *lower, int cmd,
* Name: stm32_wwdginitialize
*
* Description:
* Initialize the WWDG watchdog time. The watchdog timer is initialized and
* registers as 'devpath. The initial state of the watchdog time is
* Initialize the WWDG watchdog timer. The watchdog timer is initialized and
* registers as 'devpath'. The initial state of the watchdog timer is
* disabled.
*
* Input Parameters:
@ -753,7 +753,7 @@ void stm32_wwdginitialize(FAR const char *devpath)
wdinfo("Entry: devpath=%s\n", devpath);
/* NOTE we assume that clocking to the IWDG has already been provided by
/* NOTE we assume that clocking to the WWDG has already been provided by
* the RCC initialization logic.
*/
@ -780,7 +780,7 @@ void stm32_wwdginitialize(FAR const char *devpath)
(void)watchdog_register(devpath, (FAR struct watchdog_lowerhalf_s *)priv);
/* When the microcontroller enters debug mode (Cortex<EFBFBD>-M4F core halted),
/* When the microcontroller enters debug mode (Cortex-M core halted),
* the WWDG counter either continues to work normally or stops, depending
* on DBG_WWDG_STOP configuration bit in DBG module.
*/
@ -790,7 +790,7 @@ void stm32_wwdginitialize(FAR const char *devpath)
defined(CONFIG_STM32_JTAG_SW_ENABLE)
{
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F30XX) || \
defined(CONFIG_STM32_STM32F40XX)
defined(CONFIG_STM32_STM32F40XX) || defined(CONFIG_STM32_STM32L15XX)
uint32_t cr = getreg32(STM32_DBGMCU_APB1_FZ);
cr |= DBGMCU_APB1_WWDGSTOP;
putreg32(cr, STM32_DBGMCU_APB1_FZ);