From 3c1c29f2c4bb675ecb14d2ee72364209d33e0bc1 Mon Sep 17 00:00:00 2001 From: Xiang Xiao Date: Tue, 20 Sep 2022 08:14:31 +0800 Subject: [PATCH] arch: move non arm g_current_regs defintion to common place to avoid the code duplicaiton Signed-off-by: Xiang Xiao --- arch/arm/src/a1x/a1x_irq.c | 16 ----------- arch/arm/src/am335x/am335x_irq.c | 12 -------- arch/arm/src/c5471/c5471_irq.c | 13 --------- arch/arm/src/common/arm_initialize.c | 12 ++++++++ arch/arm/src/cxd56xx/cxd56_irq.c | 16 ----------- arch/arm/src/dm320/dm320_irq.c | 16 ----------- arch/arm/src/efm32/efm32_irq.c | 14 +--------- arch/arm/src/eoss3/eoss3_irq.c | 16 ----------- arch/arm/src/gd32f4/gd32f4xx_irq.c | 16 ----------- arch/arm/src/imx1/imx_irq.c | 28 ------------------- arch/arm/src/imx6/imx_irq.c | 16 ----------- arch/arm/src/imxrt/imxrt_irq.c | 16 ----------- arch/arm/src/kinetis/kinetis_irq.c | 16 ----------- arch/arm/src/kl/kl_irq.c | 20 ------------- arch/arm/src/lc823450/lc823450_irq.c | 10 ------- arch/arm/src/lc823450/lc823450_start.c | 4 --- arch/arm/src/lpc17xx_40xx/lpc17_40_irq.c | 16 ----------- arch/arm/src/lpc214x/lpc214x_irq.c | 28 ------------------- arch/arm/src/lpc2378/lpc23xx_irq.c | 28 ------------------- arch/arm/src/lpc31xx/lpc31_irq.c | 28 ------------------- arch/arm/src/lpc43xx/lpc43_irq.c | 16 ----------- arch/arm/src/lpc54xx/lpc54_irq.c | 16 ----------- arch/arm/src/max326xx/common/max326_irq.c | 16 ----------- arch/arm/src/moxart/moxart_irq.c | 24 ---------------- arch/arm/src/nrf52/nrf52_irq.c | 16 ----------- arch/arm/src/nrf53/nrf53_irq.c | 16 ----------- arch/arm/src/nuc1xx/nuc_irq.c | 20 ------------- arch/arm/src/phy62xx/irq.c | 16 ----------- arch/arm/src/rp2040/rp2040_irq.c | 16 ----------- arch/arm/src/rtl8720c/ameba_nvic.c | 12 -------- arch/arm/src/s32k1xx/s32k11x/s32k11x_irq.c | 20 ------------- arch/arm/src/s32k1xx/s32k14x/s32k14x_irq.c | 16 ----------- arch/arm/src/s32k3xx/s32k3xx_irq.c | 16 ----------- arch/arm/src/sam34/sam_irq.c | 16 ----------- arch/arm/src/sama5/sam_irq.c | 12 -------- arch/arm/src/samd2l2/sam_irq.c | 20 ------------- arch/arm/src/samd5e5/sam_irq.c | 16 ----------- arch/arm/src/samv7/sam_irq.c | 16 ----------- arch/arm/src/stm32/stm32_irq.c | 16 ----------- arch/arm/src/stm32f0l0g0/stm32_irq.c | 16 ----------- arch/arm/src/stm32f7/stm32_irq.c | 16 ----------- arch/arm/src/stm32h7/stm32_irq.c | 16 ----------- arch/arm/src/stm32l4/stm32l4_irq.c | 16 ----------- arch/arm/src/stm32l5/stm32l5_irq.c | 14 +--------- arch/arm/src/stm32u5/stm32_irq.c | 16 ----------- arch/arm/src/stm32wb/stm32wb_irq.c | 16 ----------- arch/arm/src/stm32wl5/stm32wl5_irq.c | 16 ----------- arch/arm/src/str71x/str71x_irq.c | 16 ----------- arch/arm/src/tiva/common/tiva_irq.c | 16 ----------- arch/arm/src/tlsr82/tlsr82_irq.c | 24 ---------------- arch/arm/src/tms570/tms570_irq.c | 16 ----------- arch/arm/src/xmc4/xmc4_irq.c | 16 ----------- arch/arm64/src/common/arm64_doirq.c | 20 ------------- arch/arm64/src/common/arm64_initialize.c | 12 ++++++++ arch/avr/src/at32uc3/at32uc3_irq.c | 10 ------- arch/avr/src/avr/up_irq.c | 10 ------- arch/avr/src/common/up_initialize.c | 10 +++++++ arch/hc/src/common/up_initialize.c | 6 ++++ arch/hc/src/m9s12/m9s12_irq.c | 10 ------- arch/mips/src/common/mips_initialize.c | 12 ++++++++ arch/mips/src/pic32mx/pic32mx_irq.c | 14 ---------- arch/mips/src/pic32mz/pic32mz_irq.c | 20 ------------- arch/misoc/src/common/misoc_initialize.c | 6 ++++ arch/misoc/src/lm32/lm32_irq.c | 10 ------- arch/misoc/src/minerva/minerva_irq.c | 10 ------- arch/or1k/src/common/up_initialize.c | 14 +++++++++- arch/or1k/src/mor1kx/up_irq.c | 16 ----------- arch/renesas/src/common/up_initialize.c | 12 ++++++++ arch/renesas/src/m16c/m16c_irq.c | 8 ------ arch/renesas/src/rx65n/rx65n_irq.c | 16 ----------- arch/renesas/src/sh1/sh1_irq.c | 10 ------- arch/risc-v/src/bl602/bl602_irq.c | 10 ------- arch/risc-v/src/c906/c906_irq.c | 10 ------- arch/risc-v/src/common/riscv_initialize.c | 6 ++++ arch/risc-v/src/esp32c3/esp32c3_irq.c | 6 ---- arch/risc-v/src/fe310/fe310_irq.c | 10 ------- arch/risc-v/src/k210/k210_irq.c | 10 ------- arch/risc-v/src/litex/litex_irq.c | 10 ------- arch/risc-v/src/mpfs/mpfs_irq.c | 10 ------- arch/risc-v/src/qemu-rv/qemu_rv_irq.c | 10 ------- arch/risc-v/src/rv32m1/rv32m1_irq.c | 10 ------- arch/sparc/src/bm3803/bm3803-irq.c | 18 ------------ arch/sparc/src/bm3823/bm3823-irq.c | 18 ------------ arch/sparc/src/common/up_initialize.c | 6 ++++ arch/x86/src/i486/up_irq.c | 4 --- arch/x86_64/src/intel64/up_irq.c | 4 --- arch/xtensa/src/common/xtensa_initialize.c | 16 +++++++++++ arch/xtensa/src/esp32/esp32_irq.c | 12 -------- arch/xtensa/src/esp32s2/esp32s2_irq.c | 12 -------- arch/xtensa/src/esp32s3/esp32s3_irq.c | 12 -------- arch/z16/src/z16f/z16f_irq.c | 4 --- arch/z80/src/common/z80_initialize.c | 10 +++++++ arch/z80/src/ez80/ez80_irq.c | 12 -------- arch/z80/src/z180/z180_irq.c | 6 ---- arch/z80/src/z80/z80_irq.c | 10 ------- .../src/imxrt_flexspi_nor_boot.h | 2 +- .../src/imxrt_flexspi_nor_boot.h | 2 +- 97 files changed, 125 insertions(+), 1212 deletions(-) diff --git a/arch/arm/src/a1x/a1x_irq.c b/arch/arm/src/a1x/a1x_irq.c index 11d5f013b8..d15e6e539c 100644 --- a/arch/arm/src/a1x/a1x_irq.c +++ b/arch/arm/src/a1x/a1x_irq.c @@ -38,18 +38,6 @@ #include "a1x_pio.h" #include "a1x_irq.h" -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/* g_current_regs[] holds a references to the current interrupt level - * register storage structure. If is non-NULL only during interrupt - * processing. Access to g_current_regs[] must be through the macro - * CURRENT_REGS for portability. - */ - -volatile uint32_t *g_current_regs[1]; - /**************************************************************************** * Private Functions ****************************************************************************/ @@ -150,10 +138,6 @@ void up_irqinitialize(void) putreg32(0, A1X_INTC_BASEADDR); - /* currents_regs is non-NULL only while processing an interrupt */ - - CURRENT_REGS = NULL; - #ifndef CONFIG_SUPPRESS_INTERRUPTS #ifdef CONFIG_A1X_PIO_IRQ /* Initialize logic to support a second level of interrupt decoding diff --git a/arch/arm/src/am335x/am335x_irq.c b/arch/arm/src/am335x/am335x_irq.c index cbe9af5d6b..29ec76771b 100644 --- a/arch/arm/src/am335x/am335x_irq.c +++ b/arch/arm/src/am335x/am335x_irq.c @@ -38,14 +38,6 @@ * Public Data ****************************************************************************/ -/* g_current_regs[] holds a references to the current interrupt level - * register storage structure. If is non-NULL only during interrupt - * processing. Access to g_current_regs[] must be through the macro - * CURRENT_REGS for portability. - */ - -volatile uint32_t *g_current_regs[1]; - /* Symbols defined via the linker script */ extern uint32_t _vector_start; /* Beginning of vector block */ @@ -120,10 +112,6 @@ void up_irqinitialize(void) getreg32(AM335X_INTC_PEND_FIQ(i)); /* Reading status clears pending interrupts */ } - /* currents_regs is non-NULL only while processing an interrupt */ - - CURRENT_REGS = NULL; - #ifndef CONFIG_SUPPRESS_INTERRUPTS /* Initialize logic to support a second level of interrupt decoding for * GPIO pins. diff --git a/arch/arm/src/c5471/c5471_irq.c b/arch/arm/src/c5471/c5471_irq.c index 09709ea0b1..b7d92f85e6 100644 --- a/arch/arm/src/c5471/c5471_irq.c +++ b/arch/arm/src/c5471/c5471_irq.c @@ -38,18 +38,6 @@ #define ILR_EDGESENSITIVE 0x00000020 #define ILR_PRIORITY 0x0000001E -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/* g_current_regs[] holds a references to the current interrupt level - * register storage structure. If is non-NULL only during interrupt - * processing. Access to g_current_regs[] must be through the macro - * CURRENT_REGS for portability. - */ - -volatile uint32_t *g_current_regs[1]; - /**************************************************************************** * Private Data ****************************************************************************/ @@ -164,7 +152,6 @@ void up_irqinitialize(void) /* Initialize hardware interrupt vectors */ up_vectorinitialize(); - CURRENT_REGS = NULL; /* And finally, enable interrupts */ diff --git a/arch/arm/src/common/arm_initialize.c b/arch/arm/src/common/arm_initialize.c index 19c2bd2b17..9e0afd33eb 100644 --- a/arch/arm/src/common/arm_initialize.c +++ b/arch/arm/src/common/arm_initialize.c @@ -28,6 +28,18 @@ #include "arm_internal.h" +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/* g_current_regs[] holds a references to the current interrupt level + * register storage structure. If is non-NULL only during interrupt + * processing. Access to g_current_regs[] must be through the macro + * CURRENT_REGS for portability. + */ + +volatile uint32_t *g_current_regs[CONFIG_SMP_NCPUS]; + /**************************************************************************** * Private Functions ****************************************************************************/ diff --git a/arch/arm/src/cxd56xx/cxd56_irq.c b/arch/arm/src/cxd56xx/cxd56_irq.c index 2d36c8653d..80fb917b17 100644 --- a/arch/arm/src/cxd56xx/cxd56_irq.c +++ b/arch/arm/src/cxd56xx/cxd56_irq.c @@ -63,18 +63,6 @@ * Public Data ****************************************************************************/ -/* g_current_regs[] holds a references to the current interrupt level - * register storage structure. If is non-NULL only during interrupt - * processing. Access to g_current_regs[] must be through the macro - * CURRENT_REGS for portability. - */ - -/* For the case of configurations with multiple CPUs, then there must be one - * such value for each processor that can receive an interrupt. - */ - -volatile uint32_t *g_current_regs[CONFIG_SMP_NCPUS]; - #ifdef CONFIG_SMP static volatile int8_t g_cpu_for_irq[CXD56_IRQ_NIRQS]; extern void up_send_irqreq(int idx, int irq, int cpu); @@ -351,10 +339,6 @@ void up_irqinitialize(void) regaddr += 4; } - /* currents_regs is non-NULL only while processing an interrupt */ - - CURRENT_REGS = NULL; - /* Attach the SVCall and Hard Fault exception handlers. The SVCall * exception is used for performing context switches; The Hard Fault * must also be caught because a SVCall may show up as a Hard Fault diff --git a/arch/arm/src/dm320/dm320_irq.c b/arch/arm/src/dm320/dm320_irq.c index 29ef4ce697..97d3e8ffee 100644 --- a/arch/arm/src/dm320/dm320_irq.c +++ b/arch/arm/src/dm320/dm320_irq.c @@ -35,18 +35,6 @@ * Pre-processor Definitions ****************************************************************************/ -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/* g_current_regs[] holds a references to the current interrupt level - * register storage structure. If is non-NULL only during interrupt - * processing. Access to g_current_regs[] must be through the macro - * CURRENT_REGS for portability. - */ - -volatile uint32_t *g_current_regs[1]; - /**************************************************************************** * Private Data ****************************************************************************/ @@ -98,10 +86,6 @@ void up_irqinitialize(void) putreg16(0, DM320_INTC_EABASE0); putreg16(0, DM320_INTC_EABASE1); - /* currents_regs is non-NULL only while processing an interrupt */ - - CURRENT_REGS = NULL; - /* And finally, enable interrupts */ #ifndef CONFIG_SUPPRESS_INTERRUPTS diff --git a/arch/arm/src/efm32/efm32_irq.c b/arch/arm/src/efm32/efm32_irq.c index fb6dcfd214..abb178ab05 100644 --- a/arch/arm/src/efm32/efm32_irq.c +++ b/arch/arm/src/efm32/efm32_irq.c @@ -61,17 +61,9 @@ #define NVIC_CLRENA_OFFSET (NVIC_IRQ0_31_CLEAR - NVIC_IRQ0_31_ENABLE) /**************************************************************************** - * Public Data + * Private Function ****************************************************************************/ -/* g_current_regs[] holds a references to the current interrupt level - * register storage structure. If is non-NULL only during interrupt - * processing. Access to g_current_regs[] must be through the macro - * CURRENT_REGS for portability. - */ - -volatile uint32_t *g_current_regs[1]; - /**************************************************************************** * Name: efm32_dumpnvic * @@ -350,10 +342,6 @@ void up_irqinitialize(void) regaddr += 4; } - /* currents_regs is non-NULL only while processing an interrupt */ - - CURRENT_REGS = NULL; - /* Attach the SVCall and Hard Fault exception handlers. The SVCall * exception is used for performing context switches; The Hard Fault * must also be caught because a SVCall may show up as a Hard Fault diff --git a/arch/arm/src/eoss3/eoss3_irq.c b/arch/arm/src/eoss3/eoss3_irq.c index 9a06055904..d6d190c5a5 100644 --- a/arch/arm/src/eoss3/eoss3_irq.c +++ b/arch/arm/src/eoss3/eoss3_irq.c @@ -59,18 +59,6 @@ #define NVIC_ENA_OFFSET (0) #define NVIC_CLRENA_OFFSET (NVIC_IRQ0_31_CLEAR - NVIC_IRQ0_31_ENABLE) -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/* g_current_regs[] holds a references to the current interrupt level - * register storage structure. If is non-NULL only during interrupt - * processing. Access to g_current_regs[] must be through the macro - * CURRENT_REGS for portability. - */ - -volatile uint32_t *g_current_regs[1]; - /**************************************************************************** * Private Functions ****************************************************************************/ @@ -335,10 +323,6 @@ void up_irqinitialize(void) regaddr += 4; } - /* currents_regs is non-NULL only while processing an interrupt */ - - CURRENT_REGS = NULL; - /* Attach the SVCall and Hard Fault exception handlers. The SVCall * exception is used for performing context switches; The Hard Fault * must also be caught because a SVCall may show up as a Hard Fault diff --git a/arch/arm/src/gd32f4/gd32f4xx_irq.c b/arch/arm/src/gd32f4/gd32f4xx_irq.c index 1c82c38f3c..f7417701b2 100644 --- a/arch/arm/src/gd32f4/gd32f4xx_irq.c +++ b/arch/arm/src/gd32f4/gd32f4xx_irq.c @@ -60,18 +60,6 @@ #define NVIC_ENA_OFFSET (0) #define NVIC_CLRENA_OFFSET (NVIC_IRQ0_31_CLEAR - NVIC_IRQ0_31_ENABLE) -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/* g_current_regs[] holds a references to the current interrupt level - * register storage structure. If is non-NULL only during interrupt - * processing. Access to g_current_regs[] must be through the macro - * CURRENT_REGS for portability. - */ - -volatile uint32_t *g_current_regs[1]; - /**************************************************************************** * Private Functions ****************************************************************************/ @@ -355,10 +343,6 @@ void up_irqinitialize(void) regaddr += 4; } - /* currents_regs is non-NULL only while processing an interrupt */ - - CURRENT_REGS = NULL; - /* Attach the SVCall and Hard Fault exception handlers. The SVCall * exception is used for performing context switches; The Hard Fault * must also be caught because a SVCall may show up as a Hard Fault diff --git a/arch/arm/src/imx1/imx_irq.c b/arch/arm/src/imx1/imx_irq.c index cff8b433ac..acc7ee460c 100644 --- a/arch/arm/src/imx1/imx_irq.c +++ b/arch/arm/src/imx1/imx_irq.c @@ -30,30 +30,6 @@ #include "chip.h" #include "arm_internal.h" -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/* g_current_regs[] holds a references to the current interrupt level - * register storage structure. If is non-NULL only during interrupt - * processing. Access to g_current_regs[] must be through the macro - * CURRENT_REGS for portability. - */ - -volatile uint32_t *g_current_regs[1]; - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - /**************************************************************************** * Public Functions ****************************************************************************/ @@ -69,10 +45,6 @@ void up_irqinitialize(void) putreg32(0, IMX_AITC_INTENABLEH); putreg32(0, IMX_AITC_INTENABLEL); - /* currents_regs is non-NULL only while processing an interrupt */ - - CURRENT_REGS = NULL; - /* Set masking of normal interrupts by priority. Writing all ones * (or -1) to the NIMASK register sets the normal interrupt mask to * -1 and does not disable any normal interrupt priority levels. diff --git a/arch/arm/src/imx6/imx_irq.c b/arch/arm/src/imx6/imx_irq.c index a2b71a61a5..537c20f739 100644 --- a/arch/arm/src/imx6/imx_irq.c +++ b/arch/arm/src/imx6/imx_irq.c @@ -44,18 +44,6 @@ * Public Data ****************************************************************************/ -/* g_current_regs[] holds a references to the current interrupt level - * register storage structure. If is non-NULL only during interrupt - * processing. Access to g_current_regs[] must be through the macro - * CURRENT_REGS for portability. - */ - -/* For the case of configurations with multiple CPUs, then there must be one - * such value for each processor that can receive an interrupt. - */ - -volatile uint32_t *g_current_regs[CONFIG_SMP_NCPUS]; - #if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7 /* In the SMP configuration, we will need custom IRQ and FIQ stacks. * These definitions provide the aligned stack allocations. @@ -148,10 +136,6 @@ void up_irqinitialize(void) cp15_wrvbar((uint32_t)&_vector_start); #endif /* CONFIG_ARCH_LOWVECTORS */ - /* currents_regs is non-NULL only while processing an interrupt */ - - CURRENT_REGS = NULL; - #ifndef CONFIG_SUPPRESS_INTERRUPTS #ifdef CONFIG_IMX6_PIO_IRQ /* Initialize logic to support a second level of interrupt decoding for diff --git a/arch/arm/src/imxrt/imxrt_irq.c b/arch/arm/src/imxrt/imxrt_irq.c index 38e3f46ccd..eb7c5ed213 100644 --- a/arch/arm/src/imxrt/imxrt_irq.c +++ b/arch/arm/src/imxrt/imxrt_irq.c @@ -62,18 +62,6 @@ #define NVIC_ENA_OFFSET (0) #define NVIC_CLRENA_OFFSET (NVIC_IRQ0_31_CLEAR - NVIC_IRQ0_31_ENABLE) -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/* g_current_regs[] holds a references to the current interrupt level - * register storage structure. If is non-NULL only during interrupt - * processing. Access to g_current_regs[] must be through the macro - * CURRENT_REGS for portability. - */ - -volatile uint32_t *g_current_regs[1]; - /**************************************************************************** * Private Functions ****************************************************************************/ @@ -455,10 +443,6 @@ void up_irqinitialize(void) putreg32(DEFPRIORITY32, regaddr); } - /* currents_regs is non-NULL only while processing an interrupt */ - - CURRENT_REGS = NULL; - /* Attach the SVCall and Hard Fault exception handlers. The SVCall * exception is used for performing context switches; The Hard Fault * must also be caught because a SVCall may show up as a Hard Fault diff --git a/arch/arm/src/kinetis/kinetis_irq.c b/arch/arm/src/kinetis/kinetis_irq.c index 1e863c6e30..2f5258f14c 100644 --- a/arch/arm/src/kinetis/kinetis_irq.c +++ b/arch/arm/src/kinetis/kinetis_irq.c @@ -57,18 +57,6 @@ #define NVIC_ENA_OFFSET (0) #define NVIC_CLRENA_OFFSET (NVIC_IRQ0_31_CLEAR - NVIC_IRQ0_31_ENABLE) -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/* g_current_regs[] holds a references to the current interrupt level - * register storage structure. If is non-NULL only during interrupt - * processing. Access to g_current_regs[] must be through the macro - * CURRENT_REGS for portability. - */ - -volatile uint32_t *g_current_regs[1]; - /**************************************************************************** * Private Functions ****************************************************************************/ @@ -385,10 +373,6 @@ void up_irqinitialize(void) putreg32(DEFPRIORITY32, regaddr); } - /* currents_regs is non-NULL only while processing an interrupt */ - - CURRENT_REGS = NULL; - /* Attach the SVCall and Hard Fault exception handlers. The SVCall * exception is used for performing context switches; The Hard Fault * must also be caught because a SVCall may show up as a Hard Fault diff --git a/arch/arm/src/kl/kl_irq.c b/arch/arm/src/kl/kl_irq.c index 5dcdb5954a..ed9a970f98 100644 --- a/arch/arm/src/kl/kl_irq.c +++ b/arch/arm/src/kl/kl_irq.c @@ -46,22 +46,6 @@ (NVIC_SYSH_PRIORITY_DEFAULT << 24 | NVIC_SYSH_PRIORITY_DEFAULT << 16 | \ NVIC_SYSH_PRIORITY_DEFAULT << 8 | NVIC_SYSH_PRIORITY_DEFAULT) -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/* g_current_regs[] holds a references to the current interrupt level - * register storage structure. If is non-NULL only during interrupt - * processing. Access to g_current_regs[] must be through the macro - * CURRENT_REGS for portability. - */ - -volatile uint32_t *g_current_regs[1]; - -/**************************************************************************** - * Private Data - ****************************************************************************/ - /**************************************************************************** * Private Functions ****************************************************************************/ @@ -205,10 +189,6 @@ void up_irqinitialize(void) putreg32(DEFPRIORITY32, regaddr); } - /* currents_regs is non-NULL only while processing an interrupt */ - - CURRENT_REGS = NULL; - /* Attach the SVCall and Hard Fault exception handlers. The SVCall * exception is used for performing context switches; The Hard Fault * must also be caught because a SVCall may show up as a Hard Fault diff --git a/arch/arm/src/lc823450/lc823450_irq.c b/arch/arm/src/lc823450/lc823450_irq.c index e177b04543..fcb29ea8fe 100644 --- a/arch/arm/src/lc823450/lc823450_irq.c +++ b/arch/arm/src/lc823450/lc823450_irq.c @@ -73,12 +73,6 @@ * Public Data ****************************************************************************/ -/* For the case of configurations with multiple CPUs, then there must be one - * such value for each processor that can receive an interrupt. - */ - -volatile uint32_t *g_current_regs[CONFIG_SMP_NCPUS]; - #if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7 /* In the SMP configuration, we will need two custom interrupt stacks. * These definitions provide the aligned stack allocations. @@ -507,10 +501,6 @@ void up_irqinitialize(void) regaddr += 4; } - /* currents_regs is non-NULL only while processing an interrupt */ - - CURRENT_REGS = NULL; - /* Attach the SVCall and Hard Fault exception handlers. The SVCall * exception is used for performing context switches; The Hard Fault * must also be caught because a SVCall may show up as a Hard Fault diff --git a/arch/arm/src/lc823450/lc823450_start.c b/arch/arm/src/lc823450/lc823450_start.c index 44d2f21d67..3264fadc91 100644 --- a/arch/arm/src/lc823450/lc823450_start.c +++ b/arch/arm/src/lc823450/lc823450_start.c @@ -330,10 +330,6 @@ void __start(void) get_cpu_ver(); - /* run as interrupt context, before scheduler running */ - - CURRENT_REGS = NULL; - nx_start(); /* Shouldn't get here */ diff --git a/arch/arm/src/lpc17xx_40xx/lpc17_40_irq.c b/arch/arm/src/lpc17xx_40xx/lpc17_40_irq.c index fe2b6e5b39..039cfece8a 100644 --- a/arch/arm/src/lpc17xx_40xx/lpc17_40_irq.c +++ b/arch/arm/src/lpc17xx_40xx/lpc17_40_irq.c @@ -58,18 +58,6 @@ #define NVIC_ENA_OFFSET (0) #define NVIC_CLRENA_OFFSET (NVIC_IRQ0_31_CLEAR - NVIC_IRQ0_31_ENABLE) -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/* g_current_regs[] holds a references to the current interrupt level - * register storage structure. If is non-NULL only during interrupt - * processing. Access to g_current_regs[] must be through the macro - * CURRENT_REGS for portability. - */ - -volatile uint32_t *g_current_regs[1]; - /**************************************************************************** * Private Functions ****************************************************************************/ @@ -352,10 +340,6 @@ void up_irqinitialize(void) putreg32(DEFPRIORITY32, regaddr); } - /* currents_regs is non-NULL only while processing an interrupt */ - - CURRENT_REGS = NULL; - /* Attach the SVCall and Hard Fault exception handlers. The SVCall * exception is used for performing context switches; The Hard Fault * must also be caught because a SVCall may show up as a Hard Fault diff --git a/arch/arm/src/lpc214x/lpc214x_irq.c b/arch/arm/src/lpc214x/lpc214x_irq.c index b9093cf454..2b8d49cf40 100644 --- a/arch/arm/src/lpc214x/lpc214x_irq.c +++ b/arch/arm/src/lpc214x/lpc214x_irq.c @@ -33,30 +33,6 @@ #include "arm_internal.h" #include "lpc214x_vic.h" -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/* g_current_regs[] holds a references to the current interrupt level - * register storage structure. If is non-NULL only during interrupt - * processing. Access to g_current_regs[] must be through the macro - * CURRENT_REGS for portability. - */ - -volatile uint32_t *g_current_regs[1]; - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - /**************************************************************************** * Public Functions ****************************************************************************/ @@ -93,10 +69,6 @@ void up_irqinitialize(void) vic_putreg(0, reg); } - /* currents_regs is non-NULL only while processing an interrupt */ - - CURRENT_REGS = NULL; - /* And finally, enable interrupts */ #ifndef CONFIG_SUPPRESS_INTERRUPTS diff --git a/arch/arm/src/lpc2378/lpc23xx_irq.c b/arch/arm/src/lpc2378/lpc23xx_irq.c index eef0a3a6c6..67316a4407 100644 --- a/arch/arm/src/lpc2378/lpc23xx_irq.c +++ b/arch/arm/src/lpc2378/lpc23xx_irq.c @@ -55,30 +55,6 @@ #include "lpc2378.h" #include "lpc23xx_vic.h" -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/* g_current_regs[] holds a references to the current interrupt level - * register storage structure. If is non-NULL only during interrupt - * processing. Access to g_current_regs[] must be through the macro - * CURRENT_REGS for portability. - */ - -volatile uint32_t *g_current_regs[1]; - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - /**************************************************************************** * Public Functions ****************************************************************************/ @@ -110,10 +86,6 @@ void up_irqinitialize(void) vic_putreg(0x0f, VIC_VECTPRIORITY0_OFFSET + (reg << 2)); } - /* currents_regs is non-NULL only while processing an interrupt */ - - CURRENT_REGS = NULL; - /* Enable global ARM interrupts */ #ifndef CONFIG_SUPPRESS_INTERRUPTS diff --git a/arch/arm/src/lpc31xx/lpc31_irq.c b/arch/arm/src/lpc31xx/lpc31_irq.c index f32c0d6dab..4c7f3dbaf8 100644 --- a/arch/arm/src/lpc31xx/lpc31_irq.c +++ b/arch/arm/src/lpc31xx/lpc31_irq.c @@ -37,30 +37,6 @@ #include "lpc31_cgudrvr.h" #include "lpc31.h" -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/* g_current_regs[] holds a references to the current interrupt level - * register storage structure. If is non-NULL only during interrupt - * processing. Access to g_current_regs[] must be through the macro - * CURRENT_REGS for portability. - */ - -volatile uint32_t *g_current_regs[1]; - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - /**************************************************************************** * Public Functions ****************************************************************************/ @@ -106,10 +82,6 @@ void up_irqinitialize(void) INTC_REQUEST_WEPRIO, address); } - /* currents_regs is non-NULL only while processing an interrupt */ - - CURRENT_REGS = NULL; - #ifndef CONFIG_SUPPRESS_INTERRUPTS /* And finally, enable interrupts */ diff --git a/arch/arm/src/lpc43xx/lpc43_irq.c b/arch/arm/src/lpc43xx/lpc43_irq.c index efbeaa6fc5..96c4a542e4 100644 --- a/arch/arm/src/lpc43xx/lpc43_irq.c +++ b/arch/arm/src/lpc43xx/lpc43_irq.c @@ -58,18 +58,6 @@ #define NVIC_ENA_OFFSET (0) #define NVIC_CLRENA_OFFSET (NVIC_IRQ0_31_CLEAR - NVIC_IRQ0_31_ENABLE) -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/* g_current_regs[] holds a references to the current interrupt level - * register storage structure. If is non-NULL only during interrupt - * processing. Access to g_current_regs[] must be through the macro - * CURRENT_REGS for portability. - */ - -volatile uint32_t *g_current_regs[1]; - /**************************************************************************** * Private Functions ****************************************************************************/ @@ -345,10 +333,6 @@ void up_irqinitialize(void) regaddr += 4; } - /* currents_regs is non-NULL only while processing an interrupt */ - - CURRENT_REGS = NULL; - /* Attach the SVCall and Hard Fault exception handlers. The SVCall * exception is used for performing context switches; The Hard Fault * must also be caught because a SVCall may show up as a Hard Fault diff --git a/arch/arm/src/lpc54xx/lpc54_irq.c b/arch/arm/src/lpc54xx/lpc54_irq.c index b4591d9230..fb3a827ffa 100644 --- a/arch/arm/src/lpc54xx/lpc54_irq.c +++ b/arch/arm/src/lpc54xx/lpc54_irq.c @@ -57,18 +57,6 @@ #define NVIC_ENA_OFFSET (0) #define NVIC_CLRENA_OFFSET (NVIC_IRQ0_31_CLEAR - NVIC_IRQ0_31_ENABLE) -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/* g_current_regs[] holds a references to the current interrupt level - * register storage structure. If is non-NULL only during interrupt - * processing. Access to g_current_regs[] must be through the macro - * CURRENT_REGS for portability. - */ - -volatile uint32_t *g_current_regs[1]; - /**************************************************************************** * Private Functions ****************************************************************************/ @@ -344,10 +332,6 @@ void up_irqinitialize(void) regaddr += 4; } - /* currents_regs is non-NULL only while processing an interrupt */ - - CURRENT_REGS = NULL; - /* Attach the SVCall and Hard Fault exception handlers. The SVCall * exception is used for performing context switches; The Hard Fault * must also be caught because a SVCall may show up as a Hard Fault diff --git a/arch/arm/src/max326xx/common/max326_irq.c b/arch/arm/src/max326xx/common/max326_irq.c index ac2fdfd63e..e01db272d9 100644 --- a/arch/arm/src/max326xx/common/max326_irq.c +++ b/arch/arm/src/max326xx/common/max326_irq.c @@ -57,18 +57,6 @@ #define NVIC_ENA_OFFSET (0) #define NVIC_CLRENA_OFFSET (NVIC_IRQ0_31_CLEAR - NVIC_IRQ0_31_ENABLE) -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/* g_current_regs[] holds a references to the current interrupt level - * register storage structure. If is non-NULL only during interrupt - * processing. Access to g_current_regs[] must be through the macro - * CURRENT_REGS for portability. - */ - -volatile uint32_t *g_current_regs[1]; - /**************************************************************************** * Private Functions ****************************************************************************/ @@ -344,10 +332,6 @@ void up_irqinitialize(void) regaddr += 4; } - /* currents_regs is non-NULL only while processing an interrupt */ - - CURRENT_REGS = NULL; - /* Attach the SVCall and Hard Fault exception handlers. The SVCall * exception is used for performing context switches; The Hard Fault * must also be caught because a SVCall may show up as a Hard Fault diff --git a/arch/arm/src/moxart/moxart_irq.c b/arch/arm/src/moxart/moxart_irq.c index 947dc815d5..0439689498 100644 --- a/arch/arm/src/moxart/moxart_irq.c +++ b/arch/arm/src/moxart/moxart_irq.c @@ -49,26 +49,6 @@ #define IRQ__LEVEL 0x10 #define IRQ__STATUS 0x14 -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/* g_current_regs[] holds a references to the current interrupt level - * register storage structure. If is non-NULL only during interrupt - * processing. Access to g_current_regs[] must be through the macro - * CURRENT_REGS for portability. - */ - -volatile uint32_t *g_current_regs[1]; - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - /**************************************************************************** * Public Functions ****************************************************************************/ @@ -116,10 +96,6 @@ void up_irqinitialize(void) putreg32(0, IRQ_REG(IRQ__MODE + 0x20)); putreg32(0, IRQ_REG(IRQ__LEVEL + 0x20)); - /* currents_regs is non-NULL only while processing an interrupt */ - - CURRENT_REGS = NULL; - /* Setup UART shared interrupt */ irq_attach(CONFIG_UART_MOXA_SHARED_IRQ, uart_decodeirq, NULL); diff --git a/arch/arm/src/nrf52/nrf52_irq.c b/arch/arm/src/nrf52/nrf52_irq.c index 442c41d20e..b7fe06dca4 100644 --- a/arch/arm/src/nrf52/nrf52_irq.c +++ b/arch/arm/src/nrf52/nrf52_irq.c @@ -59,18 +59,6 @@ #define NVIC_ENA_OFFSET (0) #define NVIC_CLRENA_OFFSET (NVIC_IRQ0_31_CLEAR - NVIC_IRQ0_31_ENABLE) -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/* g_current_regs[] holds a references to the current interrupt level - * register storage structure. If is non-NULL only during interrupt - * processing. Access to g_current_regs[] must be through the macro - * CURRENT_REGS for portability. - */ - -volatile uint32_t *g_current_regs[1]; - /**************************************************************************** * Private Functions ****************************************************************************/ @@ -346,10 +334,6 @@ void up_irqinitialize(void) regaddr += 4; } - /* currents_regs is non-NULL only while processing an interrupt */ - - CURRENT_REGS = NULL; - /* Attach the SVCall and Hard Fault exception handlers. The SVCall * exception is used for performing context switches; The Hard Fault * must also be caught because a SVCall may show up as a Hard Fault diff --git a/arch/arm/src/nrf53/nrf53_irq.c b/arch/arm/src/nrf53/nrf53_irq.c index 9e331f04c0..fb958034f3 100644 --- a/arch/arm/src/nrf53/nrf53_irq.c +++ b/arch/arm/src/nrf53/nrf53_irq.c @@ -59,18 +59,6 @@ #define NVIC_ENA_OFFSET (0) #define NVIC_CLRENA_OFFSET (NVIC_IRQ0_31_CLEAR - NVIC_IRQ0_31_ENABLE) -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/* g_current_regs[] holds a references to the current interrupt level - * register storage structure. If is non-NULL only during interrupt - * processing. Access to g_current_regs[] must be through the macro - * CURRENT_REGS for portability. - */ - -volatile uint32_t *g_current_regs[1]; - /**************************************************************************** * Private Functions ****************************************************************************/ @@ -346,10 +334,6 @@ void up_irqinitialize(void) regaddr += 4; } - /* currents_regs is non-NULL only while processing an interrupt */ - - CURRENT_REGS = NULL; - /* Attach the SVCall and Hard Fault exception handlers. The SVCall * exception is used for performing context switches; The Hard Fault * must also be caught because a SVCall may show up as a Hard Fault diff --git a/arch/arm/src/nuc1xx/nuc_irq.c b/arch/arm/src/nuc1xx/nuc_irq.c index aff2faa1ed..653d6c2f23 100644 --- a/arch/arm/src/nuc1xx/nuc_irq.c +++ b/arch/arm/src/nuc1xx/nuc_irq.c @@ -46,22 +46,6 @@ (NVIC_SYSH_PRIORITY_DEFAULT << 24 | NVIC_SYSH_PRIORITY_DEFAULT << 16 | \ NVIC_SYSH_PRIORITY_DEFAULT << 8 | NVIC_SYSH_PRIORITY_DEFAULT) -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/* g_current_regs[] holds a references to the current interrupt level - * register storage structure. If is non-NULL only during interrupt - * processing. Access to g_current_regs[] must be through the macro - * CURRENT_REGS for portability. - */ - -volatile uint32_t *g_current_regs[1]; - -/**************************************************************************** - * Private Data - ****************************************************************************/ - /**************************************************************************** * Private Functions ****************************************************************************/ @@ -205,10 +189,6 @@ void up_irqinitialize(void) putreg32(DEFPRIORITY32, regaddr); } - /* currents_regs is non-NULL only while processing an interrupt */ - - CURRENT_REGS = NULL; - /* Attach the SVCall and Hard Fault exception handlers. The SVCall * exception is used for performing context switches; The Hard Fault * must also be caught because a SVCall may show up as a Hard Fault diff --git a/arch/arm/src/phy62xx/irq.c b/arch/arm/src/phy62xx/irq.c index 827d54baad..b8b34c45a2 100644 --- a/arch/arm/src/phy62xx/irq.c +++ b/arch/arm/src/phy62xx/irq.c @@ -49,18 +49,6 @@ (NVIC_SYSH_PRIORITY_DEFAULT << 24 | NVIC_SYSH_PRIORITY_DEFAULT << 16 | \ NVIC_SYSH_PRIORITY_DEFAULT << 8 | NVIC_SYSH_PRIORITY_DEFAULT) -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/* g_current_regs[] holds a references to the current interrupt level - * register storage structure. If is non-NULL only during interrupt - * processing. Access to g_current_regs[] must be through the macro - * CURRENT_REGS for portability. - */ - -volatile uint32_t *g_current_regs[1]; - /**************************************************************************** * Private Functions ****************************************************************************/ @@ -285,10 +273,6 @@ void up_irqinitialize(void) JUMP_FUNCTION(V0_IRQ_HANDLER + 30) = (unsigned)&exception_common, /* 16+30 */ JUMP_FUNCTION(V0_IRQ_HANDLER + 31) = (unsigned)&exception_common, /* 16+31 */ - /* currents_regs is non-NULL only while processing an interrupt */ - - CURRENT_REGS = NULL; - /* Attach the SVCall and Hard Fault exception handlers. The SVCall * exception is used for performing context switches; The Hard Fault * must also be caught because a SVCall may show up as a Hard Fault diff --git a/arch/arm/src/rp2040/rp2040_irq.c b/arch/arm/src/rp2040/rp2040_irq.c index 21e1b37777..b6d8c40f0e 100644 --- a/arch/arm/src/rp2040/rp2040_irq.c +++ b/arch/arm/src/rp2040/rp2040_irq.c @@ -54,18 +54,6 @@ * Public Data ****************************************************************************/ -/* g_current_regs[] holds a references to the current interrupt level - * register storage structure. If is non-NULL only during interrupt - * processing. Access to g_current_regs[] must be through the macro - * CURRENT_REGS for portability. - */ - -/* For the case of configurations with multiple CPUs, then there must be one - * such value for each processor that can receive an interrupt. - */ - -volatile uint32_t *g_current_regs[CONFIG_SMP_NCPUS]; - #ifdef CONFIG_SMP extern void rp2040_send_irqreq(int irqreq); #endif @@ -249,10 +237,6 @@ void up_irqinitialize(void) putreg32(DEFPRIORITY32, regaddr); } - /* currents_regs is non-NULL only while processing an interrupt */ - - CURRENT_REGS = NULL; - /* Attach the SVCall and Hard Fault exception handlers. The SVCall * exception is used for performing context switches; The Hard Fault * must also be caught because a SVCall may show up as a Hard Fault diff --git a/arch/arm/src/rtl8720c/ameba_nvic.c b/arch/arm/src/rtl8720c/ameba_nvic.c index 343a8d8a70..55a50b73eb 100644 --- a/arch/arm/src/rtl8720c/ameba_nvic.c +++ b/arch/arm/src/rtl8720c/ameba_nvic.c @@ -52,18 +52,6 @@ #define NVIC_ENABLE_OFFSET (NVIC_IRQ0_31_ENABLE - NVIC_IRQ0_31_ENABLE) #define NVIC_CLEAR_OFFSET (NVIC_IRQ0_31_CLEAR - NVIC_IRQ0_31_ENABLE) -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/* g_current_regs[] holds a references to the current interrupt level - * register storage structure. If is non-NULL only during interrupt - * processing. Access to g_current_regs[] must be through the macro - * CURRENT_REGS for portability. - */ - -volatile uint32_t *g_current_regs[CONFIG_SMP_NCPUS]; - /**************************************************************************** * Private Function Declarations ****************************************************************************/ diff --git a/arch/arm/src/s32k1xx/s32k11x/s32k11x_irq.c b/arch/arm/src/s32k1xx/s32k11x/s32k11x_irq.c index d7e35e7411..488a2d95d5 100644 --- a/arch/arm/src/s32k1xx/s32k11x/s32k11x_irq.c +++ b/arch/arm/src/s32k1xx/s32k11x/s32k11x_irq.c @@ -47,22 +47,6 @@ (NVIC_SYSH_PRIORITY_DEFAULT << 24 | NVIC_SYSH_PRIORITY_DEFAULT << 16 | \ NVIC_SYSH_PRIORITY_DEFAULT << 8 | NVIC_SYSH_PRIORITY_DEFAULT) -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/* g_current_regs[] holds a references to the current interrupt level - * register storage structure. If is non-NULL only during interrupt - * processing. Access to g_current_regs[] must be through the macro - * CURRENT_REGS for portability. - */ - -volatile uint32_t *g_current_regs[1]; - -/**************************************************************************** - * Private Data - ****************************************************************************/ - /**************************************************************************** * Private Functions ****************************************************************************/ @@ -163,10 +147,6 @@ void up_irqinitialize(void) putreg32(DEFPRIORITY32, regaddr); } - /* currents_regs is non-NULL only while processing an interrupt */ - - CURRENT_REGS = NULL; - /* Attach the SVCall and Hard Fault exception handlers. The SVCall * exception is used for performing context switches; The Hard Fault * must also be caught because a SVCall may show up as a Hard Fault diff --git a/arch/arm/src/s32k1xx/s32k14x/s32k14x_irq.c b/arch/arm/src/s32k1xx/s32k14x/s32k14x_irq.c index 852232bfaf..af217da5c9 100644 --- a/arch/arm/src/s32k1xx/s32k14x/s32k14x_irq.c +++ b/arch/arm/src/s32k1xx/s32k14x/s32k14x_irq.c @@ -57,18 +57,6 @@ #define NVIC_ENA_OFFSET (0) #define NVIC_CLRENA_OFFSET (NVIC_IRQ0_31_CLEAR - NVIC_IRQ0_31_ENABLE) -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/* g_current_regs[] holds a references to the current interrupt level - * register storage structure. If is non-NULL only during interrupt - * processing. Access to g_current_regs[] must be through the macro - * CURRENT_REGS for portability. - */ - -volatile uint32_t *g_current_regs[1]; - /**************************************************************************** * Private Functions ****************************************************************************/ @@ -379,10 +367,6 @@ void up_irqinitialize(void) regaddr += 4; } - /* currents_regs is non-NULL only while processing an interrupt */ - - CURRENT_REGS = NULL; - /* Attach the SVCall and Hard Fault exception handlers. The SVCall * exception is used for performing context switches; The Hard Fault * must also be caught because a SVCall may show up as a Hard Fault diff --git a/arch/arm/src/s32k3xx/s32k3xx_irq.c b/arch/arm/src/s32k3xx/s32k3xx_irq.c index 7d1c132657..2382a0da9f 100644 --- a/arch/arm/src/s32k3xx/s32k3xx_irq.c +++ b/arch/arm/src/s32k3xx/s32k3xx_irq.c @@ -64,18 +64,6 @@ #define NVIC_ENA_OFFSET (0) #define NVIC_CLRENA_OFFSET (NVIC_IRQ0_31_CLEAR - NVIC_IRQ0_31_ENABLE) -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/* g_current_regs[] holds a references to the current interrupt level - * register storage structure. If is non-NULL only during interrupt - * processing. Access to g_current_regs[] must be through the macro - * CURRENT_REGS for portability. - */ - -volatile uint32_t *g_current_regs[1]; - /**************************************************************************** * Private Functions ****************************************************************************/ @@ -386,10 +374,6 @@ void up_irqinitialize(void) regaddr += 4; } - /* currents_regs is non-NULL only while processing an interrupt */ - - CURRENT_REGS = NULL; - /* Attach the SVCall and Hard Fault exception handlers. The SVCall * exception is used for performing context switches; The Hard Fault * must also be caught because a SVCall may show up as a Hard Fault diff --git a/arch/arm/src/sam34/sam_irq.c b/arch/arm/src/sam34/sam_irq.c index f0e2606d27..126e399e70 100644 --- a/arch/arm/src/sam34/sam_irq.c +++ b/arch/arm/src/sam34/sam_irq.c @@ -60,18 +60,6 @@ #define NVIC_ENA_OFFSET (0) #define NVIC_CLRENA_OFFSET (NVIC_IRQ0_31_CLEAR - NVIC_IRQ0_31_ENABLE) -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/* g_current_regs[] holds a references to the current interrupt level - * register storage structure. If is non-NULL only during interrupt - * processing. Access to g_current_regs[] must be through the macro - * CURRENT_REGS for portability. - */ - -volatile uint32_t *g_current_regs[CONFIG_SMP_NCPUS]; - /**************************************************************************** * Private Functions ****************************************************************************/ @@ -406,10 +394,6 @@ void up_irqinitialize(void) putreg32(DEFPRIORITY32, regaddr); } - /* currents_regs is non-NULL only while processing an interrupt */ - - CURRENT_REGS = NULL; - /* Attach the SVCall and Hard Fault exception handlers. The SVCall * exception is used for performing context switches; The Hard Fault * must also be caught because a SVCall may show up as a Hard Fault diff --git a/arch/arm/src/sama5/sam_irq.c b/arch/arm/src/sama5/sam_irq.c index 46c183fad0..5ed6cdeba0 100644 --- a/arch/arm/src/sama5/sam_irq.c +++ b/arch/arm/src/sama5/sam_irq.c @@ -63,14 +63,6 @@ typedef uint32_t *(*doirq_t)(int irq, uint32_t *regs); * Public Data ****************************************************************************/ -/* g_current_regs[] holds a references to the current interrupt level - * register storage structure. If is non-NULL only during interrupt - * processing. Access to g_current_regs[] must be through the macro - * CURRENT_REGS for portability. - */ - -volatile uint32_t *g_current_regs[1]; - /* Symbols defined via the linker script */ extern uint32_t _vector_start; /* Beginning of vector block */ @@ -537,10 +529,6 @@ void up_irqinitialize(void) #endif /* CONFIG_SAMA5_BOOT_ISRAM || CONFIG_SAMA5_BOOT_CS0FLASH */ #endif /* CONFIG_ARCH_LOWVECTORS */ - /* currents_regs is non-NULL only while processing an interrupt */ - - CURRENT_REGS = NULL; - #ifndef CONFIG_SUPPRESS_INTERRUPTS /* Initialize logic to support a second level of interrupt decoding for * PIO pins. diff --git a/arch/arm/src/samd2l2/sam_irq.c b/arch/arm/src/samd2l2/sam_irq.c index 963718a473..c3ee7ef5ae 100644 --- a/arch/arm/src/samd2l2/sam_irq.c +++ b/arch/arm/src/samd2l2/sam_irq.c @@ -46,22 +46,6 @@ (NVIC_SYSH_PRIORITY_DEFAULT << 24 | NVIC_SYSH_PRIORITY_DEFAULT << 16 | \ NVIC_SYSH_PRIORITY_DEFAULT << 8 | NVIC_SYSH_PRIORITY_DEFAULT) -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/* g_current_regs[] holds a references to the current interrupt level - * register storage structure. If is non-NULL only during interrupt - * processing. Access to g_current_regs[] must be through the macro - * CURRENT_REGS for portability. - */ - -volatile uint32_t *g_current_regs[1]; - -/**************************************************************************** - * Private Data - ****************************************************************************/ - /**************************************************************************** * Private Functions ****************************************************************************/ @@ -161,10 +145,6 @@ void up_irqinitialize(void) putreg32(DEFPRIORITY32, regaddr); } - /* currents_regs is non-NULL only while processing an interrupt */ - - CURRENT_REGS = NULL; - /* Attach the SVCall and Hard Fault exception handlers. The SVCall * exception is used for performing context switches; The Hard Fault * must also be caught because a SVCall may show up as a Hard Fault diff --git a/arch/arm/src/samd5e5/sam_irq.c b/arch/arm/src/samd5e5/sam_irq.c index 0e1a5ea894..8aa11ef390 100644 --- a/arch/arm/src/samd5e5/sam_irq.c +++ b/arch/arm/src/samd5e5/sam_irq.c @@ -60,18 +60,6 @@ #define NVIC_ENA_OFFSET (0) #define NVIC_CLRENA_OFFSET (NVIC_IRQ0_31_CLEAR - NVIC_IRQ0_31_ENABLE) -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/* g_current_regs[] holds a references to the current interrupt level - * register storage structure. If is non-NULL only during interrupt - * processing. Access to g_current_regs[] must be through the macro - * CURRENT_REGS for portability. - */ - -volatile uint32_t *g_current_regs[CONFIG_SMP_NCPUS]; - /**************************************************************************** * Private Functions ****************************************************************************/ @@ -493,10 +481,6 @@ void up_irqinitialize(void) putreg32(DEFPRIORITY32, regaddr); } - /* currents_regs is non-NULL only while processing an interrupt */ - - CURRENT_REGS = NULL; - /* Attach the SVCall and Hard Fault exception handlers. The SVCall * exception is used for performing context switches; The Hard Fault * must also be caught because a SVCall may show up as a Hard Fault diff --git a/arch/arm/src/samv7/sam_irq.c b/arch/arm/src/samv7/sam_irq.c index b6c782efa0..fddb44512c 100644 --- a/arch/arm/src/samv7/sam_irq.c +++ b/arch/arm/src/samv7/sam_irq.c @@ -60,18 +60,6 @@ #define NVIC_ENA_OFFSET (0) #define NVIC_CLRENA_OFFSET (NVIC_IRQ0_31_CLEAR - NVIC_IRQ0_31_ENABLE) -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/* g_current_regs[] holds a references to the current interrupt level - * register storage structure. If is non-NULL only during interrupt - * processing. Access to g_current_regs[] must be through the macro - * CURRENT_REGS for portability. - */ - -volatile uint32_t *g_current_regs[1]; - /**************************************************************************** * Private Functions ****************************************************************************/ @@ -408,10 +396,6 @@ void up_irqinitialize(void) putreg32(DEFPRIORITY32, regaddr); } - /* currents_regs is non-NULL only while processing an interrupt */ - - CURRENT_REGS = NULL; - /* Attach the SVCall and Hard Fault exception handlers. The SVCall * exception is used for performing context switches; The Hard Fault * must also be caught because a SVCall may show up as a Hard Fault diff --git a/arch/arm/src/stm32/stm32_irq.c b/arch/arm/src/stm32/stm32_irq.c index cfb5e0eee7..045539eb87 100644 --- a/arch/arm/src/stm32/stm32_irq.c +++ b/arch/arm/src/stm32/stm32_irq.c @@ -60,18 +60,6 @@ #define NVIC_ENA_OFFSET (0) #define NVIC_CLRENA_OFFSET (NVIC_IRQ0_31_CLEAR - NVIC_IRQ0_31_ENABLE) -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/* g_current_regs[] holds a references to the current interrupt level - * register storage structure. If is non-NULL only during interrupt - * processing. Access to g_current_regs[] must be through the macro - * CURRENT_REGS for portability. - */ - -volatile uint32_t *g_current_regs[1]; - /**************************************************************************** * Private Functions ****************************************************************************/ @@ -349,10 +337,6 @@ void up_irqinitialize(void) regaddr += 4; } - /* currents_regs is non-NULL only while processing an interrupt */ - - CURRENT_REGS = NULL; - /* Attach the SVCall and Hard Fault exception handlers. The SVCall * exception is used for performing context switches; The Hard Fault * must also be caught because a SVCall may show up as a Hard Fault diff --git a/arch/arm/src/stm32f0l0g0/stm32_irq.c b/arch/arm/src/stm32f0l0g0/stm32_irq.c index 6971e91f04..bb12773523 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_irq.c +++ b/arch/arm/src/stm32f0l0g0/stm32_irq.c @@ -47,18 +47,6 @@ (NVIC_SYSH_PRIORITY_DEFAULT << 24 | NVIC_SYSH_PRIORITY_DEFAULT << 16 | \ NVIC_SYSH_PRIORITY_DEFAULT << 8 | NVIC_SYSH_PRIORITY_DEFAULT) -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/* g_current_regs[] holds a references to the current interrupt level - * register storage structure. If is non-NULL only during interrupt - * processing. Access to g_current_regs[] must be through the macro - * CURRENT_REGS for portability. - */ - -volatile uint32_t *g_current_regs[1]; - /**************************************************************************** * Private Functions ****************************************************************************/ @@ -202,10 +190,6 @@ void up_irqinitialize(void) putreg32(DEFPRIORITY32, regaddr); } - /* currents_regs is non-NULL only while processing an interrupt */ - - CURRENT_REGS = NULL; - /* Attach the SVCall and Hard Fault exception handlers. The SVCall * exception is used for performing context switches; The Hard Fault * must also be caught because a SVCall may show up as a Hard Fault diff --git a/arch/arm/src/stm32f7/stm32_irq.c b/arch/arm/src/stm32f7/stm32_irq.c index adf3d883de..3b775a4da6 100644 --- a/arch/arm/src/stm32f7/stm32_irq.c +++ b/arch/arm/src/stm32f7/stm32_irq.c @@ -61,18 +61,6 @@ #define NVIC_ENA_OFFSET (0) #define NVIC_CLRENA_OFFSET (NVIC_IRQ0_31_CLEAR - NVIC_IRQ0_31_ENABLE) -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/* g_current_regs[] holds a references to the current interrupt level - * register storage structure. If is non-NULL only during interrupt - * processing. Access to g_current_regs[] must be through the macro - * CURRENT_REGS for portability. - */ - -volatile uint32_t *g_current_regs[1]; - /**************************************************************************** * Private Functions ****************************************************************************/ @@ -452,10 +440,6 @@ void up_irqinitialize(void) putreg32(DEFPRIORITY32, regaddr); } - /* currents_regs is non-NULL only while processing an interrupt */ - - CURRENT_REGS = NULL; - /* Attach the SVCall and Hard Fault exception handlers. The SVCall * exception is used for performing context switches; The Hard Fault * must also be caught because a SVCall may show up as a Hard Fault diff --git a/arch/arm/src/stm32h7/stm32_irq.c b/arch/arm/src/stm32h7/stm32_irq.c index 77ee3f4750..2f1e4ee4af 100644 --- a/arch/arm/src/stm32h7/stm32_irq.c +++ b/arch/arm/src/stm32h7/stm32_irq.c @@ -61,18 +61,6 @@ #define NVIC_ENA_OFFSET (0) #define NVIC_CLRENA_OFFSET (NVIC_IRQ0_31_CLEAR - NVIC_IRQ0_31_ENABLE) -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/* g_current_regs[] holds a references to the current interrupt level - * register storage structure. If is non-NULL only during interrupt - * processing. Access to g_current_regs[] must be through the macro - * CURRENT_REGS for portability. - */ - -volatile uint32_t *g_current_regs[1]; - /**************************************************************************** * Private Functions ****************************************************************************/ @@ -472,10 +460,6 @@ void up_irqinitialize(void) putreg32(DEFPRIORITY32, regaddr); } - /* currents_regs is non-NULL only while processing an interrupt */ - - CURRENT_REGS = NULL; - /* Attach the SVCall and Hard Fault exception handlers. The SVCall * exception is used for performing context switches; The Hard Fault * must also be caught because a SVCall may show up as a Hard Fault diff --git a/arch/arm/src/stm32l4/stm32l4_irq.c b/arch/arm/src/stm32l4/stm32l4_irq.c index b043cce294..b602f3cdc6 100644 --- a/arch/arm/src/stm32l4/stm32l4_irq.c +++ b/arch/arm/src/stm32l4/stm32l4_irq.c @@ -57,18 +57,6 @@ #define NVIC_ENA_OFFSET (0) #define NVIC_CLRENA_OFFSET (NVIC_IRQ0_31_CLEAR - NVIC_IRQ0_31_ENABLE) -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/* g_current_regs[] holds a references to the current interrupt level - * register storage structure. If is non-NULL only during interrupt - * processing. Access to g_current_regs[] must be through the macro - * CURRENT_REGS for portability. - */ - -volatile uint32_t *g_current_regs[1]; - /**************************************************************************** * Private Functions ****************************************************************************/ @@ -340,10 +328,6 @@ void up_irqinitialize(void) regaddr += 4; } - /* currents_regs is non-NULL only while processing an interrupt */ - - CURRENT_REGS = NULL; - /* Attach the SVCall and Hard Fault exception handlers. The SVCall * exception is used for performing context switches; The Hard Fault * must also be caught because a SVCall may show up as a Hard Fault diff --git a/arch/arm/src/stm32l5/stm32l5_irq.c b/arch/arm/src/stm32l5/stm32l5_irq.c index 99592710c3..1876ca57b6 100644 --- a/arch/arm/src/stm32l5/stm32l5_irq.c +++ b/arch/arm/src/stm32l5/stm32l5_irq.c @@ -58,17 +58,9 @@ #define NVIC_CLRENA_OFFSET (NVIC_IRQ0_31_CLEAR - NVIC_IRQ0_31_ENABLE) /**************************************************************************** - * Public Data + * Private Functions ****************************************************************************/ -/* g_current_regs[] holds a references to the current interrupt level - * register storage structure. If is non-NULL only during interrupt - * processing. Access to g_current_regs[] must be through the macro - * CURRENT_REGS for portability. - */ - -volatile uint32_t *g_current_regs[1]; - /**************************************************************************** * Name: stm32l5_dumpnvic * @@ -321,10 +313,6 @@ void up_irqinitialize(void) regaddr += 4; } - /* currents_regs is non-NULL only while processing an interrupt */ - - CURRENT_REGS = NULL; - /* Attach the SVCall and Hard Fault exception handlers. The SVCall * exception is used for performing context switches; The Hard Fault * must also be caught because a SVCall may show up as a Hard Fault diff --git a/arch/arm/src/stm32u5/stm32_irq.c b/arch/arm/src/stm32u5/stm32_irq.c index cff7e3a1d9..528d51cff7 100644 --- a/arch/arm/src/stm32u5/stm32_irq.c +++ b/arch/arm/src/stm32u5/stm32_irq.c @@ -57,18 +57,6 @@ #define NVIC_ENA_OFFSET (0) #define NVIC_CLRENA_OFFSET (NVIC_IRQ0_31_CLEAR - NVIC_IRQ0_31_ENABLE) -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/* g_current_regs[] holds a references to the current interrupt level - * register storage structure. If is non-NULL only during interrupt - * processing. Access to g_current_regs[] must be through the macro - * CURRENT_REGS for portability. - */ - -volatile uint32_t *g_current_regs[1]; - /**************************************************************************** * Private Functions ****************************************************************************/ @@ -325,10 +313,6 @@ void up_irqinitialize(void) regaddr += 4; } - /* currents_regs is non-NULL only while processing an interrupt */ - - CURRENT_REGS = NULL; - /* Attach the SVCall and Hard Fault exception handlers. The SVCall * exception is used for performing context switches; The Hard Fault * must also be caught because a SVCall may show up as a Hard Fault diff --git a/arch/arm/src/stm32wb/stm32wb_irq.c b/arch/arm/src/stm32wb/stm32wb_irq.c index b49fbe7205..3e8578ddae 100644 --- a/arch/arm/src/stm32wb/stm32wb_irq.c +++ b/arch/arm/src/stm32wb/stm32wb_irq.c @@ -58,18 +58,6 @@ #define NVIC_ENA_OFFSET (0) #define NVIC_CLRENA_OFFSET (NVIC_IRQ0_31_CLEAR - NVIC_IRQ0_31_ENABLE) -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/* g_current_regs[] holds a references to the current interrupt level - * register storage structure. If is non-NULL only during interrupt - * processing. Access to g_current_regs[] must be through the macro - * CURRENT_REGS for portability. - */ - -volatile uint32_t *g_current_regs[1]; - /**************************************************************************** * Private Functions ****************************************************************************/ @@ -347,10 +335,6 @@ void up_irqinitialize(void) regaddr += 4; } - /* currents_regs is non-NULL only while processing an interrupt */ - - CURRENT_REGS = NULL; - /* Attach the SVCall and Hard Fault exception handlers. The SVCall * exception is used for performing context switches; The Hard Fault * must also be caught because a SVCall may show up as a Hard Fault diff --git a/arch/arm/src/stm32wl5/stm32wl5_irq.c b/arch/arm/src/stm32wl5/stm32wl5_irq.c index 8c003c050a..5848b53d46 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_irq.c +++ b/arch/arm/src/stm32wl5/stm32wl5_irq.c @@ -58,18 +58,6 @@ #define NVIC_ENA_OFFSET (0) #define NVIC_CLRENA_OFFSET (NVIC_IRQ0_31_CLEAR - NVIC_IRQ0_31_ENABLE) -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/* g_current_regs[] holds a references to the current interrupt level - * register storage structure. If is non-NULL only during interrupt - * processing. Access to g_current_regs[] must be through the macro - * CURRENT_REGS for portability. - */ - -volatile uint32_t *g_current_regs[1]; - /**************************************************************************** * Private Functions ****************************************************************************/ @@ -344,10 +332,6 @@ void up_irqinitialize(void) regaddr += 4; } - /* currents_regs is non-NULL only while processing an interrupt */ - - CURRENT_REGS = NULL; - /* Attach the SVCall and Hard Fault exception handlers. The SVCall * exception is used for performing context switches; The Hard Fault * must also be caught because a SVCall may show up as a Hard Fault diff --git a/arch/arm/src/str71x/str71x_irq.c b/arch/arm/src/str71x/str71x_irq.c index a2a5daddeb..eeaef6e0cc 100644 --- a/arch/arm/src/str71x/str71x_irq.c +++ b/arch/arm/src/str71x/str71x_irq.c @@ -36,18 +36,6 @@ #include "arm_internal.h" #include "str71x.h" -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/* g_current_regs[] holds a references to the current interrupt level - * register storage structure. If is non-NULL only during interrupt - * processing. Access to g_current_regs[] must be through the macro - * CURRENT_REGS for portability. - */ - -volatile uint32_t *g_current_regs[1]; - /**************************************************************************** * Public Functions ****************************************************************************/ @@ -58,10 +46,6 @@ volatile uint32_t *g_current_regs[1]; void up_irqinitialize(void) { - /* Currents_regs is non-NULL only while processing an interrupt */ - - CURRENT_REGS = NULL; - /* The bulk of IRQ initialization if performed in str71x_head.S, so we * have very little to do here -- basically just enabling interrupts; * diff --git a/arch/arm/src/tiva/common/tiva_irq.c b/arch/arm/src/tiva/common/tiva_irq.c index 670d712b1d..47b5427132 100644 --- a/arch/arm/src/tiva/common/tiva_irq.c +++ b/arch/arm/src/tiva/common/tiva_irq.c @@ -58,18 +58,6 @@ #define NVIC_ENA_OFFSET (0) #define NVIC_CLRENA_OFFSET (NVIC_IRQ0_31_CLEAR - NVIC_IRQ0_31_ENABLE) -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/* g_current_regs[] holds a references to the current interrupt level - * register storage structure. If is non-NULL only during interrupt - * processing. Access to g_current_regs[] must be through the macro - * CURRENT_REGS for portability. - */ - -volatile uint32_t *g_current_regs[1]; - /**************************************************************************** * Private Functions ****************************************************************************/ @@ -459,10 +447,6 @@ void up_irqinitialize(void) putreg32(DEFPRIORITY32, regaddr); } - /* currents_regs is non-NULL only while processing an interrupt */ - - CURRENT_REGS = NULL; - /* Initialize support for GPIO interrupts if included in this build */ #ifdef CONFIG_TIVA_GPIO_IRQS diff --git a/arch/arm/src/tlsr82/tlsr82_irq.c b/arch/arm/src/tlsr82/tlsr82_irq.c index 5e6bc823ba..9d8618fbd2 100644 --- a/arch/arm/src/tlsr82/tlsr82_irq.c +++ b/arch/arm/src/tlsr82/tlsr82_irq.c @@ -24,26 +24,6 @@ #include "arm_internal.h" -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/* g_current_regs[] holds a references to the current interrupt level - * register storage structure. If is non-NULL only during interrupt - * processing. Access to g_current_regs[] must be through the macro - * CURRENT_REGS for portability. - */ - -volatile uint32_t *g_current_regs[CONFIG_SMP_NCPUS]; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - /**************************************************************************** * Public Functions ****************************************************************************/ @@ -65,10 +45,6 @@ void up_irqinitialize(void) up_disable_irq(i); } - /* currents_regs is non-NULL only while processing an interrupt */ - - CURRENT_REGS = NULL; - /* And finally, enable interrupts */ up_irq_enable(); diff --git a/arch/arm/src/tms570/tms570_irq.c b/arch/arm/src/tms570/tms570_irq.c index 7a4faaa660..f8cb6ac8a1 100644 --- a/arch/arm/src/tms570/tms570_irq.c +++ b/arch/arm/src/tms570/tms570_irq.c @@ -39,18 +39,6 @@ #include "tms570_esm.h" #include "tms570_irq.h" -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/* g_current_regs[] holds a references to the current interrupt level - * register storage structure. If is non-NULL only during interrupt - * processing. Access to g_current_regs[] must be through the macro - * CURRENT_REGS for portability. - */ - -volatile uint32_t *g_current_regs[1]; - /**************************************************************************** * Private Functions ****************************************************************************/ @@ -138,10 +126,6 @@ void up_irqinitialize(void) putreg32(0xffffffff, TMS570_VIM_REQENACLR3); #endif - /* currents_regs is non-NULL only while processing an interrupt */ - - CURRENT_REGS = NULL; - #ifdef CONFIG_ARMV7R_HAVE_DECODEFIQ /* By default, interrupt CHAN0 is mapped to ESM (Error Signal Module) * high level interrupt and CHAN1 is reserved for other NMI. For safety diff --git a/arch/arm/src/xmc4/xmc4_irq.c b/arch/arm/src/xmc4/xmc4_irq.c index 30fe949ace..fe66ad0178 100644 --- a/arch/arm/src/xmc4/xmc4_irq.c +++ b/arch/arm/src/xmc4/xmc4_irq.c @@ -56,18 +56,6 @@ #define NVIC_ENA_OFFSET (0) #define NVIC_CLRENA_OFFSET (NVIC_IRQ0_31_CLEAR - NVIC_IRQ0_31_ENABLE) -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/* g_current_regs[] holds a references to the current interrupt level - * register storage structure. If is non-NULL only during interrupt - * processing. Access to g_current_regs[] must be through the macro - * CURRENT_REGS for portability. - */ - -volatile uint32_t *g_current_regs[1]; - /**************************************************************************** * Private Functions ****************************************************************************/ @@ -384,10 +372,6 @@ void up_irqinitialize(void) putreg32(DEFPRIORITY32, regaddr); } - /* currents_regs is non-NULL only while processing an interrupt */ - - CURRENT_REGS = NULL; - /* Attach the SVCall and Hard Fault exception handlers. The SVCall * exception is used for performing context switches; The Hard Fault * must also be caught because a SVCall may show up as a Hard Fault diff --git a/arch/arm64/src/common/arm64_doirq.c b/arch/arm64/src/common/arm64_doirq.c index 0bf46af4a4..8780e507d4 100644 --- a/arch/arm64/src/common/arm64_doirq.c +++ b/arch/arm64/src/common/arm64_doirq.c @@ -41,22 +41,6 @@ #include "arm64_gic.h" #include "arm64_fatal.h" -/**************************************************************************** - * Public data - ****************************************************************************/ - -/* g_current_regs[] holds a references to the current interrupt level - * register storage structure. If is non-NULL only during interrupt - * processing. Access to g_current_regs[] must be through the macro - * CURRENT_REGS for portability. - */ - -/* For the case of configurations with multiple CPUs, then there must be one - * such value for each processor that can receive an interrupt. - */ - -volatile uint64_t *g_current_regs[CONFIG_SMP_NCPUS]; - /**************************************************************************** * Public Functions ****************************************************************************/ @@ -143,10 +127,6 @@ void up_irqinitialize(void) arm64_gic_initialize(); /* Initialization common to all CPUs */ - /* currents_regs is non-NULL only while processing an interrupt */ - - CURRENT_REGS = NULL; - #ifdef CONFIG_SMP arm64_smp_sgi_init(); #endif diff --git a/arch/arm64/src/common/arm64_initialize.c b/arch/arm64/src/common/arm64_initialize.c index d16bbe3158..af3047af24 100644 --- a/arch/arm64/src/common/arm64_initialize.c +++ b/arch/arm64/src/common/arm64_initialize.c @@ -45,6 +45,18 @@ * Public data ****************************************************************************/ +/* g_current_regs[] holds a references to the current interrupt level + * register storage structure. If is non-NULL only during interrupt + * processing. Access to g_current_regs[] must be through the macro + * CURRENT_REGS for portability. + */ + +/* For the case of configurations with multiple CPUs, then there must be one + * such value for each processor that can receive an interrupt. + */ + +volatile uint64_t *g_current_regs[CONFIG_SMP_NCPUS]; + #ifdef CONFIG_SMP INIT_STACK_ARRAY_DEFINE(g_cpu_idlestackalloc, CONFIG_SMP_NCPUS, SMP_STACK_SIZE); diff --git a/arch/avr/src/at32uc3/at32uc3_irq.c b/arch/avr/src/at32uc3/at32uc3_irq.c index 262421bf7e..0a47aa0016 100644 --- a/arch/avr/src/at32uc3/at32uc3_irq.c +++ b/arch/avr/src/at32uc3/at32uc3_irq.c @@ -62,12 +62,6 @@ extern uint32_t avr32_int3; #define AVR32_INT2_RADDR ((uint32_t)&avr32_int2 - (uint32_t)&vectortab) #define AVR32_INT3_RADDR ((uint32_t)&avr32_int3 - (uint32_t)&vectortab) -/**************************************************************************** - * Public Data - ****************************************************************************/ - -volatile uint32_t *g_current_regs; - /**************************************************************************** * Private Types ****************************************************************************/ @@ -204,10 +198,6 @@ void up_irqinitialize(void) putreg32(g_ipr[0], AVR32_INTC_IPR(group)); } - /* currents_regs is non-NULL only while processing an interrupt */ - - g_current_regs = NULL; - /* Attach the exception handlers */ for (irq = 0; irq < AVR32_IRQ_NEVENTS; irq++) diff --git a/arch/avr/src/avr/up_irq.c b/arch/avr/src/avr/up_irq.c index eb530dc0ae..eac64ba8e6 100644 --- a/arch/avr/src/avr/up_irq.c +++ b/arch/avr/src/avr/up_irq.c @@ -35,12 +35,6 @@ #include "up_internal.h" -/**************************************************************************** - * Public Data - ****************************************************************************/ - -volatile uint8_t *g_current_regs; - /**************************************************************************** * Public Functions ****************************************************************************/ @@ -51,10 +45,6 @@ volatile uint8_t *g_current_regs; void up_irqinitialize(void) { - /* currents_regs is non-NULL only while processing an interrupt */ - - g_current_regs = NULL; - /* Initialize GPIO interrupt facilities */ #ifdef CONFIG_AVR32_GPIOIRQ diff --git a/arch/avr/src/common/up_initialize.c b/arch/avr/src/common/up_initialize.c index 9b3283c478..263e8c2c66 100644 --- a/arch/avr/src/common/up_initialize.c +++ b/arch/avr/src/common/up_initialize.c @@ -61,6 +61,16 @@ # define USE_SERIALDRIVER 1 #endif +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#ifdef CONFIG_ARCH_FAMILY_AVR32 +volatile uint32_t *g_current_regs; +#else +volatile uint8_t *g_current_regs; +#endif + /**************************************************************************** * Private Functions ****************************************************************************/ diff --git a/arch/hc/src/common/up_initialize.c b/arch/hc/src/common/up_initialize.c index d51cd54526..27a740046e 100644 --- a/arch/hc/src/common/up_initialize.c +++ b/arch/hc/src/common/up_initialize.c @@ -28,6 +28,12 @@ #include "up_internal.h" +/**************************************************************************** + * Public Data + ****************************************************************************/ + +volatile uint8_t *g_current_regs; + /**************************************************************************** * Public Functions ****************************************************************************/ diff --git a/arch/hc/src/m9s12/m9s12_irq.c b/arch/hc/src/m9s12/m9s12_irq.c index 60c28a4485..b584c9468e 100644 --- a/arch/hc/src/m9s12/m9s12_irq.c +++ b/arch/hc/src/m9s12/m9s12_irq.c @@ -34,12 +34,6 @@ #include "up_internal.h" #include "m9s12.h" -/**************************************************************************** - * Public Data - ****************************************************************************/ - -volatile uint8_t *g_current_regs; - /**************************************************************************** * Public Functions ****************************************************************************/ @@ -50,10 +44,6 @@ volatile uint8_t *g_current_regs; void up_irqinitialize(void) { - /* currents_regs is non-NULL only while processing an interrupt */ - - g_current_regs = NULL; - /* Initialize logic to support a second level of interrupt decoding for * GPIO pins. */ diff --git a/arch/mips/src/common/mips_initialize.c b/arch/mips/src/common/mips_initialize.c index 8ea6b6642d..b4aae9a42f 100644 --- a/arch/mips/src/common/mips_initialize.c +++ b/arch/mips/src/common/mips_initialize.c @@ -28,6 +28,18 @@ #include "mips_internal.h" +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/* g_current_regs holds a references to the current interrupt level + * register storage structure. It is non-NULL only during interrupt + * processing. Access to g_current_regs must be through the macro + * CURRENT_REGS for portability. + */ + +volatile uint32_t *g_current_regs; + /**************************************************************************** * Public Functions ****************************************************************************/ diff --git a/arch/mips/src/pic32mx/pic32mx_irq.c b/arch/mips/src/pic32mx/pic32mx_irq.c index 2ef2268e28..4649a3c3e4 100644 --- a/arch/mips/src/pic32mx/pic32mx_irq.c +++ b/arch/mips/src/pic32mx/pic32mx_irq.c @@ -49,16 +49,6 @@ # error "Multi-vectors not supported" #endif -/**************************************************************************** - * Public Data - ****************************************************************************/ - -volatile uint32_t *g_current_regs; - -/**************************************************************************** - * Private Data - ****************************************************************************/ - /**************************************************************************** * Private Functions ****************************************************************************/ @@ -146,10 +136,6 @@ void up_irqinitialize(void) irq_attach(PIC32MX_IRQ_CS0, up_swint0, NULL); up_enable_irq(PIC32MX_IRQSRC_CS0); - /* currents_regs is non-NULL only while processing an interrupt */ - - CURRENT_REGS = NULL; - /* And finally, enable interrupts */ /* Interrupts are enabled by setting the IE bit in the CP0 status diff --git a/arch/mips/src/pic32mz/pic32mz_irq.c b/arch/mips/src/pic32mz/pic32mz_irq.c index fe52ca7631..65bb41ffd7 100644 --- a/arch/mips/src/pic32mz/pic32mz_irq.c +++ b/arch/mips/src/pic32mz/pic32mz_irq.c @@ -55,22 +55,6 @@ #define INT_NREGS ((NR_IRQS + 31) >> 5) -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/* g_current_regs holds a references to the current interrupt level - * register storage structure. It is non-NULL only during interrupt - * processing. Access to g_current_regs must be through the macro - * CURRENT_REGS for portability. - */ - -volatile uint32_t *g_current_regs; - -/**************************************************************************** - * Private Data - ****************************************************************************/ - /**************************************************************************** * Private Functions ****************************************************************************/ @@ -235,10 +219,6 @@ void up_irqinitialize(void) irq_attach(PIC32MZ_IRQ_CS0, up_swint0, NULL); up_enable_irq(PIC32MZ_IRQ_CS0); - /* currents_regs is non-NULL only while processing an interrupt */ - - CURRENT_REGS = NULL; - /* And finally, enable interrupts */ /* Interrupts are enabled by setting the IE bit in the CP0 status diff --git a/arch/misoc/src/common/misoc_initialize.c b/arch/misoc/src/common/misoc_initialize.c index 29daba3d02..3547c2237e 100644 --- a/arch/misoc/src/common/misoc_initialize.c +++ b/arch/misoc/src/common/misoc_initialize.c @@ -26,6 +26,12 @@ #include "misoc.h" +/**************************************************************************** + * Public Data + ****************************************************************************/ + +volatile uint32_t *g_current_regs; + /**************************************************************************** * Public Functions ****************************************************************************/ diff --git a/arch/misoc/src/lm32/lm32_irq.c b/arch/misoc/src/lm32/lm32_irq.c index 09ae3154c7..147dc91fd1 100644 --- a/arch/misoc/src/lm32/lm32_irq.c +++ b/arch/misoc/src/lm32/lm32_irq.c @@ -35,12 +35,6 @@ #include "chip.h" #include "lm32.h" -/**************************************************************************** - * Public Data - ****************************************************************************/ - -volatile uint32_t *g_current_regs; - /**************************************************************************** * Public Functions ****************************************************************************/ @@ -51,10 +45,6 @@ volatile uint32_t *g_current_regs; void up_irqinitialize(void) { - /* currents_regs is non-NULL only while processing an interrupt */ - - g_current_regs = NULL; - /* Attach the software interrupt */ irq_attach(LM32_IRQ_SWINT, lm32_swint, NULL); diff --git a/arch/misoc/src/minerva/minerva_irq.c b/arch/misoc/src/minerva/minerva_irq.c index 83ed522c4c..b1a760071b 100644 --- a/arch/misoc/src/minerva/minerva_irq.c +++ b/arch/misoc/src/minerva/minerva_irq.c @@ -35,12 +35,6 @@ #include "chip.h" #include "minerva.h" -/**************************************************************************** - * Public Data - ****************************************************************************/ - -volatile uint32_t *g_current_regs; - /**************************************************************************** * Public Functions ****************************************************************************/ @@ -51,10 +45,6 @@ volatile uint32_t *g_current_regs; void up_irqinitialize(void) { - /* currents_regs is non-NULL only while processing an interrupt */ - - g_current_regs = NULL; - /* Attach the software interrupt */ irq_attach(MINERVA_IRQ_SWINT, minerva_swint, NULL); diff --git a/arch/or1k/src/common/up_initialize.c b/arch/or1k/src/common/up_initialize.c index a0a8621599..0b418a9a6d 100644 --- a/arch/or1k/src/common/up_initialize.c +++ b/arch/or1k/src/common/up_initialize.c @@ -30,6 +30,18 @@ #include "up_internal.h" +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/* g_current_regs[] holds a references to the current interrupt level + * register storage structure. It is non-NULL only during interrupt + * processing. Access to g_current_regs[] must be through the macro + * CURRENT_REGS for portability. + */ + +volatile uint32_t *g_current_regs[CONFIG_SMP_NCPUS]; + /**************************************************************************** * Private Functions ****************************************************************************/ @@ -104,7 +116,7 @@ void up_enable_dcache(void) #if defined(CONFIG_STACK_COLORATION) && CONFIG_ARCH_INTERRUPTSTACK > 3 static inline void up_color_intstack(void) { - uint32_t *ptr = (uint32_t *)&g_intstackalloc; + uint32_t *ptr = (uint32_t *)g_intstackalloc; ssize_t size; for (size = (CONFIG_ARCH_INTERRUPTSTACK & ~3); diff --git a/arch/or1k/src/mor1kx/up_irq.c b/arch/or1k/src/mor1kx/up_irq.c index 4dbeab1924..205cd7062a 100644 --- a/arch/or1k/src/mor1kx/up_irq.c +++ b/arch/or1k/src/mor1kx/up_irq.c @@ -35,18 +35,6 @@ #include "up_internal.h" -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/* g_current_regs[] holds a references to the current interrupt level - * register storage structure. It is non-NULL only during interrupt - * processing. Access to g_current_regs[] must be through the macro - * CURRENT_REGS for portability. - */ - -volatile uint32_t *g_current_regs[1]; - /**************************************************************************** * Public Functions ****************************************************************************/ @@ -61,10 +49,6 @@ void up_irqinitialize(void) /* Set all interrupts (and exceptions) to the default priority */ - /* currents_regs is non-NULL only while processing an interrupt */ - - CURRENT_REGS = NULL; - /* And finally, enable interrupts */ up_irq_enable(); diff --git a/arch/renesas/src/common/up_initialize.c b/arch/renesas/src/common/up_initialize.c index 8320e6dd28..41accf06b8 100644 --- a/arch/renesas/src/common/up_initialize.c +++ b/arch/renesas/src/common/up_initialize.c @@ -28,6 +28,18 @@ #include "up_internal.h" +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/* This holds a references to the current interrupt level register storage + * structure. If is non-NULL only during interrupt processing. + */ + +/* Actually a pointer to the beginning of a uint8_t array */ + +volatile uint32_t *g_current_regs; + /**************************************************************************** * Public Functions ****************************************************************************/ diff --git a/arch/renesas/src/m16c/m16c_irq.c b/arch/renesas/src/m16c/m16c_irq.c index 5247ae4f1a..550ab05e1a 100644 --- a/arch/renesas/src/m16c/m16c_irq.c +++ b/arch/renesas/src/m16c/m16c_irq.c @@ -34,20 +34,12 @@ * Public Functions ****************************************************************************/ -/* This holds a references to the current interrupt level register storage - * structure. If is non-NULL only during interrupt processing. - */ - -volatile uint32_t *g_current_regs; /* Actually a pointer to the beginning of a uint8_t array */ - /**************************************************************************** * Name: up_irqinitialize ****************************************************************************/ void up_irqinitialize(void) { - g_current_regs = NULL; - /* And finally, enable interrupts */ #ifndef CONFIG_SUPPRESS_INTERRUPTS diff --git a/arch/renesas/src/rx65n/rx65n_irq.c b/arch/renesas/src/rx65n/rx65n_irq.c index b02ba9a151..668fd1e6a8 100644 --- a/arch/renesas/src/rx65n/rx65n_irq.c +++ b/arch/renesas/src/rx65n/rx65n_irq.c @@ -30,18 +30,6 @@ #include "arch/rx65n/iodefine.h" #include "up_internal.h" -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/* This holds a references to the current interrupt level register storage - * structure. If is non-NULL only during interrupt processing. - */ - -/* Actually a pointer to the beginning of a uint8_t array */ - -volatile uint32_t *g_current_regs; - /**************************************************************************** * Public Functions ****************************************************************************/ @@ -52,10 +40,6 @@ volatile uint32_t *g_current_regs; void up_irqinitialize(void) { - /* Currents_regs is non-NULL only while processing an interrupt */ - - g_current_regs = NULL; - /* Enable interrupts */ #ifndef CONFIG_SUPPRESS_INTERRUPTS diff --git a/arch/renesas/src/sh1/sh1_irq.c b/arch/renesas/src/sh1/sh1_irq.c index f4eb874e69..95ca5c8fda 100644 --- a/arch/renesas/src/sh1/sh1_irq.c +++ b/arch/renesas/src/sh1/sh1_irq.c @@ -33,12 +33,6 @@ #include "up_internal.h" #include "chip.h" -/**************************************************************************** - * Public Data - ****************************************************************************/ - -volatile uint32_t *g_current_regs; - /**************************************************************************** * Public Functions ****************************************************************************/ @@ -49,10 +43,6 @@ volatile uint32_t *g_current_regs; void up_irqinitialize(void) { - /* Currents_regs is non-NULL only while processing an interrupt */ - - g_current_regs = NULL; - /* Enable interrupts */ #ifndef CONFIG_SUPPRESS_INTERRUPTS diff --git a/arch/risc-v/src/bl602/bl602_irq.c b/arch/risc-v/src/bl602/bl602_irq.c index 1a03725f40..492d5b14e9 100644 --- a/arch/risc-v/src/bl602/bl602_irq.c +++ b/arch/risc-v/src/bl602/bl602_irq.c @@ -37,12 +37,6 @@ #include "chip.h" -/**************************************************************************** - * Public Data - ****************************************************************************/ - -volatile uintptr_t *g_current_regs[1]; - /**************************************************************************** * Private Functions ****************************************************************************/ @@ -88,10 +82,6 @@ void up_irqinitialize(void) riscv_stack_color((void *)&g_intstackalloc, intstack_size); #endif - /* currents_regs is non-NULL only while processing an interrupt */ - - CURRENT_REGS = NULL; - /* Attach the common interrupt handler */ riscv_exception_attach(); diff --git a/arch/risc-v/src/c906/c906_irq.c b/arch/risc-v/src/c906/c906_irq.c index dfdae80765..31d986ad81 100644 --- a/arch/risc-v/src/c906/c906_irq.c +++ b/arch/risc-v/src/c906/c906_irq.c @@ -35,12 +35,6 @@ #include "riscv_internal.h" #include "c906.h" -/**************************************************************************** - * Public Data - ****************************************************************************/ - -volatile uintptr_t *g_current_regs[1]; - /**************************************************************************** * Public Functions ****************************************************************************/ @@ -89,10 +83,6 @@ void up_irqinitialize(void) putreg32(0, C906_PLIC_MTHRESHOLD); - /* currents_regs is non-NULL only while processing an interrupt */ - - CURRENT_REGS = NULL; - /* Attach the common interrupt handler */ riscv_exception_attach(); diff --git a/arch/risc-v/src/common/riscv_initialize.c b/arch/risc-v/src/common/riscv_initialize.c index fc0133159f..381913b1a5 100644 --- a/arch/risc-v/src/common/riscv_initialize.c +++ b/arch/risc-v/src/common/riscv_initialize.c @@ -28,6 +28,12 @@ #include "riscv_internal.h" +/**************************************************************************** + * Public Data + ****************************************************************************/ + +volatile uintptr_t *g_current_regs[CONFIG_SMP_NCPUS]; + /**************************************************************************** * Private Functions ****************************************************************************/ diff --git a/arch/risc-v/src/esp32c3/esp32c3_irq.c b/arch/risc-v/src/esp32c3/esp32c3_irq.c index 63530261ee..de434f7f26 100644 --- a/arch/risc-v/src/esp32c3/esp32c3_irq.c +++ b/arch/risc-v/src/esp32c3/esp32c3_irq.c @@ -53,12 +53,6 @@ #define CPUINT_UNASSIGNED 0xff -/**************************************************************************** - * Public Data - ****************************************************************************/ - -volatile uintptr_t *g_current_regs[1]; - /**************************************************************************** * Private Data ****************************************************************************/ diff --git a/arch/risc-v/src/fe310/fe310_irq.c b/arch/risc-v/src/fe310/fe310_irq.c index 62e2406812..dd01fa26f9 100644 --- a/arch/risc-v/src/fe310/fe310_irq.c +++ b/arch/risc-v/src/fe310/fe310_irq.c @@ -37,12 +37,6 @@ #include "riscv_internal.h" #include "fe310.h" -/**************************************************************************** - * Public Data - ****************************************************************************/ - -volatile uintptr_t *g_current_regs[1]; - /**************************************************************************** * Public Functions ****************************************************************************/ @@ -82,10 +76,6 @@ void up_irqinitialize(void) putreg32(0, FE310_PLIC_THRESHOLD); - /* currents_regs is non-NULL only while processing an interrupt */ - - CURRENT_REGS = NULL; - /* Attach the common interrupt handler */ riscv_exception_attach(); diff --git a/arch/risc-v/src/k210/k210_irq.c b/arch/risc-v/src/k210/k210_irq.c index d09b304ce7..cd0d06efdd 100644 --- a/arch/risc-v/src/k210/k210_irq.c +++ b/arch/risc-v/src/k210/k210_irq.c @@ -35,12 +35,6 @@ #include "riscv_internal.h" #include "k210.h" -/**************************************************************************** - * Public Data - ****************************************************************************/ - -volatile uintptr_t *g_current_regs[CONFIG_SMP_NCPUS]; - /**************************************************************************** * Public Functions ****************************************************************************/ @@ -86,10 +80,6 @@ void up_irqinitialize(void) putreg32(0, K210_PLIC_THRESHOLD); - /* currents_regs is non-NULL only while processing an interrupt */ - - CURRENT_REGS = NULL; - /* Attach the common interrupt handler */ riscv_exception_attach(); diff --git a/arch/risc-v/src/litex/litex_irq.c b/arch/risc-v/src/litex/litex_irq.c index c4c1b2968a..1209c8fe07 100644 --- a/arch/risc-v/src/litex/litex_irq.c +++ b/arch/risc-v/src/litex/litex_irq.c @@ -35,12 +35,6 @@ #include "riscv_internal.h" #include "litex.h" -/**************************************************************************** - * Public Data - ****************************************************************************/ - -volatile uintptr_t *g_current_regs[1]; - /**************************************************************************** * Public Functions ****************************************************************************/ @@ -68,10 +62,6 @@ void up_irqinitialize(void) /* litex vexriscv dont have priority and threshold control */ - /* currents_regs is non-NULL only while processing an interrupt */ - - CURRENT_REGS = NULL; - /* Attach the common interrupt handler */ riscv_exception_attach(); diff --git a/arch/risc-v/src/mpfs/mpfs_irq.c b/arch/risc-v/src/mpfs/mpfs_irq.c index cff60f6d90..ddec04de7d 100644 --- a/arch/risc-v/src/mpfs/mpfs_irq.c +++ b/arch/risc-v/src/mpfs/mpfs_irq.c @@ -36,12 +36,6 @@ #include "mpfs.h" #include "mpfs_plic.h" -/**************************************************************************** - * Public Data - ****************************************************************************/ - -volatile uintptr_t *g_current_regs[1]; - /**************************************************************************** * Public Functions ****************************************************************************/ @@ -94,10 +88,6 @@ void up_irqinitialize(void) uintptr_t threshold_address = mpfs_plic_get_thresholdbase(); putreg32(0, threshold_address); - /* currents_regs is non-NULL only while processing an interrupt */ - - CURRENT_REGS = NULL; - /* Attach the common interrupt handler */ riscv_exception_attach(); diff --git a/arch/risc-v/src/qemu-rv/qemu_rv_irq.c b/arch/risc-v/src/qemu-rv/qemu_rv_irq.c index c9ea8a94bc..7f49ff7f91 100644 --- a/arch/risc-v/src/qemu-rv/qemu_rv_irq.c +++ b/arch/risc-v/src/qemu-rv/qemu_rv_irq.c @@ -35,12 +35,6 @@ #include "riscv_internal.h" #include "chip.h" -/**************************************************************************** - * Public Data - ****************************************************************************/ - -volatile uintptr_t *g_current_regs[CONFIG_SMP_NCPUS]; - /**************************************************************************** * Public Functions ****************************************************************************/ @@ -80,10 +74,6 @@ void up_irqinitialize(void) putreg32(0, QEMU_RV_PLIC_THRESHOLD); - /* currents_regs is non-NULL only while processing an interrupt */ - - CURRENT_REGS = NULL; - /* Attach the common interrupt handler */ riscv_exception_attach(); diff --git a/arch/risc-v/src/rv32m1/rv32m1_irq.c b/arch/risc-v/src/rv32m1/rv32m1_irq.c index 094db7a2da..a9dcbd7e33 100644 --- a/arch/risc-v/src/rv32m1/rv32m1_irq.c +++ b/arch/risc-v/src/rv32m1/rv32m1_irq.c @@ -37,12 +37,6 @@ #include "rv32m1.h" #include "hardware/rv32m1_eu.h" -/**************************************************************************** - * Public Data - ****************************************************************************/ - -volatile uintptr_t *g_current_regs[1]; - /**************************************************************************** * Private Functions ****************************************************************************/ @@ -115,10 +109,6 @@ void up_irqinitialize(void) irq_attach(RV32M1_IRQ_INTMUX0, rv32m1_intmuxisr, NULL); - /* currents_regs is non-NULL only while processing an interrupt */ - - CURRENT_REGS = NULL; - /* Attach the common interrupt handler */ riscv_exception_attach(); diff --git a/arch/sparc/src/bm3803/bm3803-irq.c b/arch/sparc/src/bm3803/bm3803-irq.c index 148f25ea4e..6971eeaa3f 100644 --- a/arch/sparc/src/bm3803/bm3803-irq.c +++ b/arch/sparc/src/bm3803/bm3803-irq.c @@ -37,20 +37,6 @@ #include "up_internal.h" #include "bm3803.h" -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -volatile uint32_t *g_current_regs; - -/**************************************************************************** - * Private Data - ****************************************************************************/ - /**************************************************************************** * Private Functions ****************************************************************************/ @@ -99,10 +85,6 @@ void up_irqinitialize(void) irq_attach(BM3803_IRQ_SW_SYSCALL_TA0, up_swint0, NULL); irq_attach(BM3803_IRQ_SW_SYSCALL_TA8, up_swint1, NULL); - /* currents_regs is non-NULL only while processing an interrupt */ - - g_current_regs = NULL; - /* And finally, enable interrupts */ /* Interrupts are enabled by setting the te bit in the psr status diff --git a/arch/sparc/src/bm3823/bm3823-irq.c b/arch/sparc/src/bm3823/bm3823-irq.c index 39b92fccf4..420a9e6343 100644 --- a/arch/sparc/src/bm3823/bm3823-irq.c +++ b/arch/sparc/src/bm3823/bm3823-irq.c @@ -36,20 +36,6 @@ #include "up_internal.h" #include "bm3823.h" -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -volatile uint32_t *g_current_regs; - -/**************************************************************************** - * Private Data - ****************************************************************************/ - /**************************************************************************** * Private Functions ****************************************************************************/ @@ -104,10 +90,6 @@ void up_irqinitialize(void) irq_attach(BM3823_IRQ_SW_SYSCALL_TA0, up_swint0, NULL); irq_attach(BM3823_IRQ_SW_SYSCALL_TA8, up_swint1, NULL); - /* currents_regs is non-NULL only while processing an interrupt */ - - g_current_regs = NULL; - /* And finally, enable interrupts */ /* Interrupts are enabled by setting the te bit in the psr status diff --git a/arch/sparc/src/common/up_initialize.c b/arch/sparc/src/common/up_initialize.c index 54e66eb5c3..e17136ca91 100644 --- a/arch/sparc/src/common/up_initialize.c +++ b/arch/sparc/src/common/up_initialize.c @@ -71,6 +71,12 @@ # define USE_SERIALDRIVER 1 #endif +/**************************************************************************** + * Public Data + ****************************************************************************/ + +volatile uint32_t *g_current_regs; + /**************************************************************************** * Private Functions ****************************************************************************/ diff --git a/arch/x86/src/i486/up_irq.c b/arch/x86/src/i486/up_irq.c index 70b386e7da..f8226907dd 100644 --- a/arch/x86/src/i486/up_irq.c +++ b/arch/x86/src/i486/up_irq.c @@ -246,10 +246,6 @@ static inline void up_idtinit(void) void up_irqinitialize(void) { - /* currents_regs is non-NULL only while processing an interrupt */ - - g_current_regs = NULL; - /* Initialize the IDT */ up_idtinit(); diff --git a/arch/x86_64/src/intel64/up_irq.c b/arch/x86_64/src/intel64/up_irq.c index b7e056ac07..dfe3df7e69 100644 --- a/arch/x86_64/src/intel64/up_irq.c +++ b/arch/x86_64/src/intel64/up_irq.c @@ -478,10 +478,6 @@ static inline void up_idtinit(void) void up_irqinitialize(void) { - /* currents_regs is non-NULL only while processing an interrupt */ - - g_current_regs = NULL; - /* Initialize the IST */ up_ist_init(); diff --git a/arch/xtensa/src/common/xtensa_initialize.c b/arch/xtensa/src/common/xtensa_initialize.c index d1e9c39de9..fc9d520239 100644 --- a/arch/xtensa/src/common/xtensa_initialize.c +++ b/arch/xtensa/src/common/xtensa_initialize.c @@ -28,6 +28,22 @@ #include "xtensa.h" +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/* g_current_regs[] holds a reference to the current interrupt level + * register storage structure. It is non-NULL only during interrupt + * processing. Access to g_current_regs[] must be through the macro + * CURRENT_REGS for portability. + */ + +/* For the case of architectures with multiple CPUs, then there must be one + * such value for each processor that can receive an interrupt. + */ + +volatile uint32_t *g_current_regs[CONFIG_SMP_NCPUS]; + /**************************************************************************** * Private Functions ****************************************************************************/ diff --git a/arch/xtensa/src/esp32/esp32_irq.c b/arch/xtensa/src/esp32/esp32_irq.c index 53d369bbef..616f046042 100644 --- a/arch/xtensa/src/esp32/esp32_irq.c +++ b/arch/xtensa/src/esp32/esp32_irq.c @@ -116,18 +116,6 @@ * Public Data ****************************************************************************/ -/* g_current_regs[] holds a reference to the current interrupt level - * register storage structure. It is non-NULL only during interrupt - * processing. Access to g_current_regs[] must be through the macro - * CURRENT_REGS for portability. - */ - -/* For the case of architectures with multiple CPUs, then there must be one - * such value for each processor that can receive an interrupt. - */ - -volatile uint32_t *g_current_regs[CONFIG_SMP_NCPUS]; - #if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 15 /* In the SMP configuration, we will need custom interrupt stacks. * These definitions provide the aligned stack allocations. diff --git a/arch/xtensa/src/esp32s2/esp32s2_irq.c b/arch/xtensa/src/esp32s2/esp32s2_irq.c index 6d81ab3146..cf14bb2113 100644 --- a/arch/xtensa/src/esp32s2/esp32s2_irq.c +++ b/arch/xtensa/src/esp32s2/esp32s2_irq.c @@ -80,18 +80,6 @@ #define ESP32S2_MAX_PRIORITY 5 #define ESP32S2_PRIO_INDEX(p) ((p) - ESP32S2_MIN_PRIORITY) -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/* g_current_regs[] holds a reference to the current interrupt level - * register storage structure. It is non-NULL only during interrupt - * processing. Access to g_current_regs[] must be through the macro - * CURRENT_REGS for portability. - */ - -volatile uint32_t *g_current_regs[1]; - /**************************************************************************** * Private Data ****************************************************************************/ diff --git a/arch/xtensa/src/esp32s3/esp32s3_irq.c b/arch/xtensa/src/esp32s3/esp32s3_irq.c index c9f1d8e936..ee6eea7fe1 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_irq.c +++ b/arch/xtensa/src/esp32s3/esp32s3_irq.c @@ -109,18 +109,6 @@ * Public Data ****************************************************************************/ -/* g_current_regs[] holds a reference to the current interrupt level - * register storage structure. It is non-NULL only during interrupt - * processing. Access to g_current_regs[] must be through the macro - * CURRENT_REGS for portability. - */ - -/* For the case of architectures with multiple CPUs, then there must be one - * such value for each processor that can receive an interrupt. - */ - -volatile uint32_t *g_current_regs[CONFIG_SMP_NCPUS]; - #if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 15 /* In the SMP configuration, we will need custom interrupt stacks. * These definitions provide the aligned stack allocations. diff --git a/arch/z16/src/z16f/z16f_irq.c b/arch/z16/src/z16f/z16f_irq.c index 7edf97230c..38e90bf357 100644 --- a/arch/z16/src/z16f/z16f_irq.c +++ b/arch/z16/src/z16f/z16f_irq.c @@ -53,10 +53,6 @@ void up_irqinitialize(void) putreg16(0x0000, Z16F_IRQ1_EN); putreg16(0x0000, Z16F_IRQ2_EN); - /* currents_regs is non-NULL only while processing an interrupt */ - - g_current_regs = NULL; - /* And finally, enable interrupts */ #ifndef CONFIG_SUPPRESS_INTERRUPTS diff --git a/arch/z80/src/common/z80_initialize.c b/arch/z80/src/common/z80_initialize.c index 54bbb4bb26..bf754ad958 100644 --- a/arch/z80/src/common/z80_initialize.c +++ b/arch/z80/src/common/z80_initialize.c @@ -29,6 +29,16 @@ #include "chip/switch.h" #include "z80_internal.h" +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/* This holds a references to the current interrupt level register storage + * structure. If is non-NULL only during interrupt processing. + */ + +volatile FAR chipreg_t *g_current_regs; + /**************************************************************************** * Public Functions ****************************************************************************/ diff --git a/arch/z80/src/ez80/ez80_irq.c b/arch/z80/src/ez80/ez80_irq.c index 1b4b9cd2aa..a1c3c6397e 100644 --- a/arch/z80/src/ez80/ez80_irq.c +++ b/arch/z80/src/ez80/ez80_irq.c @@ -30,16 +30,6 @@ #include "chip/switch.h" #include "z80_internal.h" -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/* This holds a references to the current interrupt level register storage - * structure. If is non-NULL only during interrupt processing. - */ - -volatile chipreg_t *g_current_regs; - /**************************************************************************** * Public Functions ****************************************************************************/ @@ -50,8 +40,6 @@ volatile chipreg_t *g_current_regs; void up_irqinitialize(void) { - g_current_regs = NULL; - /* And finally, enable interrupts */ #ifndef CONFIG_SUPPRESS_INTERRUPTS diff --git a/arch/z80/src/z180/z180_irq.c b/arch/z80/src/z180/z180_irq.c index d419281a4f..acb2193b49 100644 --- a/arch/z80/src/z180/z180_irq.c +++ b/arch/z80/src/z180/z180_irq.c @@ -39,12 +39,6 @@ * Public Data ****************************************************************************/ -/* This holds a references to the current interrupt level register storage - * structure. If is non-NULL only during interrupt processing. - */ - -volatile chipreg_t *g_current_regs; - /* This holds the value of the MMU's CBR register. This value is set to the * interrupted tasks's CBR on interrupt entry, changed to the new task's CBR * if an interrupt level context switch occurs, and restored on interrupt diff --git a/arch/z80/src/z80/z80_irq.c b/arch/z80/src/z80/z80_irq.c index 906990d78d..1e510ce611 100644 --- a/arch/z80/src/z80/z80_irq.c +++ b/arch/z80/src/z80/z80_irq.c @@ -29,16 +29,6 @@ #include "chip/switch.h" #include "z80_internal.h" -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/* This holds a references to the current interrupt level register storage - * structure. If is non-NULL only during interrupt processing. - */ - -volatile chipreg_t *g_current_regs; - /**************************************************************************** * Public Functions ****************************************************************************/ diff --git a/boards/arm/imxrt/imxrt1050-evk/src/imxrt_flexspi_nor_boot.h b/boards/arm/imxrt/imxrt1050-evk/src/imxrt_flexspi_nor_boot.h index 6551b17404..8f37895b54 100644 --- a/boards/arm/imxrt/imxrt1050-evk/src/imxrt_flexspi_nor_boot.h +++ b/boards/arm/imxrt/imxrt1050-evk/src/imxrt_flexspi_nor_boot.h @@ -63,7 +63,7 @@ #define SCLK 1 #ifdef CONFIG_IMXRT1050_EVK_SDRAM -# define DCD_ADDRESS &g_dcd_data +# define DCD_ADDRESS g_dcd_data #else # define DCD_ADDRESS 0 #endif diff --git a/boards/arm/imxrt/imxrt1064-evk/src/imxrt_flexspi_nor_boot.h b/boards/arm/imxrt/imxrt1064-evk/src/imxrt_flexspi_nor_boot.h index f9f9117baf..d8e4e93e9a 100644 --- a/boards/arm/imxrt/imxrt1064-evk/src/imxrt_flexspi_nor_boot.h +++ b/boards/arm/imxrt/imxrt1064-evk/src/imxrt_flexspi_nor_boot.h @@ -85,7 +85,7 @@ #define LOCATE_IN_SRC(x) (((uint32_t)(x)) - IMAGE_DEST + FLASH_BASE) #ifdef CONFIG_IMXRT1064_EVK_SDRAM -# define DCD_ADDRESS &g_dcd_data +# define DCD_ADDRESS g_dcd_data #else # define DCD_ADDRESS 0 #endif