arm64->fetal: Support return to thread site

The breakpoint of arm64 is fetal_handler, which needs to return to the scene

Signed-off-by: wangmingrong1 <wangmingrong1@xiaomi.com>
This commit is contained in:
wangmingrong1 2025-06-24 15:22:03 +08:00 committed by Xiang Xiao
parent 10a13b98ee
commit 3c2b203286
3 changed files with 8 additions and 4 deletions

View file

@ -548,7 +548,7 @@ static int arm64_exception_handler(uint64_t *regs)
* Public Functions
****************************************************************************/
void arm64_fatal_handler(uint64_t *regs)
uint64_t *arm64_fatal_handler(uint64_t *regs)
{
struct tcb_s *tcb = this_task();
int ret;
@ -575,6 +575,8 @@ void arm64_fatal_handler(uint64_t *regs)
/* Clear irq flag */
write_sysreg((uintptr_t)tcb & ~1ul, tpidr_el1);
return regs;
}
void arm64_register_debug_hook(int nr, fatal_handle_func_t fn)

View file

@ -182,12 +182,12 @@ typedef int (*fatal_handle_func_t)(uint64_t *regs, uint64_t far,
* Input Parameters:
* reg: exception stack reg context
*
* Returned Value: None
* Returned Value: regs
* If the function return, the exception has been handled
*
****************************************************************************/
void arm64_fatal_handler(uint64_t *reg);
uint64_t *arm64_fatal_handler(uint64_t *reg);
/****************************************************************************
* Name: arm64_register_debug_hook

View file

@ -200,7 +200,9 @@ reserved_syscall:
mov x0, sp
adrp x5, arm64_fatal_handler
add x5, x5, #:lo12:arm64_fatal_handler
br x5
blr x5
mov sp, x0
b arm64_exit_exception
/****************************************************************************
* Name: arm64_irq_handler