From 3ce85ca54e100050a5dedcda611bd5f0c573e548 Mon Sep 17 00:00:00 2001 From: Lars Kruse Date: Sat, 3 May 2025 06:16:30 +0200 Subject: [PATCH] style: fix spelling in code comments and strings --- .codespell-ignore-lines | 154 ++++++++++++++++++ .codespellrc | 24 ++- CMakeLists.txt | 8 +- CONTRIBUTING.md | 8 +- Documentation/ReleaseNotes/NuttX-7.19 | 2 +- LICENSE | 2 +- arch/Kconfig | 6 +- arch/arm/include/dm320/irq.h | 2 +- arch/arm/include/gd32f4/gd32f4xx_irq.h | 2 +- arch/arm/include/gd32f4/irq.h | 2 +- arch/arm/include/kinetis/chip.h | 12 +- arch/arm/include/mx8mp/mx8mp_irq.h | 2 +- arch/arm/include/s32k3xx/s32k3x4_irq.h | 8 +- arch/arm/include/stm32/stm32g4xxxx_irq.h | 2 +- arch/arm/src/a1x/a1x_serial.c | 2 +- arch/arm/src/am335x/am335x_i2c.c | 2 +- arch/arm/src/am335x/am335x_serial.c | 2 +- arch/arm/src/arm/arm_allocpage.c | 6 +- arch/arm/src/arm/arm_syscall.c | 2 +- arch/arm/src/armv6-m/arm_ramvec_attach.c | 2 +- arch/arm/src/armv7-a/Kconfig | 2 +- arch/arm/src/armv7-a/arm_allocpage.c | 6 +- arch/arm/src/armv7-a/arm_smpcall.c | 2 +- arch/arm/src/armv7-a/arm_syscall.c | 2 +- arch/arm/src/armv7-a/arm_vectors.S | 2 +- arch/arm/src/armv7-a/gic.h | 2 +- arch/arm/src/armv7-m/arm_exception.S | 2 +- arch/arm/src/armv7-m/arm_ramvec_attach.c | 2 +- arch/arm/src/armv7-m/etm.h | 2 +- arch/arm/src/armv7-m/nvic.h | 2 +- arch/arm/src/armv7-r/arm_mpu.c | 2 +- arch/arm/src/armv7-r/arm_smpcall.c | 2 +- arch/arm/src/armv7-r/arm_syscall.c | 2 +- arch/arm/src/armv7-r/gic.h | 2 +- arch/arm/src/armv7-r/mpu.h | 4 +- arch/arm/src/armv7-r/scu.h | 2 +- arch/arm/src/armv8-m/arm_exception.S | 2 +- arch/arm/src/armv8-m/arm_gen_nonsecfault.c | 8 +- arch/arm/src/armv8-m/arm_ramvec_attach.c | 2 +- arch/arm/src/armv8-m/etm.h | 4 +- arch/arm/src/armv8-m/nvic.h | 2 +- arch/arm/src/armv8-r/arm_syscall.c | 2 +- arch/arm/src/at32/Kconfig | 48 +++--- arch/arm/src/at32/at32_eth.c | 8 +- arch/arm/src/at32/at32_i2c.c | 2 +- arch/arm/src/at32/at32_otgfsdev.c | 6 +- arch/arm/src/at32/at32_otgfshost.c | 2 +- arch/arm/src/at32/at32_pwm.c | 8 +- arch/arm/src/at32/at32_sdio.c | 2 +- arch/arm/src/at32/at32_serial.c | 4 +- arch/arm/src/at32/hardware/at32f43xxx_rcc.h | 2 +- arch/arm/src/c5471/c5471_irq.c | 2 +- arch/arm/src/c5471/c5471_serial.c | 2 +- arch/arm/src/c5471/chip.h | 2 +- arch/arm/src/common/arm_backtrace_sp.c | 2 +- arch/arm/src/common/arm_backtrace_unwind.c | 2 +- arch/arm/src/csk6/csk6_serial.c | 2 +- arch/arm/src/cxd32xx/cxd32_serial.c | 4 +- arch/arm/src/cxd32xx/cxd32_timerisr.c | 4 +- arch/arm/src/cxd32xx/cxd32_uart.c | 2 +- arch/arm/src/cxd32xx/hardware/cxd32_timer.h | 2 +- arch/arm/src/cxd56xx/Kconfig | 4 +- arch/arm/src/cxd56xx/cxd56_clock.c | 2 +- arch/arm/src/cxd56xx/cxd56_cpu1signal.h | 2 +- arch/arm/src/cxd56xx/cxd56_nxaudio.h | 2 +- arch/arm/src/cxd56xx/cxd56_pwm.c | 2 +- arch/arm/src/cxd56xx/cxd56_rtc.c | 2 +- arch/arm/src/cxd56xx/cxd56_sdhci.c | 2 +- arch/arm/src/cxd56xx/cxd56_sdhci.h | 2 +- arch/arm/src/cxd56xx/cxd56_serial.c | 2 +- arch/arm/src/cxd56xx/cxd56_usbdev.c | 6 +- .../src/cxd56xx/hardware/cxd5602_pinconfig.h | 2 +- arch/arm/src/dm320/dm320_framebuffer.c | 2 +- arch/arm/src/dm320/dm320_serial.c | 2 +- arch/arm/src/dm320/dm320_usbdev.c | 4 +- arch/arm/src/efm32/efm32_i2c.c | 2 +- arch/arm/src/efm32/efm32_leserial.c | 2 +- arch/arm/src/efm32/efm32_serial.c | 2 +- arch/arm/src/efm32/efm32_usbdev.c | 4 +- arch/arm/src/efm32/efm32_usbhost.c | 2 +- arch/arm/src/eoss3/eoss3_serial.c | 2 +- arch/arm/src/gd32f4/gd32f4xx_dma.c | 4 +- arch/arm/src/gd32f4/gd32f4xx_dma.h | 2 +- arch/arm/src/gd32f4/gd32f4xx_enet.c | 10 +- arch/arm/src/gd32f4/gd32f4xx_gpio.c | 2 +- arch/arm/src/gd32f4/gd32f4xx_i2c.c | 2 +- arch/arm/src/gd32f4/gd32f4xx_sdio.c | 2 +- arch/arm/src/gd32f4/gd32f4xx_serial.c | 10 +- arch/arm/src/gd32f4/gd32f4xx_spi.c | 2 +- arch/arm/src/gd32f4/gd32f4xx_syscfg.c | 2 +- arch/arm/src/gd32f4/gd32f4xx_usart.h | 4 +- arch/arm/src/gd32f4/hardware/gd32f4xx_dma.h | 2 +- arch/arm/src/gd32f4/hardware/gd32f4xx_enet.h | 8 +- arch/arm/src/gd32f4/hardware/gd32f4xx_gpio.h | 24 +-- arch/arm/src/goldfish/chip.h | 2 +- arch/arm/src/imx1/imx_serial.c | 2 +- arch/arm/src/imx1/imx_uart.h | 4 +- arch/arm/src/imx6/chip.h | 2 +- arch/arm/src/imx6/hardware/imx_enet.h | 4 +- arch/arm/src/imx6/imx_enet.c | 2 +- arch/arm/src/imx6/imx_iomuxc.c | 4 +- arch/arm/src/imx6/imx_lowputc.c | 4 +- arch/arm/src/imx6/imx_serial.c | 2 +- arch/arm/src/imx6/imx_serial.h | 4 +- arch/arm/src/imx9/Kconfig | 2 +- arch/arm/src/imx9/hardware/imx9_lpit.h | 2 +- arch/arm/src/imx9/imx9_clockconfig.c | 2 +- arch/arm/src/imx9/imx9_edma.h | 2 +- arch/arm/src/imx9/imx9_flexcan.c | 8 +- arch/arm/src/imx9/imx9_lowputc.c | 2 +- arch/arm/src/imx9/imx9_lpi2c.c | 4 +- arch/arm/src/imx9/imx9_lpspi.c | 2 +- arch/arm/src/imx9/imx9_lpspi.h | 2 +- arch/arm/src/imx9/imx9_lpuart.c | 4 +- arch/arm/src/imxrt/Kconfig | 4 +- arch/arm/src/imxrt/hardware/imxrt_enet.h | 4 +- arch/arm/src/imxrt/hardware/imxrt_flexcan.h | 4 +- arch/arm/src/imxrt/hardware/imxrt_snvs.h | 2 +- .../src/imxrt/hardware/rt117x/imxrt117x_ccm.h | 8 +- .../imxrt/hardware/rt117x/imxrt117x_dcdc.h | 2 +- .../src/imxrt/hardware/rt117x/imxrt117x_gpc.h | 106 ++++++------ .../imxrt/hardware/rt117x/imxrt117x_iomuxc.h | 10 +- .../imxrt/hardware/rt117x/imxrt117x_ocotp.h | 16 +- arch/arm/src/imxrt/imxrt_adc_ver1.c | 4 +- arch/arm/src/imxrt/imxrt_clockconfig_ver2.c | 4 +- arch/arm/src/imxrt/imxrt_edma.h | 2 +- arch/arm/src/imxrt/imxrt_ehci.c | 4 +- arch/arm/src/imxrt/imxrt_enc.c | 4 +- arch/arm/src/imxrt/imxrt_enet.c | 6 +- arch/arm/src/imxrt/imxrt_flexcan.c | 8 +- arch/arm/src/imxrt/imxrt_flexspi.c | 4 +- arch/arm/src/imxrt/imxrt_iomuxc_ver1.c | 4 +- arch/arm/src/imxrt/imxrt_lowputc.c | 4 +- arch/arm/src/imxrt/imxrt_lpi2c.c | 4 +- arch/arm/src/imxrt/imxrt_serial.c | 6 +- arch/arm/src/imxrt/imxrt_serial.h | 2 +- arch/arm/src/imxrt/imxrt_start.h | 2 +- arch/arm/src/imxrt/imxrt_tickless.c | 6 +- arch/arm/src/imxrt/imxrt_usbdev.c | 6 +- arch/arm/src/imxrt/imxrt_usdhc.c | 6 +- arch/arm/src/kinetis/hardware/kinetis_enet.h | 2 +- arch/arm/src/kinetis/hardware/kinetis_usbhs.h | 2 +- .../arm/src/kinetis/hardware/kinetis_usbotg.h | 2 +- arch/arm/src/kinetis/kinetis.h | 8 +- arch/arm/src/kinetis/kinetis_edma.h | 2 +- arch/arm/src/kinetis/kinetis_i2c.c | 2 +- arch/arm/src/kinetis/kinetis_lpserial.c | 2 +- arch/arm/src/kinetis/kinetis_rtc.c | 2 +- arch/arm/src/kinetis/kinetis_sdhc.c | 2 +- arch/arm/src/kinetis/kinetis_serial.c | 2 +- arch/arm/src/kinetis/kinetis_serialinit.c | 2 +- arch/arm/src/kinetis/kinetis_usbhshost.c | 4 +- arch/arm/src/kl/kl_serial.c | 2 +- arch/arm/src/kl/kl_spi.c | 2 +- arch/arm/src/kl/kl_start.c | 2 +- arch/arm/src/lc823450/lc823450_adc.c | 2 +- arch/arm/src/lc823450/lc823450_dma.c | 2 +- arch/arm/src/lc823450/lc823450_i2c.c | 2 +- arch/arm/src/lc823450/lc823450_serial.c | 2 +- arch/arm/src/lc823450/lc823450_spi.h | 2 +- arch/arm/src/lc823450/lc823450_timer.c | 4 +- .../src/lpc17xx_40xx/hardware/lpc17_40_can.h | 4 +- .../src/lpc17xx_40xx/hardware/lpc17_40_lcd.h | 8 +- .../src/lpc17xx_40xx/hardware/lpc17_40_usb.h | 2 +- .../src/lpc17xx_40xx/lpc176x_clockconfig.c | 2 +- arch/arm/src/lpc17xx_40xx/lpc176x_gpio.c | 2 +- arch/arm/src/lpc17xx_40xx/lpc176x_gpio.h | 2 +- arch/arm/src/lpc17xx_40xx/lpc178x_40xx_gpio.c | 2 +- arch/arm/src/lpc17xx_40xx/lpc178x_40xx_gpio.h | 2 +- arch/arm/src/lpc17xx_40xx/lpc17_40_gpdma.h | 2 +- arch/arm/src/lpc17xx_40xx/lpc17_40_sdcard.c | 2 +- arch/arm/src/lpc17xx_40xx/lpc17_40_serial.c | 2 +- arch/arm/src/lpc17xx_40xx/lpc17_40_spi.c | 2 +- arch/arm/src/lpc17xx_40xx/lpc17_40_usbdev.c | 2 +- arch/arm/src/lpc17xx_40xx/lpc17_40_usbhost.c | 2 +- arch/arm/src/lpc214x/lpc214x_serial.c | 4 +- arch/arm/src/lpc214x/lpc214x_spi.h | 2 +- arch/arm/src/lpc214x/lpc214x_usbdev.c | 2 +- arch/arm/src/lpc2378/chip.h | 2 +- arch/arm/src/lpc2378/lpc23xx_pllsetup.c | 2 +- arch/arm/src/lpc2378/lpc23xx_serial.c | 4 +- arch/arm/src/lpc31xx/lpc31_cgudrvr.h | 2 +- arch/arm/src/lpc31xx/lpc31_ehci.c | 4 +- arch/arm/src/lpc31xx/lpc31_esrndx.c | 2 +- arch/arm/src/lpc31xx/lpc31_i2s.h | 4 +- arch/arm/src/lpc31xx/lpc31_lowputc.c | 2 +- arch/arm/src/lpc31xx/lpc31_serial.c | 4 +- arch/arm/src/lpc31xx/lpc31_spi.c | 2 +- .../hardware/lpc4310203050_pinconfig.h | 4 +- arch/arm/src/lpc43xx/lpc43_ehci.c | 4 +- arch/arm/src/lpc43xx/lpc43_ethernet.c | 4 +- arch/arm/src/lpc43xx/lpc43_sdmmc.c | 2 +- arch/arm/src/lpc43xx/lpc43_serial.c | 2 +- arch/arm/src/lpc43xx/lpc43_spi.c | 2 +- arch/arm/src/lpc54xx/hardware/lpc54_gpio.h | 4 +- arch/arm/src/lpc54xx/hardware/lpc54_lcd.h | 8 +- arch/arm/src/lpc54xx/lpc54_emc.h | 2 +- arch/arm/src/lpc54xx/lpc54_ethernet.c | 4 +- arch/arm/src/lpc54xx/lpc54_gpio.c | 2 +- arch/arm/src/lpc54xx/lpc54_gpio.h | 2 +- arch/arm/src/lpc54xx/lpc54_gpioirq.c | 4 +- arch/arm/src/lpc54xx/lpc54_i2c_master.c | 2 +- arch/arm/src/lpc54xx/lpc54_rng.c | 2 +- arch/arm/src/lpc54xx/lpc54_sdmmc.c | 2 +- arch/arm/src/lpc54xx/lpc54_serial.c | 2 +- arch/arm/src/lpc54xx/lpc54_serial.h | 2 +- arch/arm/src/lpc54xx/lpc54_usb0_ohci.c | 2 +- arch/arm/src/max326xx/common/max326_start.c | 2 +- .../src/max326xx/max32660/max32660_serial.c | 2 +- .../src/max326xx/max32690/max32690_gpioirq.c | 2 +- arch/arm/src/max326xx/max326_serial.h | 2 +- arch/arm/src/mcx-nxxx/nxxx_lowputc.c | 2 +- arch/arm/src/mcx-nxxx/nxxx_lpuart.c | 4 +- arch/arm/src/mps/mps_serial.c | 2 +- arch/arm/src/mx8mp/hardware/mx8mp_ccm.h | 4 +- arch/arm/src/mx8mp/mx8mp_config.h | 4 +- arch/arm/src/mx8mp/mx8mp_ecspi.c | 2 +- arch/arm/src/mx8mp/mx8mp_i2c.c | 2 +- arch/arm/src/mx8mp/mx8mp_iomuxc.h | 2 +- arch/arm/src/mx8mp/mx8mp_serial.c | 2 +- arch/arm/src/nrf52/hardware/nrf52_clock.h | 2 +- arch/arm/src/nrf52/nrf52_adc.c | 2 +- arch/arm/src/nrf52/nrf52_gpio.c | 2 +- arch/arm/src/nrf52/nrf52_gpiote.c | 2 +- arch/arm/src/nrf52/nrf52_gpiote.h | 2 +- arch/arm/src/nrf52/nrf52_ieee802154.c | 4 +- arch/arm/src/nrf52/nrf52_ieee802154_radio.c | 24 +-- arch/arm/src/nrf52/nrf52_ieee802154_radio.h | 4 +- arch/arm/src/nrf52/nrf52_ieee802154_rtc.c | 8 +- arch/arm/src/nrf52/nrf52_ieee802154_rtc.h | 2 +- arch/arm/src/nrf52/nrf52_ieee802154_tim.c | 8 +- arch/arm/src/nrf52/nrf52_ieee802154_tim.h | 4 +- arch/arm/src/nrf52/nrf52_ieee802154_trace.h | 2 +- arch/arm/src/nrf52/nrf52_radio.c | 4 +- arch/arm/src/nrf52/nrf52_radio.h | 4 +- arch/arm/src/nrf52/nrf52_serial.c | 2 +- arch/arm/src/nrf52/nrf52_serial.h | 2 +- arch/arm/src/nrf52/nrf52_usbd.c | 18 +- arch/arm/src/nrf53/hardware/nrf53_clock.h | 2 +- arch/arm/src/nrf53/hardware/nrf53_usbreg.h | 6 +- arch/arm/src/nrf53/nrf53_adc.c | 2 +- arch/arm/src/nrf53/nrf53_flash.c | 4 +- arch/arm/src/nrf53/nrf53_gpio.c | 4 +- arch/arm/src/nrf53/nrf53_gpio.h | 2 +- arch/arm/src/nrf53/nrf53_gpiote.c | 8 +- arch/arm/src/nrf53/nrf53_gpiote.h | 2 +- arch/arm/src/nrf53/nrf53_oscconfig.c | 2 +- arch/arm/src/nrf53/nrf53_rptun.c | 2 +- arch/arm/src/nrf53/nrf53_serial.c | 2 +- arch/arm/src/nrf53/nrf53_serial.h | 2 +- arch/arm/src/nrf53/nrf53_usbd.c | 18 +- arch/arm/src/nrf91/Kconfig | 4 +- arch/arm/src/nrf91/hardware/nrf91_clock.h | 2 +- arch/arm/src/nrf91/nrf91_flash.c | 4 +- arch/arm/src/nrf91/nrf91_gpio.c | 2 +- arch/arm/src/nrf91/nrf91_modem_at.c | 2 +- arch/arm/src/nrf91/nrf91_serial.c | 2 +- arch/arm/src/nrf91/nrf91_serial.h | 2 +- arch/arm/src/nuc1xx/nuc_serial.c | 2 +- arch/arm/src/nuc1xx/nuc_start.c | 2 +- arch/arm/src/phy62xx/ble/ble_controller.h | 4 +- arch/arm/src/phy62xx/error.h | 8 +- arch/arm/src/phy62xx/flash.h | 2 +- arch/arm/src/phy62xx/gpio.c | 2 +- arch/arm/src/phy62xx/jump_table.c | 2 +- arch/arm/src/phy62xx/phy62xx_ble.c | 4 +- arch/arm/src/phy62xx/phyplus_gpio.c | 2 +- arch/arm/src/phy62xx/phyplus_tim.h | 2 +- arch/arm/src/phy62xx/pplus_mtd_flash.c | 4 +- arch/arm/src/phy62xx/pwrmgr.c | 2 +- arch/arm/src/qemu/chip.h | 2 +- arch/arm/src/ra4/ra_serial.c | 2 +- arch/arm/src/rp2040/rp2040_config.h | 4 +- arch/arm/src/rp2040/rp2040_pio.h | 2 +- arch/arm/src/rp2040/rp2040_serial.c | 2 +- arch/arm/src/rp2040/rp2040_ws2812.pio | 2 +- .../src/rp23xx/hardware/rp23xx_usbctrl_regs.h | 8 +- arch/arm/src/rp23xx/rp23xx_config.h | 4 +- arch/arm/src/rp23xx/rp23xx_pio.h | 2 +- arch/arm/src/rp23xx/rp23xx_ws2812.pio | 2 +- arch/arm/src/rtl8720c/ameba_uart.c | 2 +- arch/arm/src/rtl8720c/amebaz_hci_board.c | 8 +- arch/arm/src/s32k1xx/Kconfig | 2 +- arch/arm/src/s32k1xx/hardware/s32k1xx_enet.h | 4 +- arch/arm/src/s32k1xx/hardware/s32k1xx_ftm.h | 16 +- arch/arm/src/s32k1xx/s32k1xx_clockconfig.c | 8 +- arch/arm/src/s32k1xx/s32k1xx_edma.h | 2 +- arch/arm/src/s32k1xx/s32k1xx_eeeprom.c | 2 +- arch/arm/src/s32k1xx/s32k1xx_lowputc.c | 2 +- arch/arm/src/s32k1xx/s32k1xx_lpi2c.c | 4 +- arch/arm/src/s32k1xx/s32k1xx_progmem.c | 6 +- arch/arm/src/s32k1xx/s32k1xx_serial.c | 6 +- arch/arm/src/s32k1xx/s32k1xx_serial.h | 2 +- arch/arm/src/s32k3xx/Kconfig | 4 +- arch/arm/src/s32k3xx/hardware/s32k3xx_emac.h | 8 +- arch/arm/src/s32k3xx/hardware/s32k3xx_fxosc.h | 2 +- arch/arm/src/s32k3xx/hardware/s32k3xx_mscm.h | 2 +- arch/arm/src/s32k3xx/hardware/s32k3xx_qspi.h | 2 +- arch/arm/src/s32k3xx/hardware/s32k3xx_sxosc.h | 2 +- arch/arm/src/s32k3xx/s32k3xx_clockconfig.c | 2 +- arch/arm/src/s32k3xx/s32k3xx_edma.h | 2 +- arch/arm/src/s32k3xx/s32k3xx_emac.c | 6 +- arch/arm/src/s32k3xx/s32k3xx_lowputc.c | 2 +- arch/arm/src/s32k3xx/s32k3xx_lpi2c.c | 4 +- arch/arm/src/s32k3xx/s32k3xx_pin.h | 4 +- arch/arm/src/s32k3xx/s32k3xx_qspi.c | 2 +- arch/arm/src/s32k3xx/s32k3xx_serial.c | 4 +- arch/arm/src/s32k3xx/s32k3xx_serial.h | 2 +- arch/arm/src/sam34/hardware/sam4cm_supc.h | 2 +- arch/arm/src/sam34/hardware/sam_dmac.h | 2 +- arch/arm/src/sam34/hardware/sam_supc.h | 2 +- arch/arm/src/sam34/sam4cm_tc.c | 2 +- arch/arm/src/sam34/sam4l_clockconfig.c | 8 +- arch/arm/src/sam34/sam_dmac.c | 4 +- arch/arm/src/sam34/sam_emac.c | 4 +- arch/arm/src/sam34/sam_serial.c | 2 +- arch/arm/src/sam34/sam_spi.c | 2 +- arch/arm/src/sam34/sam_udp.c | 2 +- arch/arm/src/sama5/hardware/sam_dmac.h | 2 +- arch/arm/src/sama5/sam_adc.c | 6 +- arch/arm/src/sama5/sam_can.c | 6 +- arch/arm/src/sama5/sam_classd.c | 2 +- arch/arm/src/sama5/sam_dbgu.c | 4 +- arch/arm/src/sama5/sam_dbgu.h | 2 +- arch/arm/src/sama5/sam_dmac.c | 6 +- arch/arm/src/sama5/sam_ehci.c | 4 +- arch/arm/src/sama5/sam_emaca.c | 4 +- arch/arm/src/sama5/sam_emacb.c | 2 +- arch/arm/src/sama5/sam_flexcom_serial.c | 2 +- arch/arm/src/sama5/sam_flexcom_spi.c | 4 +- arch/arm/src/sama5/sam_gmac.c | 4 +- arch/arm/src/sama5/sam_hsmci.c | 4 +- arch/arm/src/sama5/sam_lcd.c | 2 +- arch/arm/src/sama5/sam_nand.c | 2 +- arch/arm/src/sama5/sam_nand.h | 2 +- arch/arm/src/sama5/sam_pwm.c | 2 +- arch/arm/src/sama5/sam_qspi.c | 2 +- arch/arm/src/sama5/sam_sdmmc.c | 2 +- arch/arm/src/sama5/sam_serial.c | 2 +- arch/arm/src/sama5/sam_serial.h | 6 +- arch/arm/src/sama5/sam_serialinit.c | 2 +- arch/arm/src/sama5/sam_spi.c | 2 +- arch/arm/src/sama5/sam_ssc.c | 2 +- arch/arm/src/sama5/sam_tc.c | 2 +- arch/arm/src/sama5/sam_tsd.c | 6 +- arch/arm/src/sama5/sam_udphs.c | 2 +- arch/arm/src/sama5/sam_wdt.c | 2 +- arch/arm/src/sama5/sam_xdmac.c | 4 +- arch/arm/src/samd2l2/hardware/samd_dmac.h | 8 +- arch/arm/src/samd2l2/hardware/saml_dmac.h | 6 +- arch/arm/src/samd2l2/hardware/saml_eic.h | 4 +- arch/arm/src/samd2l2/hardware/saml_evsys.h | 4 +- .../arm/src/samd2l2/hardware/saml_i2c_slave.h | 2 +- arch/arm/src/samd2l2/hardware/saml_pm.h | 2 +- arch/arm/src/samd2l2/hardware/saml_supc.h | 4 +- arch/arm/src/samd2l2/hardware/saml_wdt.h | 4 +- arch/arm/src/samd2l2/sam_serial.c | 2 +- arch/arm/src/samd2l2/sam_spi.c | 2 +- arch/arm/src/samd2l2/sam_start.c | 2 +- arch/arm/src/samd2l2/sam_usb.c | 6 +- arch/arm/src/samd5e5/hardware/sam_dmac.h | 8 +- arch/arm/src/samd5e5/hardware/sam_eic.h | 2 +- arch/arm/src/samd5e5/hardware/sam_i2c_slave.h | 2 +- arch/arm/src/samd5e5/hardware/sam_supc.h | 2 +- arch/arm/src/samd5e5/hardware/sam_wdt.h | 4 +- arch/arm/src/samd5e5/sam_gmac.c | 4 +- arch/arm/src/samd5e5/sam_oneshot.h | 2 +- arch/arm/src/samd5e5/sam_oneshot_lowerhalf.c | 2 +- arch/arm/src/samd5e5/sam_serial.c | 2 +- arch/arm/src/samd5e5/sam_spi.c | 2 +- arch/arm/src/samd5e5/sam_usb.c | 16 +- arch/arm/src/samv7/hardware/sam_supc.h | 2 +- arch/arm/src/samv7/sam_1wire.c | 2 +- arch/arm/src/samv7/sam_emac.c | 2 +- arch/arm/src/samv7/sam_ethernet.h | 2 +- arch/arm/src/samv7/sam_hsmci.c | 2 +- arch/arm/src/samv7/sam_lin_sock.c | 2 +- arch/arm/src/samv7/sam_mcan.c | 12 +- arch/arm/src/samv7/sam_pwm.c | 6 +- arch/arm/src/samv7/sam_qencoder.c | 4 +- arch/arm/src/samv7/sam_qspi.c | 2 +- arch/arm/src/samv7/sam_rswdt.c | 2 +- arch/arm/src/samv7/sam_serial.c | 6 +- arch/arm/src/samv7/sam_spi.c | 2 +- arch/arm/src/samv7/sam_spi_slave.c | 4 +- arch/arm/src/samv7/sam_ssc.c | 2 +- arch/arm/src/samv7/sam_tc.c | 2 +- arch/arm/src/samv7/sam_usbdevhs.c | 2 +- arch/arm/src/samv7/sam_wdt.c | 2 +- arch/arm/src/samv7/sam_xdmac.c | 6 +- arch/arm/src/stm32/Kconfig | 54 +++--- arch/arm/src/stm32/hardware/stm32_adc_v2g4.h | 2 +- arch/arm/src/stm32/hardware/stm32_otghs.h | 2 +- arch/arm/src/stm32/hardware/stm32_tim_v1v2.h | 2 +- arch/arm/src/stm32/hardware/stm32_tim_v3.h | 2 +- arch/arm/src/stm32/stm32_1wire.c | 2 +- arch/arm/src/stm32/stm32_capture.h | 2 +- arch/arm/src/stm32/stm32_capture_lowerhalf.c | 8 +- arch/arm/src/stm32/stm32_cordic.c | 2 +- arch/arm/src/stm32/stm32_dma2d.c | 2 +- arch/arm/src/stm32/stm32_dma_v1.c | 2 +- arch/arm/src/stm32/stm32_dma_v2.c | 2 +- arch/arm/src/stm32/stm32_fdcan.c | 14 +- arch/arm/src/stm32/stm32_fdcan_sock.c | 10 +- arch/arm/src/stm32/stm32_i2c.c | 2 +- arch/arm/src/stm32/stm32_i2c_alt.c | 2 +- arch/arm/src/stm32/stm32_i2c_v2.c | 2 +- arch/arm/src/stm32/stm32_i2s.c | 2 +- arch/arm/src/stm32/stm32_ltdc.c | 4 +- arch/arm/src/stm32/stm32_otgfsdev.c | 6 +- arch/arm/src/stm32/stm32_otgfshost.c | 2 +- arch/arm/src/stm32/stm32_otghsdev.c | 6 +- arch/arm/src/stm32/stm32_otghshost.c | 2 +- arch/arm/src/stm32/stm32_pwm.c | 8 +- arch/arm/src/stm32/stm32_qencoder.c | 2 +- arch/arm/src/stm32/stm32_sdio.c | 2 +- arch/arm/src/stm32/stm32_serial.c | 4 +- arch/arm/src/stm32/stm32f30xxx_rcc.c | 2 +- arch/arm/src/stm32/stm32f40xxx_i2c.c | 2 +- arch/arm/src/stm32f0l0g0/hardware/stm32_crc.h | 2 +- arch/arm/src/stm32f0l0g0/hardware/stm32_crs.h | 2 +- arch/arm/src/stm32f0l0g0/hardware/stm32_tim.h | 2 +- arch/arm/src/stm32f0l0g0/stm32_adc.c | 2 +- arch/arm/src/stm32f0l0g0/stm32_dma_v1.c | 2 +- arch/arm/src/stm32f0l0g0/stm32_hsi48.c | 2 +- arch/arm/src/stm32f0l0g0/stm32_hsi48.h | 2 +- arch/arm/src/stm32f0l0g0/stm32_i2c.c | 2 +- arch/arm/src/stm32f0l0g0/stm32_pwm.c | 2 +- arch/arm/src/stm32f0l0g0/stm32_serial_v1.c | 2 +- arch/arm/src/stm32f0l0g0/stm32_serial_v2.c | 2 +- arch/arm/src/stm32f7/hardware/stm32_sai.h | 2 +- .../src/stm32f7/hardware/stm32f72xx73xx_tim.h | 2 +- .../src/stm32f7/hardware/stm32f74xx75xx_tim.h | 2 +- .../src/stm32f7/hardware/stm32f76xx77xx_tim.h | 2 +- arch/arm/src/stm32f7/stm32_dma2d.c | 2 +- arch/arm/src/stm32f7/stm32_ethernet.c | 6 +- arch/arm/src/stm32f7/stm32_i2c.c | 2 +- arch/arm/src/stm32f7/stm32_i2s.c | 2 +- arch/arm/src/stm32f7/stm32_ltdc.c | 4 +- arch/arm/src/stm32f7/stm32_otgdev.c | 6 +- arch/arm/src/stm32f7/stm32_otghost.c | 2 +- arch/arm/src/stm32f7/stm32_pwm.c | 8 +- arch/arm/src/stm32f7/stm32_sai.c | 4 +- arch/arm/src/stm32f7/stm32_sdmmc.c | 2 +- arch/arm/src/stm32f7/stm32_serial.c | 4 +- arch/arm/src/stm32f7/stm32f72xx73xx_rcc.c | 2 +- arch/arm/src/stm32f7/stm32f74xx75xx_rcc.c | 2 +- arch/arm/src/stm32f7/stm32f76xx77xx_rcc.c | 2 +- arch/arm/src/stm32h5/Kconfig | 4 +- arch/arm/src/stm32h5/hardware/stm32_crs.h | 2 +- arch/arm/src/stm32h5/hardware/stm32_tim.h | 2 +- .../arm/src/stm32h5/hardware/stm32h5xxx_rcc.h | 4 +- arch/arm/src/stm32h5/stm32_adc.c | 2 +- arch/arm/src/stm32h5/stm32_ethernet.c | 6 +- arch/arm/src/stm32h5/stm32_fdcan.c | 14 +- arch/arm/src/stm32h5/stm32_hsi48.c | 2 +- arch/arm/src/stm32h5/stm32_hsi48.h | 2 +- arch/arm/src/stm32h5/stm32_i2c.c | 6 +- arch/arm/src/stm32h5/stm32_serial.c | 2 +- arch/arm/src/stm32h7/Kconfig | 4 +- arch/arm/src/stm32h7/hardware/stm32_dac.h | 22 +-- arch/arm/src/stm32h7/hardware/stm32_fdcan.h | 2 +- arch/arm/src/stm32h7/hardware/stm32_tim.h | 2 +- arch/arm/src/stm32h7/stm32_adc.c | 2 +- arch/arm/src/stm32h7/stm32_ethernet.c | 6 +- arch/arm/src/stm32h7/stm32_fdcan_sock.c | 6 +- arch/arm/src/stm32h7/stm32_i2c.c | 2 +- arch/arm/src/stm32h7/stm32_ltdc.c | 4 +- arch/arm/src/stm32h7/stm32_otgdev.c | 6 +- arch/arm/src/stm32h7/stm32_otghost.c | 2 +- arch/arm/src/stm32h7/stm32_pwm.c | 8 +- arch/arm/src/stm32h7/stm32_sdmmc.c | 2 +- arch/arm/src/stm32h7/stm32_serial.c | 6 +- arch/arm/src/stm32h7/stm32_start.c | 2 +- arch/arm/src/stm32h7/stm32h7x3xx_rcc.c | 2 +- arch/arm/src/stm32h7/stm32h7x7xx_rcc.c | 2 +- arch/arm/src/stm32l4/Kconfig | 6 +- arch/arm/src/stm32l4/hardware/stm32l4_crs.h | 2 +- arch/arm/src/stm32l4/hardware/stm32l4_sai.h | 2 +- arch/arm/src/stm32l4/stm32l4_1wire.c | 2 +- arch/arm/src/stm32l4/stm32l4_can.c | 6 +- arch/arm/src/stm32l4/stm32l4_hsi48.c | 2 +- arch/arm/src/stm32l4/stm32l4_hsi48.h | 2 +- arch/arm/src/stm32l4/stm32l4_i2c.c | 4 +- arch/arm/src/stm32l4/stm32l4_otgfshost.c | 2 +- arch/arm/src/stm32l4/stm32l4_pwm.c | 6 +- arch/arm/src/stm32l4/stm32l4_sdmmc.c | 2 +- arch/arm/src/stm32l4/stm32l4_serial.c | 2 +- .../src/stm32l5/hardware/stm32l562xx_pinmap.h | 2 +- .../hardware/stm32l562xx_pinmap_legacy.h | 2 +- arch/arm/src/stm32l5/hardware/stm32l5_tim.h | 2 +- arch/arm/src/stm32l5/stm32l5_serial.c | 2 +- arch/arm/src/stm32l5/stm32l5_spi.c | 6 +- arch/arm/src/stm32u5/hardware/stm32_pwr.h | 2 +- arch/arm/src/stm32u5/hardware/stm32_tim.h | 2 +- .../src/stm32u5/hardware/stm32u5xx_pinmap.h | 2 +- arch/arm/src/stm32u5/hardware/stm32u5xx_rcc.h | 2 +- arch/arm/src/stm32u5/stm32_i2c.c | 4 +- arch/arm/src/stm32u5/stm32_pwr.c | 2 +- arch/arm/src/stm32u5/stm32_pwr.h | 2 +- arch/arm/src/stm32u5/stm32_serial.c | 2 +- arch/arm/src/stm32wb/stm32wb_blehci.c | 2 +- arch/arm/src/stm32wb/stm32wb_gpio.c | 2 +- arch/arm/src/stm32wb/stm32wb_i2c.c | 2 +- arch/arm/src/stm32wb/stm32wb_mbox.c | 2 +- arch/arm/src/stm32wb/stm32wb_rcc.h | 2 +- arch/arm/src/stm32wb/stm32wb_rcc_hsi48.c | 2 +- arch/arm/src/stm32wb/stm32wb_serial.c | 2 +- .../arm/src/stm32wl5/hardware/stm32wl5_exti.h | 2 +- .../src/stm32wl5/hardware/stm32wl5_flash.h | 2 +- arch/arm/src/stm32wl5/hardware/stm32wl5_pwr.h | 6 +- arch/arm/src/stm32wl5/hardware/stm32wl5_tim.h | 2 +- arch/arm/src/stm32wl5/stm32wl5_ipcc.c | 10 +- arch/arm/src/stm32wl5/stm32wl5_ipcc.h | 2 +- arch/arm/src/stm32wl5/stm32wl5_rcc.c | 2 +- arch/arm/src/stm32wl5/stm32wl5_serial.c | 2 +- arch/arm/src/str71x/str71x_emi.h | 4 +- arch/arm/src/str71x/str71x_head.S | 2 +- arch/arm/src/str71x/str71x_pcu.h | 2 +- arch/arm/src/str71x/str71x_serial.c | 2 +- arch/arm/src/tiva/common/tiva_i2c.c | 4 +- arch/arm/src/tiva/common/tiva_serial.c | 2 +- arch/arm/src/tiva/common/tiva_sock_can.c | 2 +- arch/arm/src/tiva/common/tiva_timerlib.c | 2 +- .../tiva/hardware/cc13x0/cc13x0_ddi0_osc.h | 2 +- .../cc13x2_cc26x2/cc13x2_cc26x2_ddi0_osc.h | 2 +- arch/arm/src/tiva/hardware/tiva_ssi.h | 2 +- arch/arm/src/tiva/tm4c/tm4c_ethernet.c | 6 +- arch/arm/src/tlsr82/Kconfig | 18 +- .../src/tlsr82/chip/b87/boot/cstartup_flash.S | 2 +- arch/arm/src/tlsr82/hardware/tlsr82_adc.h | 4 +- arch/arm/src/tlsr82/hardware/tlsr82_dma.h | 2 +- .../arm/src/tlsr82/hardware/tlsr82_register.h | 2 +- arch/arm/src/tlsr82/hardware/tlsr82_uart.h | 2 +- arch/arm/src/tlsr82/tc32/tc32_backtrace.c | 12 +- arch/arm/src/tlsr82/tc32/tc32_exception.S | 4 +- arch/arm/src/tlsr82/tlsr82_adc.c | 12 +- arch/arm/src/tlsr82/tlsr82_aes.c | 2 +- arch/arm/src/tlsr82/tlsr82_analog.c | 4 +- arch/arm/src/tlsr82/tlsr82_cpu.h | 2 +- arch/arm/src/tlsr82/tlsr82_flash.c | 10 +- arch/arm/src/tlsr82/tlsr82_flash_mtd.c | 10 +- arch/arm/src/tlsr82/tlsr82_gpio.c | 16 +- arch/arm/src/tlsr82/tlsr82_gpio_cfg.c | 2 +- arch/arm/src/tlsr82/tlsr82_pwm.c | 4 +- arch/arm/src/tlsr82/tlsr82_serial.c | 22 +-- arch/arm/src/tlsr82/tlsr82_spi_console.c | 2 +- arch/arm/src/tms570/hardware/tms570_sci.h | 4 +- arch/arm/src/tms570/tms570_clockconfig.c | 2 +- arch/arm/src/tms570/tms570_lowputc.c | 2 +- arch/arm/src/tms570/tms570_serial.c | 2 +- arch/arm/src/xmc4/hardware/xmc4_ethernet.h | 4 +- arch/arm/src/xmc4/hardware/xmc4_posif.h | 18 +- arch/arm/src/xmc4/hardware/xmc4_vadc.h | 2 +- arch/arm/src/xmc4/xmc4_ccu4.c | 2 +- arch/arm/src/xmc4/xmc4_i2c.c | 12 +- arch/arm/src/xmc4/xmc4_lowputc.h | 2 +- arch/arm/src/xmc4/xmc4_pwm.c | 8 +- arch/arm/src/xmc4/xmc4_serial.c | 2 +- arch/arm/src/xmc4/xmc4_spi.c | 2 +- arch/arm/src/xmc4/xmc4_tickless.c | 2 +- arch/arm/src/xmc4/xmc4_vadc.c | 2 +- arch/arm/src/xmc4/xmc4_vadc.h | 2 +- arch/arm64/Kconfig | 6 +- arch/arm64/include/imx9/imx93_irq.h | 4 +- arch/arm64/include/zynq-mpsoc/irq.h | 2 +- arch/arm64/src/a64/a64_mipi_dsi.c | 4 +- arch/arm64/src/a64/a64_serial.c | 2 +- arch/arm64/src/a64/a64_twi.c | 8 +- arch/arm64/src/a64/hardware/a64_twi.h | 2 +- arch/arm64/src/bcm2711/bcm2711_serial.c | 2 +- .../src/bcm2711/hardware/bcm2711_memmap.h | 2 +- arch/arm64/src/common/arm64_gic.h | 2 +- arch/arm64/src/common/arm64_head.S | 4 +- arch/arm64/src/common/arm64_internal.h | 2 +- arch/arm64/src/common/arm64_mmu.h | 2 +- arch/arm64/src/common/arm64_mpu.c | 2 +- arch/arm64/src/common/arm64_smpcall.c | 2 +- arch/arm64/src/common/arm64_syscall.c | 2 +- arch/arm64/src/imx8/imx8_serial.h | 4 +- arch/arm64/src/imx8/imx8qm_serial.c | 2 +- arch/arm64/src/imx9/Kconfig | 6 +- arch/arm64/src/imx9/hardware/imx9_blk_ctrl.h | 2 +- arch/arm64/src/imx9/hardware/imx9_enet.h | 4 +- arch/arm64/src/imx9/hardware/imx9_flexcan.h | 4 +- arch/arm64/src/imx9/hardware/imx9_lpit.h | 2 +- arch/arm64/src/imx9/imx9_ccm.c | 2 +- arch/arm64/src/imx9/imx9_edma.h | 2 +- arch/arm64/src/imx9/imx9_enet.c | 10 +- arch/arm64/src/imx9/imx9_flexcan.c | 4 +- arch/arm64/src/imx9/imx9_flexspi.c | 4 +- arch/arm64/src/imx9/imx9_flexspi_nor.c | 2 +- arch/arm64/src/imx9/imx9_lowputc.c | 2 +- arch/arm64/src/imx9/imx9_lpi2c.c | 4 +- arch/arm64/src/imx9/imx9_lpspi.c | 2 +- arch/arm64/src/imx9/imx9_lpspi.h | 2 +- arch/arm64/src/imx9/imx9_lpuart.c | 4 +- arch/arm64/src/imx9/imx9_system_ctl.c | 2 +- arch/arm64/src/imx9/imx9_usbdev.c | 6 +- arch/arm64/src/imx9/imx9_usdhc.c | 2 +- arch/arm64/src/qemu/Kconfig | 2 +- arch/arm64/src/rk3399/rk3399_serial.c | 2 +- arch/arm64/src/zynq-mpsoc/hardware/zynq_pll.h | 8 +- arch/arm64/src/zynq-mpsoc/zynq_boot.c | 2 +- arch/arm64/src/zynq-mpsoc/zynq_enet.c | 4 +- arch/arm64/src/zynq-mpsoc/zynq_pll.c | 42 ++--- arch/arm64/src/zynq-mpsoc/zynq_serial.c | 2 +- arch/avr/src/at32uc3/at32uc3_irq.c | 2 +- arch/avr/src/at32uc3/at32uc3_serial.c | 2 +- arch/avr/src/at90usb/at90usb_serial.c | 2 +- arch/avr/src/atmega/atmega_serial.c | 4 +- arch/ceva/include/spinlock.h | 2 +- arch/ceva/include/xm6/barriers.h | 2 +- arch/ceva/include/xm6/spinlock.h | 2 +- arch/ceva/src/common/ceva_board.c | 2 +- arch/ceva/src/common/ceva_svcall.c | 4 +- arch/ceva/src/xc5/Kconfig | 2 +- arch/ceva/src/xc5/fork.S | 4 +- arch/ceva/src/xm6/fork.S | 4 +- arch/hc/include/hcs12/irq.h | 4 +- arch/hc/src/m9s12/m9s12_saveusercontext.S | 4 +- arch/hc/src/m9s12/m9s12_serial.c | 2 +- arch/hc/src/m9s12/m9s12_start.S | 2 +- arch/hc/src/m9s12/m9s12_vectors.S | 6 +- arch/mips/include/mips32/cp0.h | 2 +- arch/mips/include/mips32/irq.h | 2 +- arch/mips/src/mips32/mips_fork.c | 2 +- arch/mips/src/pic32mx/Kconfig | 2 +- arch/mips/src/pic32mx/pic32mx_ethernet.c | 8 +- arch/mips/src/pic32mx/pic32mx_oc.h | 2 +- arch/mips/src/pic32mx/pic32mx_serial.c | 2 +- arch/mips/src/pic32mz/hardware/pic32mz_osc.h | 2 +- arch/mips/src/pic32mz/pic32mz_ethernet.c | 6 +- arch/mips/src/pic32mz/pic32mz_i2c.c | 4 +- arch/mips/src/pic32mz/pic32mz_serial.c | 2 +- arch/misoc/src/common/misoc_serial.c | 2 +- arch/misoc/src/lm32/lm32_decodeirq.c | 2 +- arch/misoc/src/minerva/minerva_decodeirq.c | 2 +- arch/or1k/src/mor1kx/mor1kx_serial.c | 2 +- arch/renesas/src/m16c/m16c_serial.c | 2 +- arch/renesas/src/m16c/m16c_timerisr.c | 4 +- arch/renesas/src/rx65n/rx65n_dtc.c | 4 +- arch/renesas/src/rx65n/rx65n_eth.c | 6 +- arch/renesas/src/rx65n/rx65n_lowputc.c | 2 +- arch/renesas/src/rx65n/rx65n_riic.c | 8 +- arch/renesas/src/rx65n/rx65n_rspi.c | 2 +- arch/renesas/src/rx65n/rx65n_rspi_sw.c | 2 +- arch/renesas/src/rx65n/rx65n_rtc.c | 6 +- arch/renesas/src/rx65n/rx65n_serial.c | 2 +- arch/renesas/src/rx65n/rx65n_usbdev.c | 4 +- arch/renesas/src/rx65n/rx65n_usbhost.c | 24 +-- arch/renesas/src/sh1/sh1_lowputc.c | 2 +- arch/renesas/src/sh1/sh1_serial.c | 2 +- arch/risc-v/Kconfig | 2 +- arch/risc-v/include/irq.h | 2 +- arch/risc-v/src/bl602/Kconfig | 2 +- arch/risc-v/src/bl602/bl602_dma.c | 4 +- arch/risc-v/src/bl602/bl602_i2c.c | 4 +- arch/risc-v/src/bl602/bl602_netdev.c | 12 +- .../src/bl602/bl602_oneshot_lowerhalf.c | 2 +- arch/risc-v/src/bl602/bl602_rtc.c | 8 +- arch/risc-v/src/bl602/bl602_serial.c | 2 +- arch/risc-v/src/bl602/bl602_spi.c | 2 +- arch/risc-v/src/bl602/bl602_tim.c | 2 +- arch/risc-v/src/bl602/bl602_tim.h | 2 +- arch/risc-v/src/bl808/bl808_i2c.c | 4 +- arch/risc-v/src/bl808/bl808_serial.c | 2 +- arch/risc-v/src/bl808/bl808_serial.h | 2 +- arch/risc-v/src/bl808/bl808_spi.c | 2 +- arch/risc-v/src/bl808/bl808_start.c | 2 +- arch/risc-v/src/c906/c906_serial.c | 2 +- arch/risc-v/src/common/espressif/esp_adc.c | 2 +- arch/risc-v/src/common/espressif/esp_i2c.c | 2 +- .../src/common/espressif/esp_i2c_slave.c | 4 +- .../src/common/espressif/esp_i2c_slave.h | 2 +- arch/risc-v/src/common/espressif/esp_i2s.c | 6 +- arch/risc-v/src/common/espressif/esp_ledc.c | 6 +- arch/risc-v/src/common/espressif/esp_nxdiag.c | 4 +- arch/risc-v/src/common/espressif/esp_rmt.c | 2 +- .../src/common/espressif/esp_spiflash.c | 4 +- .../src/common/espressif/esp_spiflash_mtd.c | 4 +- .../common/espressif/esp_temperature_sensor.c | 4 +- arch/risc-v/src/common/espressif/esp_wlan.c | 6 +- arch/risc-v/src/common/espressif/esp_wlan.h | 2 +- .../src/common/riscv_exception_common.S | 2 +- arch/risc-v/src/common/riscv_macros.S | 2 +- arch/risc-v/src/common/riscv_pmp.c | 2 +- arch/risc-v/src/common/riscv_tcbinfo.c | 2 +- .../src/common/supervisor/riscv_syscall.S | 2 +- arch/risc-v/src/eic7700x/eic7700x_start.c | 2 +- arch/risc-v/src/esp32c3-legacy/esp32c3_aes.c | 4 +- arch/risc-v/src/esp32c3-legacy/esp32c3_aes.h | 4 +- arch/risc-v/src/esp32c3-legacy/esp32c3_ble.c | 6 +- .../src/esp32c3-legacy/esp32c3_ble_adapter.c | 6 +- .../src/esp32c3-legacy/esp32c3_efuse_table.c | 4 +- arch/risc-v/src/esp32c3-legacy/esp32c3_i2c.c | 2 +- .../esp32c3_oneshot_lowerhalf.c | 4 +- arch/risc-v/src/esp32c3-legacy/esp32c3_pm.c | 10 +- arch/risc-v/src/esp32c3-legacy/esp32c3_pm.h | 2 +- arch/risc-v/src/esp32c3-legacy/esp32c3_rtc.c | 2 +- .../src/esp32c3-legacy/esp32c3_serial.c | 8 +- .../src/esp32c3-legacy/esp32c3_spiflash.c | 2 +- .../src/esp32c3-legacy/esp32c3_spiflash_mtd.c | 6 +- .../src/esp32c3-legacy/esp32c3_wifi_adapter.c | 6 +- .../src/esp32c3-legacy/esp32c3_wifi_adapter.h | 2 +- arch/risc-v/src/esp32c3-legacy/esp32c3_wlan.c | 4 +- .../src/esp32c3-legacy/hardware/esp32c3_aes.h | 2 +- .../esp32c3-legacy/hardware/esp32c3_rtccntl.h | 2 +- .../src/esp32c3-legacy/hardware/esp32c3_spi.h | 6 +- .../esp32c3-legacy/hardware/esp32c3_uart.h | 4 +- .../src/esp32c3-legacy/rom/esp32c3_spiflash.h | 4 +- arch/risc-v/src/esp32c3/esp_ble.c | 2 +- arch/risc-v/src/esp32c3/esp_coex_adapter.c | 2 +- arch/risc-v/src/esp32c3/esp_wifi_adapter.c | 2 +- arch/risc-v/src/esp32c6/esp_coex_adapter.c | 2 +- arch/risc-v/src/esp32c6/esp_wifi_adapter.c | 2 +- arch/risc-v/src/fe310/fe310_serial.c | 2 +- arch/risc-v/src/hpm6000/Kconfig | 6 +- arch/risc-v/src/hpm6000/hardware/hpm_gpio.h | 2 +- arch/risc-v/src/hpm6000/hpm_clockconfig.c | 2 +- arch/risc-v/src/hpm6000/hpm_serial.c | 2 +- .../risc-v/src/hpm6750/hardware/hpm6750_ioc.h | 2 +- arch/risc-v/src/hpm6750/hpm6750_serial.c | 2 +- arch/risc-v/src/jh7110/jh7110_timerisr.c | 2 +- arch/risc-v/src/k210/k210_serial.c | 2 +- arch/risc-v/src/litex/litex_emac.c | 4 +- arch/risc-v/src/litex/litex_sdio.c | 2 +- arch/risc-v/src/litex/litex_serial.c | 2 +- arch/risc-v/src/litex/litex_ticked.c | 2 +- arch/risc-v/src/mpfs/Kconfig | 2 +- .../src/mpfs/hardware/mpfs250t_484_pinmap.h | 2 +- arch/risc-v/src/mpfs/hardware/mpfs_gpio.h | 4 +- arch/risc-v/src/mpfs/hardware/mpfs_ihc.h | 2 +- arch/risc-v/src/mpfs/hardware/mpfs_wdog.h | 6 +- arch/risc-v/src/mpfs/mpfs_coremmc.c | 6 +- arch/risc-v/src/mpfs/mpfs_ddr.c | 2 +- arch/risc-v/src/mpfs/mpfs_dma.c | 4 +- arch/risc-v/src/mpfs/mpfs_emmcsd.c | 6 +- arch/risc-v/src/mpfs/mpfs_ethernet.c | 2 +- arch/risc-v/src/mpfs/mpfs_ihc.c | 4 +- arch/risc-v/src/mpfs/mpfs_opensbi.c | 2 +- arch/risc-v/src/mpfs/mpfs_opensbi_trap.S | 4 +- arch/risc-v/src/mpfs/mpfs_plic.c | 2 +- arch/risc-v/src/mpfs/mpfs_serial.c | 2 +- arch/risc-v/src/mpfs/mpfs_usb.c | 4 +- arch/risc-v/src/nuttsbi/sbi_internal.h | 2 +- arch/risc-v/src/nuttsbi/sbi_mtrap.S | 2 +- arch/risc-v/src/qemu-rv/qemu_rv_rptun.c | 4 +- arch/risc-v/src/rv32m1/hardware/rv32m1_lpit.h | 2 +- .../src/rv32m1/hardware/rv32m1_lpuart.h | 2 +- .../src/rv32m1/hardware/rv32m1ri5cy_scg.h | 4 +- arch/risc-v/src/rv32m1/rv32m1_clockconfig.c | 2 +- arch/risc-v/src/rv32m1/rv32m1_delay.c | 4 +- arch/risc-v/src/rv32m1/rv32m1_gpio.c | 4 +- arch/risc-v/src/rv32m1/rv32m1_serial.c | 4 +- arch/risc-v/src/rv32m1/rv32m1_timersvc.c | 2 +- arch/risc-v/src/sg2000/sg2000_start.c | 2 +- arch/sim/src/sim/posix/sim_linuxi2c.c | 2 +- arch/sim/src/sim/posix/sim_linuxspi.c | 12 +- arch/sim/src/sim/sim_lcd.c | 2 +- arch/sim/src/sim/sim_offload.h | 2 +- arch/sim/src/sim/sim_rpmsg_virtio.c | 2 +- arch/sim/src/sim/sim_rptun.c | 2 +- arch/sim/src/sim/sim_usbdev.c | 2 +- arch/sim/src/sim/sim_wifidriver.c | 6 +- arch/sparc/include/sparc_v8/irq.h | 20 +-- arch/sparc/src/bm3803/bm3803-irq.c | 2 +- arch/sparc/src/bm3803/bm3803-serial.c | 2 +- arch/sparc/src/bm3803/bm3803.h | 2 +- arch/sparc/src/bm3823/bm3823-irq.c | 2 +- arch/sparc/src/bm3823/bm3823-serial.c | 2 +- arch/sparc/src/bm3823/bm3823.h | 2 +- arch/sparc/src/s698pm/s698pm-irq.c | 4 +- arch/sparc/src/s698pm/s698pm-serial.c | 2 +- arch/sparc/src/s698pm/s698pm-timerisr.c | 2 +- arch/sparc/src/s698pm/s698pm.h | 2 +- arch/sparc/src/s698pm/s698pm_exceptions.S | 2 +- arch/sparc/src/s698pm/s698pm_head.S | 2 +- arch/sparc/src/sparc_v8/sparc_v8_romgetc.c | 2 +- arch/sparc/src/sparc_v8/sparc_v8_sigdeliver.c | 2 +- arch/tricore/src/common/Ifx_Cfg_Trap.h | 2 +- arch/tricore/src/tc3xx/tc3xx_libc.c | 2 +- arch/tricore/src/tc3xx/tc3xx_serial.c | 2 +- arch/x86_64/include/acpi.h | 4 +- arch/x86_64/include/intel64/arch.h | 2 +- arch/x86_64/src/common/x86_64_acpi.c | 10 +- arch/x86_64/src/common/x86_64_addrenv.c | 2 +- arch/x86_64/src/common/x86_64_hwdebug.c | 6 +- arch/x86_64/src/common/x86_64_hwdebug.h | 2 +- arch/x86_64/src/intel64/Kconfig | 4 +- .../src/intel64/intel64_check_capability.c | 2 +- arch/x86_64/src/intel64/intel64_cpu.c | 8 +- arch/x86_64/src/intel64/intel64_fbterm.c | 2 +- arch/x86_64/src/intel64/intel64_fpucmp.c | 2 +- arch/x86_64/src/intel64/intel64_head.S | 6 +- arch/x86_64/src/intel64/intel64_hpet.c | 2 +- .../x86_64/src/intel64/intel64_initialstate.c | 2 +- arch/x86_64/src/intel64/intel64_irq.c | 4 +- arch/x86_64/src/intel64/intel64_oneshot.c | 6 +- arch/x86_64/src/intel64/intel64_regdump.c | 2 +- arch/x86_64/src/intel64/intel64_serial.c | 2 +- arch/x86_64/src/intel64/intel64_smpcall.c | 2 +- arch/x86_64/src/intel64/intel64_start.c | 2 +- .../x86_64/src/intel64/intel64_tsc_tickless.c | 2 +- arch/x86_64/src/intel64/intel64_vectors.S | 8 +- arch/xtensa/Kconfig | 4 +- arch/xtensa/include/arch.h | 14 +- arch/xtensa/include/simcall.h | 2 +- arch/xtensa/src/common/espressif/esp_adc.c | 2 +- .../src/common/espressif/esp_i2c_slave.c | 4 +- .../src/common/espressif/esp_i2c_slave.h | 2 +- arch/xtensa/src/common/espressif/esp_i2s.c | 6 +- arch/xtensa/src/common/espressif/esp_nxdiag.c | 4 +- .../xtensa/src/common/espressif/esp_openeth.c | 2 +- arch/xtensa/src/common/espressif/esp_rmt.c | 2 +- .../src/common/espressif/esp_spiflash.c | 4 +- .../src/common/espressif/esp_spiflash_mtd.c | 4 +- .../common/espressif/esp_temperature_sensor.c | 4 +- .../src/common/espressif/esp_wireless.c | 4 +- arch/xtensa/src/common/espressif/esp_wlan.c | 6 +- arch/xtensa/src/common/xtensa_assert.c | 2 +- arch/xtensa/src/common/xtensa_backtrace.c | 2 +- arch/xtensa/src/esp32/esp32_aes.c | 4 +- arch/xtensa/src/esp32/esp32_aes.h | 4 +- arch/xtensa/src/esp32/esp32_ble_adapter.c | 6 +- arch/xtensa/src/esp32/esp32_cpustart.c | 2 +- arch/xtensa/src/esp32/esp32_emac.c | 2 +- arch/xtensa/src/esp32/esp32_himem.c | 2 +- arch/xtensa/src/esp32/esp32_himem_chardev.c | 2 +- arch/xtensa/src/esp32/esp32_i2c.c | 2 +- arch/xtensa/src/esp32/esp32_i2s.c | 8 +- .../src/esp32/esp32_oneshot_lowerhalf.c | 4 +- arch/xtensa/src/esp32/esp32_psram.c | 2 +- arch/xtensa/src/esp32/esp32_rtc.c | 2 +- arch/xtensa/src/esp32/esp32_serial.c | 8 +- arch/xtensa/src/esp32/esp32_spiflash.c | 4 +- arch/xtensa/src/esp32/esp32_touch.c | 4 +- arch/xtensa/src/esp32/esp32_wifi_adapter.c | 6 +- arch/xtensa/src/esp32/hardware/esp32_i2s.h | 2 +- arch/xtensa/src/esp32/hardware/esp32_ledc.h | 32 ++-- arch/xtensa/src/esp32/hardware/esp32_pcnt.h | 16 +- arch/xtensa/src/esp32/hardware/esp32_rtc_io.h | 16 +- arch/xtensa/src/esp32/hardware/esp32_uart.h | 2 +- arch/xtensa/src/esp32/hardware/esp32_uhci.h | 12 +- arch/xtensa/src/esp32/rom/esp32_spiflash.h | 2 +- arch/xtensa/src/esp32s2/esp32s2_efuse_table.c | 4 +- arch/xtensa/src/esp32s2/esp32s2_i2c.c | 2 +- arch/xtensa/src/esp32s2/esp32s2_i2s.c | 8 +- arch/xtensa/src/esp32s2/esp32s2_psram.h | 2 +- arch/xtensa/src/esp32s2/esp32s2_rtc.c | 2 +- arch/xtensa/src/esp32s2/esp32s2_rtcheap.c | 14 +- arch/xtensa/src/esp32s2/esp32s2_rtcheap.h | 14 +- arch/xtensa/src/esp32s2/esp32s2_serial.c | 6 +- arch/xtensa/src/esp32s2/esp32s2_spiram.c | 2 +- arch/xtensa/src/esp32s2/esp32s2_textheap.c | 4 +- .../src/esp32s2/esp32s2_tim_lowerhalf.c | 2 +- arch/xtensa/src/esp32s2/esp32s2_touch.c | 2 +- .../src/esp32s2/esp32s2_touch_lowerhalf.h | 4 +- .../xtensa/src/esp32s2/esp32s2_wifi_adapter.c | 4 +- .../xtensa/src/esp32s2/hardware/esp32s2_aes.h | 2 +- .../src/esp32s2/hardware/esp32s2_rtccntl.h | 6 +- .../xtensa/src/esp32s2/hardware/esp32s2_soc.h | 2 +- .../esp32s2/hardware/esp32s2_spi_mem_reg.h | 2 +- .../src/esp32s2/hardware/esp32s2_system.h | 4 +- .../src/esp32s2/rom/esp32s2_opi_flash.h | 4 +- .../xtensa/src/esp32s2/rom/esp32s2_spiflash.h | 2 +- arch/xtensa/src/esp32s3/esp32s3_aes.c | 4 +- arch/xtensa/src/esp32s3/esp32s3_aes.h | 4 +- arch/xtensa/src/esp32s3/esp32s3_ble.c | 2 +- arch/xtensa/src/esp32s3/esp32s3_efuse_table.c | 4 +- arch/xtensa/src/esp32s3/esp32s3_himem.c | 2 +- arch/xtensa/src/esp32s3/esp32s3_i2c.c | 2 +- arch/xtensa/src/esp32s3/esp32s3_lcd.c | 18 +- arch/xtensa/src/esp32s3/esp32s3_ledc.c | 2 +- arch/xtensa/src/esp32s3/esp32s3_otg_device.c | 6 +- arch/xtensa/src/esp32s3/esp32s3_pm.c | 10 +- arch/xtensa/src/esp32s3/esp32s3_pm.h | 2 +- arch/xtensa/src/esp32s3/esp32s3_psram.h | 2 +- arch/xtensa/src/esp32s3/esp32s3_qspi.c | 18 +- arch/xtensa/src/esp32s3/esp32s3_qspi.h | 4 +- arch/xtensa/src/esp32s3/esp32s3_rtc.c | 4 +- arch/xtensa/src/esp32s3/esp32s3_rtcheap.c | 2 +- arch/xtensa/src/esp32s3/esp32s3_rtcheap.h | 2 +- arch/xtensa/src/esp32s3/esp32s3_sdmmc.c | 6 +- arch/xtensa/src/esp32s3/esp32s3_serial.c | 8 +- arch/xtensa/src/esp32s3/esp32s3_spiflash.c | 6 +- .../xtensa/src/esp32s3/esp32s3_spiflash_mtd.c | 16 +- arch/xtensa/src/esp32s3/esp32s3_touch.c | 2 +- .../src/esp32s3/esp32s3_touch_lowerhalf.h | 4 +- .../xtensa/src/esp32s3/esp32s3_wifi_adapter.c | 6 +- .../xtensa/src/esp32s3/esp32s3_wifi_adapter.h | 2 +- .../xtensa/src/esp32s3/hardware/esp32s3_aes.h | 2 +- .../src/esp32s3/hardware/esp32s3_efuse.h | 4 +- .../xtensa/src/esp32s3/hardware/esp32s3_i2s.h | 2 +- .../hardware/esp32s3_interrupt_core0.h | 2 +- .../hardware/esp32s3_interrupt_core1.h | 4 +- .../src/esp32s3/hardware/esp32s3_lcd_cam.h | 2 +- .../src/esp32s3/hardware/esp32s3_rtccntl.h | 32 ++-- .../src/esp32s3/hardware/esp32s3_sensitive.h | 16 +- .../xtensa/src/esp32s3/hardware/esp32s3_spi.h | 6 +- .../src/esp32s3/hardware/esp32s3_syscon.h | 2 +- .../src/esp32s3/hardware/esp32s3_uart.h | 8 +- .../xtensa/src/esp32s3/rom/esp32s3_spiflash.h | 4 +- arch/z16/src/z16f/z16f_espi.c | 2 +- arch/z80/src/Makefile.clang | 2 +- arch/z80/src/Makefile.sdccl | 2 +- arch/z80/src/Makefile.sdccw | 2 +- arch/z80/src/ez80/ez80F91.inc | 2 +- arch/z80/src/ez80/ez80f91.h | 2 +- arch/z80/src/ez80/ez80f91_emac.h | 2 +- arch/z80/src/ez80/ez80f92.h | 2 +- arch/z80/src/z180/z180_mmu.c | 2 +- audio/audio.c | 10 +- boards/arm/at32/at32f437-mini/src/at32_usb.c | 2 +- .../at32/at32f437-mini/src/at32f437-mini.h | 2 +- .../drivers/audio/cxd56_audio_ac_reg.c | 2 +- .../drivers/audio/cxd56_audio_filter.c | 2 +- boards/arm/cxd56xx/spresense/Kconfig | 2 +- boards/arm/cxd56xx/spresense/include/board.h | 2 +- .../arm/cxd56xx/spresense/src/cxd56_bringup.c | 2 +- .../cxd56xx/spresense/src/cxd56_composite.c | 2 +- .../arm/cxd56xx/spresense/src/cxd56_power.c | 2 +- .../gd32f450zk-aiotbox/src/gd32f4xx_i2c.c | 12 +- .../gd32f470zk-aiotbox/src/gd32f4xx_i2c.c | 12 +- .../src/imxrt_flexspi_nor_flash.h | 2 +- .../src/imxrt_flexspi_nor_flash.h | 2 +- .../imxrt1060-evk/scripts/flash-ocram.ld | 2 +- .../src/imxrt_flexspi_nor_flash.h | 2 +- .../imxrt1064-evk/scripts/flash-ocram.ld | 2 +- .../src/imxrt_flexspi_nor_flash.h | 2 +- .../imxrt1170-evk/scripts/flash-ocram.ld | 4 +- .../arm/imxrt/imxrt1170-evk/src/imxrt_boot.c | 2 +- .../src/imxrt_flexspi_nor_flash.h | 2 +- boards/arm/imxrt/teensy-4.x/Kconfig | 4 +- .../imxrt/teensy-4.x/scripts/flash-ocram.ld | 2 +- .../teensy-4.x/src/imxrt_flexspi_nor_flash.h | 2 +- .../kinetis/freedom-k28f/src/freedom-k28f.h | 4 +- .../arm/kinetis/freedom-k28f/src/k28_sdhc.c | 2 +- .../kinetis/freedom-k64f/src/freedom-k64f.h | 2 +- .../arm/kinetis/freedom-k64f/src/k64_sdhc.c | 2 +- .../kinetis/freedom-k66f/src/freedom-k66f.h | 2 +- .../kinetis/kwikstik-k40/src/k40_appinit.c | 2 +- .../arm/kinetis/twr-k60n512/src/k60_appinit.c | 2 +- .../arm/kinetis/twr-k64f120m/src/k64_leds.c | 4 +- .../arm/kinetis/twr-k64f120m/src/k64_sdhc.c | 2 +- boards/arm/kinetis/twr-k64f120m/src/twrk64.h | 2 +- .../arm/kl/freedom-kl25z/src/freedom-kl25z.h | 2 +- .../arm/kl/freedom-kl26z/src/freedom-kl26z.h | 2 +- .../lpc17xx_40xx/lincoln60/include/board.h | 2 +- .../lpc4088-devkit/include/board.h | 2 +- .../lpc4088-quickstart/include/board.h | 2 +- .../lpcxpresso-lpc1768/include/board.h | 2 +- .../arm/lpc17xx_40xx/lx_cpu/include/board.h | 3 +- .../olimex-lpc1766stk/include/board.h | 2 +- .../arm/lpc17xx_40xx/open1788/include/board.h | 2 +- .../lpc17xx_40xx/pnev5180b/include/board.h | 2 +- .../lpc17xx_40xx/u-blox-c027/include/board.h | 2 +- .../zkit-arm-1769/include/board.h | 2 +- .../mcu123-lpc214x/src/lpc2148_composite.c | 2 +- boards/arm/lpc31xx/ea3131/src/ea3131.h | 2 +- boards/arm/lpc31xx/ea3131/src/lpc31_usbhost.c | 2 +- boards/arm/lpc31xx/ea3131/tools/lpchdr.c | 2 +- boards/arm/lpc31xx/ea3131/tools/lpchdr.h | 2 +- boards/arm/lpc31xx/ea3152/tools/lpchdr.c | 2 +- boards/arm/lpc31xx/ea3152/tools/lpchdr.h | 2 +- .../olimex-lpc-h3131/src/lpc31_usbhost.c | 2 +- .../lpc31xx/olimex-lpc-h3131/src/lpc_h3131.h | 2 +- .../lpc31xx/olimex-lpc-h3131/tools/lpchdr.c | 2 +- .../lpc31xx/olimex-lpc-h3131/tools/lpchdr.h | 2 +- .../arm/lpc43xx/bambino-200e/include/board.h | 2 +- .../lpc43xx/lpc4330-xplorer/include/board.h | 2 +- .../arm/lpc43xx/lpc4357-evb/include/board.h | 2 +- .../lpcxpresso-lpc54628/src/lpc54_sdram.c | 2 +- boards/arm/moxart/moxa/include/board.h | 2 +- .../arm/nrf52/common/src/nrf52_ieee802154.c | 2 +- boards/arm/nrf52/common/src/nrf52_mrf24j40.c | 2 +- .../arm/nrf52/nrf52840-dk/src/nrf52840-dk.h | 2 +- boards/arm/nrf52/nrf52840-dk/src/nrf52_adc.c | 2 +- boards/arm/nrf52/nrf52840-dk/src/nrf52_mx25.c | 2 +- boards/arm/nrf53/nrf5340-dk/src/nrf5340-dk.h | 2 +- boards/arm/nrf53/nrf5340-dk/src/nrf53_adc.c | 2 +- boards/arm/nrf53/nrf5340-dk/src/nrf53_mx25.c | 2 +- .../nutiny-nuc120/src/nuc_boardinitialize.c | 2 +- .../nuc1xx/nutiny-nuc120/src/nutiny-nuc120.h | 2 +- .../arm/rp2040/common/src/rp2040_composite.c | 2 +- .../arm/rp2040/common/src/rp2040_firmware.c | 4 +- .../arm/rp2040/common/src/rp2040_uniqueid.c | 2 +- .../arm/rp2040/w5500-evb-pico/include/board.h | 2 +- .../arm/rp23xx/common/src/rp23xx_composite.c | 2 +- .../arm/rp23xx/common/src/rp23xx_uniqueid.c | 2 +- .../rddrone-bms772/src/s32k1xx_smbus_sbd.c | 2 +- .../s32k3xx/mr-canhubk3/src/s32k3xx_bringup.c | 4 +- boards/arm/sam34/arduino-due/include/board.h | 4 +- boards/arm/sam34/sam3u-ek/include/board.h | 2 +- boards/arm/sama5/giant-board/src/sam_boot.c | 2 +- boards/arm/sama5/giant-board/src/sam_sdram.c | 2 +- boards/arm/sama5/giant-board/src/sam_usb.c | 2 +- .../sama5/jupiter-nano/include/board_384mhz.h | 2 +- .../sama5/jupiter-nano/include/board_396mhz.h | 2 +- .../sama5/jupiter-nano/include/board_498mhz.h | 2 +- .../sama5/jupiter-nano/include/board_528mhz.h | 2 +- boards/arm/sama5/jupiter-nano/src/sam_boot.c | 2 +- boards/arm/sama5/jupiter-nano/src/sam_sdram.c | 4 +- boards/arm/sama5/jupiter-nano/src/sam_usb.c | 2 +- .../sama5/sama5d2-xult/include/board_384mhz.h | 2 +- .../sama5/sama5d2-xult/include/board_396mhz.h | 2 +- .../sama5/sama5d2-xult/include/board_498mhz.h | 2 +- .../sama5/sama5d2-xult/include/board_528mhz.h | 2 +- boards/arm/sama5/sama5d2-xult/src/sam_boot.c | 2 +- boards/arm/sama5/sama5d2-xult/src/sam_sdram.c | 4 +- boards/arm/sama5/sama5d2-xult/src/sam_usb.c | 2 +- .../sama5d3-xplained/include/board_384mhz.h | 2 +- .../sama5d3-xplained/include/board_396mhz.h | 2 +- .../sama5d3-xplained/include/board_528mhz.h | 2 +- .../sama5/sama5d3-xplained/src/sam_hsmci.c | 2 +- .../sama5/sama5d3-xplained/src/sam_sdram.c | 4 +- .../sama5/sama5d3x-ek/include/board_384mhz.h | 2 +- .../sama5/sama5d3x-ek/include/board_396mhz.h | 2 +- .../sama5/sama5d3x-ek/include/board_528mhz.h | 2 +- boards/arm/sama5/sama5d3x-ek/src/sam_boot.c | 2 +- boards/arm/sama5/sama5d3x-ek/src/sam_hsmci.c | 2 +- boards/arm/sama5/sama5d3x-ek/src/sam_sdram.c | 4 +- boards/arm/sama5/sama5d3x-ek/src/sam_usb.c | 2 +- .../arm/sama5/sama5d3x-ek/src/sama5d3x-ek.h | 2 +- .../sama5/sama5d4-ek/include/board_384mhz.h | 2 +- .../sama5/sama5d4-ek/include/board_396mhz.h | 2 +- .../sama5/sama5d4-ek/include/board_528mhz.h | 2 +- boards/arm/sama5/sama5d4-ek/src/sam_boot.c | 2 +- boards/arm/sama5/sama5d4-ek/src/sam_sdram.c | 2 +- boards/arm/sama5/sama5d4-ek/src/sama5d4-ek.h | 2 +- .../arm/samd5e5/metro-m4/src/sam_composite.c | 2 +- .../common/include/board_uart_rxdma_poll.h | 2 +- .../samv7/common/scripts/memory.ld.template | 2 +- boards/arm/samv7/common/src/sam_gpio_enc.c | 2 +- boards/arm/samv7/common/src/sam_reset.c | 2 +- .../samv7/common/src/sam_uart_rxdma_poll.c | 2 +- .../same70-xplained/src/same70-xplained.h | 2 +- .../arm/samv7/samv71-xult/src/sam_composite.c | 2 +- boards/arm/stm32/axoloti/src/stm32_usbhost.c | 2 +- boards/arm/stm32/b-g431b-esc1/src/stm32_can.c | 2 +- .../stm32/b-g431b-esc1/src/stm32_cansock.c | 2 +- .../arm/stm32/b-g474e-dpow1/src/stm32_smps.c | 2 +- .../stm32/clicker2-stm32/src/clicker2-stm32.h | 2 +- .../arm/stm32/clicker2-stm32/src/stm32_boot.c | 2 +- .../stm32/clicker2-stm32/src/stm32_mrf24j40.c | 2 +- .../arm/stm32/clicker2-stm32/src/stm32_usb.c | 2 +- boards/arm/stm32/cloudctrl/src/cloudctrl.h | 2 +- boards/arm/stm32/cloudctrl/src/stm32_usb.c | 2 +- boards/arm/stm32/common/src/stm32_ihm07m1.c | 2 +- boards/arm/stm32/common/src/stm32_ihm08m1.c | 2 +- boards/arm/stm32/common/src/stm32_ihm16m1.c | 2 +- .../arm/stm32/et-stm32-stamp/include/board.h | 2 +- boards/arm/stm32/fire-stm32v2/include/board.h | 2 +- .../arm/stm32/hymini-stm32v/include/board.h | 2 +- .../stm32/hymini-stm32v/src/stm32_r61505u.c | 2 +- boards/arm/stm32/maple/include/board.h | 2 +- .../arm/stm32/mikroe-stm32f4/src/stm32_boot.c | 2 +- .../arm/stm32/mikroe-stm32f4/src/stm32_usb.c | 2 +- .../arm/stm32/nucleo-f103rb/include/board.h | 2 +- .../arm/stm32/nucleo-f207zg/src/stm32_usb.c | 2 +- .../arm/stm32/nucleo-f302r8/include/board.h | 2 +- .../arm/stm32/nucleo-f303re/include/board.h | 2 +- .../arm/stm32/nucleo-f303ze/include/board.h | 2 +- .../arm/stm32/nucleo-f334r8/include/board.h | 2 +- .../arm/stm32/nucleo-f334r8/src/stm32_spwm.c | 6 +- .../arm/stm32/nucleo-f412zg/src/stm32_usb.c | 2 +- .../arm/stm32/nucleo-f429zi/src/nucleo-144.h | 2 +- .../arm/stm32/nucleo-f429zi/src/stm32_usb.c | 2 +- .../arm/stm32/nucleo-f446re/src/stm32_can.c | 2 +- .../stm32/nucleo-f446re/src/stm32_cansock.c | 2 +- .../arm/stm32/nucleo-g431rb/src/stm32_can.c | 2 +- .../arm/stm32/nucleo-l152re/include/board.h | 2 +- boards/arm/stm32/odrive36/src/stm32_foc.c | 4 +- boards/arm/stm32/odrive36/src/stm32_usb.c | 2 +- .../stm32/olimex-stm32-e407/src/stm32_boot.c | 2 +- .../olimex-stm32-e407/src/stm32_mrf24j40.c | 2 +- .../stm32/olimex-stm32-e407/src/stm32_usb.c | 2 +- .../stm32/olimex-stm32-h405/src/stm32_boot.c | 2 +- .../stm32/olimex-stm32-h405/src/stm32_usb.c | 2 +- .../stm32/olimex-stm32-h407/src/stm32_boot.c | 2 +- .../stm32/olimex-stm32-h407/src/stm32_usb.c | 2 +- .../olimex-stm32-p207/src/olimex-stm32-p207.h | 2 +- .../stm32/olimex-stm32-p207/src/stm32_usb.c | 2 +- .../olimex-stm32-p407/src/olimex-stm32-p407.h | 2 +- .../stm32/olimex-stm32-p407/src/stm32_usb.c | 2 +- .../arm/stm32/olimexino-stm32/include/board.h | 2 +- .../olimexino-stm32/src/stm32_composite.c | 2 +- boards/arm/stm32/omnibusf4/src/stm32_usb.c | 2 +- boards/arm/stm32/photon/src/stm32_usb.c | 2 +- boards/arm/stm32/shenzhou/src/stm32_ili93xx.c | 2 +- boards/arm/stm32/shenzhou/src/stm32_usb.c | 2 +- boards/arm/stm32/stm3210e-eval/Kconfig | 2 +- .../arm/stm32/stm3210e-eval/include/board.h | 2 +- .../stm32/stm3210e-eval/src/stm32_composite.c | 2 +- .../stm32/stm3210e-eval/src/stm32_extmem.c | 2 +- .../arm/stm32/stm3210e-eval/src/stm32_lcd.c | 6 +- .../stm32/stm3220g-eval/src/stm3220g-eval.h | 2 +- .../arm/stm32/stm3220g-eval/src/stm32_boot.c | 2 +- .../arm/stm32/stm3220g-eval/src/stm32_usb.c | 2 +- .../stm32/stm3240g-eval/src/stm3240g-eval.h | 2 +- .../arm/stm32/stm3240g-eval/src/stm32_usb.c | 2 +- boards/arm/stm32/stm32_tiny/include/board.h | 2 +- .../arm/stm32/stm32f334-disco/include/board.h | 6 +- .../stm32/stm32f334-disco/src/stm32_smps.c | 2 +- .../stm32/stm32f3discovery/include/board.h | 2 +- .../stm32/stm32f3discovery/src/stm32_boot.c | 2 +- .../stm32/stm32f3discovery/src/stm32_usb.c | 2 +- .../stm32f3discovery/src/stm32f3discovery.h | 2 +- .../stm32/stm32f401rc-rs485/include/board.h | 2 +- .../stm32/stm32f401rc-rs485/src/stm32_usb.c | 2 +- .../stm32f411-minimum/src/stm32_composite.c | 2 +- .../stm32/stm32f411-minimum/src/stm32_usb.c | 2 +- .../stm32/stm32f411e-disco/src/stm32_usb.c | 2 +- .../stm32/stm32f429i-disco/src/stm32_usb.c | 2 +- .../stm32f429i-disco/src/stm32f429i-disco.h | 4 +- .../stm32/stm32f4discovery/src/CMakeLists.txt | 2 +- .../stm32f4discovery/src/stm32_composite.c | 2 +- .../stm32/stm32f4discovery/src/stm32_usb.c | 2 +- .../stm32f4discovery/src/stm32f4discovery.h | 2 +- .../arm/stm32/stm32ldiscovery/include/board.h | 8 +- .../arm/stm32/stm32ldiscovery/src/stm32_lcd.c | 8 +- .../include/board-stm32f103vct6.h | 2 +- .../b-l072z-lrwan1/include/board.h | 2 +- .../stm32f0l0g0/nucleo-f072rb/include/board.h | 2 +- .../nucleo-f072rb/src/stm32_bringup.c | 2 +- .../stm32f0l0g0/nucleo-f091rc/include/board.h | 2 +- .../stm32f0l0g0/nucleo-l073rz/include/board.h | 2 +- .../stm32f051-discovery/include/board.h | 2 +- .../stm32f072-discovery/include/board.h | 2 +- .../stm32l0538-disco/include/board.h | 2 +- .../stm32f7/common/src/stm32_cansock_setup.c | 2 +- .../stm32f7/nucleo-f722ze/src/nucleo-f722ze.h | 2 +- .../nucleo-f722ze/src/stm32_composite.c | 2 +- .../arm/stm32f7/nucleo-f722ze/src/stm32_usb.c | 2 +- .../stm32f7/nucleo-f746zg/src/nucleo-f746zg.h | 2 +- .../nucleo-f746zg/src/stm32_composite.c | 2 +- .../arm/stm32f7/nucleo-f746zg/src/stm32_usb.c | 2 +- .../nucleo-f767zi/src/stm32_composite.c | 2 +- .../arm/stm32f7/nucleo-f767zi/src/stm32_usb.c | 2 +- .../arm/stm32f7/stm32f746-ws/src/stm32_usb.c | 2 +- .../stm32f7/stm32f746g-disco/src/stm32_usb.c | 2 +- .../src/stm32_composite.c | 2 +- .../stm32f777zit6-meadow/src/stm32_usb.c | 2 +- .../stm32h7/linum-stm32h753bi/include/board.h | 2 +- .../linum-stm32h753bi/src/linum-stm32h753bi.h | 2 +- .../stm32h7/linum-stm32h753bi/src/stm32_usb.c | 2 +- .../stm32h7/nucleo-h743zi/src/nucleo-h743zi.h | 2 +- .../nucleo-h743zi/src/stm32_composite.c | 2 +- .../arm/stm32h7/nucleo-h743zi/src/stm32_usb.c | 2 +- .../nucleo-h743zi2/src/nucleo-h743zi2.h | 2 +- .../stm32h7/nucleo-h743zi2/src/stm32_usb.c | 2 +- .../arm/stm32h7/nucleo-h745zi/src/stm32_usb.c | 2 +- boards/arm/stm32h7/openh743i/src/openh743i.h | 2 +- .../stm32h7/openh743i/src/stm32_composite.c | 2 +- .../arm/stm32h7/openh743i/src/stm32_sdmmc.c | 2 +- boards/arm/stm32h7/openh743i/src/stm32_usb.c | 2 +- .../arm/stm32h7/openh743i/src/stm32_usbmsc.c | 2 +- .../stm32h7/stm32h745i-disco/src/stm32_usb.c | 2 +- .../stm32h745i-disco/src/stm32h745i_disco.h | 2 +- .../stm32h7/stm32h747i-disco/src/stm32_usb.c | 2 +- .../arm/stm32h7/stm32h750b-dk/src/stm32_usb.c | 2 +- .../stm32h7/stm32h750b-dk/src/stm32h750b-dk.h | 2 +- .../stm32l4/b-l475e-iot01a/src/stm32_spirit.c | 2 +- .../stm32l4/nucleo-l496zg/src/nucleo-144.h | 2 +- .../arm/stm32l4/nucleo-l496zg/src/stm32_usb.c | 2 +- .../stm32l4/steval-stlcs01v1/src/stm32_boot.c | 2 +- .../stm32l4/steval-stlcs01v1/src/stm32_usb.c | 2 +- .../include/stm32l4r9ai-disco-clocking.h | 2 +- .../include/flipperzero-clocking.h | 2 +- .../nucleo-wb55rg/include/nucleo-wb55rg.h | 2 +- boards/arm/stm32wl5/nucleo-wl55jc/Kconfig | 2 +- .../src/tm4c1294-launchpad.h | 2 +- .../src/tm4c129e-launchpad.h | 2 +- .../tlsr8278adk80d/scripts/flash_boot_ble.ld | 4 +- .../tms570/launchxl-tms57004/include/board.h | 2 +- .../launchxl-tms57004/scripts/flash-sram.ld | 2 +- .../tms570ls31x-usb-kit/include/board.h | 2 +- .../arm64/zynq-mpsoc/zcu111/include/board.h | 2 +- boards/avr/at32uc3/avr32dev1/include/board.h | 2 +- boards/avr/at32uc3/mizar32a/include/board.h | 2 +- .../mips/pic32mx/sure-pic32mx/include/board.h | 2 +- .../sure-pic32mx/src/pic32mx_autoleds.c | 2 +- .../pic32mx/sure-pic32mx/src/sure-pic32mx.h | 2 +- boards/renesas/m16c/skp16c26/include/board.h | 2 +- .../m16c/skp16c26/src/m16c_lcdconsole.c | 2 +- boards/renesas/sh1/us7032evb1/shterm/shterm.c | 2 +- boards/risc-v/k230/canmv230/src/Makefile | 2 +- boards/risc-v/litex/arty_a7/src/litex_sdio.c | 2 +- .../risc-v/mpfs/common/src/mpfs_composite.c | 2 +- boards/risc-v/mpfs/common/src/mpfs_ihc.c | 2 +- boards/risc-v/qemu-rv/rv-virt/src/Makefile | 2 +- boards/sparc/s698pm/s698pm-dkit/Kconfig | 2 +- .../tc397/scripts/Lcf_Gnuc_Tricore_Tc.lsl | 4 +- .../esp32/common/include/esp32_board_adc.h | 2 +- .../esp32/common/include/esp32_board_dac.h | 2 +- .../xtensa/esp32/common/src/esp32_board_adc.c | 2 +- boards/xtensa/esp32/common/src/esp32_cs4344.c | 2 +- boards/xtensa/esp32/common/src/esp32_es8388.c | 2 +- .../common/include/esp32s2_board_adc.h | 2 +- .../esp32s2/common/src/esp32s2_board_adc.c | 2 +- .../esp32s2/common/src/esp32s2_cs4344.c | 2 +- .../esp32s2/common/src/esp32s2_es8311.c | 2 +- .../common/include/esp32s3_board_adc.h | 2 +- .../esp32s3/common/src/esp32s3_board_adc.c | 2 +- .../esp32s3/common/src/esp32s3_cs4344.c | 2 +- .../esp32s3/common/src/esp32s3_es8311.c | 2 +- .../src/esp32s3_board_lcd_ili9342c.c | 6 +- .../src/esp32s3_board_lcd_st7789.c | 2 +- .../esp32s3-eye/src/esp32s3_board_lcd.c | 2 +- .../esp32s3/esp32s3-lcd-ev/src/esp32s3_lcd.c | 2 +- .../src/esp32s3_board_lcd.c | 2 +- cmake/nuttx_add_dependencies.cmake | 2 +- cmake/nuttx_add_romfs.cmake | 4 +- cmake/nuttx_add_symtab.cmake | 2 +- cmake/nuttx_remove_compile_options.cmake | 2 +- crypto/cryptosoft.c | 2 +- drivers/analog/ads1115.c | 6 +- drivers/analog/ads1255.c | 2 +- drivers/analog/hx711.c | 6 +- drivers/analog/pga11x.c | 6 +- drivers/audio/cs4344.c | 2 +- drivers/audio/cs43l22.c | 2 +- drivers/audio/vs1053.c | 2 +- drivers/audio/wm8904.c | 2 +- drivers/audio/wm8994.c | 2 +- drivers/audio/wm8994.h | 22 +-- drivers/can/can_sender.c | 2 +- drivers/can/ctucanfd.h | 4 +- drivers/can/ctucanfd_pci.c | 2 +- drivers/can/kvaser_pci.c | 2 +- drivers/clk/clk.c | 2 +- drivers/clk/clk_rpmsg.c | 2 +- drivers/coresight/coresight_common.c | 2 +- drivers/coresight/coresight_core.c | 4 +- drivers/coresight/coresight_etb.c | 2 +- drivers/coresight/coresight_etm4.c | 2 +- drivers/coresight/coresight_tmc_core.c | 4 +- drivers/coresight/coresight_tmc_etf.c | 6 +- drivers/devicetree/fdt_cfi.c | 2 +- drivers/i3c/device.c | 2 +- drivers/i3c/master.c | 4 +- drivers/input/aw86225.c | 6 +- drivers/input/ff_dummy.c | 2 +- drivers/input/ff_upper.c | 2 +- drivers/input/spq10kbd.c | 2 +- drivers/input/stmpe811_tsc.c | 2 +- drivers/ioexpander/sx1509.c | 6 +- drivers/ipcc/ipcc_close.c | 2 +- drivers/ipcc/ipcc_open.c | 2 +- drivers/ipcc/ipcc_unlink.c | 4 +- drivers/ipcc/ipcc_write.c | 2 +- drivers/lcd/apa102.c | 2 +- drivers/lcd/gc9a01.c | 2 +- drivers/lcd/jd9851.c | 2 +- drivers/lcd/mio283qt2.c | 2 +- drivers/lcd/mio283qt9a.c | 2 +- drivers/lcd/pcd8544.h | 4 +- drivers/lcd/pcf8833.h | 2 +- drivers/lcd/ssd1680.c | 2 +- drivers/lcd/st7789.c | 4 +- drivers/leds/lp503x.c | 2 +- drivers/misc/rpmsgblk.c | 34 ++-- drivers/misc/rpmsgdev.c | 28 ++-- drivers/mmcsd/Kconfig | 2 +- drivers/mmcsd/sdio.c | 2 +- drivers/modem/alt1250/alt1250.c | 8 +- drivers/modem/alt1250/altcom_hdlr_firmware.c | 4 +- drivers/modem/alt1250/altcom_hdlr_net.c | 8 +- drivers/modem/alt1250/altcom_hdlr_sms.c | 2 +- drivers/modem/alt1250/altcom_hdlr_socket.c | 2 +- drivers/modem/alt1250/altmdm.c | 2 +- drivers/motor/Make.defs | 2 +- drivers/motor/foc/drv8301.c | 2 +- drivers/motor/foc/foc_pwr.c | 2 +- drivers/mtd/gd55.c | 2 +- drivers/mtd/mtd_config_fs.c | 6 +- drivers/mtd/mtd_onfi.c | 2 +- drivers/mtd/rpmsgmtd.c | 34 ++-- drivers/mtd/smart.c | 4 +- drivers/mtd/w25.c | 2 +- drivers/net/e1000.c | 18 +- drivers/net/e1000.h | 4 +- drivers/net/encx24j600.c | 2 +- drivers/net/igc.c | 14 +- drivers/net/igc.h | 4 +- drivers/net/ksz9477.c | 4 +- drivers/net/lan9250.c | 4 +- drivers/net/netdev_upperhalf.c | 4 +- drivers/net/tun.c | 2 +- drivers/net/wifi_sim.c | 4 +- drivers/note/note_driver.c | 2 +- drivers/pci/pci.c | 34 ++-- drivers/pci/pci_ecam.c | 4 +- drivers/pci/pci_ep_test.c | 6 +- drivers/pci/pci_qemu_edu.c | 4 +- drivers/power/battery/axp202.c | 2 +- drivers/power/battery/goldfish_battery.c | 4 +- drivers/power/pm/Kconfig | 2 +- drivers/power/pm/pm_activity.c | 4 +- drivers/power/supply/Kconfig | 2 +- drivers/power/supply/smps.c | 10 +- drivers/rc/lirc_dev.c | 2 +- drivers/regmap/regmap_spi.c | 2 +- drivers/reset/core.c | 6 +- drivers/rpmsg/rpmsg_port_uart.c | 2 +- drivers/rpmsg/rpmsg_virtio_ivshmem.c | 2 +- drivers/rptun/rptun_ivshmem.c | 4 +- drivers/sensors/amg88xx.c | 2 +- drivers/sensors/apds9922.c | 4 +- drivers/sensors/bmi088.c | 4 +- drivers/sensors/bmi088_uorb.c | 4 +- drivers/sensors/bmi160_uorb.c | 4 +- drivers/sensors/bmm150_uorb.c | 2 +- drivers/sensors/bmp280_uorb.c | 6 +- drivers/sensors/ds18b20_uorb.c | 6 +- drivers/sensors/gnss_uorb.c | 2 +- drivers/sensors/lis2mdl_uorb.c | 2 +- drivers/sensors/lis3dsh.c | 2 +- drivers/sensors/mcp9844.c | 2 +- drivers/sensors/mpu9250_uorb.c | 2 +- drivers/sensors/sensor.c | 2 +- drivers/sensors/sensor_rpmsg.c | 4 +- drivers/sensors/zerocross.c | 4 +- drivers/serial/serial_cmsdk.c | 4 +- drivers/serial/serial_gdbstub.c | 2 +- drivers/serial/uart_16550.c | 2 +- drivers/serial/uart_pci_16550.c | 2 +- drivers/spi/spi_slave_driver.c | 4 +- drivers/syslog/Kconfig | 2 +- drivers/syslog/ramlog.c | 4 +- drivers/syslog/syslog_device.c | 2 +- drivers/thermal/thermal_core.c | 2 +- drivers/thermal/thermal_cpufreq_cooling.c | 2 +- drivers/timers/Kconfig | 4 +- drivers/timers/arch_alarm.c | 2 +- drivers/timers/capture.c | 6 +- drivers/timers/oneshot.c | 4 +- drivers/usbdev/cdcncm.c | 6 +- drivers/usbdev/usbmsc.c | 2 +- drivers/usbdev/usbmsc.h | 2 +- drivers/usbdev/usbmsc_scsi.c | 4 +- drivers/usbhost/usbhost_bthci.c | 2 +- drivers/usbhost/usbhost_hidkbd.c | 4 +- drivers/usbhost/usbhost_max3421e.c | 2 +- drivers/usbhost/usbhost_skeleton.c | 2 +- drivers/usbhost/usbhost_storage.c | 16 +- drivers/usbhost/usbhost_xboxcontroller.c | 2 +- drivers/usbmisc/fusb302.c | 2 +- drivers/vhost/vhost.c | 6 +- drivers/video/isx019.c | 4 +- drivers/video/max7456.c | 4 +- drivers/video/mipidsi/mipi_dsi_device.c | 2 +- drivers/video/vnc/vnc_fbdev.c | 4 +- drivers/video/vnc/vnc_keymap.c | 2 +- drivers/video/vnc/vnc_server.c | 2 +- drivers/video/vnc/vnc_updater.c | 2 +- drivers/virtio/virtio-mmio.c | 4 +- drivers/virtio/virtio-rng.c | 2 +- drivers/virtio/virtio-rpmb.c | 2 +- drivers/virtio/virtio-serial.c | 8 +- drivers/wireless/Kconfig | 2 +- drivers/wireless/bluetooth/bt_rpmsghci.c | 14 +- .../wireless/bluetooth/bt_rpmsghci_server.c | 24 +-- drivers/wireless/bluetooth/bt_slip.c | 4 +- .../wireless/ieee80211/bcm43xxx/bcmf_driver.c | 4 +- .../wireless/ieee802154/at86rf23x/at86rf23x.c | 2 +- drivers/wireless/ieee802154/xbee/xbee.c | 2 +- drivers/wireless/ieee802154/xbee/xbee.h | 2 +- drivers/wireless/ieee802154/xbee/xbee_mac.c | 2 +- drivers/wireless/lpwan/sx127x/sx127x.h | 4 +- drivers/wireless/spirit/include/spirit_irq.h | 2 +- .../spirit/include/spirit_pktcommon.h | 4 +- .../wireless/spirit/include/spirit_pktstack.h | 2 +- drivers/wireless/spirit/include/spirit_regs.h | 4 +- drivers/wireless/spirit/include/spirit_spi.h | 2 +- .../wireless/spirit/include/spirit_timer.h | 8 +- .../wireless/spirit/lib/spirit_pktcommon.c | 4 +- drivers/wireless/spirit/lib/spirit_timer.c | 8 +- fs/aio/Kconfig | 2 +- fs/fat/fs_fat32.c | 2 +- fs/fat/fs_fat32dirent.c | 4 +- fs/hostfs/Kconfig | 2 +- fs/inode/fs_inoderemove.c | 2 +- fs/inode/inode.h | 2 +- fs/littlefs/lfs_getsetattr.patch | 2 +- fs/mnemofs/mnemofs.c | 8 +- fs/mnemofs/mnemofs.h | 12 +- fs/mnemofs/mnemofs_ctz.c | 2 +- fs/mnemofs/mnemofs_fsobj.c | 4 +- fs/mnemofs/mnemofs_lru.c | 4 +- fs/mnemofs/mnemofs_master.c | 2 +- fs/nfs/nfs_vfsops.c | 2 +- fs/nfs/rpc_clnt.c | 4 +- fs/notify/Kconfig | 2 +- fs/nxffs/Kconfig | 6 +- fs/nxffs/nxffs_inode.c | 2 +- fs/nxffs/nxffs_open.c | 2 +- fs/nxffs/nxffs_pack.c | 2 +- fs/nxffs/nxffs_read.c | 2 +- fs/partition/fs_gpt.c | 2 +- fs/procfs/fs_procfsutil.c | 2 +- fs/romfs/fs_romfs.c | 2 +- fs/romfs/fs_romfs.h | 2 +- fs/shm/shmfs.c | 2 +- fs/spiffs/src/spiffs_check.c | 2 +- fs/spiffs/src/spiffs_vfs.c | 2 +- fs/unionfs/fs_unionfs.c | 2 +- fs/v9fs/client.c | 2 +- fs/vfs/fs_dir.c | 2 +- fs/vfs/fs_dup2.c | 2 +- fs/vfs/fs_epoll.c | 6 +- fs/vfs/fs_read.c | 2 +- fs/vfs/fs_symlink.c | 2 +- fs/vfs/fs_write.c | 2 +- graphics/nxbe/nxbe_move.c | 2 +- graphics/nxbe/nxbe_setsize.c | 2 +- graphics/nxterm/nxterm_driver.c | 6 +- graphics/nxterm/nxterm_font.c | 2 +- include/crypto/bn.h | 4 +- include/crypto/siphash.h | 2 +- include/dsp.h | 6 +- include/dspb16.h | 8 +- include/fixedmath.h | 4 +- include/nuttx/analog/hx711.h | 6 +- include/nuttx/binfmt/ieee695.h | 2 +- include/nuttx/board.h | 2 +- include/nuttx/compiler.h | 6 +- include/nuttx/coresight/coresight_funnel.h | 2 +- include/nuttx/drivers/rpmsgblk.h | 2 +- include/nuttx/drivers/rpmsgdev.h | 2 +- include/nuttx/fs/nxffs.h | 6 +- include/nuttx/fs/procfs.h | 2 +- include/nuttx/i3c/device.h | 2 +- include/nuttx/i3c/i3c_driver.h | 2 +- include/nuttx/i3c/master.h | 10 +- include/nuttx/input/aw86225.h | 2 +- include/nuttx/input/ff.h | 6 +- include/nuttx/input/ff_dummy.h | 2 +- include/nuttx/input/mouse.h | 2 +- include/nuttx/input/stmpe811.h | 2 +- include/nuttx/input/touchscreen.h | 2 +- include/nuttx/input/x11_xf86keysym.h | 4 +- include/nuttx/instrument.h | 2 +- include/nuttx/ioexpander/gpio.h | 2 +- include/nuttx/ioexpander/ioexpander.h | 2 +- include/nuttx/ipcc.h | 2 +- include/nuttx/lcd/ht16k33.h | 2 +- include/nuttx/lcd/ili9225.h | 6 +- include/nuttx/lcd/lcd.h | 4 +- include/nuttx/leds/pca9635pw.h | 8 +- include/nuttx/lib/elf.h | 2 +- include/nuttx/lin.h | 10 +- include/nuttx/math/fft.h | 2 +- include/nuttx/mm/kasan.h | 4 +- include/nuttx/mm/mempool.h | 8 +- include/nuttx/motor/foc/foc.h | 6 +- include/nuttx/motor/stepper.h | 2 +- include/nuttx/mqueue.h | 4 +- include/nuttx/mtd/mtd.h | 2 +- include/nuttx/mtd/nand_wrapper.h | 2 +- include/nuttx/net/gmii.h | 2 +- include/nuttx/net/icmpv6.h | 2 +- include/nuttx/net/ioctl.h | 6 +- include/nuttx/net/net.h | 6 +- include/nuttx/net/netdev.h | 2 +- include/nuttx/net/netdev_lowerhalf.h | 2 +- include/nuttx/net/sixlowpan.h | 2 +- include/nuttx/note/note_driver.h | 2 +- include/nuttx/nx/nx.h | 2 +- include/nuttx/nx/nxmu.h | 2 +- include/nuttx/nx/nxterm.h | 4 +- include/nuttx/pci/pci.h | 22 +-- include/nuttx/pci/pci_regs.h | 2 +- include/nuttx/power/battery_gauge.h | 2 +- include/nuttx/power/battery_ioctl.h | 2 +- include/nuttx/power/pm.h | 6 +- include/nuttx/power/regulator.h | 2 +- include/nuttx/rc/lirc_dev.h | 2 +- include/nuttx/reset/reset.h | 4 +- include/nuttx/rpmsg/rpmsg_port.h | 2 +- include/nuttx/sched.h | 4 +- include/nuttx/sched_note.h | 4 +- include/nuttx/scsi.h | 4 +- include/nuttx/sdio.h | 2 +- include/nuttx/sdio_slave.h | 6 +- include/nuttx/sensors/gnss.h | 4 +- include/nuttx/sensors/lis2mdl.h | 2 +- include/nuttx/sensors/ltc4151.h | 2 +- include/nuttx/sensors/qencoder.h | 6 +- include/nuttx/sensors/sensor.h | 6 +- include/nuttx/serial/uart_16550.h | 2 +- include/nuttx/serial/uart_cmsdk.h | 2 +- include/nuttx/spi/slave.h | 2 +- include/nuttx/spinlock.h | 20 ++- include/nuttx/timers/capture.h | 8 +- include/nuttx/timers/pwm.h | 4 +- include/nuttx/timers/timer.h | 2 +- include/nuttx/usb/audio.h | 2 +- include/nuttx/usb/ehci.h | 8 +- include/nuttx/usb/usbdev.h | 2 +- include/nuttx/usb/usbdev_trace.h | 2 +- include/nuttx/usb/usbhost.h | 2 +- include/nuttx/video/fb.h | 12 +- include/nuttx/video/mipi_dsi.h | 10 +- include/nuttx/wireless/bluetooth/bt_ioctl.h | 2 +- include/nuttx/wireless/cellular/cellular.h | 2 +- include/nuttx/wireless/ieee80211/ieee80211.h | 4 +- .../wireless/ieee802154/ieee802154_mac.h | 2 +- include/nuttx/wireless/lpwan/sx126x.h | 4 +- include/nuttx/wireless/lte/lte.h | 16 +- include/semaphore.h | 4 +- include/sys/poll.h | 4 +- include/sys/videoio.h | 2 +- libs/libc/aio/aio_error.c | 2 +- libs/libc/ctype/lib_ctype.c | 2 +- libs/libc/elf/elf_depend.c | 4 +- libs/libc/elf/elf_loadhdrs.c | 2 +- libs/libc/gdbstub/lib_gdbstub.c | 26 +-- libs/libc/machine/arm64/gnu/arch_strcmp.S | 2 +- libs/libc/machine/arm64/gnu/arch_strcpy.S | 2 +- libs/libc/machine/arm64/gnu/arch_strnlen.S | 2 +- libs/libc/machine/risc-v/arch_elf.c | 2 +- libs/libc/machine/x86_64/arch_elf64.c | 2 +- libs/libc/machine/x86_64/gnu/arch_memcmp.S | 2 +- libs/libc/machine/x86_64/gnu/arch_strcmp.S | 4 +- libs/libc/misc/lib_backtrace.c | 4 +- libs/libc/misc/lib_bitmap.c | 4 +- libs/libc/misc/lib_envpath.c | 2 +- libs/libc/misc/lib_instrument.c | 2 +- libs/libc/misc/lib_ncompress.c | 2 +- libs/libc/netdb/lib_dnsquery.c | 6 +- libs/libc/netdb/lib_parsehostfile.c | 6 +- libs/libc/netdb/lib_rexec.c | 2 +- libs/libc/pthread/pthread_setcancelstate.c | 6 +- libs/libc/pthread/pthread_setcanceltype.c | 6 +- libs/libc/pthread/pthread_testcancel.c | 2 +- libs/libc/regex/regcomp.c | 2 +- libs/libc/sched/task_cancelpt.c | 2 +- libs/libc/stdio/Kconfig | 2 +- libs/libc/stdio/lib_fgetwc.c | 6 +- libs/libc/stdio/lib_getwc.c | 2 +- libs/libc/stdio/lib_libvscanf.c | 2 +- libs/libc/stdio/lib_setvbuf.c | 4 +- libs/libc/stdlib/lib_bsearch.c | 2 +- libs/libc/stdlib/lib_reallocarray.c | 2 +- libs/libc/string/lib_bsdmemccpy.c | 2 +- libs/libc/string/lib_bsdmemchr.c | 2 +- libs/libc/string/lib_bsdmemcmp.c | 2 +- libs/libc/string/lib_bsdmemcpy.c | 2 +- libs/libc/string/lib_bsdmemrchr.c | 2 +- libs/libc/string/lib_memmem.c | 2 +- libs/libc/time/lib_strftime.c | 8 +- libs/libc/unistd/lib_getopt_common.c | 2 +- libs/libc/userfs/lib_userfs.c | 2 +- libs/libc/wchar/lib_wcsncmp.c | 2 +- libs/libc/wchar/lib_wcswidth.c | 2 +- libs/libdsp/lib_foc.c | 2 +- libs/libdsp/lib_foc_b16.c | 2 +- libs/libdsp/lib_motor.c | 2 +- libs/libdsp/lib_motor_b16.c | 2 +- libs/libdsp/lib_pid.c | 2 +- libs/libdsp/lib_pid_b16.c | 2 +- libs/libm/libm/lib_lgamma.c | 14 +- ...uild-error-remove-unused-file-fenv.h.patch | 4 +- ...-build-error-do-not-include-config.h.patch | 4 +- ...ld-error-INFINITY-error-in-quickjs.c.patch | 2 +- ...ewlib-disable-optmisation-for-sincos.patch | 2 +- libs/libm/newlib/CMakeLists.txt | 2 +- libs/libm/newlib/Make.defs | 2 +- libs/libm/newlib/include/machine/ieeefp.h | 4 +- ...t-error-float_t-has-not-been-declare.patch | 2 +- ...add-math.h-and-complex.h-to-openlibm.patch | 2 +- libs/libm/openlibm/Make.defs | 2 +- libs/libnx/nxfonts/nxfonts_cache.c | 2 +- libs/libnx/nxglib/nxglib_nullrect.c | 2 +- libs/libnx/nxglib/nxglib_splitline.c | 4 +- libs/libnx/nxmu/nx_synch.c | 2 +- libs/libnx/nxtk/nxtk_containerclip.c | 2 +- ...rload-constructor-of-filebuf-ostream.patch | 2 +- mm/map/vm_region.c | 2 +- mm/mm_gran/mm_grantable.h | 2 +- mm/mm_heap/mm.h | 2 +- mm/shm/shm.h | 2 +- ...ining-on-implicit-pointer-conversion.patch | 2 +- net/arp/arp.h | 2 +- net/arp/arp_out.c | 4 +- net/arp/arp_table.c | 2 +- net/bluetooth/bluetooth_poll.c | 2 +- net/can/can_callback.c | 4 +- net/can/can_sockif.c | 2 +- net/devif/devif_poll.c | 2 +- net/icmp/icmp_sockif.c | 2 +- net/icmpv6/icmpv6_linkipaddr.c | 2 +- net/icmpv6/icmpv6_radvertise.c | 6 +- net/icmpv6/icmpv6_sockif.c | 2 +- net/ieee802154/ieee802154.h | 2 +- net/ieee802154/ieee802154_sockif.c | 2 +- net/inet/inet_sockif.c | 2 +- net/inet/ipv4_build_header.c | 2 +- net/ipforward/ipv6_forward.c | 2 +- net/ipfrag/ipfrag.c | 4 +- net/ipfrag/ipv4_frag.c | 4 +- net/ipfrag/ipv6_frag.c | 8 +- net/local/local_accept.c | 6 +- net/local/local_conn.c | 4 +- net/local/local_sockif.c | 2 +- net/mld/mld_report.c | 2 +- net/nat/ipv4_nat.c | 2 +- net/nat/ipv6_nat.c | 2 +- net/nat/nat.h | 2 +- net/neighbor/neighbor.h | 2 +- net/neighbor/neighbor_add.c | 2 +- net/neighbor/neighbor_ethernet_out.c | 2 +- net/neighbor/neighbor_out.c | 2 +- net/netdev/netdev_input.c | 2 +- net/netdev/netdev_ipv6.c | 2 +- net/netdev/netdev_register.c | 4 +- net/route/fileroute.h | 2 +- net/route/net_fileroute.c | 2 +- net/sixlowpan/sixlowpan.h | 2 +- net/sixlowpan/sixlowpan_framelist.c | 2 +- net/sixlowpan/sixlowpan_input.c | 2 +- net/sixlowpan/sixlowpan_reassbuf.c | 2 +- net/sixlowpan/sixlowpan_tcpsend.c | 2 +- net/tcp/tcp.h | 14 +- net/tcp/tcp_cc.c | 2 +- net/tcp/tcp_conn.c | 2 +- net/tcp/tcp_input.c | 2 +- net/tcp/tcp_send.c | 2 +- net/udp/udp_conn.c | 2 +- net/usrsock/usrsock_devif.c | 2 +- net/usrsock/usrsock_sockif.c | 2 +- net/utils/net_ipchksum.c | 2 +- net/utils/net_lock.c | 6 +- net/utils/net_mask2pref.c | 4 +- net/utils/utils.h | 6 +- ...wledge-the-received-creation-message.patch | 4 +- ...ature-to-64-bit-in-all-virtio_dispat.patch | 2 +- sched/group/group_childstatus.c | 2 +- sched/irq/irq_attach_thread.c | 2 +- sched/irq/irq_attach_wqueue.c | 2 +- sched/mqueue/mq_send.c | 8 +- sched/pthread/pthread_exit.c | 2 +- sched/pthread/pthread_mutex.c | 4 +- sched/pthread/pthread_mutextrylock.c | 2 +- sched/sched/sched_releasetcb.c | 2 +- sched/signal/sig_action.c | 2 +- sched/signal/sig_default.c | 2 +- sched/task/task_activate.c | 2 +- sched/task/task_setup.c | 2 +- tools/ci/docker/linux/Dockerfile | 2 +- tools/ci/testrun/README.md | 2 +- tools/ci/testrun/utils/common.py | 4 +- tools/configure.c | 2 +- tools/copydir.bat | 2 +- tools/copydir.sh | 2 +- tools/define.bat | 2 +- tools/define.sh | 2 +- tools/doreleasenotes.py | 2 +- tools/kconfig2html.c | 4 +- tools/mkfsdata.py | 2 +- tools/parsetrace.py | 2 +- tools/pynuttx/nxgdb/dmesg.py | 2 +- tools/pynuttx/nxgdb/fs.py | 2 +- tools/pynuttx/nxgdb/macros.py | 2 +- tools/pynuttx/nxgdb/stack.py | 2 +- tools/pynuttx/nxgdb/thread.py | 2 +- tools/pynuttx/nxgdb/utils.py | 2 +- tools/uncrustify.cfg | 2 +- wireless/ieee802154/mac802154_internal.h | 6 +- 1670 files changed, 3162 insertions(+), 2991 deletions(-) diff --git a/.codespell-ignore-lines b/.codespell-ignore-lines index 5b1ac140ba..71a0129b63 100644 --- a/.codespell-ignore-lines +++ b/.codespell-ignore-lines @@ -15,4 +15,158 @@ Linix 45ZWN24-40 2 0.5 Ohm 0.400 mH 2.34A 24V * [#14540](https://github.com/apache/nuttx/pull/14540) CMake/preprocess: fix typo PREPROCES -> PREPROCESS * [#14927](https://github.com/apache/nuttx/pull/14927) spelling: fix spelling typo premption -> preemption * [#15520](https://github.com/apache/nuttx/pull/15520) drivers/note: fix typo falgs and align local name to irq_mask +* [#4526](https://github.com/apache/nuttx/pull/4526) Rearch video +* [#6447](https://github.com/apache/nuttx/pull/6447) bcm43xxx: Remove bcmf_txavail_work and resue bcmf_tx_poll_work ans init + * CAF : Depends on CONFIG_NET_PROMISCUOUS + * been lost). If ORE is set along with RXNE then it tells you + /* GIR bits must be masked! */ +#define MU_GIER_GIE(n) (1 << (n)) /* Bit n: MUA/MUB General Purpose Interrupt Enable n (GIEn) */ + tloadr r1, DEBUG_GPIO @0x80058a PB oen + .word (0x80058a) @ PBx oen + * FLASH_STATUS_WEL: The Write Enable Latch (WEL) bit indicates the + * 1. Enable the SPI and I2C for GroupA and GroupD; +/* HALP - Hall Current and Expected patterns */ +#define USIC_TCSR_FLEMD (1 << 2) /* Bit 2: FLE Mode */ + * (due to CALL or RCALL instruction). +/* Selete the SCIBR register value */ + addd #(TOTALFRAME_SIZE-INTFRAME_SIZE) + addd #INTFRAME_SIZE + unsigned short ATTCH:1; + unsigned long ACEND:1; + unsigned long ENDE:1; + * Description : Clear the specified port's ATTCH-bit; "ATTCH Interrupt + * Description : Enable ATTCH (attach) interrupt of the specified USB + * Description : Disable ATTCH (attach) interrupt of the specified USB + * Description : Disable USB Bus Interrupts OVRCR, ATTCH, DTCH, and BCHG. + /* ATTCH status Clear */ + /* ATTCH Clear */ + /* ATTCH interrupt disable */ + /* ATTCH interrupt enable */ + /* The previous command is not accepted, leaving the WEL + * as long as the following conditions are aheared to. + as long as the following conditions are aheared to. + * The licence and distribution terms for any publically available version or + The licence and distribution terms for any publically available version or + * The licence and distribution terms for any publically + The licence and distribution terms for any publically + (WEL bit) and in AAI mode (AAI bit). +#define W25QXXXJV_READ_STATUS_1 0x05 /* SRP|SEC|TB |BP2|BP1|BP0|WEL|BUSY */ +#define W25QXXXJV_WRITE_STATUS_1 0x01 /* SRP|SEC|TB |BP2|BP1|BP0|WEL|BUSY */ + * WEL=1. + * instruction, WEL=1. + ret = apds9960_i2c_write8(priv, APDS9960_GCONFIG4, (GMODE | GIEN)); + uint32_t allo = 0; + allo++; + spiffs_gcinfo("Wipe pallo=%" PRIu32 " pdele=%" PRIu32 "\n", allo, dele); + fs->alloc_pages -= allo; +#define XK_Arabic_tehmarbuta 0x05c9 /* U+0629 ARABIC LETTER TEH MARBUTA */ +#define XK_Arabic_teh 0x05ca /* U+062A ARABIC LETTER TEH */ +#define XK_Greek_LAMDA 0x07cb /* U+039B GREEK CAPITAL LETTER LAMDA */ +#define XK_Greek_LAMBDA 0x07cb /* U+039B GREEK CAPITAL LETTER LAMDA */ +#define XK_Greek_lamda 0x07eb /* U+03BB GREEK SMALL LETTER LAMDA */ +#define XK_Greek_lambda 0x07eb /* U+03BB GREEK SMALL LETTER LAMDA */ +#define XK_Armenian_SE 0x100054d /* U+054D ARMENIAN CAPITAL LETTER SEH */ +#define XK_Armenian_se 0x100057d /* U+057D ARMENIAN SMALL LETTER SEH */ +#define XK_Armenian_VEV 0x100054e /* U+054E ARMENIAN CAPITAL LETTER VEW */ +#define XK_Armenian_vev 0x100057e /* U+057E ARMENIAN SMALL LETTER VEW */ +#define XK_Sinh_o2 0x1000ddc /* U+0DDC SINHALA KOMBUVA HAA AELA-PILLA*/ +#define XK_Sinh_oo2 0x1000ddd /* U+0DDD SINHALA KOMBUVA HAA DIGA AELA-PILLA*/ +#define XK_Sinh_au2 0x1000dde /* U+0DDE SINHALA KOMBUVA HAA GAYANUKITTA */ +#define GIEN (1 << 1) /* Bit 1: Gesture Interrupt Enable */ +/* See also http://vektor.theorem.ca/graphics/ycbcr/ */ + * is in froms[] array which points to tos[] array + " + ofo %d" + % ("txbuf", "rxbuf", "ofo", "local_address", "remote_address") + FAR int_fast32_t *offsetp); + FAR int_fast32_t *offsetp) + ans = (FAR struct dns_answer_s *)nameptr; + * been lost). If ORE is set along with RXNE then it tells you +# define WR9_INTACKEN (0x20) /* Bit 5: Software INTACK Enable */ + FAR struct dns_answer_s *ans; + * We use RUNSTALL and RESETING signals to ensure that the App core stops + /* Reply with a WONT, that means we will not work in + /* Reply with a WONT */ + exten = (extcfg & ADC_CFGR_EXTEN_MASK); + exten = (extcfg & ADC_EXTREG_EXTEN_MASK); + exten = extcfg & ADC_EXTREG_EXTEN_MASK; + if (exten > 0) + setbits = (extsel | exten); + setbits = extsel | exten; + uint32_t exten = 0; + * SPDX-FileContributor: Daniel Pereira Volpato + * SPDX-FileContributor: Guillherme da Silva Amaral + * SPDX-FileCopyrightText: 2019 Fundação CERTI. All rights reserved. + Copyright (C) 2019 Fundação CERTI. All rights reserved. + * SPDX-FileCopyrightText: Fundação CERTI. All rights reserved. + /* TSS (IST) for 64 bit long mode will be filled in up_irq. */ +/* IST data structures ****************************************************** + /* NOE, NWE, NE1, NBL1 */ + /* NOE, NWE, and NE1 */ + /* NOE, NWE, and NE3 */ + /* NOE, NWE */ + * PD4: FSMC NOE PE2: FSMC A23 + * SCL High Time: Thi = divider * SCLhi + * Fscl = Finput / (Thi + Tlo) + * If Thi == TloL: Fscl = Finput / (divider * SCL * 2) + * Thi = Tspi * CLKCFG.high + * Fbaud = 1 / (Thi + Tlow) + * If we assume that Thi == Tlow, then: + * Thi = Tspi * CLKCFG.high + * Fbaud = 1 / (2 * Thi) + * Te = (3/2) * p * (lambda_d * i_q - lambda_q * i_d) + * Te = (3/2) * p * (lambda_m * i_q + (L_d - L_q) * i_q * i_d) + * Te = (3/2) * p * i_q * (lambda_m + (L_d - L_q) * i_d) + * Pem = wm * Te + * Te = Tl + Td + B * wm + J * (d/dt) * wm + * Te = Tl + J * (d/dt) * wm + * (d/dt) * wm = (Te - Tl) / J + * Te - electromagnetic torque + * R0 = saveregs = pinter saved array + /* Get EXTEN and EXTSEL from input */ + set(SRCS regcomp.c regexec.c regerror.c tre-mem.c) +CSRCS += regcomp.c regexec.c regerror.c tre-mem.c +#include "tre.h" +/* from tre-compile.h +/* from tre-ast.c and tre-ast.h +/* from tre-stack.c and tre-stack.h +/* from tre-parse.c and tre-parse.h +/* from tre-compile.c +/* from tre-mem.h: */ + * libs/libc/regex/tre.h + * libs/libc/regex/tre-mem.c +libs/libc/tre.h +libs/libc/tre-mem.c +#define EDMA_ES_NCE (1 << 3) /* Bit 3: NBYTES/CITER Configuration Error (NCE) */ +#define EDMA_CH_ES_NCE (1 << 3) /* Bit 3: NBYTES/CITER Configuration Error (NCE) */ +#define CAN_RERRAR_NCE (1 << 24) /* Bit 24: Non-Correctable Error (NCE) */ +#define PINT_PMCTRL_SELPMATCH (1 << 0) /* Bit 0: Rin interrupts interrupt or pattern match function */ +#define STR71X_IRQ_T0TOI (29) /* IRQ 29: T0.TOI Timer 0 Overflow interrupt */ +#define CP0_CONFIG_KU_SHIFT (25) /* Bits 25-27: KUSEG and USEG cacheability */ +#define NT_PPC_TM_CFPR 0x109 /* TM checkpointed FPR Registers */ +#define FT08X_EFFECT_CHACK 0x58 /* Chack */ +#define XK_Thai_fofa 0x0dbd /* U+0E1D THAI CHARACTER FO FA */ + * ODER -> disabled + gpioinfo(" ODER: %08x OVR: %08x PVR: %08x PUER: %08x\n", + uint32_t fpr; + fpr = getreg32(STM32_EXTI_FPR1); + if (((rpr & mask) != 0) || ((fpr & mask) != 0)) + * (SPOFF Bits 0-7 = 0xA5) */ + * (SPOFF Bits 8-9 = 0); (SPON Bits 8-9 = 0) */ + [ESR_ELX_EC_SME] = "SME", + [ESR_ELX_EC_SME] = "SME", + IS_PADD(segment_hdr.load_addr) ? "padd" : + ret = register_mtddriver("/dev/fram", mtd_dev, 0755, NULL); + ret = nx_mount("/dev/fram", "/mnt/lfs", "littlefs", 0, + * TWRITE/TREAD + /* size[4] Tread tag[2] fid[4] offset[8] count[4] + * (see http://csrc.nist.gov/cryptval/shs/sha256-384-512.pdf) uses this + * PERIPHERAL 10AA AAS. IIII IIII MMMM MMMM MMMM MMMM + leas 2, sp + * To initialize the nCE, configure any PIO as an output pin (refer to Tips + * and Tricks for the supported nCE connection types) + * PCM Clock = (Crystal * (ND + 1 + FRACR/2^22) / (QDPMC + 1)) / 8 + /* The Figure of Merit (FoM) characterizing the ranging measurement */ + * | 0 | 1 | x | EXT | RIN | IN | off | + * FIFO mode, INT1 , THS 0 + * REG03[3] ITERM Termination Current Limit 128-1024mA Default: 256mA diff --git a/.codespellrc b/.codespellrc index 9e746d3f8c..d29107d13a 100644 --- a/.codespellrc +++ b/.codespellrc @@ -19,16 +19,20 @@ ignore-words-list = ACI, AFE, afile, - ALS, - AMEBA, + als, + ameba, ARCHTYPE, + BU, DAA, dout, emac, eeeprom, extint, filp, + finitel, + froms, FRAM, + FRO, hart, hsi, iif, @@ -37,16 +41,24 @@ ignore-words-list = inport, lod, mot, - NWE, - OEN, - PRES, + mis, + nexted, + numer, + nwe, + oen, + parm, + parms, + pres, RCALL, REGONS, SAIs, - SER, + sie, + ser, + servent, synopsys, TE, TIMOUT, + THRE, tolen, UE, WRON, diff --git a/CMakeLists.txt b/CMakeLists.txt index 0402b282d3..2bc93fc9d2 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -158,7 +158,7 @@ if(NOT EXISTS "${NUTTX_DEFCONFIG}") message(FATAL_ERROR "No config file found at ${NUTTX_DEFCONFIG}") endif() -# Generate inital .config ################################################### +# Generate initial .config ################################################### # This is needed right before any other configure step so that we can source # Kconfig variables into CMake variables @@ -267,7 +267,7 @@ if(NOT EXISTS ${CMAKE_BINARY_DIR}/boards/dummy/Kconfig) endif() endif() -# board platfrom driver +# board platform driver file(MAKE_DIRECTORY ${CMAKE_BINARY_DIR}/drivers) @@ -314,7 +314,7 @@ if(NOT EXISTS ${CMAKE_BINARY_DIR}/arch/${CONFIG_ARCH}/src/chip) ${CMAKE_BINARY_DIR}/arch/${CONFIG_ARCH}/src/chip) endif() -# Unsupport custom board/chips yet, workaround +# Unsupported custom board/chips yet, workaround if(NOT EXISTS ${NUTTX_APPS_BINDIR}/platform/board/Kconfig) file(MAKE_DIRECTORY ${NUTTX_APPS_BINDIR}/platform/board) @@ -381,7 +381,7 @@ include(nuttx_generate_headers) include(nuttx_generate_outputs) include(nuttx_add_library) -# add NuttX CMake extenstion after nuttx_add_library +# add NuttX CMake extension after nuttx_add_library include(nuttx_extensions) include(nuttx_add_application) diff --git a/CONTRIBUTING.md b/CONTRIBUTING.md index 0efbc0e7ba..e30eca11bb 100644 --- a/CONTRIBUTING.md +++ b/CONTRIBUTING.md @@ -37,7 +37,7 @@ standardized pull requests processing, as well as long term self-compatibility and maintenance of the project. Because every change may affect users, products, or services around the world, -all rules apply equally to all authors, reviewers, committers and maintainters. +all rules apply equally to all authors, reviewers, committers and maintainers. This is our Check-List for processing every incoming pull request. Also, we filter out breaking changes and handle them accordingly. @@ -282,7 +282,7 @@ We avoid breaking changes unless absolutely necessary and unavoidable **mandatory**. Help of the community is welcome. 7. Breaking change requires at least 4 independent positive PR reviews (see 1.16), all discussions resolved, and zero "request changes". - 8. Change must be well documented (buid / runtime test logs, pr, git + 8. Change must be well documented (build / runtime test logs, pr, git commit, documentation, release notes, etc) with clear notes on how to fix the introduced problems. 9. Breaking Change must be clearly marked with a `[BREAKING]` tag in the @@ -306,7 +306,7 @@ verification and minimizes possible negative impact on various users. See: https://github.com/apache/nuttx/blob/master/INVIOLABLES.md -### 1.15. Reviews reuqirements. +### 1.15. Review requirements. Before PR can be merged to the master repository it requires: @@ -409,7 +409,7 @@ as described in requirement 1.7. * Is new feature added? Is existing feature changed? NO / YES (please describe if yes). * Impact on user (will user need to adapt to change)? NO / YES (please describe if yes). - * Impact on build (will build process change)? NO / YES (please descibe if yes). + * Impact on build (will build process change)? NO / YES (please describe if yes). * Impact on hardware (will arch(s) / board(s) / driver(s) change)? NO / YES (please describe if yes). * Impact on documentation (is update required / provided)? NO / YES (please describe if yes). * Impact on security (any sort of implications)? NO / YES (please describe if yes). diff --git a/Documentation/ReleaseNotes/NuttX-7.19 b/Documentation/ReleaseNotes/NuttX-7.19 index 4738aa548e..78af93d9f5 100644 --- a/Documentation/ReleaseNotes/NuttX-7.19 +++ b/Documentation/ReleaseNotes/NuttX-7.19 @@ -317,7 +317,7 @@ for SMP. - graphics/traveler/tcledit and libwld: Add an X11 Tcl/Tk tool that can be used to edit Traveler world files. -- Graphics: Remove all NX server taks. Instead, call boardctl() to the +- Graphics: Remove all NX server tasks. Instead, call boardctl() to the NX server kernel thread. * Applications: apps/examples: diff --git a/LICENSE b/LICENSE index c2413baa83..41feb44395 100644 --- a/LICENSE +++ b/LICENSE @@ -6275,7 +6275,7 @@ libs/libc/stdlib/lib_ldiv.c libs/libc/stdlib/lib_lldiv.c ============================= -A direct leverage of the div() inplement by: +A direct leverage of the div() implemented by: Copyright (C) 2015 Stavros Polymenis. All rights reserved. diff --git a/arch/Kconfig b/arch/Kconfig index af25e857cc..af0fd00f6a 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -912,7 +912,7 @@ config PAGING default n depends on BUILD_KERNEL && ARCH_USE_MMU && !ARCH_ROMPGTABLE && !LEGACY_PAGING ---help--- - If set =y in your configation file, this setting will enable on-demand + If set =y in your configuration file, this setting will enable on-demand paging, which relies on a MMU to enable larger virtual memory spaces and map it to physical memory on-demand (usually during a page-fault exception). @@ -922,7 +922,7 @@ menuconfig LEGACY_PAGING default n depends on EXPERIMENTAL && ARCH_USE_MMU && !ARCH_ROMPGTABLE ---help--- - If set =y in your configation file, this setting will enable lazy loading + If set =y in your configuration file, this setting will enable lazy loading backed up by the experimental on-demand paging feature as described in https://nuttx.apache.org/docs/latest/components/paging.html. @@ -1186,7 +1186,7 @@ config ARCH_MINIMAL_VECTORTABLE if it occurs will result in an unexpected interrupt crash. config ARCH_MINIMAL_VECTORTABLE_DYNAMIC - bool "Dynaminc Minimal RAM usage for vector table" + bool "Dynamic Minimal RAM usage for vector table" default n depends on ARCH_MINIMAL_VECTORTABLE ---help--- diff --git a/arch/arm/include/dm320/irq.h b/arch/arm/include/dm320/irq.h index c07e98fb26..cce67c8ab8 100644 --- a/arch/arm/include/dm320/irq.h +++ b/arch/arm/include/dm320/irq.h @@ -75,7 +75,7 @@ #define DM320_IRQ_EXT14 35 /* IRQ35: External Interrupt #14 (GIO14) */ #define DM320_IRQ_EXT15 36 /* IRQ36: External Interrupt #15 (GIO15) */ #define DM320_IRQ_PREV0 37 /* IRQ37: Preview Engine 0 (Preview Over) */ -#define DM320_IRQ_PREV1 38 /* IRQ38: Preview Engine 1 (Preview Historgram Over) */ +#define DM320_IRQ_PREV1 38 /* IRQ38: Preview Engine 1 (Preview Histogram Over) */ #define DM320_IRQ_WDT 39 /* IRQ39: Watchdog Timer Interrupt */ #define DM320_IRQ_I2C 40 /* IRQ40: I2C Interrupt */ #define DM320_IRQ_CLKC 41 /* IRQ41: Clock controller Interrupt (wake up) */ diff --git a/arch/arm/include/gd32f4/gd32f4xx_irq.h b/arch/arm/include/gd32f4/gd32f4xx_irq.h index f13cfbb63a..afea23b302 100644 --- a/arch/arm/include/gd32f4/gd32f4xx_irq.h +++ b/arch/arm/include/gd32f4/gd32f4xx_irq.h @@ -209,7 +209,7 @@ #define GD32_IRQ_FPU (GD32_IRQ_EXINT+81) /* 81: FPU interrupt */ #else - #error "Unkonwn GD32F4xx chip." + #error "Unknown GD32F4xx chip." #endif /* CONFIG_GD32F4_GD32F450 */ #if defined(CONFIG_GD32F4_GD32F450) || defined(CONFIG_GD32F4_GD32F470) diff --git a/arch/arm/include/gd32f4/irq.h b/arch/arm/include/gd32f4/irq.h index c491d0b03d..7be202b305 100644 --- a/arch/arm/include/gd32f4/irq.h +++ b/arch/arm/include/gd32f4/irq.h @@ -74,7 +74,7 @@ #if defined(CONFIG_GD32F4_GD32F4XX) # include #else -# error "Uknown GD32 chip" +# error "Unknown GD32 chip" #endif /**************************************************************************** diff --git a/arch/arm/include/kinetis/chip.h b/arch/arm/include/kinetis/chip.h index 9014501fe3..98ee7b88a1 100644 --- a/arch/arm/include/kinetis/chip.h +++ b/arch/arm/include/kinetis/chip.h @@ -1224,7 +1224,7 @@ # define KINETIS_NUSBDEV 1 /* One USB device controller */ # define KINETIS_NSDHC 1 /* SD host controller */ # define KINETIS_NI2C 3 /* Three I2C modules */ -# define KINETIS_NUART 6 /* Six UART modues */ +# define KINETIS_NUART 6 /* Six UART modules */ # define KINETIS_NSPI 3 /* Three SPI modules */ # define KINETIS_NCAN 1 /* One CAN controllers */ # define KINETIS_NI2S 1 /* One I2S modules */ @@ -1263,7 +1263,7 @@ # define KINETIS_NUSBDEV 1 /* One USB device controller */ # define KINETIS_NSDHC 1 /* SD host controller */ # define KINETIS_NI2C 3 /* Three I2C modules */ -# define KINETIS_NUART 6 /* Six UART modues */ +# define KINETIS_NUART 6 /* Six UART modules */ # define KINETIS_NSPI 3 /* Three SPI modules */ # define KINETIS_NCAN 1 /* One CAN controllers */ # define KINETIS_NI2S 1 /* One I2S modules */ @@ -1380,7 +1380,7 @@ # define KINETIS_NUSBDEV 1 /* One USB device controller */ # define KINETIS_NSDHC 1 /* SD host controller */ # define KINETIS_NI2C 3 /* Three I2C modules */ -# define KINETIS_NUART 6 /* Six UART modues */ +# define KINETIS_NUART 6 /* Six UART modules */ # define KINETIS_NSPI 3 /* Three SPI modules */ # define KINETIS_NCAN 1 /* One CAN controllers */ # define KINETIS_NI2S 1 /* One I2S modules */ @@ -1419,7 +1419,7 @@ # define KINETIS_NUSBDEV 1 /* One USB device controller */ # define KINETIS_NSDHC 1 /* SD host controller */ # define KINETIS_NI2C 3 /* Three I2C modules */ -# define KINETIS_NUART 6 /* Six UART modues */ +# define KINETIS_NUART 6 /* Six UART modules */ # define KINETIS_NSPI 3 /* Three SPI modules */ # define KINETIS_NCAN 1 /* One CAN controllers */ # define KINETIS_NI2S 1 /* One I2S modules */ @@ -1458,7 +1458,7 @@ # define KINETIS_NUSBDEV 1 /* One USB device controller */ # define KINETIS_NSDHC 1 /* SD host controller */ # define KINETIS_NI2C 3 /* Three I2C modules */ -# define KINETIS_NUART 6 /* Six UART modues */ +# define KINETIS_NUART 6 /* Six UART modules */ # define KINETIS_NSPI 3 /* Three SPI modules */ # define KINETIS_NCAN 1 /* One CAN controllers */ # define KINETIS_NI2S 1 /* One I2S modules */ @@ -1497,7 +1497,7 @@ # define KINETIS_NUSBDEV 1 /* One USB device controller */ # define KINETIS_NSDHC 1 /* SD host controller */ # define KINETIS_NI2C 3 /* Three I2C modules */ -# define KINETIS_NUART 6 /* Six UART modues */ +# define KINETIS_NUART 6 /* Six UART modules */ # define KINETIS_NSPI 3 /* Three SPI modules */ # define KINETIS_NCAN 1 /* One CAN controllers */ # define KINETIS_NI2S 1 /* One I2S modules */ diff --git a/arch/arm/include/mx8mp/mx8mp_irq.h b/arch/arm/include/mx8mp/mx8mp_irq.h index c256291c08..6ec90e8d49 100644 --- a/arch/arm/include/mx8mp/mx8mp_irq.h +++ b/arch/arm/include/mx8mp/mx8mp_irq.h @@ -207,7 +207,7 @@ #define MX8MP_IRQ_SOFT_GPIO_START MX8MP_IRQ_NVECTORS -/* GPIO1 has dedicated interrupts for pins 0-7, however theses pin are also +/* GPIO1 has dedicated interrupts for pins 0-7, however these pins are also * connected to the multiplexed IRQ and both can be triggered together is * enabled. Here we choose to no use the dedicated IRQ. * REVISIT: add an option to choose the strategy: diff --git a/arch/arm/include/s32k3xx/s32k3x4_irq.h b/arch/arm/include/s32k3xx/s32k3x4_irq.h index c824b3d7f8..0f188fdafc 100644 --- a/arch/arm/include/s32k3xx/s32k3x4_irq.h +++ b/arch/arm/include/s32k3xx/s32k3x4_irq.h @@ -45,10 +45,10 @@ /* CPU to CPU and Directed Interrupts */ -#define S32K3XX_IRQ_CPU_TO_CPU1 (S32K3XX_IRQ_EXTINT + 0) /* 0: CPU to CPU interupt 0 (Core 0 --> Core 1) */ -#define S32K3XX_IRQ_CPU_TO_CPU2 (S32K3XX_IRQ_EXTINT + 1) /* 1: CPU to CPU interupt 1 (Core 0 --> Core 1) */ -#define S32K3XX_IRQ_CPU_TO_CPU3 (S32K3XX_IRQ_EXTINT + 2) /* 2: CPU to CPU interupt 2 (Core 0 <-- Core 1) */ -#define S32K3XX_IRQ_CPU_TO_CPU4 (S32K3XX_IRQ_EXTINT + 3) /* 3: CPU to CPU interupt 3 (Core 0 <-- Core 1) */ +#define S32K3XX_IRQ_CPU_TO_CPU1 (S32K3XX_IRQ_EXTINT + 0) /* 0: CPU to CPU interrupt 0 (Core 0 --> Core 1) */ +#define S32K3XX_IRQ_CPU_TO_CPU2 (S32K3XX_IRQ_EXTINT + 1) /* 1: CPU to CPU interrupt 1 (Core 0 --> Core 1) */ +#define S32K3XX_IRQ_CPU_TO_CPU3 (S32K3XX_IRQ_EXTINT + 2) /* 2: CPU to CPU interrupt 2 (Core 0 <-- Core 1) */ +#define S32K3XX_IRQ_CPU_TO_CPU4 (S32K3XX_IRQ_EXTINT + 3) /* 3: CPU to CPU interrupt 3 (Core 0 <-- Core 1) */ /* Shared Peripheral Interrupts - On-Platform Vectors */ diff --git a/arch/arm/include/stm32/stm32g4xxxx_irq.h b/arch/arm/include/stm32/stm32g4xxxx_irq.h index e600d2c2bf..be0ebc350c 100644 --- a/arch/arm/include/stm32/stm32g4xxxx_irq.h +++ b/arch/arm/include/stm32/stm32g4xxxx_irq.h @@ -167,7 +167,7 @@ #define STM32_IRQ_DMA2CH8 (STM32_IRQ_FIRST + 99) /* 99: DMA2 channel 8 global interrupt */ #define STM32_IRQ_CORDIC (STM32_IRQ_FIRST + 100) /* 100: CORDIC trigonometric accelerator interrupt */ -#define STM32_IRQ_FMAC (STM32_IRQ_FIRST + 101) /* 101: FMAC filter math acclerator interrupt */ +#define STM32_IRQ_FMAC (STM32_IRQ_FIRST + 101) /* 101: FMAC filter math accelerator interrupt */ #define STM32_IRQ_NEXTINT (102) #define NR_IRQS (STM32_IRQ_FIRST + 102) diff --git a/arch/arm/src/a1x/a1x_serial.c b/arch/arm/src/a1x/a1x_serial.c index 39c01d2757..a5c8b0250d 100644 --- a/arch/arm/src/a1x/a1x_serial.c +++ b/arch/arm/src/a1x/a1x_serial.c @@ -1442,7 +1442,7 @@ static bool up_txempty(struct uart_dev_s *dev) * * Description: * Performs the low level UART initialization early in debug so that the - * serial console will be available during bootup. This must be called + * serial console will be available during boot up. This must be called * before arm_serialinit. * * NOTE: Configuration of the CONSOLE UART was performed by up_lowsetup() diff --git a/arch/arm/src/am335x/am335x_i2c.c b/arch/arm/src/am335x/am335x_i2c.c index ba4b03a09a..d6e624e9e6 100644 --- a/arch/arm/src/am335x/am335x_i2c.c +++ b/arch/arm/src/am335x/am335x_i2c.c @@ -1557,7 +1557,7 @@ static int am335x_i2c_reset(struct i2c_master_s *dev) out: - /* Release the port for re-use by other clients */ + /* Release the port for reuse by other clients */ nxmutex_unlock(&priv->lock); return ret; diff --git a/arch/arm/src/am335x/am335x_serial.c b/arch/arm/src/am335x/am335x_serial.c index 927faf685f..a57d75b952 100644 --- a/arch/arm/src/am335x/am335x_serial.c +++ b/arch/arm/src/am335x/am335x_serial.c @@ -1266,7 +1266,7 @@ static bool up_txempty(struct uart_dev_s *dev) * * Description: * Performs the low level UART initialization early in debug so that the - * serial console will be available during bootup. This must be called + * serial console will be available during boot up. This must be called * before arm_serialinit. * * NOTE: Configuration of the CONSOLE UART was performed by up_lowsetup() diff --git a/arch/arm/src/arm/arm_allocpage.c b/arch/arm/src/arm/arm_allocpage.c index e8d19af415..9a2080c8ac 100644 --- a/arch/arm/src/arm/arm_allocpage.c +++ b/arch/arm/src/arm/arm_allocpage.c @@ -72,15 +72,15 @@ typedef uint32_t l2ndx_t; /* Free pages in memory are managed by indices ranging from up to * CONFIG_PAGING_NPAGED. Initially all pages are free so the page can be * simply allocated in order: 0, 1, 2, ... . After all CONFIG_PAGING_NPAGED - * pages have be filled, then they are blindly freed and re-used in the + * pages have be filled, then they are blindly freed and reused in the * same order 0, 1, 2, ... because we don't know any better. No smart "least * recently used" kind of logic is supported. */ static pgndx_t g_pgndx; -/* After CONFIG_PAGING_NPAGED have been allocated, the pages will be re-used. - * In order to re-used the page, we will have un-map the page from its +/* After CONFIG_PAGING_NPAGED have been allocated, the pages will be reused. + * In order to reused the page, we will have un-map the page from its * previous mapping. In order to that, we need to be able to map a physical * address to to an index into the PTE where it was mapped. The following * table supports this backward lookup - it is indexed by the page number diff --git a/arch/arm/src/arm/arm_syscall.c b/arch/arm/src/arm/arm_syscall.c index 8dfafd0412..e549a8b2f9 100644 --- a/arch/arm/src/arm/arm_syscall.c +++ b/arch/arm/src/arm/arm_syscall.c @@ -76,7 +76,7 @@ uint32_t *arm_syscall(uint32_t *regs) cmd = regs[REG_R0]; /* if cmd == SYS_restore_context (*running_task)->xcp.regs is valid - * should not be overwriten + * should not be overwritten */ if (cmd != SYS_restore_context) diff --git a/arch/arm/src/armv6-m/arm_ramvec_attach.c b/arch/arm/src/armv6-m/arm_ramvec_attach.c index 7f72a547f1..7441f993a2 100644 --- a/arch/arm/src/armv6-m/arm_ramvec_attach.c +++ b/arch/arm/src/armv6-m/arm_ramvec_attach.c @@ -71,7 +71,7 @@ int arm_ramvec_attach(int irq, up_vector_t vector) irqstate_t flags; /* If the new vector is NULL, then the vector is being detached. In - * this case, disable the itnerrupt and direct any interrupts to the + * this case, disable the interrupt and direct any interrupts to the * common exception handler. */ diff --git a/arch/arm/src/armv7-a/Kconfig b/arch/arm/src/armv7-a/Kconfig index 446eb8f086..519bf83425 100644 --- a/arch/arm/src/armv7-a/Kconfig +++ b/arch/arm/src/armv7-a/Kconfig @@ -32,7 +32,7 @@ config ARMV7A_GICV2_LEGACY_IRQ0 int "pci legacy irq0 default val" default 35 ---help--- - The qemu pci lagacy irq0 default is 35. -1 mean disable + The qemu pci legacy irq0 default is 35. -1 means disable config ARMV7A_GICv2M bool "gic support msi irq" diff --git a/arch/arm/src/armv7-a/arm_allocpage.c b/arch/arm/src/armv7-a/arm_allocpage.c index 613bfd6456..c9a8c2ef47 100644 --- a/arch/arm/src/armv7-a/arm_allocpage.c +++ b/arch/arm/src/armv7-a/arm_allocpage.c @@ -67,15 +67,15 @@ typedef uint32_t l1ndx_t; /* Free pages in memory are managed by indices ranging from up to * CONFIG_PAGING_NPAGED. Initially all pages are free so the page can be * simply allocated in order: 0, 1, 2, ... . After all CONFIG_PAGING_NPAGED - * pages have be filled, then they are blindly freed and re-used in the + * pages have be filled, then they are blindly freed and reused in the * same order 0, 1, 2, ... because we don't know any better. No smart "least * recently used" kind of logic is supported. */ static pgndx_t g_pgndx; -/* After CONFIG_PAGING_NPAGED have been allocated, the pages will be re-used. - * In order to re-used the page, we will have un-map the page from its +/* After CONFIG_PAGING_NPAGED have been allocated, the pages will be reused. + * In order to reused the page, we will have un-map the page from its * previous mapping. In order to that, we need to be able to map a physical * address to to an index into the PTE where it was mapped. The following * table supports this backward lookup - it is indexed by the page number diff --git a/arch/arm/src/armv7-a/arm_smpcall.c b/arch/arm/src/armv7-a/arm_smpcall.c index 7f25433956..ac1c6608e0 100644 --- a/arch/arm/src/armv7-a/arm_smpcall.c +++ b/arch/arm/src/armv7-a/arm_smpcall.c @@ -56,7 +56,7 @@ * * 1. It saves the current task state at the head of the current assigned * task list. - * 2. It porcess g_delivertasks + * 2. It processes g_delivertasks * 3. Returns from interrupt, restoring the state of the new task at the * head of the ready to run list. * diff --git a/arch/arm/src/armv7-a/arm_syscall.c b/arch/arm/src/armv7-a/arm_syscall.c index 1c024a4c18..c42bf603a7 100644 --- a/arch/arm/src/armv7-a/arm_syscall.c +++ b/arch/arm/src/armv7-a/arm_syscall.c @@ -184,7 +184,7 @@ uint32_t *arm_syscall(uint32_t *regs) cmd = regs[REG_R0]; /* if cmd == SYS_restore_context (*running_task)->xcp.regs is valid - * should not be overwriten + * should not be overwritten */ if (cmd != SYS_restore_context) diff --git a/arch/arm/src/armv7-a/arm_vectors.S b/arch/arm/src/armv7-a/arm_vectors.S index 5666beaccc..e4768144be 100644 --- a/arch/arm/src/armv7-a/arm_vectors.S +++ b/arch/arm/src/armv7-a/arm_vectors.S @@ -48,7 +48,7 @@ * Name: cpuindex * * Description: - * Return an index idenifying the current CPU. Single CPU case. Must be + * Return an index identifying the current CPU. Single CPU case. Must be * provided by MCU-specific logic in chip.h for the SMP case. * ****************************************************************************/ diff --git a/arch/arm/src/armv7-a/gic.h b/arch/arm/src/armv7-a/gic.h index cb294666e2..e23193d6bc 100644 --- a/arch/arm/src/armv7-a/gic.h +++ b/arch/arm/src/armv7-a/gic.h @@ -843,7 +843,7 @@ int arm_start_handler(int irq, void *context, void *arg); * * 1. It saves the current task state at the head of the current assigned * task list. - * 2. It porcess g_delivertasks + * 2. It processes g_delivertasks * 3. Returns from interrupt, restoring the state of the new task at the * head of the ready to run list. * diff --git a/arch/arm/src/armv7-m/arm_exception.S b/arch/arm/src/armv7-m/arm_exception.S index 4d13589c23..d209e4cf85 100644 --- a/arch/arm/src/armv7-m/arm_exception.S +++ b/arch/arm/src/armv7-m/arm_exception.S @@ -177,7 +177,7 @@ exception_common: */ #if CONFIG_ARCH_INTERRUPTSTACK < 7 - /* If CONFIG_ARCH_INTERRUPTSTACK is not defined, we will re-use the + /* If CONFIG_ARCH_INTERRUPTSTACK is not defined, we will reuse the * interrupted thread's stack. That may mean using either MSP or PSP * stack for interrupt level processing (in kernel mode). */ diff --git a/arch/arm/src/armv7-m/arm_ramvec_attach.c b/arch/arm/src/armv7-m/arm_ramvec_attach.c index ad331046bc..6f273ad7ec 100644 --- a/arch/arm/src/armv7-m/arm_ramvec_attach.c +++ b/arch/arm/src/armv7-m/arm_ramvec_attach.c @@ -71,7 +71,7 @@ int arm_ramvec_attach(int irq, up_vector_t vector) irqstate_t flags; /* If the new vector is NULL, then the vector is being detached. In - * this case, disable the itnerrupt and direct any interrupts to the + * this case, disable the interrupt and direct any interrupts to the * common exception handler. */ diff --git a/arch/arm/src/armv7-m/etm.h b/arch/arm/src/armv7-m/etm.h index 704ffdeaa7..cb114b1f70 100644 --- a/arch/arm/src/armv7-m/etm.h +++ b/arch/arm/src/armv7-m/etm.h @@ -533,7 +533,7 @@ #define _ETM_ETMCCER_EICEWPNT_MASK 0xF0000UL /* Bit mask for ETM_EICEWPNT */ #define _ETM_ETMCCER_EICEWPNT_DEFAULT 0x00000004UL /* Mode DEFAULT for ETM_ETMCCER */ #define ETM_ETMCCER_EICEWPNT_DEFAULT (_ETM_ETMCCER_EICEWPNT_DEFAULT << 16) /* Shifted mode DEFAULT for ETM_ETMCCER */ -#define ETM_ETMCCER_TEICEWPNT (0x1UL << 20) /* Trace Sart/Stop Block Uses EmbeddedICE watchpoint inputs */ +#define ETM_ETMCCER_TEICEWPNT (0x1UL << 20) /* Trace Start/Stop Block Uses EmbeddedICE watchpoint inputs */ #define _ETM_ETMCCER_TEICEWPNT_SHIFT 20 /* Shift value for ETM_TEICEWPNT */ #define _ETM_ETMCCER_TEICEWPNT_MASK 0x100000UL /* Bit mask for ETM_TEICEWPNT */ #define _ETM_ETMCCER_TEICEWPNT_DEFAULT 0x00000001UL /* Mode DEFAULT for ETM_ETMCCER */ diff --git a/arch/arm/src/armv7-m/nvic.h b/arch/arm/src/armv7-m/nvic.h index a48fc67e11..49d0af1633 100644 --- a/arch/arm/src/armv7-m/nvic.h +++ b/arch/arm/src/armv7-m/nvic.h @@ -187,7 +187,7 @@ #define NVIC_CPUID_BASE_OFFSET 0x0d00 /* CPUID base register */ #define NVIC_INTCTRL_OFFSET 0x0d04 /* Interrupt control state register */ #define NVIC_VECTAB_OFFSET 0x0d08 /* Vector table offset register */ -#define NVIC_AIRCR_OFFSET 0x0d0c /* Application interrupt/reset control registr */ +#define NVIC_AIRCR_OFFSET 0x0d0c /* Application interrupt/reset control register */ #define NVIC_SYSCON_OFFSET 0x0d10 /* System control register */ #define NVIC_CFGCON_OFFSET 0x0d14 /* Configuration control register */ #define NVIC_SYSH_PRIORITY_OFFSET(n) (0x0d14 + 4*((n) >> 2)) diff --git a/arch/arm/src/armv7-r/arm_mpu.c b/arch/arm/src/armv7-r/arm_mpu.c index cb5570a1bf..00fe6a492f 100644 --- a/arch/arm/src/armv7-r/arm_mpu.c +++ b/arch/arm/src/armv7-r/arm_mpu.c @@ -486,7 +486,7 @@ unsigned int mpu_configure_region(uintptr_t base, size_t size, * Configure a region for privileged, strongly ordered memory * * Input Parameters: - * table - MPU Initiaze table. + * table - MPU Initialize table. * count - Initialize the number of entries in the region table. * * Returned Value: diff --git a/arch/arm/src/armv7-r/arm_smpcall.c b/arch/arm/src/armv7-r/arm_smpcall.c index 1f5ae5410f..c6985ed557 100644 --- a/arch/arm/src/armv7-r/arm_smpcall.c +++ b/arch/arm/src/armv7-r/arm_smpcall.c @@ -56,7 +56,7 @@ * * 1. It saves the current task state at the head of the current assigned * task list. - * 2. It porcess g_delivertasks + * 2. It processes g_delivertasks * 3. Returns from interrupt, restoring the state of the new task at the * head of the ready to run list. * diff --git a/arch/arm/src/armv7-r/arm_syscall.c b/arch/arm/src/armv7-r/arm_syscall.c index 5961e0eaf4..275e0aa6f6 100644 --- a/arch/arm/src/armv7-r/arm_syscall.c +++ b/arch/arm/src/armv7-r/arm_syscall.c @@ -181,7 +181,7 @@ uint32_t *arm_syscall(uint32_t *regs) cmd = regs[REG_R0]; /* if cmd == SYS_restore_context (*running_task)->xcp.regs is valid - * should not be overwriten + * should not be overwritten */ if (cmd != SYS_restore_context) diff --git a/arch/arm/src/armv7-r/gic.h b/arch/arm/src/armv7-r/gic.h index 9699cdc4e7..ceb1b5594e 100644 --- a/arch/arm/src/armv7-r/gic.h +++ b/arch/arm/src/armv7-r/gic.h @@ -813,7 +813,7 @@ int arm_start_handler(int irq, void *context, void *arg); * * 1. It saves the current task state at the head of the current assigned * task list. - * 2. It porcess g_delivertasks + * 2. It processes g_delivertasks * 3. Returns from interrupt, restoring the state of the new task at the * head of the ready to run list. * diff --git a/arch/arm/src/armv7-r/mpu.h b/arch/arm/src/armv7-r/mpu.h index 5c1b6dfb1f..ac1f564cfc 100644 --- a/arch/arm/src/armv7-r/mpu.h +++ b/arch/arm/src/armv7-r/mpu.h @@ -337,7 +337,7 @@ unsigned int mpu_configure_region(uintptr_t base, size_t size, * Configure a region for privileged, strongly ordered memory * * Input Parameters: - * table - MPU Initiaze table. + * table - MPU Initialize table. * count - Initialize the number of entries in the region table. * * Returned Value: @@ -690,7 +690,7 @@ static inline void mpu_control(bool enable) * Name: mpu_peripheral * * Description: - * Configure a region as privileged periperal address space + * Configure a region as privileged peripheral address space * ****************************************************************************/ diff --git a/arch/arm/src/armv7-r/scu.h b/arch/arm/src/armv7-r/scu.h index f1786013f6..f7cd063f81 100644 --- a/arch/arm/src/armv7-r/scu.h +++ b/arch/arm/src/armv7-r/scu.h @@ -53,7 +53,7 @@ #define SCU_DEBUGRAM_OFFSET 0x0070 /* SCU Debug Tag RAM Operation Register */ #define SCU_DEBUGRAMDATA_OFFSET 0x0074 /* SCU Debug Tag RAM Data Value Register */ #define SCU_DEBUGRAMECC_OFFSET 0x0078 /* SCU Debug Tag RAM ECC Chunk Register */ -#define SCU_ECCERR_OFFSET 0x007c /* ECC Fatal Error Registe */ +#define SCU_ECCERR_OFFSET 0x007c /* ECC Fatal Error Register */ #define SCU_FPPFILTERSTART_OFFSET(n) (0x0080 + (n)*8) /* FPP Filtering Start Address Register for core n */ #define SCU_FPPFILTEREND_OFFSET(n) (0x0084 + (n)*8) /* FPP Filtering End Address Register for core n */ diff --git a/arch/arm/src/armv8-m/arm_exception.S b/arch/arm/src/armv8-m/arm_exception.S index 2798a1d0a7..5c54747c1f 100644 --- a/arch/arm/src/armv8-m/arm_exception.S +++ b/arch/arm/src/armv8-m/arm_exception.S @@ -188,7 +188,7 @@ exception_common: mrs r0, ipsr #if CONFIG_ARCH_INTERRUPTSTACK < 7 - /* If CONFIG_ARCH_INTERRUPTSTACK is not defined, we will re-use the + /* If CONFIG_ARCH_INTERRUPTSTACK is not defined, we will reuse the * interrupted thread's stack. That may mean using either MSP or PSP * stack for interrupt level processing (in kernel mode). */ diff --git a/arch/arm/src/armv8-m/arm_gen_nonsecfault.c b/arch/arm/src/armv8-m/arm_gen_nonsecfault.c index a18567dbf8..3d9040289a 100644 --- a/arch/arm/src/armv8-m/arm_gen_nonsecfault.c +++ b/arch/arm/src/armv8-m/arm_gen_nonsecfault.c @@ -81,13 +81,13 @@ bool weak_function arm_should_gen_nonsecurefault(void) * * Description: * For TEE & REE, securefault & busfault are not banked, so the faults can - * only forword to TEE/REE. + * only forward to TEE/REE. * But how to crash dump the other core which not handled faults ? * * Here we provide a way to resolve this problem: * 1. Set the securefault & busfault to TEE - * 2. busfault happend from TEE, then directly dump TEE - * 3. busfault happend from REE, then generate nonsecurefault + * 2. busfault happened from TEE, then directly dump TEE + * 3. busfault happened from REE, then generate nonsecurefault * 4. Back to REE, and dump * * Return values: @@ -121,7 +121,7 @@ int arm_gen_nonsecurefault(int irq, uint32_t *regs) return 0; } - /* Redict busfault to REE */ + /* Redirect busfault to REE */ up_secure_irq(NVIC_IRQ_BUSFAULT, false); } diff --git a/arch/arm/src/armv8-m/arm_ramvec_attach.c b/arch/arm/src/armv8-m/arm_ramvec_attach.c index a08ea3af21..abaf51b7d3 100644 --- a/arch/arm/src/armv8-m/arm_ramvec_attach.c +++ b/arch/arm/src/armv8-m/arm_ramvec_attach.c @@ -71,7 +71,7 @@ int arm_ramvec_attach(int irq, up_vector_t vector) irqstate_t flags; /* If the new vector is NULL, then the vector is being detached. In - * this case, disable the itnerrupt and direct any interrupts to the + * this case, disable the interrupt and direct any interrupts to the * common exception handler. */ diff --git a/arch/arm/src/armv8-m/etm.h b/arch/arm/src/armv8-m/etm.h index a150501ad7..59f00fbf19 100644 --- a/arch/arm/src/armv8-m/etm.h +++ b/arch/arm/src/armv8-m/etm.h @@ -277,7 +277,7 @@ #define _ETM_ETMCCR_TRACESS_MASK 0x4000000UL /* Bit mask for ETM_TRACESS */ #define _ETM_ETMCCR_TRACESS_DEFAULT 0x00000001UL /* Mode DEFAULT for ETM_ETMCCR */ #define ETM_ETMCCR_TRACESS_DEFAULT (_ETM_ETMCCR_TRACESS_DEFAULT << 26) /* Shifted mode DEFAULT for ETM_ETMCCR */ -#define ETM_ETMCCR_MMACCESS (0x1UL << 27) /* Coprocessor and Memeory Access */ +#define ETM_ETMCCR_MMACCESS (0x1UL << 27) /* Coprocessor and Memory Access */ #define _ETM_ETMCCR_MMACCESS_SHIFT 27 /* Shift value for ETM_MMACCESS */ #define _ETM_ETMCCR_MMACCESS_MASK 0x8000000UL /* Bit mask for ETM_MMACCESS */ #define _ETM_ETMCCR_MMACCESS_DEFAULT 0x00000001UL /* Mode DEFAULT for ETM_ETMCCR */ @@ -533,7 +533,7 @@ #define _ETM_ETMCCER_EICEWPNT_MASK 0xF0000UL /* Bit mask for ETM_EICEWPNT */ #define _ETM_ETMCCER_EICEWPNT_DEFAULT 0x00000004UL /* Mode DEFAULT for ETM_ETMCCER */ #define ETM_ETMCCER_EICEWPNT_DEFAULT (_ETM_ETMCCER_EICEWPNT_DEFAULT << 16) /* Shifted mode DEFAULT for ETM_ETMCCER */ -#define ETM_ETMCCER_TEICEWPNT (0x1UL << 20) /* Trace Sart/Stop Block Uses EmbeddedICE watchpoint inputs */ +#define ETM_ETMCCER_TEICEWPNT (0x1UL << 20) /* Trace Start/Stop Block Uses EmbeddedICE watchpoint inputs */ #define _ETM_ETMCCER_TEICEWPNT_SHIFT 20 /* Shift value for ETM_TEICEWPNT */ #define _ETM_ETMCCER_TEICEWPNT_MASK 0x100000UL /* Bit mask for ETM_TEICEWPNT */ #define _ETM_ETMCCER_TEICEWPNT_DEFAULT 0x00000001UL /* Mode DEFAULT for ETM_ETMCCER */ diff --git a/arch/arm/src/armv8-m/nvic.h b/arch/arm/src/armv8-m/nvic.h index 87bc35efa9..646ebbf33e 100644 --- a/arch/arm/src/armv8-m/nvic.h +++ b/arch/arm/src/armv8-m/nvic.h @@ -207,7 +207,7 @@ #define NVIC_CPUID_BASE_OFFSET 0x0d00 /* CPUID base register */ #define NVIC_INTCTRL_OFFSET 0x0d04 /* Interrupt control state register */ #define NVIC_VECTAB_OFFSET 0x0d08 /* Vector table offset register */ -#define NVIC_AIRCR_OFFSET 0x0d0c /* Application interrupt/reset control registr */ +#define NVIC_AIRCR_OFFSET 0x0d0c /* Application interrupt/reset control register */ #define NVIC_SYSCON_OFFSET 0x0d10 /* System control register */ #define NVIC_CFGCON_OFFSET 0x0d14 /* Configuration control register */ #define NVIC_SYSH_PRIORITY_OFFSET(n) (0x0d14 + 4*((n) >> 2)) diff --git a/arch/arm/src/armv8-r/arm_syscall.c b/arch/arm/src/armv8-r/arm_syscall.c index 475d0a4f9b..baa3146689 100644 --- a/arch/arm/src/armv8-r/arm_syscall.c +++ b/arch/arm/src/armv8-r/arm_syscall.c @@ -181,7 +181,7 @@ uint32_t *arm_syscall(uint32_t *regs) cmd = regs[REG_R0]; /* if cmd == SYS_restore_context (*running_task)->xcp.regs is valid - * should not be overwriten + * should not be overwritten */ if (cmd != SYS_restore_context) diff --git a/arch/arm/src/at32/Kconfig b/arch/arm/src/at32/Kconfig index a224009283..de2c0fe528 100644 --- a/arch/arm/src/at32/Kconfig +++ b/arch/arm/src/at32/Kconfig @@ -4431,10 +4431,10 @@ config AT32_TIM1_CHANNEL channel {1,..,4} config AT32_TIM1_CLOCK - int "TIM1 work frequence for capture" + int "TIM1 work frequency for capture" default 1000000 ---help--- - This clock frequence limiting the count rate at the expense of resolution. + This clock frequency limiting the count rate at the expense of resolution. endif # AT32_TIM1_CAP @@ -4460,10 +4460,10 @@ config AT32_TIM2_CHANNEL channel {1,..,4} config AT32_TIM2_CLOCK - int "TIM2 work frequence for capture" + int "TIM2 work frequency for capture" default 1000000 ---help--- - This clock frequence limiting the count rate at the expense of resolution. + This clock frequency limiting the count rate at the expense of resolution. endif # AT32_TIM2_CAP @@ -4489,10 +4489,10 @@ config AT32_TIM3_CHANNEL channel {1,..,4} config AT32_TIM3_CLOCK - int "TIM3 work frequence for capture" + int "TIM3 work frequency for capture" default 1000000 ---help--- - This clock frequence limiting the count rate at the expense of resolution. + This clock frequency limiting the count rate at the expense of resolution. endif # AT32_TIM3_CAP @@ -4518,10 +4518,10 @@ config AT32_TIM4_CHANNEL channel {1,..,4} config AT32_TIM4_CLOCK - int "TIM4 work frequence for capture" + int "TIM4 work frequency for capture" default 1000000 ---help--- - This clock frequence limiting the count rate at the expense of resolution. + This clock frequency limiting the count rate at the expense of resolution. endif # AT32_TIM4_CAP @@ -4547,10 +4547,10 @@ config AT32_TIM5_CHANNEL channel {1,..,4} config AT32_TIM5_CLOCK - int "TIM5 work frequence for capture" + int "TIM5 work frequency for capture" default 1000000 ---help--- - This clock frequence limiting the count rate at the expense of resolution. + This clock frequency limiting the count rate at the expense of resolution. endif # AT32_TIM5_CAP @@ -4576,10 +4576,10 @@ config AT32_TIM8_CHANNEL channel {1,..,4} config AT32_TIM8_CLOCK - int "TIM8 work frequence for capture" + int "TIM8 work frequency for capture" default 1000000 ---help--- - This clock frequence limiting the count rate at the expense of resolution. + This clock frequency limiting the count rate at the expense of resolution. endif # AT32_TIM8_CAP @@ -4605,10 +4605,10 @@ config AT32_TIM9_CHANNEL channel {1,..,4} config AT32_TIM9_CLOCK - int "TIM9 work frequence for capture" + int "TIM9 work frequency for capture" default 1000000 ---help--- - This clock frequence limiting the count rate at the expense of resolution. + This clock frequency limiting the count rate at the expense of resolution. endif # AT32_TIM9_CAP @@ -4634,10 +4634,10 @@ config AT32_TIM10_CHANNEL channel {1,..,4} config AT32_TIM10_CLOCK - int "TIM10 work frequence for capture" + int "TIM10 work frequency for capture" default 1000000 ---help--- - This clock frequence limiting the count rate at the expense of resolution. + This clock frequency limiting the count rate at the expense of resolution. endif # AT32_TIM10_CAP @@ -4663,10 +4663,10 @@ config AT32_TIM11_CHANNEL channel {1,..,4} config AT32_TIM11_CLOCK - int "TIM11 work frequence for capture" + int "TIM11 work frequency for capture" default 1000000 ---help--- - This clock frequence limiting the count rate at the expense of resolution. + This clock frequency limiting the count rate at the expense of resolution. endif # AT32_TIM11_CAP @@ -4692,10 +4692,10 @@ config AT32_TIM12_CHANNEL channel {1,..,4} config AT32_TIM12_CLOCK - int "TIM12 work frequence for capture" + int "TIM12 work frequency for capture" default 1000000 ---help--- - This clock frequence limiting the count rate at the expense of resolution. + This clock frequency limiting the count rate at the expense of resolution. endif # AT32_TIM12_CAP @@ -4721,10 +4721,10 @@ config AT32_TIM13_CHANNEL channel {1,..,4} config AT32_TIM13_CLOCK - int "TIM13 work frequence for capture" + int "TIM13 work frequency for capture" default 1000000 ---help--- - This clock frequence limiting the count rate at the expense of resolution. + This clock frequency limiting the count rate at the expense of resolution. endif # AT32_TIM13_CAP @@ -4750,10 +4750,10 @@ config AT32_TIM14_CHANNEL channel {1,..,4} config AT32_TIM14_CLOCK - int "TIM14 work frequence for capture" + int "TIM14 work frequency for capture" default 1000000 ---help--- - This clock frequence limiting the count rate at the expense of resolution. + This clock frequency limiting the count rate at the expense of resolution. endif # AT32_TIM14_CAP diff --git a/arch/arm/src/at32/at32_eth.c b/arch/arm/src/at32/at32_eth.c index be003545f5..dd8dbd5da1 100644 --- a/arch/arm/src/at32/at32_eth.c +++ b/arch/arm/src/at32/at32_eth.c @@ -1510,7 +1510,7 @@ static int at32_recvframe(struct at32_ethmac_s *priv) * 3) All of the TX descriptors are in flight. * * This last case is obscure. It is due to that fact that each packet - * that we receive can generate an unstoppable transmisson. So we have + * that we receive can generate an unstoppable transmission. So we have * to stop receiving when we can not longer transmit. In this case, the * transmit logic should also have disabled further RX interrupts. */ @@ -1769,7 +1769,7 @@ static void at32_receive(struct at32_ethmac_s *priv) } /* We are finished with the RX buffer. NOTE: If the buffer is - * re-used for transmission, the dev->d_buf field will have been + * reused for transmission, the dev->d_buf field will have been * nullified. */ @@ -2003,11 +2003,11 @@ static void at32_interrupt_work(void *arg) at32_putreg(ETH_DMAINT_NIS, AT32_ETH_DMASR); } - /* Handle error interrupt only if CONFIG_DEBUG_NET is eanbled */ + /* Handle error interrupt only if CONFIG_DEBUG_NET is enabled */ #ifdef CONFIG_DEBUG_NET - /* Check if there are pending "anormal" interrupts */ + /* Check if there are pending "abnormal" interrupts */ if ((dmasr & ETH_DMAINT_AIS) != 0) { diff --git a/arch/arm/src/at32/at32_i2c.c b/arch/arm/src/at32/at32_i2c.c index bf3620d5f0..7486ff4ef0 100644 --- a/arch/arm/src/at32/at32_i2c.c +++ b/arch/arm/src/at32/at32_i2c.c @@ -2496,7 +2496,7 @@ static int at32_i2c_reset(struct i2c_master_s *dev) out: - /* Release the port for re-use by other clients */ + /* Release the port for reuse by other clients */ nxmutex_unlock(&priv->lock); return ret; diff --git a/arch/arm/src/at32/at32_otgfsdev.c b/arch/arm/src/at32/at32_otgfsdev.c index a1dd5b6cf3..b5c12b1cae 100644 --- a/arch/arm/src/at32/at32_otgfsdev.c +++ b/arch/arm/src/at32/at32_otgfsdev.c @@ -2230,8 +2230,8 @@ static inline void at32_ep0out_testmode(struct at32_usbdev_s *priv, * Name: at32_ep0out_stdrequest * * Description: - * Handle a stanard request on EP0. Pick off the things of interest to the - * USB device controller driver; pass what is left to the class driver. + * Handle a standard request on EP0. Pick off the things of interest to + * the USB device controller driver; pass what is left to the class driver. * ****************************************************************************/ @@ -5646,7 +5646,7 @@ void arm_usbinitialize(void) arm_usbuninitialize(); - /* Initialie the driver data structure */ + /* Initialize the driver data structure */ at32_swinitialize(priv); diff --git a/arch/arm/src/at32/at32_otgfshost.c b/arch/arm/src/at32/at32_otgfshost.c index fcd699cb67..fdf7cb8648 100644 --- a/arch/arm/src/at32/at32_otgfshost.c +++ b/arch/arm/src/at32/at32_otgfshost.c @@ -2774,7 +2774,7 @@ static inline void at32_gint_hcoutisr(struct at32_usbhost_s *priv, else if ((pending & OTGFS_HCINT_STALL) != 0) { - /* Clear the pending the STALL response receiv (STALL) interrupt */ + /* Clear the pending the STALL response receive (STALL) interrupt */ at32_putreg(AT32_OTGFS_HCINT(chidx), OTGFS_HCINT_STALL); diff --git a/arch/arm/src/at32/at32_pwm.c b/arch/arm/src/at32/at32_pwm.c index 3802b5230e..4edfadb1ae 100644 --- a/arch/arm/src/at32/at32_pwm.c +++ b/arch/arm/src/at32/at32_pwm.c @@ -2800,7 +2800,7 @@ static int pwm_outputs_enable(struct pwm_lowerhalf_s *dev, uint32_t ccer = 0; uint32_t regval = 0; - /* Get curren register state */ + /* Get current register state */ ccer = pwm_getreg(priv, AT32_GTIM_CCER_OFFSET); @@ -2823,7 +2823,7 @@ static int pwm_outputs_enable(struct pwm_lowerhalf_s *dev, if (state == true) { - /* Enable outpus - set bits */ + /* Enable outputs - set bits */ ccer |= regval; } @@ -2886,7 +2886,7 @@ errout: * Name: pwm_trgo_configure * * Description: - * Confiugre an output synchronisation event for PWM timer (TRGO/TRGO2) + * Configure an output synchronisation event for PWM timer (TRGO/TRGO2) * ****************************************************************************/ @@ -2989,7 +2989,7 @@ static uint16_t pwm_outputs_from_channels(struct at32_pwmtimer_s *priv) if (channel != 0) { - /* Enable output if confiugred */ + /* Enable output if configured */ if (priv->channels[i].out1.in_use == 1) { diff --git a/arch/arm/src/at32/at32_sdio.c b/arch/arm/src/at32/at32_sdio.c index feeac9406c..d7d72b6714 100644 --- a/arch/arm/src/at32/at32_sdio.c +++ b/arch/arm/src/at32/at32_sdio.c @@ -2189,7 +2189,7 @@ static int at32_waitresponse(struct sdio_dev_s *dev, uint32_t cmd) * * Returned Value: * Number of bytes sent on success; a negated errno on failure. Here a - * failure means only a faiure to obtain the requested response (due to + * failure means only a failure to obtain the requested response (due to * transport problem -- timeout, CRC, etc.). The implementation only * assures that the response is returned intacta and does not check errors * within the response itself. diff --git a/arch/arm/src/at32/at32_serial.c b/arch/arm/src/at32/at32_serial.c index eea623c626..fec04d6e9f 100644 --- a/arch/arm/src/at32/at32_serial.c +++ b/arch/arm/src/at32/at32_serial.c @@ -246,7 +246,7 @@ struct up_dev_s #ifdef SERIAL_HAVE_TXDMA const unsigned int txdma_channel; /* DMA channel assigned */ - DMA_HANDLE txdma; /* currently-open trasnmit DMA stream */ + DMA_HANDLE txdma; /* currently-open transmit DMA stream */ #endif #ifdef SERIAL_HAVE_RXDMA @@ -2824,7 +2824,7 @@ uart_dev_t *at32_serial_get_uart(int uart_num) * * Description: * Performs the low level USART initialization early in debug so that the - * serial console will be available during bootup. This must be called + * serial console will be available during boot up. This must be called * before arm_serialinit. * ****************************************************************************/ diff --git a/arch/arm/src/at32/hardware/at32f43xxx_rcc.h b/arch/arm/src/at32/hardware/at32f43xxx_rcc.h index 46de4253e4..ec5698e2c2 100644 --- a/arch/arm/src/at32/hardware/at32f43xxx_rcc.h +++ b/arch/arm/src/at32/hardware/at32f43xxx_rcc.h @@ -215,7 +215,7 @@ # define CRM_CFG_CLKOUT2DIV1_1_4 (6 << CRM_CFG_CLKOUT2DIV1_SHIFT) /* CLKOUT2/4 */ # define CRM_CFG_CLKOUT2DIV1_1_5 (7 << CRM_CFG_CLKOUT2DIV1_SHIFT) /* CLKOUT2/5 */ -#define CRM_CFG_CLKOUT2_SEL1_SHIFT (30) /* clock output2 selecction 1 */ +#define CRM_CFG_CLKOUT2_SEL1_SHIFT (30) /* clock output2 selection 1 */ #define CRM_CFG_CLKOUT2_SEL1_MASK (3 << CRM_CFG_CLKOUT2_SEL1_SHIFT) # define CRM_CFG_CLKOUT2_SEL1_SCLK (0 << CRM_CFG_CLKOUT2_SEL1_SHIFT) /* Output from SCLK */ # define CRM_CFG_CLKOUT2_SEL1_2 (1 << CRM_CFG_CLKOUT2_SEL1_SHIFT) /* Output determine from CRM_MISC1 */ diff --git a/arch/arm/src/c5471/c5471_irq.c b/arch/arm/src/c5471/c5471_irq.c index cd4765f34f..4f2ea1550e 100644 --- a/arch/arm/src/c5471/c5471_irq.c +++ b/arch/arm/src/c5471/c5471_irq.c @@ -76,7 +76,7 @@ static up_vector_t g_vectorinittab[] = * Name: up_ackirq * * Description: - * Acknowlede the IRQ.Bit 0 of the Interrupt Control + * Acknowledge the IRQ.Bit 0 of the Interrupt Control * Register == New IRQ agreement (NEW_IRQ_AGR). Reset IRQ * output. Clear source IRQ register. Enables a new IRQ * generation. Reset by internal logic. diff --git a/arch/arm/src/c5471/c5471_serial.c b/arch/arm/src/c5471/c5471_serial.c index d4e58fe957..63166e8f50 100644 --- a/arch/arm/src/c5471/c5471_serial.c +++ b/arch/arm/src/c5471/c5471_serial.c @@ -793,7 +793,7 @@ static bool up_txempty(struct uart_dev_s *dev) * Description: * Performs the low level UART initialization early in * debug so that the serial console will be available - * during bootup. This must be called before arm_serialinit. + * during boot up. This must be called before arm_serialinit. * ****************************************************************************/ diff --git a/arch/arm/src/c5471/chip.h b/arch/arm/src/c5471/chip.h index a9adc3d9b1..c7deeb85c4 100644 --- a/arch/arm/src/c5471/chip.h +++ b/arch/arm/src/c5471/chip.h @@ -62,7 +62,7 @@ #define ENET0_FLWCONTROL 0xffff0110 /* Flow control register */ #define ENET0_VTYPE 0xffff0114 /* VTYPE tag register */ #define ENET0_SEISR 0xffff0118 /* System error int status register */ -#define ENET0_TXBUFRDY 0xffff011c /* TX descripter buffer ready */ +#define ENET0_TXBUFRDY 0xffff011c /* TX descriptor buffer ready */ #define ENET0_TDBA 0xffff0120 /* TX descriptor base address */ #define ENET0_RDBA 0xffff0124 /* RX descriptor base address */ #define ENET0_PARHI 0xffff0128 /* Dest phys address match (HI) */ diff --git a/arch/arm/src/common/arm_backtrace_sp.c b/arch/arm/src/common/arm_backtrace_sp.c index be2d1d2a28..dad816e6fd 100644 --- a/arch/arm/src/common/arm_backtrace_sp.c +++ b/arch/arm/src/common/arm_backtrace_sp.c @@ -35,7 +35,7 @@ * Pre-processor Definitions ****************************************************************************/ -/* Macro and definitions for simple decoding of instuctions. +/* Macro and definitions for simple decoding of instructions. * To check an instruction, it is ANDed with the IMASK_ and * the result is compared with the IOP_. The macro INSTR_IS * does this and returns !0 to indicate a match. diff --git a/arch/arm/src/common/arm_backtrace_unwind.c b/arch/arm/src/common/arm_backtrace_unwind.c index 2200d94fc2..7adc97cb33 100644 --- a/arch/arm/src/common/arm_backtrace_unwind.c +++ b/arch/arm/src/common/arm_backtrace_unwind.c @@ -233,7 +233,7 @@ static unsigned long unwind_get_byte(struct unwind_ctrl_s *ctrl) * Name: unwind_pop_register * * Description: - * Before poping a register check whether it is feasible or not + * Before popping a register check whether it is feasible or not * ****************************************************************************/ diff --git a/arch/arm/src/csk6/csk6_serial.c b/arch/arm/src/csk6/csk6_serial.c index e74d1a05a8..23a9a37ea2 100644 --- a/arch/arm/src/csk6/csk6_serial.c +++ b/arch/arm/src/csk6/csk6_serial.c @@ -53,7 +53,7 @@ void arm_serialinit(void) * * Description: * Performs the low level UART initialization early in debug so that the - * serial console will be available during bootup. This must be called + * serial console will be available during boot up. This must be called * before arm_serialinit. * ***************************************************************************/ diff --git a/arch/arm/src/cxd32xx/cxd32_serial.c b/arch/arm/src/cxd32xx/cxd32_serial.c index d7b1d08bf8..89173f1d16 100644 --- a/arch/arm/src/cxd32xx/cxd32_serial.c +++ b/arch/arm/src/cxd32xx/cxd32_serial.c @@ -328,7 +328,7 @@ static void up_set_format(struct uart_dev_s *dev) up_serialout(priv, CXD32_UART_LCR_H, lcr); - /* CXD32 does not have CTS/RTS pin, so these are disbled */ + /* CXD32 does not have CTS/RTS pin, so these are disabled */ cr &= ~(UART_CR_RTSEN | UART_CR_CTSEN); up_serialout(priv, CXD32_UART_CR, cr | cr_en); @@ -925,7 +925,7 @@ static bool up_txempty(struct uart_dev_s *dev) * * Description: * Performs the low level UART initialization early in debug so that the - * serial console will be available during bootup. This must be called + * serial console will be available during boot up. This must be called * before arm_serialinit. * * NOTE: Configuration of the CONSOLE UART was performed by up_lowsetup() diff --git a/arch/arm/src/cxd32xx/cxd32_timerisr.c b/arch/arm/src/cxd32xx/cxd32_timerisr.c index e0898d9745..2274dcef39 100644 --- a/arch/arm/src/cxd32xx/cxd32_timerisr.c +++ b/arch/arm/src/cxd32xx/cxd32_timerisr.c @@ -54,7 +54,7 @@ #define TICK_RELOAD ((CXD32_TIMER_BASEFREQ / CLK_TCK) - 1) -/* The size of the reload field is 24 bits. Verify taht the reload value +/* The size of the reload field is 24 bits. Verify that the reload value * will fit in the reload register. */ @@ -140,7 +140,7 @@ static void cxd32_timer1_initialize(void) { uint32_t ctrl; - /* Configure the coutner */ + /* Configure the counter */ putreg32(TIMER4_CH1_INITVALUE, TIMER4_CH1 + CXD32_TIMER_LOAD); diff --git a/arch/arm/src/cxd32xx/cxd32_uart.c b/arch/arm/src/cxd32xx/cxd32_uart.c index 1a53e26d86..75a9928e3d 100644 --- a/arch/arm/src/cxd32xx/cxd32_uart.c +++ b/arch/arm/src/cxd32xx/cxd32_uart.c @@ -219,7 +219,7 @@ void cxd32_uart_reset(int ch) void cxd32_uart_setup(int ch) { - /* XXX: enabling uart contrller */ + /* XXX: enabling uart controller */ } /**************************************************************************** diff --git a/arch/arm/src/cxd32xx/hardware/cxd32_timer.h b/arch/arm/src/cxd32xx/hardware/cxd32_timer.h index 5117fd4094..73aad7b390 100644 --- a/arch/arm/src/cxd32xx/hardware/cxd32_timer.h +++ b/arch/arm/src/cxd32xx/hardware/cxd32_timer.h @@ -41,7 +41,7 @@ #define CXD32_TIMER_INTCLR (0x000C) /* Clear Interrupt register [WO] */ #define CXD32_TIMER_RIS (0x0010) /* Raw Interrupt Status register [RO] */ #define CXD32_TIMER_MIS (0x0014) /* Interrupt Status register [RO] */ -#define CXD32_TIMER_BGLOAD (0x0018) /* Backround Load register [RO] */ +#define CXD32_TIMER_BGLOAD (0x0018) /* Background Load register [RO] */ #define CXD32_TIMER_ITCR (0x0F00) /* Integration Test Control register */ #define CXD32_TIMER_ITOP (0x0F04) /* Integration Test Output register [WO] */ #define CXD32_TIMER_PERIPHID0 (0x0FE0) /* Peripheral ID0 register [RO] */ diff --git a/arch/arm/src/cxd56xx/Kconfig b/arch/arm/src/cxd56xx/Kconfig index f28d0692e1..998302b01c 100644 --- a/arch/arm/src/cxd56xx/Kconfig +++ b/arch/arm/src/cxd56xx/Kconfig @@ -115,7 +115,7 @@ config CXD56_FARAPI_VERSION_CHECK default y ---help--- Enable the Far API version compatibility check. If the version - mismatch is detected during system bootup, the target system shows + mismatch is detected during system boot up, the target system shows the message to update the loader and gnssfw firmwares. if CXD56_FARAPI_VERSION_CHECK @@ -1093,7 +1093,7 @@ config CXD56_SCU_PREDIV default 64 range 1 256 ---help--- - This configuration ralated to maximum sampling rate based + This configuration related to maximum sampling rate based on 32.768KHz. e.g. 32768 / 64 = 512 (samples) diff --git a/arch/arm/src/cxd56xx/cxd56_clock.c b/arch/arm/src/cxd56xx/cxd56_clock.c index 537bebdf18..c1551651c1 100644 --- a/arch/arm/src/cxd56xx/cxd56_clock.c +++ b/arch/arm/src/cxd56xx/cxd56_clock.c @@ -296,7 +296,7 @@ static void do_power_control2(uint32_t reg1, uint32_t mask1, uint32_t stat1, static inline void release_pwd_reset(uint32_t domain) { - /* Reset acts only belows + /* Reset affects only: * [ 0] SCU * [ 6] SYSIOP_SUB * [ 8] APP diff --git a/arch/arm/src/cxd56xx/cxd56_cpu1signal.h b/arch/arm/src/cxd56xx/cxd56_cpu1signal.h index 73231f5b72..ca54f5e7a0 100644 --- a/arch/arm/src/cxd56xx/cxd56_cpu1signal.h +++ b/arch/arm/src/cxd56xx/cxd56_cpu1signal.h @@ -23,7 +23,7 @@ #ifndef __ARCH_ARM_SRC_CXD56XX_CXD56_CPU1SIGNAL_H #define __ARCH_ARM_SRC_CXD56XX_CXD56_CPU1SIGNAL_H -/* CPU1 Notifyable functions */ +/* CPU1 Notifiable functions */ #define CXD56_CPU1_DATA_TYPE_GNSS 0 #define CXD56_CPU1_DATA_TYPE_GEOFENCE 1 diff --git a/arch/arm/src/cxd56xx/cxd56_nxaudio.h b/arch/arm/src/cxd56xx/cxd56_nxaudio.h index cce6fda13f..efb5e95d2b 100644 --- a/arch/arm/src/cxd56xx/cxd56_nxaudio.h +++ b/arch/arm/src/cxd56xx/cxd56_nxaudio.h @@ -278,7 +278,7 @@ struct cxd56_dev_s #ifdef CONFIG_AUDIO_CXD56_SRC struct dq_queue_s down_pendq; /* Pending SRC buffers to be DMA'd */ struct dq_queue_s down_runq; /* SRC buffers being processed */ - struct dq_queue_s down_doneq; /* Done SRC buffers to be re-used */ + struct dq_queue_s down_doneq; /* Done SRC buffers to be reused */ #endif uint32_t samplerate; /* Sample rate */ diff --git a/arch/arm/src/cxd56xx/cxd56_pwm.c b/arch/arm/src/cxd56xx/cxd56_pwm.c index 158a40020e..2be7861ba0 100644 --- a/arch/arm/src/cxd56xx/cxd56_pwm.c +++ b/arch/arm/src/cxd56xx/cxd56_pwm.c @@ -254,7 +254,7 @@ static int convert_freq2period(uint32_t freq, ub16_t duty, uint32_t *param, return -1; } - /* calcurate prescale */ + /* calculate prescale */ if ((freq << 8) < (pwmfreq >> 8)) { diff --git a/arch/arm/src/cxd56xx/cxd56_rtc.c b/arch/arm/src/cxd56xx/cxd56_rtc.c index 2e6cf7c007..0ef881d6f4 100644 --- a/arch/arm/src/cxd56xx/cxd56_rtc.c +++ b/arch/arm/src/cxd56xx/cxd56_rtc.c @@ -582,7 +582,7 @@ int cxd56_rtc_setalarm(struct alm_setalarm_s *alminfo) count -= g_rtc_save->offset; - /* clear previsous setting */ + /* clear previous setting */ mask = RTCREG_ALM0_ERR_FLAG_MASK | RTCREG_ALM0_FLAG_MASK; mask <<= id; diff --git a/arch/arm/src/cxd56xx/cxd56_sdhci.c b/arch/arm/src/cxd56xx/cxd56_sdhci.c index 1371e8658a..d2b47cbac0 100644 --- a/arch/arm/src/cxd56xx/cxd56_sdhci.c +++ b/arch/arm/src/cxd56xx/cxd56_sdhci.c @@ -2189,7 +2189,7 @@ static int cxd56_sdio_waitresponse(struct sdio_dev_s *dev, uint32_t cmd) * * Returned Value: * Number of bytes sent on success; a negated errno on failure. Here a - * failure means only a faiure to obtain the requested response (due to + * failure means only a failure to obtain the requested response (due to * transport problem -- timeout, CRC, etc.). The implementation only * assures that the response is returned intacta and does not check errors * within the response itself. diff --git a/arch/arm/src/cxd56xx/cxd56_sdhci.h b/arch/arm/src/cxd56xx/cxd56_sdhci.h index 169634a7d3..442a21fe90 100644 --- a/arch/arm/src/cxd56xx/cxd56_sdhci.h +++ b/arch/arm/src/cxd56xx/cxd56_sdhci.h @@ -221,7 +221,7 @@ extern "C" #define SDHCI_SYSCTL_ICLKEN (1 << 0) /* Bit 0: Internal Clock Enable */ #define SDHCI_SYSCTL_ICLKSTA (1 << 1) /* Bit 1: Internal Clock Stable */ #define SDHCI_SYSCTL_SDCLKEN (1 << 2) /* Bit 2: SD Clock Enable */ -#define SDHCI_SYSCTL_GENSEL (1 << 5) /* Bit 5: Clock Generetor Select */ +#define SDHCI_SYSCTL_GENSEL (1 << 5) /* Bit 5: Clock Generator Select */ #define SDHCI_SYSCTL_SDCLKFSUP_SHIFT (6) /* Bits 6-7: Divisor */ #define SDHCI_SYSCTL_SDCLKFSUP_MASK (3 << SDHCI_SYSCTL_SDCLKFSUP_SHIFT) #define SDHCI_SYSCTL_SDCLKFS_SHIFT (8) /* Bits 8-15: SDCLK Frequency Select */ diff --git a/arch/arm/src/cxd56xx/cxd56_serial.c b/arch/arm/src/cxd56xx/cxd56_serial.c index 8195126933..d8e79fb42d 100644 --- a/arch/arm/src/cxd56xx/cxd56_serial.c +++ b/arch/arm/src/cxd56xx/cxd56_serial.c @@ -1060,7 +1060,7 @@ static bool up_txempty(struct uart_dev_s *dev) * * Description: * Performs the low level UART initialization early in debug so that the - * serial console will be available during bootup. This must be called + * serial console will be available during boot up. This must be called * before arm_serialinit. * * NOTE: Configuration of the CONSOLE UART was performed by up_lowsetup() diff --git a/arch/arm/src/cxd56xx/cxd56_usbdev.c b/arch/arm/src/cxd56xx/cxd56_usbdev.c index 2ec84ba7ce..bb04e5e885 100644 --- a/arch/arm/src/cxd56xx/cxd56_usbdev.c +++ b/arch/arm/src/cxd56xx/cxd56_usbdev.c @@ -2914,7 +2914,7 @@ static void cxd56_epinitialize(struct cxd56_usbdev_s *priv) priv->usbdev.ep0 = &priv->eplist[0].ep; - /* Initilialize USB hardware */ + /* Initialize USB hardware */ for (i = 1; i < CXD56_NENDPOINTS; i++) { @@ -2996,7 +2996,7 @@ static int cxd56_vbusinterrupt(int irq, void *context, void *arg) } /* Notify attach signal. - * if class driver not binded, can't get supply curret value. + * if class driver not bound, can't get supply current value. */ if (!priv->driver) @@ -3307,7 +3307,7 @@ static void cxd56_usbreset(struct cxd56_usbdev_s *priv) mask &= ~(1 << i << (priv->eplist[i].in ? 0 : 16)); putreg32(mask, CXD56_USB_DEV_EP_INTR_MASK); - /* DMA descripter setting */ + /* DMA descriptor setting */ priv->eplist[i].buffer = NULL; priv->eplist[i].desc->status = DESC_BS_HOST_BUSY; diff --git a/arch/arm/src/cxd56xx/hardware/cxd5602_pinconfig.h b/arch/arm/src/cxd56xx/hardware/cxd5602_pinconfig.h index 610a0343cd..41961c9794 100644 --- a/arch/arm/src/cxd56xx/hardware/cxd5602_pinconfig.h +++ b/arch/arm/src/cxd56xx/hardware/cxd5602_pinconfig.h @@ -35,7 +35,7 @@ /* Set the standard pinconf macro Definitions * - If it's used as input pin, then set 1. Otherwise set 0 (default). - * - If it's drived in 4mA, then set 1. Otherwise set 0 (default 2mA). + * - If it's driven with 4mA, then set 1. Otherwise set 0 (default 2mA). * - If it's used as weak pull-up/down, * then set PINCONF_PULLUP/PINCONF_PULLDOWN. * Otherwise set 0 (default). diff --git a/arch/arm/src/dm320/dm320_framebuffer.c b/arch/arm/src/dm320/dm320_framebuffer.c index 8c773b8862..13f9b014ce 100644 --- a/arch/arm/src/dm320/dm320_framebuffer.c +++ b/arch/arm/src/dm320/dm320_framebuffer.c @@ -771,7 +771,7 @@ static void dm320_disable(void) { /* Disable all planes */ - ginfo("Inactivate OSD:\n"); + ginfo("Deactivate OSD:\n"); putreg16(0, DM320_OSD_OSDWIN0MD); /* Win0 mode = 0 (1:active) */ putreg16(0, DM320_OSD_OSDWIN1MD); /* Win1 mode = 0 (1:active) */ diff --git a/arch/arm/src/dm320/dm320_serial.c b/arch/arm/src/dm320/dm320_serial.c index 535a995b28..807d207896 100644 --- a/arch/arm/src/dm320/dm320_serial.c +++ b/arch/arm/src/dm320/dm320_serial.c @@ -705,7 +705,7 @@ static bool up_txempty(struct uart_dev_s *dev) * Description: * Performs the low level UART initialization early in * debug so that the serial console will be available - * during bootup. This must be called before arm_serialinit. + * during boot up. This must be called before arm_serialinit. * ****************************************************************************/ diff --git a/arch/arm/src/dm320/dm320_usbdev.c b/arch/arm/src/dm320/dm320_usbdev.c index 93f47cc8c8..8e3c77a125 100644 --- a/arch/arm/src/dm320/dm320_usbdev.c +++ b/arch/arm/src/dm320/dm320_usbdev.c @@ -1709,7 +1709,7 @@ static int dm320_ctlrinterrupt(int irq, void *context, void *arg) * Name: dm320_attachinterrupt * * Description: - * Attach GIO interrtup handler + * Attach GIO interrupt handler * ****************************************************************************/ @@ -2485,7 +2485,7 @@ void arm_usbinitialize(void) GIO_OUTPUT(CONFIG_DM320_GIO_USBDPPULLUP); GIO_SET_OUTPUT(CONFIG_DM320_GIO_USBDPPULLUP); - /* Initilialize USB attach GIO */ + /* Initialize USB attach GIO */ GIO_INTERRUPT(CONFIG_DM320_GIO_USBATTACH); GIO_BOTHEDGES(CONFIG_DM320_GIO_USBATTACH); diff --git a/arch/arm/src/efm32/efm32_i2c.c b/arch/arm/src/efm32/efm32_i2c.c index 7c206a1d4b..b1496e2db8 100644 --- a/arch/arm/src/efm32/efm32_i2c.c +++ b/arch/arm/src/efm32/efm32_i2c.c @@ -1595,7 +1595,7 @@ int efm32_i2c_reset(struct i2c_master_s *dev) out: - /* Release the port for re-use by other clients */ + /* Release the port for reuse by other clients */ nxmutex_unlock(&priv->lock); return ret; diff --git a/arch/arm/src/efm32/efm32_leserial.c b/arch/arm/src/efm32/efm32_leserial.c index be4af95dee..0da0a01548 100644 --- a/arch/arm/src/efm32/efm32_leserial.c +++ b/arch/arm/src/efm32/efm32_leserial.c @@ -765,7 +765,7 @@ static bool efm32_txempty(struct uart_dev_s *dev) * * Description: * Performs the low level UART initialization early in debug so that the - * serial console will be available during bootup. This must be called + * serial console will be available during boot up. This must be called * before arm_serialinit. NOTE: This function depends on GPIO pin * configuration performed in efm32_consoleinit() and main clock * initialization performed in efm32_clkinitialize(). diff --git a/arch/arm/src/efm32/efm32_serial.c b/arch/arm/src/efm32/efm32_serial.c index 087465195d..6f08fffbe4 100644 --- a/arch/arm/src/efm32/efm32_serial.c +++ b/arch/arm/src/efm32/efm32_serial.c @@ -1121,7 +1121,7 @@ static bool efm32_txempty(struct uart_dev_s *dev) * * Description: * Performs the low level UART initialization early in debug so that the - * serial console will be available during bootup. This must be called + * serial console will be available during boot up. This must be called * before arm_serialinit. NOTE: This function depends on GPIO pin * configuration performed in efm32_consoleinit() and main clock * initialization performed in efm32_clkinitialize(). diff --git a/arch/arm/src/efm32/efm32_usbdev.c b/arch/arm/src/efm32/efm32_usbdev.c index e4fd0157a0..43b667f140 100644 --- a/arch/arm/src/efm32/efm32_usbdev.c +++ b/arch/arm/src/efm32/efm32_usbdev.c @@ -2121,7 +2121,7 @@ static inline void efm32_ep0out_testmode(struct efm32_usbdev_s *priv, * Name: efm32_ep0out_stdrequest * * Description: - * Handle a stanard request on EP0. Pick off the things of interest to + * Handle a standard request on EP0. Pick off the things of interest to * the USB device controller driver; pass what is left to the class driver. * ****************************************************************************/ @@ -5591,7 +5591,7 @@ void arm_usbinitialize(void) arm_usbuninitialize(); - /* Initialie the driver data structure */ + /* Initialize the driver data structure */ efm32_swinitialize(priv); diff --git a/arch/arm/src/efm32/efm32_usbhost.c b/arch/arm/src/efm32/efm32_usbhost.c index 671798257f..fa794055f2 100644 --- a/arch/arm/src/efm32/efm32_usbhost.c +++ b/arch/arm/src/efm32/efm32_usbhost.c @@ -2793,7 +2793,7 @@ static inline void efm32_gint_hcoutisr(struct efm32_usbhost_s *priv, else if ((pending & USB_HC_INT_STALL) != 0) { - /* Clear the pending the STALL response receiv (STALL) interrupt */ + /* Clear the pending the STALL response receive (STALL) interrupt */ efm32_putreg(EFM32_USB_HC_INT(chidx), USB_HC_INT_STALL); diff --git a/arch/arm/src/eoss3/eoss3_serial.c b/arch/arm/src/eoss3/eoss3_serial.c index 3f00281042..e75218c028 100644 --- a/arch/arm/src/eoss3/eoss3_serial.c +++ b/arch/arm/src/eoss3/eoss3_serial.c @@ -534,7 +534,7 @@ static bool eoss3_txempty(struct uart_dev_s *dev) * * Description: * Performs the low level UART initialization early in debug so that the - * serial console will be available during bootup. This must be called + * serial console will be available during boot up. This must be called * before arm_serialinit. * ****************************************************************************/ diff --git a/arch/arm/src/gd32f4/gd32f4xx_dma.c b/arch/arm/src/gd32f4/gd32f4xx_dma.c index 5282a9d1b7..4287334641 100644 --- a/arch/arm/src/gd32f4/gd32f4xx_dma.c +++ b/arch/arm/src/gd32f4/gd32f4xx_dma.c @@ -566,7 +566,7 @@ void weak_function arm_dma_initialize(void) * gd32_dma_channel_free(). * * Input Parameters: - * periph_req - Identifies the DMA channle is request by which peripheral + * periph_req - Identifies the DMA channel is request by which peripheral * * Returned Value: * If periph_req is valid, this function ALWAYS returns a non-NULL @@ -704,7 +704,7 @@ void gd32_dma_singlemode_setup(struct gd32_dma_channel_s *dmachan, regaddr = GD32_DMA_CHCNT(dmachan->dmabase, dmachan->chan_num); putreg32(init_struct->number, regaddr); - /* Configure peripheral and memory transfer width, channel priotity, + /* Configure peripheral and memory transfer width, channel priority, * transfer mode */ diff --git a/arch/arm/src/gd32f4/gd32f4xx_dma.h b/arch/arm/src/gd32f4/gd32f4xx_dma.h index bb60bc16fc..b493537e49 100644 --- a/arch/arm/src/gd32f4/gd32f4xx_dma.h +++ b/arch/arm/src/gd32f4/gd32f4xx_dma.h @@ -135,7 +135,7 @@ extern "C" * gd32_dma_channel_free(). * * Input Parameters: - * periph_req - Identifies the DMA channle is request by which peripheral + * periph_req - Identifies the DMA channel is request by which peripheral * * Returned Value: * If periph_req is valid, this function ALWAYS returns a non-NULL diff --git a/arch/arm/src/gd32f4/gd32f4xx_enet.c b/arch/arm/src/gd32f4/gd32f4xx_enet.c index ba926a05e6..145121dca6 100644 --- a/arch/arm/src/gd32f4/gd32f4xx_enet.c +++ b/arch/arm/src/gd32f4/gd32f4xx_enet.c @@ -839,7 +839,7 @@ static void gd32_enet_clock_enable(void) regaddr = GD32_RCU_AHB1EN; - /* Check clock if alreay enable. */ + /* Check clock if already enable. */ if (rcu_en != (rcu_en & getreg32(regaddr))) { @@ -1492,7 +1492,7 @@ static int gd32_receive_frame(struct gd32_enet_mac_s *priv) * 3) All of the TX descriptors are in flight. * * This last case is obscure. It is due to that fact that each packet - * that we receive can generate an unstoppable transmisson. So we have + * that we receive can generate an unstoppable transmission. So we have * to stop receiving when we can not longer transmit. In this case, the * transmit logic should also have disabled further RX interrupts. */ @@ -1730,7 +1730,7 @@ static void gd32_receive(struct gd32_enet_mac_s *priv) } /* We are finished with the RX buffer. NOTE: If the buffer is - * re-used for transmission, the dev->d_buf field will have been + * reused for transmission, the dev->d_buf field will have been * nullified. */ @@ -1965,11 +1965,11 @@ static void gd32_interrupt_work(void *arg) gd32_reg_write(ENET_DMA_INTEN_NIE, GD32_ENET_DMA_STAT); } - /* Handle error interrupt only if CONFIG_DEBUG_NET is eanbled */ + /* Handle error interrupt only if CONFIG_DEBUG_NET is enabled */ #ifdef CONFIG_DEBUG_NET - /* Check if there are pending "anormal" interrupts */ + /* Check if there are pending "abnormal" interrupts */ if ((dma_reg & ENET_DMA_STAT_AI) != 0) { diff --git a/arch/arm/src/gd32f4/gd32f4xx_gpio.c b/arch/arm/src/gd32f4/gd32f4xx_gpio.c index 4e981d0571..54c7802e43 100644 --- a/arch/arm/src/gd32f4/gd32f4xx_gpio.c +++ b/arch/arm/src/gd32f4/gd32f4xx_gpio.c @@ -318,7 +318,7 @@ int gd32_gpio_config(uint32_t cfgset) port_base = g_gpio_base[port]; - /* Eable the GPIO port clock */ + /* Enable the GPIO port clock */ gd32_gpio_clock_enable(port_base); diff --git a/arch/arm/src/gd32f4/gd32f4xx_i2c.c b/arch/arm/src/gd32f4/gd32f4xx_i2c.c index 9c4353f935..4cb860da87 100644 --- a/arch/arm/src/gd32f4/gd32f4xx_i2c.c +++ b/arch/arm/src/gd32f4/gd32f4xx_i2c.c @@ -2555,7 +2555,7 @@ static int gd32_i2c_reset(struct i2c_master_s *dev) out: - /* Release the port for re-use by other clients */ + /* Release the port for reuse by other clients */ nxmutex_unlock(&priv->lock); return ret; diff --git a/arch/arm/src/gd32f4/gd32f4xx_sdio.c b/arch/arm/src/gd32f4/gd32f4xx_sdio.c index 60c63f505c..6dbd909eae 100644 --- a/arch/arm/src/gd32f4/gd32f4xx_sdio.c +++ b/arch/arm/src/gd32f4/gd32f4xx_sdio.c @@ -2155,7 +2155,7 @@ static int gd32_wait_response(struct sdio_dev_s *dev, uint32_t cmd) * * Returned Value: * Number of bytes sent on success; a negated errno on failure. Here a - * failure means only a faiure to obtain the requested response (due to + * failure means only a failure to obtain the requested response (due to * transport problem -- timeout, CRC, etc.). The implementation only * assures that the response is returned intacta and does not check errors * within the response itself. diff --git a/arch/arm/src/gd32f4/gd32f4xx_serial.c b/arch/arm/src/gd32f4/gd32f4xx_serial.c index 3ce5cafc36..c63c6e38a3 100644 --- a/arch/arm/src/gd32f4/gd32f4xx_serial.c +++ b/arch/arm/src/gd32f4/gd32f4xx_serial.c @@ -176,7 +176,7 @@ struct up_dev_s #ifdef SERIAL_HAVE_TXDMA const uint32_t txdma_channel; /* DMA channel assigned */ - DMA_HANDLE txdma; /* currently-open trasnmit DMA stream */ + DMA_HANDLE txdma; /* currently-open transmit DMA stream */ #endif /* RX DMA state */ @@ -1982,7 +1982,7 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg) # endif #endif - /* Only availible in USART0,1,2,5 */ + /* Only available in USART0,1,2,5 */ #ifdef CONFIG_GD32F4_USART_INVERT case TIOCSINVERT: @@ -2379,7 +2379,7 @@ static void up_dma_tx_callback(DMA_HANDLE handle, uint16_t status, void *arg) dma_init_struct.priority = USART_DMA_PRIO; dma_init_struct.circular_mode = DMA_CIRCULAR_MODE_DISABLE; - /* Configure DMA for USART transmmit */ + /* Configure DMA for USART transmit */ gd32_dma_setup(priv->txdma, &dma_init_struct, 1); @@ -2470,7 +2470,7 @@ static void up_dma_send(struct uart_dev_s *dev) dma_init_struct.priority = USART_DMA_PRIO; dma_init_struct.circular_mode = DMA_CIRCULAR_MODE_DISABLE; - /* Configure DMA for USART transmmit */ + /* Configure DMA for USART transmit */ gd32_dma_setup(priv->txdma, &dma_init_struct, 1); @@ -2748,7 +2748,7 @@ static int up_pm_prepare(struct pm_callback_s *cb, int domain, * * Description: * Performs the low level USART initialization early in debug so that the - * serial console will be available during bootup. This must be called + * serial console will be available during boot up. This must be called * before arm_serialinit. * ****************************************************************************/ diff --git a/arch/arm/src/gd32f4/gd32f4xx_spi.c b/arch/arm/src/gd32f4/gd32f4xx_spi.c index e887d29c7f..d0c0f3c53d 100644 --- a/arch/arm/src/gd32f4/gd32f4xx_spi.c +++ b/arch/arm/src/gd32f4/gd32f4xx_spi.c @@ -1080,7 +1080,7 @@ static uint32_t spi_setfrequency(struct spi_dev_s *dev, uint32_t actual; uint32_t plk_div; - /* Check if the requested frequence is the same as the frequency + /* Check if the requested frequency is the same as the frequency * selection. */ diff --git a/arch/arm/src/gd32f4/gd32f4xx_syscfg.c b/arch/arm/src/gd32f4/gd32f4xx_syscfg.c index 33b45430e9..0f138aa377 100644 --- a/arch/arm/src/gd32f4/gd32f4xx_syscfg.c +++ b/arch/arm/src/gd32f4/gd32f4xx_syscfg.c @@ -217,7 +217,7 @@ void gd32_syscfg_clock_enable(void) regaddr = GD32_RCU_APB2EN; - /* Check clock if alreay enable. */ + /* Check clock if already enable. */ if (rcu_en != (rcu_en & getreg32(regaddr))) { diff --git a/arch/arm/src/gd32f4/gd32f4xx_usart.h b/arch/arm/src/gd32f4/gd32f4xx_usart.h index 710a9cf732..0611b1b7ee 100644 --- a/arch/arm/src/gd32f4/gd32f4xx_usart.h +++ b/arch/arm/src/gd32f4/gd32f4xx_usart.h @@ -490,11 +490,11 @@ /* USART interrupts maps, each interrupt of the USART can be individually * configured by software. The following definitions provide the bit - * encodingthat used to define the interrupt and control register offset. + * encoding that used to define the interrupt and control register offset. * * 24-bit Encoding: 2222 2222 1111 1111 1100 0000 0000 * 7654 3210 9876 5432 1098 7654 3210 - * ENCODING SHIF + * ENCODING SHIFT * * CTL SHIFT: Bit24-27, CTL2 int: Bit8-23, CTL3 int: Bit6-7, * CTL1 int: Bit5, CTL0 int: Bit0-4, diff --git a/arch/arm/src/gd32f4/hardware/gd32f4xx_dma.h b/arch/arm/src/gd32f4/hardware/gd32f4xx_dma.h index 25d446e88d..2ac32f4baf 100644 --- a/arch/arm/src/gd32f4/hardware/gd32f4xx_dma.h +++ b/arch/arm/src/gd32f4/hardware/gd32f4xx_dma.h @@ -189,7 +189,7 @@ /* DMA_CHxCTL,x=0..7 */ #define DMA_CHXCTL_CHEN (1 << 0) /* Bit 0: channel x enable */ #define DMA_CHXCTL_SDEIE (1 << 1) /* Bit 1: enable bit for channel x single data mode exception interrupt */ -#define DMA_CHXCTL_TAEIE (1 << 2) /* Bit 2: enable bit for channel x tranfer access error interrupt */ +#define DMA_CHXCTL_TAEIE (1 << 2) /* Bit 2: enable bit for channel x transfer access error interrupt */ #define DMA_CHXCTL_HTFIE (1 << 3) /* Bit 3: enable bit for channel x half transfer finish interrupt */ #define DMA_CHXCTL_FTFIE (1 << 4) /* Bit 4: enable bit for channel x full transfer finish interrupt */ #define DMA_CHXCTL_TFCS (1 << 5) /* Bit 5: transfer flow controller select */ diff --git a/arch/arm/src/gd32f4/hardware/gd32f4xx_enet.h b/arch/arm/src/gd32f4/hardware/gd32f4xx_enet.h index 52ebc1e187..b84832bf44 100644 --- a/arch/arm/src/gd32f4/hardware/gd32f4xx_enet.h +++ b/arch/arm/src/gd32f4/hardware/gd32f4xx_enet.h @@ -50,7 +50,7 @@ #define GD32_ENET_MAC_FCTL_OFFSET 0x0018 /* MAC flow control register offset */ #define GD32_ENET_MAC_VLT_OFFSET 0x001C /* MAC VLAN tag register offset */ #define GD32_ENET_MAC_RWFF_OFFSET 0x0028 /* MAC remote wakeup frame filter register offset */ -#define GD32_ENET_MAC_WUM_OFFSET 0x002C /* MAC wakeup managenment register offset */ +#define GD32_ENET_MAC_WUM_OFFSET 0x002C /* MAC wakeup management register offset */ #define GD32_ENET_MAC_DBG_OFFSET 0x0034 /* MAC debug register offset */ #define GD32_ENET_MAC_INTF_OFFSET 0x0038 /* MAC interrupt flag register offset */ @@ -75,7 +75,7 @@ #define GD32_ENET_MSC_TINTMSK_OFFSET 0x0110 /* MSC transmit interrupt mask register offset */ #define GD32_ENET_MSC_SCCNT_OFFSET 0x014C /* MSC transmitted good frames after a single collision counter register offset */ -#define GD32_ENET_MSC_MSCCNT_OFFSET 0x0150 /* MSC transmitted good frames after more than a signle collision counter register offset */ +#define GD32_ENET_MSC_MSCCNT_OFFSET 0x0150 /* MSC transmitted good frames after more than a single collision counter register offset */ #define GD32_ENET_MSC_TGFCNT_OFFSET 0x0168 /* MSC transmitted good frames counter register offset */ @@ -438,7 +438,7 @@ #define ENET_MAC_FCTH_RFA_SHIFT (0) /* Bits 0-2 threshold of active flow control */ #define ENET_MAC_FCTH_RFA_MASK (7 << ENET_MAC_FCTH_RFA_SHIFT) -#define ENET_MAC_FCTH_RFD_SHIFT (4) /* Bits 4-6 threshold of deactive flow control */ +#define ENET_MAC_FCTH_RFD_SHIFT (4) /* Bits 4-6 threshold of deactivate flow control */ #define ENET_MAC_FCTH_RFD_MASK (7 << ENET_MAC_FCTH_RFD_SHIFT) /* MSC Registers */ @@ -647,7 +647,7 @@ #define ENET_RX_STATE_WAITING (3 << ENET_DMA_STAT_RP_SHIFT) /* 011: waiting for receive packet */ #define ENET_RX_STATE_SUSPENDED (4 << ENET_DMA_STAT_RP_SHIFT) /* 100: Rx descriptor unavailable */ #define ENET_RX_STATE_CLOSING (5 << ENET_DMA_STAT_RP_SHIFT) /* 101: closing receive descriptor */ -#define ENET_RX_STATE_QUEUING (6 << ENET_DMA_STAT_RP_SHIFT) /* 111: transferring the receive packet data from recevie buffer to host memory */ +#define ENET_RX_STATE_QUEUING (6 << ENET_DMA_STAT_RP_SHIFT) /* 111: transferring the receive packet data from receive buffer to host memory */ #define ENET_DMA_STAT_TP_SHIFT (20) /* Bits 20-22: transmit process state */ #define ENET_DMA_STAT_TP_MASK (7 << ENET_DMA_STAT_TP_SHIFT) diff --git a/arch/arm/src/gd32f4/hardware/gd32f4xx_gpio.h b/arch/arm/src/gd32f4/hardware/gd32f4xx_gpio.h index 03f246de75..641a95ecbc 100644 --- a/arch/arm/src/gd32f4/hardware/gd32f4xx_gpio.h +++ b/arch/arm/src/gd32f4/hardware/gd32f4xx_gpio.h @@ -40,18 +40,18 @@ /* Register Offsets *********************************************************/ -#define GD32_GPIO_CTL_OFFSET 0x0000 /* GPIO port control register offfset */ -#define GD32_GPIO_OMODE_OFFSET 0x0004 /* GPIO port output mode register offfset */ -#define GD32_GGPIO_OSPD_OFFSET 0x0008 /* GPIO port output speed register offfset */ -#define GD32_GPIO_PUD_OFFSET 0x000c /* GPIO port pull-up/pull-down register offfset */ -#define GD32_GPIO_ISTAT_OFFSET 0x0010 /* GPIO port input status register offfset */ -#define GD32_GPIO_OCTL_OFFSET 0x0014 /* GPIO port output control register offfset */ -#define GD32_GPIO_BOP_OFFSET 0x0018 /* GPIO port bit operation register offfset */ -#define GD32_GPIO_LOCK_OFFSET 0x001c /* GPIO port configuration lock register offfset */ -#define GD32_GPIO_AFSEL0_OFFSET 0x0020 /* GPIO alternate function selected register 0 offfset */ -#define GD32_GPIO_AFSEL1_OFFSET 0x0024 /* GPIO alternate function selected register 1 offfset */ -#define GD32_GPIO_BC_OFFSET 0x0028 /* GPIO bit clear register offfset */ -#define GD32_GPIO_TG_OFFSET 0x002c /* GPIO port bit toggle register offfset */ +#define GD32_GPIO_CTL_OFFSET 0x0000 /* GPIO port control register offset */ +#define GD32_GPIO_OMODE_OFFSET 0x0004 /* GPIO port output mode register offset */ +#define GD32_GGPIO_OSPD_OFFSET 0x0008 /* GPIO port output speed register offset */ +#define GD32_GPIO_PUD_OFFSET 0x000c /* GPIO port pull-up/pull-down register offset */ +#define GD32_GPIO_ISTAT_OFFSET 0x0010 /* GPIO port input status register offset */ +#define GD32_GPIO_OCTL_OFFSET 0x0014 /* GPIO port output control register offset */ +#define GD32_GPIO_BOP_OFFSET 0x0018 /* GPIO port bit operation register offset */ +#define GD32_GPIO_LOCK_OFFSET 0x001c /* GPIO port configuration lock register offset */ +#define GD32_GPIO_AFSEL0_OFFSET 0x0020 /* GPIO alternate function selected register 0 offset */ +#define GD32_GPIO_AFSEL1_OFFSET 0x0024 /* GPIO alternate function selected register 1 offset */ +#define GD32_GPIO_BC_OFFSET 0x0028 /* GPIO bit clear register offset */ +#define GD32_GPIO_TG_OFFSET 0x002c /* GPIO port bit toggle register offset */ /* Register Addresses *******************************************************/ diff --git a/arch/arm/src/goldfish/chip.h b/arch/arm/src/goldfish/chip.h index 2a50d0e0b0..cb71cc9e4f 100644 --- a/arch/arm/src/goldfish/chip.h +++ b/arch/arm/src/goldfish/chip.h @@ -66,7 +66,7 @@ * Name: cpuindex * * Description: - * Return an index idenifying the current CPU. + * Return an index identifying the current CPU. * ****************************************************************************/ diff --git a/arch/arm/src/imx1/imx_serial.c b/arch/arm/src/imx1/imx_serial.c index bea801dd87..03c8b7b731 100644 --- a/arch/arm/src/imx1/imx_serial.c +++ b/arch/arm/src/imx1/imx_serial.c @@ -1062,7 +1062,7 @@ static bool up_txempty(struct uart_dev_s *dev) * Description: * Performs the low level UART initialization early in * debug so that the serial console will be available - * during bootup. This must be called before arm_serialinit. + * during boot up. This must be called before arm_serialinit. * ****************************************************************************/ diff --git a/arch/arm/src/imx1/imx_uart.h b/arch/arm/src/imx1/imx_uart.h index b827dec3d5..f821858d3d 100644 --- a/arch/arm/src/imx1/imx_uart.h +++ b/arch/arm/src/imx1/imx_uart.h @@ -136,8 +136,8 @@ #define UART2_UCR3_INVT (1 << 1) /* Bit 1: Inverted Infrared Transmission */ #define UART2_UCR3_REF30 (1 << 2) /* Bit 2: Reference frequency 30 mhz */ #define UART2_UCR3_REF25 (1 << 3) /* Bit 3: Reference frequency 25 mhz */ -#define UART2_UCR3_AWAKEN (1 << 4) /* Bit 4: Asychronous WAKE Interrupt Enable */ -#define UART2_UCR3_AIRINTEN (1 << 5) /* Bit 5: Asychronous IR WAKE Interrupt Enable */ +#define UART2_UCR3_AWAKEN (1 << 4) /* Bit 4: Asynchronous WAKE Interrupt Enable */ +#define UART2_UCR3_AIRINTEN (1 << 5) /* Bit 5: Asynchronous IR WAKE Interrupt Enable */ #define UART2_UCR3_RXDSEN (1 << 6) /* Bit 6: Receive Status Interrupt Enable */ #define UART2_UCR3_RI (1 << 7) /* Bit 7: Ring Indicator */ #define UART2_UCR3_Reserved2 (1 << 8) /* Bit 8: Reserved */ diff --git a/arch/arm/src/imx6/chip.h b/arch/arm/src/imx6/chip.h index 76ff64a06d..ac29e07282 100644 --- a/arch/arm/src/imx6/chip.h +++ b/arch/arm/src/imx6/chip.h @@ -63,7 +63,7 @@ * Name: cpuindex * * Description: - * Return an index idenifying the current CPU. + * Return an index identifying the current CPU. * ****************************************************************************/ diff --git a/arch/arm/src/imx6/hardware/imx_enet.h b/arch/arm/src/imx6/hardware/imx_enet.h index 0f2112daca..c23098b967 100644 --- a/arch/arm/src/imx6/hardware/imx_enet.h +++ b/arch/arm/src/imx6/hardware/imx_enet.h @@ -309,7 +309,7 @@ #define ENET_TXIC_ICFT_SHIFT (20) /* Bits 0-15: Interrupt coalescing timer threshold */ #define ENET_TXIC_ICFT_SHIFT_MASK (0xff << ENET_TXIC_ICFT_SHIFT) #define ENET_TXIC_ICTT_ICCS (1 << 30) /* Bit 30: Interrupt Coalescing Timer Clock Source Select */ -#define ENET_TXIC_ICTT_ICEN (1 << 31) /* Bit 31: Eable/disabel Interrupt Coalescing */ +#define ENET_TXIC_ICTT_ICEN (1 << 31) /* Bit 31: Enable/disable Interrupt Coalescing */ /* Receive Interrupt Coalescing Register */ @@ -319,7 +319,7 @@ #define ENET_RXIC_ICFT_SHIFT (20) /* Bits 0-15: Interrupt coalescing timer threshold */ #define ENET_RXIC_ICFT_SHIFT_MASK (0xff << ENET_TXIC_ICFT_SHIFT) #define ENET_RXIC_ICTT_ICCS (1 << 30) /* Bit 30: Interrupt Coalescing Timer Clock Source Select */ -#define ENET_RXIC_ICTT_ICEN (1 << 31) /* Bit 31: Eable/disabel Interrupt Coalescing */ +#define ENET_RXIC_ICTT_ICEN (1 << 31) /* Bit 31: Enable/disable Interrupt Coalescing */ #endif /* if 0 */ diff --git a/arch/arm/src/imx6/imx_enet.c b/arch/arm/src/imx6/imx_enet.c index 258d4dc8cc..b9770702a7 100644 --- a/arch/arm/src/imx6/imx_enet.c +++ b/arch/arm/src/imx6/imx_enet.c @@ -2510,7 +2510,7 @@ int imx_netinitialize(int intf) memset(priv, 0, sizeof(struct imx_driver_s)); - priv->base = IMX_ENET_VBASE; /* Assigne base address */ + priv->base = IMX_ENET_VBASE; /* Assign base address */ priv->dev.d_ifup = imx_ifup; /* I/F up (new IP address) callback */ priv->dev.d_ifdown = imx_ifdown; /* I/F down callback */ diff --git a/arch/arm/src/imx6/imx_iomuxc.c b/arch/arm/src/imx6/imx_iomuxc.c index 04b598ad92..aae995a773 100644 --- a/arch/arm/src/imx6/imx_iomuxc.c +++ b/arch/arm/src/imx6/imx_iomuxc.c @@ -423,12 +423,12 @@ int imx_iomux_configure(uintptr_t padctl, iomux_pinset_t ioset) value = (ioset & IOMUX_DRIVE_MASK) >> IOMUX_DRIVE_SHIFT; regval |= PADCTL_DSE(value); - /* Select spped */ + /* Select speed */ value = (ioset & IOMUX_SPEED_MASK) >> IOMUX_SPEED_SHIFT; regval |= PADCTL_SPEED(value); - /* Select CMOS output or Open Drain outpout */ + /* Select CMOS output or Open Drain output */ if ((ioset & IOMUX_OPENDRAIN) != 0) { diff --git a/arch/arm/src/imx6/imx_lowputc.c b/arch/arm/src/imx6/imx_lowputc.c index 3dc4b63f8e..939657e9a7 100644 --- a/arch/arm/src/imx6/imx_lowputc.c +++ b/arch/arm/src/imx6/imx_lowputc.c @@ -579,8 +579,8 @@ void imx_lowputc(int ch) while ((getreg32(IMX_CONSOLE_VBASE + UART_USR2_OFFSET) & UART_USR2_TXFE) == 0); - /* If the character to output is a newline, then pre-pend a carriage - * return + /* If the character to output is a newline, then prepend a carriage + * return. */ /* Send the character by writing it into the UART_TXD register. */ diff --git a/arch/arm/src/imx6/imx_serial.c b/arch/arm/src/imx6/imx_serial.c index f644d14f89..c68f7c79b0 100644 --- a/arch/arm/src/imx6/imx_serial.c +++ b/arch/arm/src/imx6/imx_serial.c @@ -1060,7 +1060,7 @@ static bool imx_txempty(struct uart_dev_s *dev) * Description: * Performs the low level UART initialization early in * debug so that the serial console will be available - * during bootup. This must be called before arm_serialinit. + * during boot up. This must be called before arm_serialinit. * ****************************************************************************/ diff --git a/arch/arm/src/imx6/imx_serial.h b/arch/arm/src/imx6/imx_serial.h index 65ac11270d..a2c0491939 100644 --- a/arch/arm/src/imx6/imx_serial.h +++ b/arch/arm/src/imx6/imx_serial.h @@ -68,7 +68,7 @@ extern "C" * * Description: * Performs the low level UART initialization early in debug so that the - * serial console will be available during bootup. This must be called + * serial console will be available during boot up. This must be called * before arm_serialinit. * ****************************************************************************/ @@ -82,7 +82,7 @@ void imx_earlyserialinit(void); * * Description: * Performs the low level UART initialization early in debug so that the - * serial console will be available during bootup. This must be called + * serial console will be available during boot up. This must be called * before arm_serialinit. * ****************************************************************************/ diff --git a/arch/arm/src/imx9/Kconfig b/arch/arm/src/imx9/Kconfig index dff046685a..5cc1555f75 100644 --- a/arch/arm/src/imx9/Kconfig +++ b/arch/arm/src/imx9/Kconfig @@ -755,7 +755,7 @@ config IMX9_LPI2C_DMA_MAXMSG default 8 depends on IMX9_LPI2C_DMA ---help--- - This option set the mumber of mesg that can be in a transfer. + This option set the number of mesg that can be in a transfer. It is used to allocate space for the 16 bit LPI2C commands that will be DMA-ed to the LPI2C device. diff --git a/arch/arm/src/imx9/hardware/imx9_lpit.h b/arch/arm/src/imx9/hardware/imx9_lpit.h index f6f7af42a8..002c06948e 100644 --- a/arch/arm/src/imx9/hardware/imx9_lpit.h +++ b/arch/arm/src/imx9/hardware/imx9_lpit.h @@ -38,7 +38,7 @@ #define IMX9_LPIT_PARAM_OFFSET 0x0004 /* Parameter */ #define IMX9_LPIT_MCR_OFFSET 0x0008 /* Module Control */ #define IMX9_LPIT_MSR_OFFSET 0x000c /* Module Status Register */ -#define IMX9_LPIT_MIER_OFFSET 0x0010 /* Moduel Interrupt Enable */ +#define IMX9_LPIT_MIER_OFFSET 0x0010 /* Module Interrupt Enable */ #define IMX9_LPIT_SETTEN_OFFSET 0x0014 /* Set Timer Enable */ #define IMX9_LPIT_CLRTEN_OFFSET 0x0018 /* Clear Timer Enable */ #define IMX9_LPIT_TVAL0_OFFSET 0x0020 /* Timer Channel 0 Value */ diff --git a/arch/arm/src/imx9/imx9_clockconfig.c b/arch/arm/src/imx9/imx9_clockconfig.c index 6a02e95ebf..b0a06ea03e 100644 --- a/arch/arm/src/imx9/imx9_clockconfig.c +++ b/arch/arm/src/imx9/imx9_clockconfig.c @@ -83,7 +83,7 @@ void imx9_clockconfig(void) IMX9_GPC_CTRL_CMC_MISC_SLEEP_HOLD_EN_FLAG, 0); #endif - /* Cortex-M33 with SM does PLL initalization */ + /* Cortex-M33 with SM does PLL initialization */ } #ifdef CONFIG_IMX9_CLK_OVER_SCMI diff --git a/arch/arm/src/imx9/imx9_edma.h b/arch/arm/src/imx9/imx9_edma.h index 243d2f8345..a680716116 100644 --- a/arch/arm/src/imx9/imx9_edma.h +++ b/arch/arm/src/imx9/imx9_edma.h @@ -83,7 +83,7 @@ * i mxrt_dmach_stop(handle); * * 7. The callback will be received when the DMA completes (or an error - * occurs). After that, you may free the DMA channel, or re-use it on + * occurs). After that, you may free the DMA channel, or reuse it on * subsequent DMAs. * * imx9_dmach_free(handle); diff --git a/arch/arm/src/imx9/imx9_flexcan.c b/arch/arm/src/imx9/imx9_flexcan.c index 5936b65d4a..0795d814d9 100644 --- a/arch/arm/src/imx9/imx9_flexcan.c +++ b/arch/arm/src/imx9/imx9_flexcan.c @@ -747,9 +747,9 @@ static int imx9_transmit(struct imx9_driver_s *priv) mb->cs = cs; /* Go. */ /* Errata ER005829 step 8: Write twice into the first TX MB - * Errata mentions writng 0x8 value, but this one couses + * Errata mentions writing 0x8 value, but this one causes * the ESR2_LPTM register to choose the reserved MB for - * transmiting the package, hence we write 0x3 + * transmitting the package, hence we write 0x3. */ struct mb_s *buffer = flexcan_get_mb(priv, RXMBCOUNT); @@ -1777,9 +1777,9 @@ static int imx9_initialize(struct imx9_driver_s *priv) } /* Errata ER005829 step 7: Reserve first TX MB - * Errata mentions writng 0x8 value, but this one couses + * Errata mentions writing 0x8 value, but this one causes * the ESR2_LPTM register to choose the reserved MB for - * transmiting the package, hence we write 0x3 + * transmitting the package, hence we write 0x3. */ struct mb_s *buffer = flexcan_get_mb(priv, RXMBCOUNT); diff --git a/arch/arm/src/imx9/imx9_lowputc.c b/arch/arm/src/imx9/imx9_lowputc.c index c3d7023f59..0501230f42 100644 --- a/arch/arm/src/imx9/imx9_lowputc.c +++ b/arch/arm/src/imx9/imx9_lowputc.c @@ -555,7 +555,7 @@ void arm_lowputc(char ch) } /* If the character to output is a newline, - * then pre-pend a carriage return + * then prepend a carriage return. */ if (ch == '\n') diff --git a/arch/arm/src/imx9/imx9_lpi2c.c b/arch/arm/src/imx9/imx9_lpi2c.c index 2026bd62a8..5caa3437e1 100644 --- a/arch/arm/src/imx9/imx9_lpi2c.c +++ b/arch/arm/src/imx9/imx9_lpi2c.c @@ -1974,7 +1974,7 @@ static int imx9_lpi2c_dma_transfer(struct imx9_lpi2c_priv_s *priv) LPI2C_MSR_ALF | LPI2C_MSR_FEF); - /* Enable the Iterrupts */ + /* Enable the Interrupts */ imx9_lpi2c_putreg(priv, IMX9_LPI2C_MIER_OFFSET, LPI2C_MIER_NDIE | LPI2C_MIER_ALIE | @@ -2291,7 +2291,7 @@ static int imx9_lpi2c_reset(struct i2c_master_s *dev) out: - /* Release the port for re-use by other clients */ + /* Release the port for reuse by other clients */ nxmutex_unlock(&priv->lock); return ret; diff --git a/arch/arm/src/imx9/imx9_lpspi.c b/arch/arm/src/imx9/imx9_lpspi.c index 0fad5fbb85..5177896d94 100644 --- a/arch/arm/src/imx9/imx9_lpspi.c +++ b/arch/arm/src/imx9/imx9_lpspi.c @@ -2114,7 +2114,7 @@ struct spi_dev_s *imx9_lpspibus_initialize(int bus) * Name: imx9_lpspibus_uninitialize * * Description: - * Unitialize the selected SPI bus + * Uninitialize the selected SPI bus * * Input Parameters: * dev - Device-specific state data diff --git a/arch/arm/src/imx9/imx9_lpspi.h b/arch/arm/src/imx9/imx9_lpspi.h index d1e2f3f617..dc98f80ced 100644 --- a/arch/arm/src/imx9/imx9_lpspi.h +++ b/arch/arm/src/imx9/imx9_lpspi.h @@ -74,7 +74,7 @@ struct spi_dev_s *imx9_lpspibus_initialize(int bus); * Name: imx9_lpspibus_uninitialize * * Description: - * Unitialize the selected SPI bus if refcount is 1 + * Uninitialize the selected SPI bus if refcount is 1 * * Input Parameters: * dev - Device-specific state data diff --git a/arch/arm/src/imx9/imx9_lpuart.c b/arch/arm/src/imx9/imx9_lpuart.c index 3e35c26ccd..9a7d5056da 100644 --- a/arch/arm/src/imx9/imx9_lpuart.c +++ b/arch/arm/src/imx9/imx9_lpuart.c @@ -1297,7 +1297,7 @@ static int imx9_dma_setup(struct uart_dev_s *dev) modifyreg32(priv->uartbase + IMX9_LPUART_BAUD_OFFSET, 0, LPUART_BAUD_RDMAE); - /* Enable interrupt on idle and erros */ + /* Enable interrupt on idle and errors */ modifyreg32(priv->uartbase + IMX9_LPUART_CTRL_OFFSET, 0, LPUART_CTRL_PEIE | @@ -2565,7 +2565,7 @@ static int up_pm_prepare(struct pm_callback_s *cb, int domain, * * Description: * Performs the low level UART initialization early in debug so that the - * serial console will be available during bootup. This must be called + * serial console will be available during boot up. This must be called * before arm_serialinit. * ****************************************************************************/ diff --git a/arch/arm/src/imxrt/Kconfig b/arch/arm/src/imxrt/Kconfig index 7e202d208e..93cae607fb 100644 --- a/arch/arm/src/imxrt/Kconfig +++ b/arch/arm/src/imxrt/Kconfig @@ -2633,7 +2633,7 @@ config IMXRT_SRAM_HEAPOFFSET endmenu # i.MX RT Heap Configuration config IMXRT_FLEXRAM_PARTITION - bool "Set FlexRAM Paritioning" + bool "Set FlexRAM Partitioning" depends on ARCH_FAMILY_IMXRT117x endmenu # Memory Configuration @@ -2656,7 +2656,7 @@ config IMXRT_LPI2C_DMA_MAXMSG default 8 depends on IMXRT_LPI2C_DMA ---help--- - This option set the mumber of mesg that can be in a transfer. + This option set the number of mesg that can be in a transfer. It is used to allocate space for the 16 bit LPI2C commands that will be DMA-ed to the LPI2C device. diff --git a/arch/arm/src/imxrt/hardware/imxrt_enet.h b/arch/arm/src/imxrt/hardware/imxrt_enet.h index ed16700718..98acb3851a 100644 --- a/arch/arm/src/imxrt/hardware/imxrt_enet.h +++ b/arch/arm/src/imxrt/hardware/imxrt_enet.h @@ -304,7 +304,7 @@ #define ENET_TXIC_ICFT_SHIFT (20) /* Bits 0-15: Interrupt coalescing timer threshold */ #define ENET_TXIC_ICFT_SHIFT_MASK (0xff << ENET_TXIC_ICFT_SHIFT) #define ENET_TXIC_ICTT_ICCS (1 << 30) /* Bit 30: Interrupt Coalescing Timer Clock Source Select */ -#define ENET_TXIC_ICTT_ICEN (1 << 31) /* Bit 31: Eable/disabel Interrupt Coalescing */ +#define ENET_TXIC_ICTT_ICEN (1 << 31) /* Bit 31: Enable/disable Interrupt Coalescing */ /* Receive Interrupt Coalescing Register */ @@ -314,7 +314,7 @@ #define ENET_RXIC_ICFT_SHIFT (20) /* Bits 0-15: Interrupt coalescing timer threshold */ #define ENET_RXIC_ICFT_SHIFT_MASK (0xff << ENET_TXIC_ICFT_SHIFT) #define ENET_RXIC_ICTT_ICCS (1 << 30) /* Bit 30: Interrupt Coalescing Timer Clock Source Select */ -#define ENET_RXIC_ICTT_ICEN (1 << 31) /* Bit 31: Eable/disabel Interrupt Coalescing */ +#define ENET_RXIC_ICTT_ICEN (1 << 31) /* Bit 31: Enable/disable Interrupt Coalescing */ /* Transmit FIFO Watermark Register */ diff --git a/arch/arm/src/imxrt/hardware/imxrt_flexcan.h b/arch/arm/src/imxrt/hardware/imxrt_flexcan.h index 30ebd9f071..d55ac68ee1 100644 --- a/arch/arm/src/imxrt/hardware/imxrt_flexcan.h +++ b/arch/arm/src/imxrt/hardware/imxrt_flexcan.h @@ -263,7 +263,7 @@ #define CAN_ESR1_TWRNINT (1 << 17) /* Bit 17: Tx Warning Interrupt Flag */ #define CAN_ESR1_SYNCH (1 << 18) /* Bit 18: CAN Synchronization Status */ #define CAN_ESR1_BOFFDONEINT (1 << 19) /* Bit 19: Bus Off Done Interrupt */ -#define CAN_ESR1_ERRINTFAST (1 << 20) /* Bit 20: Error Iterrupt for Errors Detected in Data Phase of CAN FD frames */ +#define CAN_ESR1_ERRINTFAST (1 << 20) /* Bit 20: Error Interrupt for Errors Detected in Data Phase of CAN FD frames */ #define CAN_ESR1_ERROVR (1 << 21) /* Bit 21: Error Overrun */ /* Bits 21-25: Reserved */ #define CAN_ESR1_STFERRFAST (1 << 26) /* Bit 26: Stuffing Error in the Data Phase of CAN FD frames */ @@ -375,7 +375,7 @@ #define CAN_CBT_ERJW_SHIFT (16) /* Bits 16-20: Extended Resync Jump Width */ #define CAN_CBT_ERJW_MASK (0x1f << CAN_CBT_ERJW_SHIFT) #define CAN_CBT_ERJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_ERJW_SHIFT)) & CAN_CBT_ERJW_MASK) -#define CAN_CBT_EPRESDIV_SHIFT (21) /* Bits 21-30: Extendet Prescaler Division Factor */ +#define CAN_CBT_EPRESDIV_SHIFT (21) /* Bits 21-30: Extended Prescaler Division Factor */ #define CAN_CBT_EPRESDIV_MASK (0x3ff << CAN_CBT_EPRESDIV_SHIFT) #define CAN_CBT_EPRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPRESDIV_SHIFT)) & CAN_CBT_EPRESDIV_MASK) #define CAN_CBT_BTF (1 << 31) /* Bit 31: Bit Timing Format Enable */ diff --git a/arch/arm/src/imxrt/hardware/imxrt_snvs.h b/arch/arm/src/imxrt/hardware/imxrt_snvs.h index fb2e24ee94..11ca03b715 100644 --- a/arch/arm/src/imxrt/hardware/imxrt_snvs.h +++ b/arch/arm/src/imxrt/hardware/imxrt_snvs.h @@ -150,7 +150,7 @@ # define SNVS_HPCR_HPCALBVAL_M1 (31 << SNVS_HPCR_HPCALBVAL_SHIFT) /* -1 counts per 32768 ticks */ /* Bits 15: Reserved */ -#define SNVS_HPCR_HPTS (1 << 16) /* Bit 16: LPSRTC time sychronization */ +#define SNVS_HPCR_HPTS (1 << 16) /* Bit 16: LPSRTC time synchronization */ /* Bits 17-23: Reserved */ #define SNVS_HPCR_BTNCONFIG_SHIFT (24) /* Bits 24-26: Button Configuration */ #define SNVS_HPCR_BTNCONFIG_MASK (7 << SNVS_HPCR_BTNCONFIG_SHIFT) diff --git a/arch/arm/src/imxrt/hardware/rt117x/imxrt117x_ccm.h b/arch/arm/src/imxrt/hardware/rt117x/imxrt117x_ccm.h index 13853d6ae7..0df4f9d1b8 100644 --- a/arch/arm/src/imxrt/hardware/rt117x/imxrt117x_ccm.h +++ b/arch/arm/src/imxrt/hardware/rt117x/imxrt117x_ccm.h @@ -726,7 +726,7 @@ #define CCM_CR_CKO2 78 /* CLOCK ROOT CKO2. */ /* Note IMXRT7 uses the definition LPCG instead of CCGR as the clock gate - * register but for compatiblity we define them as LPCG + * register but for compatibility we define them as LPCG. */ #define CCM_CG_OFF (0) /* Clock is off during all modes */ @@ -756,7 +756,7 @@ #define CCM_CCGR_MU_A 20 #define CCM_CCGR_MU_B 21 #define CCM_CCGR_EDMA 22 -#define CCM_CCGR_DMA 22 /* Note Added CTRL for compatiblity */ +#define CCM_CCGR_DMA 22 /* Note Added CTRL for compatibility */ #define CCM_CCGR_EDMA_LPSR 23 #define CCM_CCGR_ROMCP 24 #define CCM_CCGR_OCRAM 25 @@ -772,10 +772,10 @@ #define CCM_CCGR_IEE 35 #define CCM_CCGR_KEY_MANAGER 36 #define CCM_CCGR_PUF 36 -#define CCM_CCGR_OCOTP_CTRL 37 /* Note Added CTRL for compatiblity */ +#define CCM_CCGR_OCOTP_CTRL 37 /* Note Added CTRL for compatibility */ #define CCM_CCGR_SNVS_HP 38 #define CCM_CCGR_SNVS 39 -#define CCM_CCGR_SNVS_LP 39 /* Note Added CTRL for compatiblity */ +#define CCM_CCGR_SNVS_LP 39 /* Note Added CTRL for compatibility */ #define CCM_CCGR_CAAM 40 #define CCM_CCGR_JTAG_MUX 41 #define CCM_CCGR_CSTRACE 42 diff --git a/arch/arm/src/imxrt/hardware/rt117x/imxrt117x_dcdc.h b/arch/arm/src/imxrt/hardware/rt117x/imxrt117x_dcdc.h index 92e0f00610..a6192a53d0 100644 --- a/arch/arm/src/imxrt/hardware/rt117x/imxrt117x_dcdc.h +++ b/arch/arm/src/imxrt/hardware/rt117x/imxrt117x_dcdc.h @@ -189,7 +189,7 @@ #define DCDC_REG3_REG_FBK_SEL_SHIFT (22) /* Bits 22-24: Select the feedback point of the internal regulator */ #define DCDC_REG3_REG_FBK_SEL_MASK (0x3 << DCDC_REG3_REG_FBK_SEL_SHIFT) #define DCDC_REG3_REG_FBK_SEL(n) (((n) << DCDC_REG3_REG_FBK_SEL_SHIFT) & DCDC_REG3_REG_FBK_SEL_MASK) -#define DCDC_REG3_MINPWR_DC_HALFCLK (1 << 24) /* Bit 24: Set DCDC clock to half freqeuncy for continuous mode. */ +#define DCDC_REG3_MINPWR_DC_HALFCLK (1 << 24) /* Bit 24: Set DCDC clock to half frequency for continuous mode. */ #define DCDC_REG3_MINPWR_HALF_FETS (1 << 26) /* Bit 26: Use half switch FET */ #define DCDC_REG3_MISC_DELAY_TIMING (1 << 27) /* Bit 27: Miscellaneous Delay Timing */ #define DCDC_REG3_VDD1P0CTRL_DISABLE_STEP (1 << 29) /* Bit 29: Disable Step for VDD1P0 */ diff --git a/arch/arm/src/imxrt/hardware/rt117x/imxrt117x_gpc.h b/arch/arm/src/imxrt/hardware/rt117x/imxrt117x_gpc.h index a7bdf617e1..33a5e119af 100644 --- a/arch/arm/src/imxrt/hardware/rt117x/imxrt117x_gpc.h +++ b/arch/arm/src/imxrt/hardware/rt117x/imxrt117x_gpc.h @@ -351,7 +351,7 @@ #define GPC_CPU_MODE_CTRL_CM_NON_IRQ_WAKEUP_STAT_DEBUG_WAKEUP_STAT (1 << 1) /* Bit 1: Debug wakeup status */ /* CM sleep SSAR control (CM_SLEEP_SSAR_CTRL) */ -#define GPC_CPU_MODE_CTRL_CM_SLEEP_SSAR_CTRL_STEP_CNT_SHIFT (0) /* Bits 0-16: Step count, useage is depending on CNT_MODE. */ +#define GPC_CPU_MODE_CTRL_CM_SLEEP_SSAR_CTRL_STEP_CNT_SHIFT (0) /* Bits 0-16: Step count, usage is depending on CNT_MODE. */ #define GPC_CPU_MODE_CTRL_CM_SLEEP_SSAR_CTRL_STEP_CNT_MASK (0xFFFF << GPC_CPU_MODE_CTRL_CM_SLEEP_SSAR_CTRL_STEP_CNT_SHIFT) #define GPC_CPU_MODE_CTRL_CM_SLEEP_SSAR_CTRL_STEP_CNT(n) (((n) << GPC_CPU_MODE_CTRL_CM_SLEEP_SSAR_CTRL_STEP_CNT_SHIFT) & GPC_CPU_MODE_CTRL_CM_SLEEP_SSAR_CTRL_STEP_CNT_MASK) #define GPC_CPU_MODE_CTRL_CM_SLEEP_SSAR_CTRL_CNT_MODE_SHIFT (28) /* Bits 28-30: Count mode */ @@ -360,7 +360,7 @@ #define GPC_CPU_MODE_CTRL_CM_SLEEP_SSAR_CTRL_DISABLE (1 << 31) /* Bit 31: Disable this step */ /* CM sleep LPCG control (CM_SLEEP_LPCG_CTRL) */ -#define GPC_CPU_MODE_CTRL_CM_SLEEP_LPCG_CTRL_STEP_CNT_SHIFT (0) /* Bits 0-16: Step count, useage is depending on CNT_MODE */ +#define GPC_CPU_MODE_CTRL_CM_SLEEP_LPCG_CTRL_STEP_CNT_SHIFT (0) /* Bits 0-16: Step count, usage is depending on CNT_MODE */ #define GPC_CPU_MODE_CTRL_CM_SLEEP_LPCG_CTRL_STEP_CNT_MASK (0xFFFF << GPC_CPU_MODE_CTRL_CM_SLEEP_LPCG_CTRL_STEP_CNT_SHIFT) #define GPC_CPU_MODE_CTRL_CM_SLEEP_LPCG_CTRL_STEP_CNT(n) (((n) << GPC_CPU_MODE_CTRL_CM_SLEEP_LPCG_CTRL_STEP_CNT_SHIFT) & GPC_CPU_MODE_CTRL_CM_SLEEP_LPCG_CTRL_STEP_CNT_MASK) #define GPC_CPU_MODE_CTRL_CM_SLEEP_LPCG_CTRL_CNT_MODE_SHIFT (28) /* Bits 28-30: Count mode */ @@ -369,7 +369,7 @@ #define GPC_CPU_MODE_CTRL_CM_SLEEP_LPCG_CTRL_DISABLE (1 << 31) /* Bit 31: Disable this step */ /* CM sleep PLL control (CM_SLEEP_PLL_CTRL) */ -#define GPC_CPU_MODE_CTRL_CM_SLEEP_PLL_CTRL_STEP_CNT_SHIFT (0) /* Bits 0-16: Step count, useage is depending on CNT_MODE */ +#define GPC_CPU_MODE_CTRL_CM_SLEEP_PLL_CTRL_STEP_CNT_SHIFT (0) /* Bits 0-16: Step count, usage is depending on CNT_MODE */ #define GPC_CPU_MODE_CTRL_CM_SLEEP_PLL_CTRL_STEP_CNT_MASK (0xFFFF << GPC_CPU_MODE_CTRL_CM_SLEEP_PLL_CTRL_STEP_CNT_SHIFT) #define GPC_CPU_MODE_CTRL_CM_SLEEP_PLL_CTRL_STEP_CNT(n) (((n) << GPC_CPU_MODE_CTRL_CM_SLEEP_PLL_CTRL_STEP_CNT_SHIFT) & GPC_CPU_MODE_CTRL_CM_SLEEP_PLL_CTRL_STEP_CNT_MASK) #define GPC_CPU_MODE_CTRL_CM_SLEEP_PLL_CTRL_CNT_MODE_SHIFT (28) /* Bits 28-30: Count mode */ @@ -378,7 +378,7 @@ #define GPC_CPU_MODE_CTRL_CM_SLEEP_PLL_CTRL_DISABLE (1 << 31) /* Bit 31: Disable this step */ /* CM sleep isolation control (CM_SLEEP_ISO_CTRL) */ -#define GPC_CPU_MODE_CTRL_CM_SLEEP_ISO_CTRL_STEP_CNT_SHIFT (0) /* Bits 0-16: Step count, useage is depending on CNT_MODE */ +#define GPC_CPU_MODE_CTRL_CM_SLEEP_ISO_CTRL_STEP_CNT_SHIFT (0) /* Bits 0-16: Step count, usage is depending on CNT_MODE */ #define GPC_CPU_MODE_CTRL_CM_SLEEP_ISO_CTRL_STEP_CNT_MASK (0xFFFF << GPC_CPU_MODE_CTRL_CM_SLEEP_ISO_CTRL_STEP_CNT_SHIFT) #define GPC_CPU_MODE_CTRL_CM_SLEEP_ISO_CTRL_STEP_CNT(n) (((n) << GPC_CPU_MODE_CTRL_CM_SLEEP_ISO_CTRL_STEP_CNT_SHIFT) & GPC_CPU_MODE_CTRL_CM_SLEEP_ISO_CTRL_STEP_CNT_MASK) #define GPC_CPU_MODE_CTRL_CM_SLEEP_ISO_CTRL_CNT_MODE_SHIFT (28) /* Bits 28-30: Count mode */ @@ -387,7 +387,7 @@ #define GPC_CPU_MODE_CTRL_CM_SLEEP_ISO_CTRL_DISABLE (1 << 31) /* Bit 31: Disable this step */ /* CM sleep reset control (CM_SLEEP_RESET_CTRL) */ -#define GPC_CPU_MODE_CTRL_CM_SLEEP_RESET_CTRL_STEP_CNT_SHIFT (0) /* Bits 0-16: Step count, useage is depending on CNT_MODE */ +#define GPC_CPU_MODE_CTRL_CM_SLEEP_RESET_CTRL_STEP_CNT_SHIFT (0) /* Bits 0-16: Step count, usage is depending on CNT_MODE */ #define GPC_CPU_MODE_CTRL_CM_SLEEP_RESET_CTRL_STEP_CNT_MASK (0xFFFF << GPC_CPU_MODE_CTRL_CM_SLEEP_RESET_CTRL_STEP_CNT_SHIFT) #define GPC_CPU_MODE_CTRL_CM_SLEEP_RESET_CTRL_STEP_CNT(n) (((n) << GPC_CPU_MODE_CTRL_CM_SLEEP_RESET_CTRL_STEP_CNT_SHIFT) & GPC_CPU_MODE_CTRL_CM_SLEEP_RESET_CTRL_STEP_CNT_MASK) #define GPC_CPU_MODE_CTRL_CM_SLEEP_RESET_CTRL_CNT_MODE_SHIFT (28) /* Bits 28-30: Count mode */ @@ -396,7 +396,7 @@ #define GPC_CPU_MODE_CTRL_CM_SLEEP_RESET_CTRL_DISABLE (1 << 31) /* Bit 31: Disable this step */ /* CM sleep power control (CM_SLEEP_POWER_CTRL) */ -#define GPC_CPU_MODE_CTRL_CM_SLEEP_POWER_CTRL_STEP_CNT_SHIFT (0) /* Bits 0-16: Step count, useage is depending on CNT_MODE */ +#define GPC_CPU_MODE_CTRL_CM_SLEEP_POWER_CTRL_STEP_CNT_SHIFT (0) /* Bits 0-16: Step count, usage is depending on CNT_MODE */ #define GPC_CPU_MODE_CTRL_CM_SLEEP_POWER_CTRL_STEP_CNT_MASK (0xFFFF << GPC_CPU_MODE_CTRL_CM_SLEEP_POWER_CTRL_STEP_CNT_SHIFT) #define GPC_CPU_MODE_CTRL_CM_SLEEP_POWER_CTRL_STEP_CNT(n) (((n) << GPC_CPU_MODE_CTRL_CM_SLEEP_POWER_CTRL_STEP_CNT_SHIFT) & GPC_CPU_MODE_CTRL_CM_SLEEP_POWER_CTRL_STEP_CNT_MASK) #define GPC_CPU_MODE_CTRL_CM_SLEEP_POWER_CTRL_CNT_MODE_SHIFT (28) /* Bits 28-30: Count mode */ @@ -405,7 +405,7 @@ #define GPC_CPU_MODE_CTRL_CM_SLEEP_POWER_CTRL_DISABLE (1 << 31) /* Bit 31: Disable this step */ /* CM wakeup power control (CM_WAKEUP_POWER_CTRL) */ -#define GPC_CPU_MODE_CTRL_CM_WAKEUP_POWER_CTRL_STEP_CNT_SHIFT (0) /* Bits 0-16: Step count, useage is depending on CNT_MODE */ +#define GPC_CPU_MODE_CTRL_CM_WAKEUP_POWER_CTRL_STEP_CNT_SHIFT (0) /* Bits 0-16: Step count, usage is depending on CNT_MODE */ #define GPC_CPU_MODE_CTRL_CM_WAKEUP_POWER_CTRL_STEP_CNT_MASK (0xFFFF << GPC_CPU_MODE_CTRL_CM_WAKEUP_POWER_CTRL_STEP_CNT_SHIFT) #define GPC_CPU_MODE_CTRL_CM_WAKEUP_POWER_CTRL_STEP_CNT(n) (((n) << GPC_CPU_MODE_CTRL_CM_WAKEUP_POWER_CTRL_STEP_CNT_SHIFT) & GPC_CPU_MODE_CTRL_CM_WAKEUP_POWER_CTRL_STEP_CNT_MASK) #define GPC_CPU_MODE_CTRL_CM_WAKEUP_POWER_CTRL_CNT_MODE_SHIFT (28) /* Bits 28-30: Count mode */ @@ -414,7 +414,7 @@ #define GPC_CPU_MODE_CTRL_CM_WAKEUP_POWER_CTRL_DISABLE (1 << 31) /* Bit 31: Disable this step */ /* CM wakeup reset control (CM_WAKEUP_RESET_CTRL) */ -#define GPC_CPU_MODE_CTRL_CM_WAKEUP_RESET_CTRL_STEP_CNT_SHIFT (0) /* Bits 0-16: Step count, useage is depending on CNT_MODE */ +#define GPC_CPU_MODE_CTRL_CM_WAKEUP_RESET_CTRL_STEP_CNT_SHIFT (0) /* Bits 0-16: Step count, usage is depending on CNT_MODE */ #define GPC_CPU_MODE_CTRL_CM_WAKEUP_RESET_CTRL_STEP_CNT_MASK (0xFFFF << GPC_CPU_MODE_CTRL_CM_WAKEUP_RESET_CTRL_STEP_CNT_SHIFT) #define GPC_CPU_MODE_CTRL_CM_WAKEUP_RESET_CTRL_STEP_CNT(n) (((n) << GPC_CPU_MODE_CTRL_CM_WAKEUP_RESET_CTRL_STEP_CNT_SHIFT) & GPC_CPU_MODE_CTRL_CM_WAKEUP_RESET_CTRL_STEP_CNT_MASK) #define GPC_CPU_MODE_CTRL_CM_WAKEUP_RESET_CTRL_CNT_MODE_SHIFT (28) /* Bits 28-30: Count mode */ @@ -423,7 +423,7 @@ #define GPC_CPU_MODE_CTRL_CM_WAKEUP_RESET_CTRL_DISABLE (1 << 31) /* Bit 31: Disable this step */ /* CM wakeup isolation control (CM_WAKEUP_ISO_CTRL) */ -#define GPC_CPU_MODE_CTRL_CM_WAKEUP_ISO_CTRL_STEP_CNT_SHIFT (0) /* Bits 0-16: Step count, useage is depending on CNT_MODE */ +#define GPC_CPU_MODE_CTRL_CM_WAKEUP_ISO_CTRL_STEP_CNT_SHIFT (0) /* Bits 0-16: Step count, usage is depending on CNT_MODE */ #define GPC_CPU_MODE_CTRL_CM_WAKEUP_ISO_CTRL_STEP_CNT_MASK (0xFFFF << GPC_CPU_MODE_CTRL_CM_WAKEUP_ISO_CTRL_STEP_CNT_SHIFT) #define GPC_CPU_MODE_CTRL_CM_WAKEUP_ISO_CTRL_STEP_CNT(n) (((n) << GPC_CPU_MODE_CTRL_CM_WAKEUP_ISO_CTRL_STEP_CNT_SHIFT) & GPC_CPU_MODE_CTRL_CM_WAKEUP_ISO_CTRL_STEP_CNT_MASK) #define GPC_CPU_MODE_CTRL_CM_WAKEUP_ISO_CTRL_CNT_MODE_SHIFT (28) /* Bits 28-30: Count mode */ @@ -432,7 +432,7 @@ #define GPC_CPU_MODE_CTRL_CM_WAKEUP_ISO_CTRL_DISABLE (1 << 31) /* Bit 31: Disable this step */ /* CM wakeup PLL control (CM_WAKEUP_PLL_CTRL) */ -#define GPC_CPU_MODE_CTRL_CM_WAKEUP_PLL_CTRL_STEP_CNT_SHIFT (0) /* Bits 0-16: Step count, useage is depending on CNT_MODE */ +#define GPC_CPU_MODE_CTRL_CM_WAKEUP_PLL_CTRL_STEP_CNT_SHIFT (0) /* Bits 0-16: Step count, usage is depending on CNT_MODE */ #define GPC_CPU_MODE_CTRL_CM_WAKEUP_PLL_CTRL_STEP_CNT_MASK (0xFFFF << GPC_CPU_MODE_CTRL_CM_WAKEUP_PLL_CTRL_STEP_CNT_SHIFT) #define GPC_CPU_MODE_CTRL_CM_WAKEUP_PLL_CTRL_STEP_CNT(n) (((n) << GPC_CPU_MODE_CTRL_CM_WAKEUP_PLL_CTRL_STEP_CNT_SHIFT) & GPC_CPU_MODE_CTRL_CM_WAKEUP_PLL_CTRL_STEP_CNT_MASK) #define GPC_CPU_MODE_CTRL_CM_WAKEUP_PLL_CTRL_CNT_MODE_SHIFT (28) /* Bits 28-30: Count mode */ @@ -441,7 +441,7 @@ #define GPC_CPU_MODE_CTRL_CM_WAKEUP_PLL_CTRL_DISABLE (1 << 31) /* Bit 31: Disable this step */ /* CM wakeup LPCG control (CM_WAKEUP_LPCG_CTRL) */ -#define GPC_CPU_MODE_CTRL_CM_WAKEUP_LPCG_CTRL_STEP_CNT_SHIFT (0) /* Bits 0-16: Step count, useage is depending on CNT_MODE */ +#define GPC_CPU_MODE_CTRL_CM_WAKEUP_LPCG_CTRL_STEP_CNT_SHIFT (0) /* Bits 0-16: Step count, usage is depending on CNT_MODE */ #define GPC_CPU_MODE_CTRL_CM_WAKEUP_LPCG_CTRL_STEP_CNT_MASK (0xFFFF << GPC_CPU_MODE_CTRL_CM_WAKEUP_LPCG_CTRL_STEP_CNT_SHIFT) #define GPC_CPU_MODE_CTRL_CM_WAKEUP_LPCG_CTRL_STEP_CNT(n) (((n) << GPC_CPU_MODE_CTRL_CM_WAKEUP_LPCG_CTRL_STEP_CNT_SHIFT) & GPC_CPU_MODE_CTRL_CM_WAKEUP_LPCG_CTRL_STEP_CNT_MASK) #define GPC_CPU_MODE_CTRL_CM_WAKEUP_LPCG_CTRL_CNT_MODE_SHIFT (28) /* Bits 28-30: Count mode */ @@ -450,7 +450,7 @@ #define GPC_CPU_MODE_CTRL_CM_WAKEUP_LPCG_CTRL_DISABLE (1 << 31) /* Bit 31: Disable this step */ /* CM wakeup SSAR control (CM_WAKEUP_SSAR_CTRL) */ -#define GPC_CPU_MODE_CTRL_CM_WAKEUP_SSAR_CTRL_STEP_CNT_SHIFT (0) /* Bits 0-16: Step count, useage is depending on CNT_MODE */ +#define GPC_CPU_MODE_CTRL_CM_WAKEUP_SSAR_CTRL_STEP_CNT_SHIFT (0) /* Bits 0-16: Step count, usage is depending on CNT_MODE */ #define GPC_CPU_MODE_CTRL_CM_WAKEUP_SSAR_CTRL_STEP_CNT_MASK (0xFFFF << GPC_CPU_MODE_CTRL_CM_WAKEUP_SSAR_CTRL_STEP_CNT_SHIFT) #define GPC_CPU_MODE_CTRL_CM_WAKEUP_SSAR_CTRL_STEP_CNT(n) (((n) << GPC_CPU_MODE_CTRL_CM_WAKEUP_SSAR_CTRL_STEP_CNT_SHIFT) & GPC_CPU_MODE_CTRL_CM_WAKEUP_SSAR_CTRL_STEP_CNT_MASK) #define GPC_CPU_MODE_CTRL_CM_WAKEUP_SSAR_CTRL_CNT_MODE_SHIFT (28) /* Bits 28-30: Count mode */ @@ -471,7 +471,7 @@ #define GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_WAKEUP_SHIFT (11) /* Bits 11-15: The Setpoint that CPU want the system to transit to on next CPU platform wakeup sequence */ #define GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_WAKEUP_MASK (0xF << GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_WAKEUP_SHIFT) #define GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_WAKEUP(n) (((n) << GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_WAKEUP_SHIFT) & GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_WAKEUP_MASK) -#define GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_WAKEUP_SEL (1 << 15) /* Bit 15: Select the Setpoint transiton on the next CPU platform wakeup sequence */ +#define GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_WAKEUP_SEL (1 << 15) /* Bit 15: Select the Setpoint transition on the next CPU platform wakeup sequence */ /* CM Setpoint Status (CM_SP_STAT) */ #define GPC_CPU_MODE_CTRL_CM_SP_STAT_CPU_SP_CURRENT_SHIFT (0) /* Bits 0-4: The current Setpoint of the system */ @@ -771,7 +771,7 @@ #define GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP15_PRIORITY(n) (((n) << GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP15_PRIORITY_SHIFT) & GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP15_PRIORITY_MASK) /* SP SSAR save control (SP_SSAR_SAVE_CTRL) */ -#define GPC_SET_POINT_CTRL_SP_SSAR_SAVE_CTRL_STEP_CNT_SHIFT (0) /* Bits 0-16: Step count, useage is depending on CNT_MODE */ +#define GPC_SET_POINT_CTRL_SP_SSAR_SAVE_CTRL_STEP_CNT_SHIFT (0) /* Bits 0-16: Step count, usage is depending on CNT_MODE */ #define GPC_SET_POINT_CTRL_SP_SSAR_SAVE_CTRL_STEP_CNT_MASK (0xFFFF << GPC_SET_POINT_CTRL_SP_SSAR_SAVE_CTRL_STEP_CNT_SHIFT) #define GPC_SET_POINT_CTRL_SP_SSAR_SAVE_CTRL_STEP_CNT(n) (((n) << GPC_SET_POINT_CTRL_SP_SSAR_SAVE_CTRL_STEP_CNT_SHIFT) & GPC_SET_POINT_CTRL_SP_SSAR_SAVE_CTRL_STEP_CNT_MASK) #define GPC_SET_POINT_CTRL_SP_SSAR_SAVE_CTRL_CNT_MODE_SHIFT (28) /* Bits 28-30: Count mode */ @@ -780,7 +780,7 @@ #define GPC_SET_POINT_CTRL_SP_SSAR_SAVE_CTRL_DISABLE (1 << 31) /* Bit 31: Disable this step */ /* SP LPCG off control (SP_LPCG_OFF_CTRL) */ -#define GPC_SET_POINT_CTRL_SP_LPCG_OFF_CTRL_STEP_CNT_SHIFT (0) /* Bits 0-16: Step count, useage is depending on CNT_MODE */ +#define GPC_SET_POINT_CTRL_SP_LPCG_OFF_CTRL_STEP_CNT_SHIFT (0) /* Bits 0-16: Step count, usage is depending on CNT_MODE */ #define GPC_SET_POINT_CTRL_SP_LPCG_OFF_CTRL_STEP_CNT_MASK (0xFFFF << GPC_SET_POINT_CTRL_SP_LPCG_OFF_CTRL_STEP_CNT_SHIFT) #define GPC_SET_POINT_CTRL_SP_LPCG_OFF_CTRL_STEP_CNT(n) (((n) << GPC_SET_POINT_CTRL_SP_LPCG_OFF_CTRL_STEP_CNT_SHIFT) & GPC_SET_POINT_CTRL_SP_LPCG_OFF_CTRL_STEP_CNT_MASK) #define GPC_SET_POINT_CTRL_SP_LPCG_OFF_CTRL_CNT_MODE_SHIFT (28) /* Bits 28-30: Count mode */ @@ -789,7 +789,7 @@ #define GPC_SET_POINT_CTRL_SP_LPCG_OFF_CTRL_DISABLE (1 << 31) /* Bit 31: Disable this step */ /* SP group down control (SP_GROUP_DOWN_CTRL) */ -#define GPC_SET_POINT_CTRL_SP_GROUP_DOWN_CTRL_STEP_CNT_SHIFT (0) /* Bits 0-16: Step count, useage is depending on CNT_MODE */ +#define GPC_SET_POINT_CTRL_SP_GROUP_DOWN_CTRL_STEP_CNT_SHIFT (0) /* Bits 0-16: Step count, usage is depending on CNT_MODE */ #define GPC_SET_POINT_CTRL_SP_GROUP_DOWN_CTRL_STEP_CNT_MASK (0xFFFF << GPC_SET_POINT_CTRL_SP_GROUP_DOWN_CTRL_STEP_CNT_SHIFT) #define GPC_SET_POINT_CTRL_SP_GROUP_DOWN_CTRL_STEP_CNT(n) (((n) << GPC_SET_POINT_CTRL_SP_GROUP_DOWN_CTRL_STEP_CNT_SHIFT) & GPC_SET_POINT_CTRL_SP_GROUP_DOWN_CTRL_STEP_CNT_MASK) #define GPC_SET_POINT_CTRL_SP_GROUP_DOWN_CTRL_CNT_MODE_SHIFT (28) /* Bits 28-30: Count mode */ @@ -798,7 +798,7 @@ #define GPC_SET_POINT_CTRL_SP_GROUP_DOWN_CTRL_DISABLE (1 << 31) /* Bit 31: Disable this step */ /* SP root down control (SP_ROOT_DOWN_CTRL) */ -#define GPC_SET_POINT_CTRL_SP_ROOT_DOWN_CTRL_STEP_CNT_SHIFT (0) /* Bits 0-16: Step count, useage is depending on CNT_MODE */ +#define GPC_SET_POINT_CTRL_SP_ROOT_DOWN_CTRL_STEP_CNT_SHIFT (0) /* Bits 0-16: Step count, usage is depending on CNT_MODE */ #define GPC_SET_POINT_CTRL_SP_ROOT_DOWN_CTRL_STEP_CNT_MASK (0xFFFF << GPC_SET_POINT_CTRL_SP_ROOT_DOWN_CTRL_STEP_CNT_SHIFT) #define GPC_SET_POINT_CTRL_SP_ROOT_DOWN_CTRL_STEP_CNT(n) (((n) << GPC_SET_POINT_CTRL_SP_ROOT_DOWN_CTRL_STEP_CNT_SHIFT) & GPC_SET_POINT_CTRL_SP_ROOT_DOWN_CTRL_STEP_CNT_MASK) #define GPC_SET_POINT_CTRL_SP_ROOT_DOWN_CTRL_CNT_MODE_SHIFT (28) /* Bits 28-30: Count mode */ @@ -807,7 +807,7 @@ #define GPC_SET_POINT_CTRL_SP_ROOT_DOWN_CTRL_DISABLE (1 << 31) /* Bit 31: Disable this step */ /* SP PLL off control (SP_PLL_OFF_CTRL) */ -#define GPC_SET_POINT_CTRL_SP_PLL_OFF_CTRL_STEP_CNT_SHIFT (0) /* Bits 0-16: Step count, useage is depending on CNT_MODE */ +#define GPC_SET_POINT_CTRL_SP_PLL_OFF_CTRL_STEP_CNT_SHIFT (0) /* Bits 0-16: Step count, usage is depending on CNT_MODE */ #define GPC_SET_POINT_CTRL_SP_PLL_OFF_CTRL_STEP_CNT_MASK (0xFFFF << GPC_SET_POINT_CTRL_SP_PLL_OFF_CTRL_STEP_CNT_SHIFT) #define GPC_SET_POINT_CTRL_SP_PLL_OFF_CTRL_STEP_CNT(n) (((n) << GPC_SET_POINT_CTRL_SP_PLL_OFF_CTRL_STEP_CNT_SHIFT) & GPC_SET_POINT_CTRL_SP_PLL_OFF_CTRL_STEP_CNT_MASK) #define GPC_SET_POINT_CTRL_SP_PLL_OFF_CTRL_CNT_MODE_SHIFT (28) /* Bits 28-30: Count mode */ @@ -816,7 +816,7 @@ #define GPC_SET_POINT_CTRL_SP_PLL_OFF_CTRL_DISABLE (1 << 31) /* Bit 31: Disable this step */ /* SP ISO on control (SP_ISO_ON_CTRL) */ -#define GPC_SET_POINT_CTRL_SP_ISO_ON_CTRL_STEP_CNT_SHIFT (0) /* Bits 0-16: Step count, useage is depending on CNT_MODE */ +#define GPC_SET_POINT_CTRL_SP_ISO_ON_CTRL_STEP_CNT_SHIFT (0) /* Bits 0-16: Step count, usage is depending on CNT_MODE */ #define GPC_SET_POINT_CTRL_SP_ISO_ON_CTRL_STEP_CNT_MASK (0xFFFF << GPC_SET_POINT_CTRL_SP_ISO_ON_CTRL_STEP_CNT_SHIFT) #define GPC_SET_POINT_CTRL_SP_ISO_ON_CTRL_STEP_CNT(n) (((n) << GPC_SET_POINT_CTRL_SP_ISO_ON_CTRL_STEP_CNT_SHIFT) & GPC_SET_POINT_CTRL_SP_ISO_ON_CTRL_STEP_CNT_MASK) #define GPC_SET_POINT_CTRL_SP_ISO_ON_CTRL_CNT_MODE_SHIFT (28) /* Bits 28-30: Count mode */ @@ -825,7 +825,7 @@ #define GPC_SET_POINT_CTRL_SP_ISO_ON_CTRL_DISABLE (1 << 31) /* Bit 31: Disable this step */ /* SP reset early control (SP_RESET_EARLY_CTRL) */ -#define GPC_SET_POINT_CTRL_SP_RESET_EARLY_CTRL_STEP_CNT_SHIFT (0) /* Bits 0-16: Step count, useage is depending on CNT_MODE */ +#define GPC_SET_POINT_CTRL_SP_RESET_EARLY_CTRL_STEP_CNT_SHIFT (0) /* Bits 0-16: Step count, usage is depending on CNT_MODE */ #define GPC_SET_POINT_CTRL_SP_RESET_EARLY_CTRL_STEP_CNT_MASK (0xFFFF << GPC_SET_POINT_CTRL_SP_RESET_EARLY_CTRL_STEP_CNT_SHIFT) #define GPC_SET_POINT_CTRL_SP_RESET_EARLY_CTRL_STEP_CNT(n) (((n) << GPC_SET_POINT_CTRL_SP_RESET_EARLY_CTRL_STEP_CNT_SHIFT) & GPC_SET_POINT_CTRL_SP_RESET_EARLY_CTRL_STEP_CNT_MASK) #define GPC_SET_POINT_CTRL_SP_RESET_EARLY_CTRL_CNT_MODE_SHIFT (28) /* Bits 28-30: Count mode */ @@ -834,7 +834,7 @@ #define GPC_SET_POINT_CTRL_SP_RESET_EARLY_CTRL_DISABLE (1 << 31) /* Bit 31: Disable this step */ /* SP power off control (SP_POWER_OFF_CTRL) */ -#define GPC_SET_POINT_CTRL_SP_POWER_OFF_CTRL_STEP_CNT_SHIFT (0) /* Bits 0-16: Step count, useage is depending on CNT_MODE */ +#define GPC_SET_POINT_CTRL_SP_POWER_OFF_CTRL_STEP_CNT_SHIFT (0) /* Bits 0-16: Step count, usage is depending on CNT_MODE */ #define GPC_SET_POINT_CTRL_SP_POWER_OFF_CTRL_STEP_CNT_MASK (0xFFFF << GPC_SET_POINT_CTRL_SP_POWER_OFF_CTRL_STEP_CNT_SHIFT) #define GPC_SET_POINT_CTRL_SP_POWER_OFF_CTRL_STEP_CNT(n) (((n) << GPC_SET_POINT_CTRL_SP_POWER_OFF_CTRL_STEP_CNT_SHIFT) & GPC_SET_POINT_CTRL_SP_POWER_OFF_CTRL_STEP_CNT_MASK) #define GPC_SET_POINT_CTRL_SP_POWER_OFF_CTRL_CNT_MODE_SHIFT (28) /* Bits 28-30: Count mode */ @@ -843,7 +843,7 @@ #define GPC_SET_POINT_CTRL_SP_POWER_OFF_CTRL_DISABLE (1 << 31) /* Bit 31: Disable this step */ /* SP bias off control (SP_BIAS_OFF_CTRL) */ -#define GPC_SET_POINT_CTRL_SP_BIAS_OFF_CTRL_STEP_CNT_SHIFT (0) /* Bits 0-16: Step count, useage is depending on CNT_MODE */ +#define GPC_SET_POINT_CTRL_SP_BIAS_OFF_CTRL_STEP_CNT_SHIFT (0) /* Bits 0-16: Step count, usage is depending on CNT_MODE */ #define GPC_SET_POINT_CTRL_SP_BIAS_OFF_CTRL_STEP_CNT_MASK (0xFFFF << GPC_SET_POINT_CTRL_SP_BIAS_OFF_CTRL_STEP_CNT_SHIFT) #define GPC_SET_POINT_CTRL_SP_BIAS_OFF_CTRL_STEP_CNT(n) (((n) << GPC_SET_POINT_CTRL_SP_BIAS_OFF_CTRL_STEP_CNT_SHIFT) & GPC_SET_POINT_CTRL_SP_BIAS_OFF_CTRL_STEP_CNT_MASK) #define GPC_SET_POINT_CTRL_SP_BIAS_OFF_CTRL_CNT_MODE_SHIFT (28) /* Bits 28-30: Count mode */ @@ -852,7 +852,7 @@ #define GPC_SET_POINT_CTRL_SP_BIAS_OFF_CTRL_DISABLE (1 << 31) /* Bit 31: Disable this step */ /* SP bandgap and PLL_LDO off control (SP_BG_PLDO_OFF_CTRL) */ -#define GPC_SET_POINT_CTRL_SP_BG_PLDO_OFF_CTRL_STEP_CNT_SHIFT (0) /* Bits 0-16: Step count, useage is depending on CNT_MODE */ +#define GPC_SET_POINT_CTRL_SP_BG_PLDO_OFF_CTRL_STEP_CNT_SHIFT (0) /* Bits 0-16: Step count, usage is depending on CNT_MODE */ #define GPC_SET_POINT_CTRL_SP_BG_PLDO_OFF_CTRL_STEP_CNT_MASK (0xFFFF << GPC_SET_POINT_CTRL_SP_BG_PLDO_OFF_CTRL_STEP_CNT_SHIFT) #define GPC_SET_POINT_CTRL_SP_BG_PLDO_OFF_CTRL_STEP_CNT(n) (((n) << GPC_SET_POINT_CTRL_SP_BG_PLDO_OFF_CTRL_STEP_CNT_SHIFT) & GPC_SET_POINT_CTRL_SP_BG_PLDO_OFF_CTRL_STEP_CNT_MASK) #define GPC_SET_POINT_CTRL_SP_BG_PLDO_OFF_CTRL_CNT_MODE_SHIFT (28) /* Bits 28-30: Count mode */ @@ -861,7 +861,7 @@ #define GPC_SET_POINT_CTRL_SP_BG_PLDO_OFF_CTRL_DISABLE (1 << 31) /* Bit 31: Disable this step */ /* SP LDO pre control (SP_LDO_PRE_CTRL) */ -#define GPC_SET_POINT_CTRL_SP_LDO_PRE_CTRL_STEP_CNT_SHIFT (0) /* Bits 0-16: Step count, useage is depending on CNT_MODE */ +#define GPC_SET_POINT_CTRL_SP_LDO_PRE_CTRL_STEP_CNT_SHIFT (0) /* Bits 0-16: Step count, usage is depending on CNT_MODE */ #define GPC_SET_POINT_CTRL_SP_LDO_PRE_CTRL_STEP_CNT_MASK (0xFFFF << GPC_SET_POINT_CTRL_SP_LDO_PRE_CTRL_STEP_CNT_SHIFT) #define GPC_SET_POINT_CTRL_SP_LDO_PRE_CTRL_STEP_CNT(n) (((n) << GPC_SET_POINT_CTRL_SP_LDO_PRE_CTRL_STEP_CNT_SHIFT) & GPC_SET_POINT_CTRL_SP_LDO_PRE_CTRL_STEP_CNT_MASK) #define GPC_SET_POINT_CTRL_SP_LDO_PRE_CTRL_CNT_MODE_SHIFT (28) /* Bits 28-30: Count mode */ @@ -870,7 +870,7 @@ #define GPC_SET_POINT_CTRL_SP_LDO_PRE_CTRL_DISABLE (1 << 31) /* Bit 31: Disable this step */ /* SP DCDC down control (SP_DCDC_DOWN_CTRL) */ -#define GPC_SET_POINT_CTRL_SP_DCDC_DOWN_CTRL_STEP_CNT_SHIFT (0) /* Bits 0-16: Step count, useage is depending on CNT_MODE */ +#define GPC_SET_POINT_CTRL_SP_DCDC_DOWN_CTRL_STEP_CNT_SHIFT (0) /* Bits 0-16: Step count, usage is depending on CNT_MODE */ #define GPC_SET_POINT_CTRL_SP_DCDC_DOWN_CTRL_STEP_CNT_MASK (0xFFFF << GPC_SET_POINT_CTRL_SP_DCDC_DOWN_CTRL_STEP_CNT_SHIFT) #define GPC_SET_POINT_CTRL_SP_DCDC_DOWN_CTRL_STEP_CNT(n) (((n) << GPC_SET_POINT_CTRL_SP_DCDC_DOWN_CTRL_STEP_CNT_SHIFT) & GPC_SET_POINT_CTRL_SP_DCDC_DOWN_CTRL_STEP_CNT_MASK) #define GPC_SET_POINT_CTRL_SP_DCDC_DOWN_CTRL_CNT_MODE_SHIFT (28) /* Bits 28-30: Count mode */ @@ -879,7 +879,7 @@ #define GPC_SET_POINT_CTRL_SP_DCDC_DOWN_CTRL_DISABLE (1 << 31) /* Bit 31: Disable this step */ /* SP DCDC up control (SP_DCDC_UP_CTRL) */ -#define GPC_SET_POINT_CTRL_SP_DCDC_UP_CTRL_STEP_CNT_SHIFT (0) /* Bits 0-16: Step count, useage is depending on CNT_MODE */ +#define GPC_SET_POINT_CTRL_SP_DCDC_UP_CTRL_STEP_CNT_SHIFT (0) /* Bits 0-16: Step count, usage is depending on CNT_MODE */ #define GPC_SET_POINT_CTRL_SP_DCDC_UP_CTRL_STEP_CNT_MASK (0xFFFF << GPC_SET_POINT_CTRL_SP_DCDC_UP_CTRL_STEP_CNT_SHIFT) #define GPC_SET_POINT_CTRL_SP_DCDC_UP_CTRL_STEP_CNT(n) (((n) << GPC_SET_POINT_CTRL_SP_DCDC_UP_CTRL_STEP_CNT_SHIFT) & GPC_SET_POINT_CTRL_SP_DCDC_UP_CTRL_STEP_CNT_MASK) #define GPC_SET_POINT_CTRL_SP_DCDC_UP_CTRL_CNT_MODE_SHIFT (28) /* Bits 28-30: Count mode */ @@ -888,7 +888,7 @@ #define GPC_SET_POINT_CTRL_SP_DCDC_UP_CTRL_DISABLE (1 << 31) /* Bit 31: Disable this step */ /* SP LDO post control (SP_LDO_POST_CTRL) */ -#define GPC_SET_POINT_CTRL_SP_LDO_POST_CTRL_STEP_CNT_SHIFT (0) /* Bits 0-16: Step count, useage is depending on CNT_MODE */ +#define GPC_SET_POINT_CTRL_SP_LDO_POST_CTRL_STEP_CNT_SHIFT (0) /* Bits 0-16: Step count, usage is depending on CNT_MODE */ #define GPC_SET_POINT_CTRL_SP_LDO_POST_CTRL_STEP_CNT_MASK (0xFFFF << GPC_SET_POINT_CTRL_SP_LDO_POST_CTRL_STEP_CNT_SHIFT) #define GPC_SET_POINT_CTRL_SP_LDO_POST_CTRL_STEP_CNT(n) (((n) << GPC_SET_POINT_CTRL_SP_LDO_POST_CTRL_STEP_CNT_SHIFT) & GPC_SET_POINT_CTRL_SP_LDO_POST_CTRL_STEP_CNT_MASK) #define GPC_SET_POINT_CTRL_SP_LDO_POST_CTRL_CNT_MODE_SHIFT (28) /* Bits 28-30: Count mode */ @@ -897,7 +897,7 @@ #define GPC_SET_POINT_CTRL_SP_LDO_POST_CTRL_DISABLE (1 << 31) /* Bit 31: Disable this step */ /* SP bandgap and PLL_LDO on control (SP_BG_PLDO_ON_CTRL) */ -#define GPC_SET_POINT_CTRL_SP_BG_PLDO_ON_CTRL_STEP_CNT_SHIFT (0) /* Bits 0-16: Step count, useage is depending on CNT_MODE */ +#define GPC_SET_POINT_CTRL_SP_BG_PLDO_ON_CTRL_STEP_CNT_SHIFT (0) /* Bits 0-16: Step count, usage is depending on CNT_MODE */ #define GPC_SET_POINT_CTRL_SP_BG_PLDO_ON_CTRL_STEP_CNT_MASK (0xFFFF << GPC_SET_POINT_CTRL_SP_BG_PLDO_ON_CTRL_STEP_CNT_SHIFT) #define GPC_SET_POINT_CTRL_SP_BG_PLDO_ON_CTRL_STEP_CNT(n) (((n) << GPC_SET_POINT_CTRL_SP_BG_PLDO_ON_CTRL_STEP_CNT_SHIFT) & GPC_SET_POINT_CTRL_SP_BG_PLDO_ON_CTRL_STEP_CNT_MASK) #define GPC_SET_POINT_CTRL_SP_BG_PLDO_ON_CTRL_CNT_MODE_SHIFT (28) /* Bits 28-30: Count mode */ @@ -906,7 +906,7 @@ #define GPC_SET_POINT_CTRL_SP_BG_PLDO_ON_CTRL_DISABLE (1 << 31) /* Bit 31: Disable this step */ /* SP bias on control (SP_BIAS_ON_CTRL) */ -#define GPC_SET_POINT_CTRL_SP_BIAS_ON_CTRL_STEP_CNT_SHIFT (0) /* Bits 0-16: Step count, useage is depending on CNT_MODE */ +#define GPC_SET_POINT_CTRL_SP_BIAS_ON_CTRL_STEP_CNT_SHIFT (0) /* Bits 0-16: Step count, usage is depending on CNT_MODE */ #define GPC_SET_POINT_CTRL_SP_BIAS_ON_CTRL_STEP_CNT_MASK (0xFFFF << GPC_SET_POINT_CTRL_SP_BIAS_ON_CTRL_STEP_CNT_SHIFT) #define GPC_SET_POINT_CTRL_SP_BIAS_ON_CTRL_STEP_CNT(n) (((n) << GPC_SET_POINT_CTRL_SP_BIAS_ON_CTRL_STEP_CNT_SHIFT) & GPC_SET_POINT_CTRL_SP_BIAS_ON_CTRL_STEP_CNT_MASK) #define GPC_SET_POINT_CTRL_SP_BIAS_ON_CTRL_CNT_MODE_SHIFT (28) /* Bits 28-30: Count mode */ @@ -915,7 +915,7 @@ #define GPC_SET_POINT_CTRL_SP_BIAS_ON_CTRL_DISABLE (1 << 31) /* Bit 31: Disable this step */ /* SP power on control (SP_POWER_ON_CTRL) */ -#define GPC_SET_POINT_CTRL_SP_POWER_ON_CTRL_STEP_CNT_SHIFT (0) /* Bits 0-16: Step count, useage is depending on CNT_MODE */ +#define GPC_SET_POINT_CTRL_SP_POWER_ON_CTRL_STEP_CNT_SHIFT (0) /* Bits 0-16: Step count, usage is depending on CNT_MODE */ #define GPC_SET_POINT_CTRL_SP_POWER_ON_CTRL_STEP_CNT_MASK (0xFFFF << GPC_SET_POINT_CTRL_SP_POWER_ON_CTRL_STEP_CNT_SHIFT) #define GPC_SET_POINT_CTRL_SP_POWER_ON_CTRL_STEP_CNT(n) (((n) << GPC_SET_POINT_CTRL_SP_POWER_ON_CTRL_STEP_CNT_SHIFT) & GPC_SET_POINT_CTRL_SP_POWER_ON_CTRL_STEP_CNT_MASK) #define GPC_SET_POINT_CTRL_SP_POWER_ON_CTRL_CNT_MODE_SHIFT (28) /* Bits 28-30: Count mode */ @@ -924,7 +924,7 @@ #define GPC_SET_POINT_CTRL_SP_POWER_ON_CTRL_DISABLE (1 << 31) /* Bit 31: Disable this step */ /* SP reset late control (SP_RESET_LATE_CTRL) */ -#define GPC_SET_POINT_CTRL_SP_RESET_LATE_CTRL_STEP_CNT_SHIFT (0) /* Bits 0-16: Step count, useage is depending on CNT_MODE */ +#define GPC_SET_POINT_CTRL_SP_RESET_LATE_CTRL_STEP_CNT_SHIFT (0) /* Bits 0-16: Step count, usage is depending on CNT_MODE */ #define GPC_SET_POINT_CTRL_SP_RESET_LATE_CTRL_STEP_CNT_MASK (0xFFFF << GPC_SET_POINT_CTRL_SP_RESET_LATE_CTRL_STEP_CNT_SHIFT) #define GPC_SET_POINT_CTRL_SP_RESET_LATE_CTRL_STEP_CNT(n) (((n) << GPC_SET_POINT_CTRL_SP_RESET_LATE_CTRL_STEP_CNT_SHIFT) & GPC_SET_POINT_CTRL_SP_RESET_LATE_CTRL_STEP_CNT_MASK) #define GPC_SET_POINT_CTRL_SP_RESET_LATE_CTRL_CNT_MODE_SHIFT (28) /* Bits 28-30: Count mode */ @@ -933,7 +933,7 @@ #define GPC_SET_POINT_CTRL_SP_RESET_LATE_CTRL_DISABLE (1 << 31) /* Bit 31: Disable this step */ /* SP ISO off control (SP_ISO_OFF_CTRL) */ -#define GPC_SET_POINT_CTRL_SP_ISO_OFF_CTRL_STEP_CNT_SHIFT (0) /* Bits 0-16: Step count, useage is depending on CNT_MODE */ +#define GPC_SET_POINT_CTRL_SP_ISO_OFF_CTRL_STEP_CNT_SHIFT (0) /* Bits 0-16: Step count, usage is depending on CNT_MODE */ #define GPC_SET_POINT_CTRL_SP_ISO_OFF_CTRL_STEP_CNT_MASK (0xFFFF << GPC_SET_POINT_CTRL_SP_ISO_OFF_CTRL_STEP_CNT_SHIFT) #define GPC_SET_POINT_CTRL_SP_ISO_OFF_CTRL_STEP_CNT(n) (((n) << GPC_SET_POINT_CTRL_SP_ISO_OFF_CTRL_STEP_CNT_SHIFT) & GPC_SET_POINT_CTRL_SP_ISO_OFF_CTRL_STEP_CNT_MASK) #define GPC_SET_POINT_CTRL_SP_ISO_OFF_CTRL_CNT_MODE_SHIFT (28) /* Bits 28-30: Count mode */ @@ -942,7 +942,7 @@ #define GPC_SET_POINT_CTRL_SP_ISO_OFF_CTRL_DISABLE (1 << 31) /* Bit 31: Disable this step */ /* SP PLL on control (SP_PLL_ON_CTRL) */ -#define GPC_SET_POINT_CTRL_SP_PLL_ON_CTRL_STEP_CNT_SHIFT (0) /* Bits 0-16: Step count, useage is depending on CNT_MODE */ +#define GPC_SET_POINT_CTRL_SP_PLL_ON_CTRL_STEP_CNT_SHIFT (0) /* Bits 0-16: Step count, usage is depending on CNT_MODE */ #define GPC_SET_POINT_CTRL_SP_PLL_ON_CTRL_STEP_CNT_MASK (0xFFFF << GPC_SET_POINT_CTRL_SP_PLL_ON_CTRL_STEP_CNT_SHIFT) #define GPC_SET_POINT_CTRL_SP_PLL_ON_CTRL_STEP_CNT(n) (((n) << GPC_SET_POINT_CTRL_SP_PLL_ON_CTRL_STEP_CNT_SHIFT) & GPC_SET_POINT_CTRL_SP_PLL_ON_CTRL_STEP_CNT_MASK) #define GPC_SET_POINT_CTRL_SP_PLL_ON_CTRL_CNT_MODE_SHIFT (28) /* Bits 28-30: Count mode */ @@ -951,7 +951,7 @@ #define GPC_SET_POINT_CTRL_SP_PLL_ON_CTRL_DISABLE (1 << 31) /* Bit 31: Disable this step */ /* SP root up control (SP_ROOT_UP_CTRL) */ -#define GPC_SET_POINT_CTRL_SP_ROOT_UP_CTRL_STEP_CNT_SHIFT (0) /* Bits 0-16: Step count, useage is depending on CNT_MODE */ +#define GPC_SET_POINT_CTRL_SP_ROOT_UP_CTRL_STEP_CNT_SHIFT (0) /* Bits 0-16: Step count, usage is depending on CNT_MODE */ #define GPC_SET_POINT_CTRL_SP_ROOT_UP_CTRL_STEP_CNT_MASK (0xFFFF << GPC_SET_POINT_CTRL_SP_ROOT_UP_CTRL_STEP_CNT_SHIFT) #define GPC_SET_POINT_CTRL_SP_ROOT_UP_CTRL_STEP_CNT(n) (((n) << GPC_SET_POINT_CTRL_SP_ROOT_UP_CTRL_STEP_CNT_SHIFT) & GPC_SET_POINT_CTRL_SP_ROOT_UP_CTRL_STEP_CNT_MASK) #define GPC_SET_POINT_CTRL_SP_ROOT_UP_CTRL_CNT_MODE_SHIFT (28) /* Bits 28-30: Count mode */ @@ -960,7 +960,7 @@ #define GPC_SET_POINT_CTRL_SP_ROOT_UP_CTRL_DISABLE (1 << 31) /* Bit 31: Disable this step */ /* SP group up control (SP_GROUP_UP_CTRL) */ -#define GPC_SET_POINT_CTRL_SP_GROUP_UP_CTRL_STEP_CNT_SHIFT (0) /* Bits 0-16: Step count, useage is depending on CNT_MODE */ +#define GPC_SET_POINT_CTRL_SP_GROUP_UP_CTRL_STEP_CNT_SHIFT (0) /* Bits 0-16: Step count, usage is depending on CNT_MODE */ #define GPC_SET_POINT_CTRL_SP_GROUP_UP_CTRL_STEP_CNT_MASK (0xFFFF << GPC_SET_POINT_CTRL_SP_GROUP_UP_CTRL_STEP_CNT_SHIFT) #define GPC_SET_POINT_CTRL_SP_GROUP_UP_CTRL_STEP_CNT(n) (((n) << GPC_SET_POINT_CTRL_SP_GROUP_UP_CTRL_STEP_CNT_SHIFT) & GPC_SET_POINT_CTRL_SP_GROUP_UP_CTRL_STEP_CNT_MASK) #define GPC_SET_POINT_CTRL_SP_GROUP_UP_CTRL_CNT_MODE_SHIFT (28) /* Bits 28-30: Count mode */ @@ -969,7 +969,7 @@ #define GPC_SET_POINT_CTRL_SP_GROUP_UP_CTRL_DISABLE (1 << 31) /* Bit 31: Disable this step */ /* SP LPCG on control (SP_LPCG_ON_CTRL) */ -#define GPC_SET_POINT_CTRL_SP_LPCG_ON_CTRL_STEP_CNT_SHIFT (0) /* Bits 0-16: Step count, useage is depending on CNT_MODE */ +#define GPC_SET_POINT_CTRL_SP_LPCG_ON_CTRL_STEP_CNT_SHIFT (0) /* Bits 0-16: Step count, usage is depending on CNT_MODE */ #define GPC_SET_POINT_CTRL_SP_LPCG_ON_CTRL_STEP_CNT_MASK (0xFFFF << GPC_SET_POINT_CTRL_SP_LPCG_ON_CTRL_STEP_CNT_SHIFT) #define GPC_SET_POINT_CTRL_SP_LPCG_ON_CTRL_STEP_CNT(n) (((n) << GPC_SET_POINT_CTRL_SP_LPCG_ON_CTRL_STEP_CNT_SHIFT) & GPC_SET_POINT_CTRL_SP_LPCG_ON_CTRL_STEP_CNT_MASK) #define GPC_SET_POINT_CTRL_SP_LPCG_ON_CTRL_CNT_MODE_SHIFT (28) /* Bits 28-30: Count mode */ @@ -978,7 +978,7 @@ #define GPC_SET_POINT_CTRL_SP_LPCG_ON_CTRL_DISABLE (1 << 31) /* Bit 31: Disable this step */ /* SP SSAR restore control (SP_SSAR_RESTORE_CTRL) */ -#define GPC_SET_POINT_CTRL_SP_SSAR_RESTORE_CTRL_STEP_CNT_SHIFT (0) /* Bits 0-16: Step count, useage is depending on CNT_MODE */ +#define GPC_SET_POINT_CTRL_SP_SSAR_RESTORE_CTRL_STEP_CNT_SHIFT (0) /* Bits 0-16: Step count, usage is depending on CNT_MODE */ #define GPC_SET_POINT_CTRL_SP_SSAR_RESTORE_CTRL_STEP_CNT_MASK (0xFFFF << GPC_SET_POINT_CTRL_SP_SSAR_RESTORE_CTRL_STEP_CNT_SHIFT) #define GPC_SET_POINT_CTRL_SP_SSAR_RESTORE_CTRL_STEP_CNT(n) (((n) << GPC_SET_POINT_CTRL_SP_SSAR_RESTORE_CTRL_STEP_CNT_SHIFT) & GPC_SET_POINT_CTRL_SP_SSAR_RESTORE_CTRL_STEP_CNT_MASK) #define GPC_SET_POINT_CTRL_SP_SSAR_RESTORE_CTRL_CNT_MODE_SHIFT (28) /* Bits 28-30: Count mode */ @@ -1038,7 +1038,7 @@ #define GPC_STBY_CTRL_STBY_MISC_FORCE_CPU3_STBY (1 << 3) /* Bit 3: Force CPU3 requesting standby mode */ /* STBY lpcg_in control (STBY_LPCG_IN_CTRL) */ -#define GPC_STBY_CTRL_STBY_LPCG_IN_CTRL_STEP_CNT_SHIFT (0) /* Bits 0-16: Step count, useage is depending on CNT_MODE */ +#define GPC_STBY_CTRL_STBY_LPCG_IN_CTRL_STEP_CNT_SHIFT (0) /* Bits 0-16: Step count, usage is depending on CNT_MODE */ #define GPC_STBY_CTRL_STBY_LPCG_IN_CTRL_STEP_CNT_MASK (0xFFFF << GPC_STBY_CTRL_STBY_LPCG_IN_CTRL_STEP_CNT_SHIFT) #define GPC_STBY_CTRL_STBY_LPCG_IN_CTRL_STEP_CNT(n) (((n) << GPC_STBY_CTRL_STBY_LPCG_IN_CTRL_STEP_CNT_SHIFT) & GPC_STBY_CTRL_STBY_LPCG_IN_CTRL_STEP_CNT_MASK) #define GPC_STBY_CTRL_STBY_LPCG_IN_CTRL_CNT_MODE_SHIFT (28) /* Bits 28-30: Count mode */ @@ -1047,7 +1047,7 @@ #define GPC_STBY_CTRL_STBY_LPCG_IN_CTRL_DISABLE (1 << 31) /* Bit 31: Disable this step */ /* STBY pll_in control (STBY_PLL_IN_CTRL) */ -#define GPC_STBY_CTRL_STBY_PLL_IN_CTRL_STEP_CNT_SHIFT (0) /* Bits 0-16: Step count, useage is depending on CNT_MODE */ +#define GPC_STBY_CTRL_STBY_PLL_IN_CTRL_STEP_CNT_SHIFT (0) /* Bits 0-16: Step count, usage is depending on CNT_MODE */ #define GPC_STBY_CTRL_STBY_PLL_IN_CTRL_STEP_CNT_MASK (0xFFFF << GPC_STBY_CTRL_STBY_PLL_IN_CTRL_STEP_CNT_SHIFT) #define GPC_STBY_CTRL_STBY_PLL_IN_CTRL_STEP_CNT(n) (((n) << GPC_STBY_CTRL_STBY_PLL_IN_CTRL_STEP_CNT_SHIFT) & GPC_STBY_CTRL_STBY_PLL_IN_CTRL_STEP_CNT_MASK) #define GPC_STBY_CTRL_STBY_PLL_IN_CTRL_CNT_MODE_SHIFT (28) /* Bits 28-30: Count mode */ @@ -1056,7 +1056,7 @@ #define GPC_STBY_CTRL_STBY_PLL_IN_CTRL_DISABLE (1 << 31) /* Bit 31: Disable this step */ /* STBY bias_in control (STBY_BIAS_IN_CTRL) */ -#define GPC_STBY_CTRL_STBY_BIAS_IN_CTRL_STEP_CNT_SHIFT (0) /* Bits 0-16: Step count, useage is depending on CNT_MODE */ +#define GPC_STBY_CTRL_STBY_BIAS_IN_CTRL_STEP_CNT_SHIFT (0) /* Bits 0-16: Step count, usage is depending on CNT_MODE */ #define GPC_STBY_CTRL_STBY_BIAS_IN_CTRL_STEP_CNT_MASK (0xFFFF << GPC_STBY_CTRL_STBY_BIAS_IN_CTRL_STEP_CNT_SHIFT) #define GPC_STBY_CTRL_STBY_BIAS_IN_CTRL_STEP_CNT(n) (((n) << GPC_STBY_CTRL_STBY_BIAS_IN_CTRL_STEP_CNT_SHIFT) & GPC_STBY_CTRL_STBY_BIAS_IN_CTRL_STEP_CNT_MASK) #define GPC_STBY_CTRL_STBY_BIAS_IN_CTRL_CNT_MODE_SHIFT (28) /* Bits 28-30: Count mode */ @@ -1065,7 +1065,7 @@ #define GPC_STBY_CTRL_STBY_BIAS_IN_CTRL_DISABLE (1 << 31) /* Bit 31: Disable this step */ /* STBY pldo_in control (STBY_PLDO_IN_CTRL) */ -#define GPC_STBY_CTRL_STBY_PLDO_IN_CTRL_STEP_CNT_SHIFT (0) /* Bits 0-16: Step count, useage is depending on CNT_MODE */ +#define GPC_STBY_CTRL_STBY_PLDO_IN_CTRL_STEP_CNT_SHIFT (0) /* Bits 0-16: Step count, usage is depending on CNT_MODE */ #define GPC_STBY_CTRL_STBY_PLDO_IN_CTRL_STEP_CNT_MASK (0xFFFF << GPC_STBY_CTRL_STBY_PLDO_IN_CTRL_STEP_CNT_SHIFT) #define GPC_STBY_CTRL_STBY_PLDO_IN_CTRL_STEP_CNT(n) (((n) << GPC_STBY_CTRL_STBY_PLDO_IN_CTRL_STEP_CNT_SHIFT) & GPC_STBY_CTRL_STBY_PLDO_IN_CTRL_STEP_CNT_MASK) #define GPC_STBY_CTRL_STBY_PLDO_IN_CTRL_CNT_MODE_SHIFT (28) /* Bits 28-30: Count mode */ @@ -1074,7 +1074,7 @@ #define GPC_STBY_CTRL_STBY_PLDO_IN_CTRL_DISABLE (1 << 31) /* Bit 31: Disable this step */ /* STBY bandgap_in control (STBY_BANDGAP_IN_CTRL) */ -#define GPC_STBY_CTRL_STBY_BANDGAP_IN_CTRL_STEP_CNT_SHIFT (0) /* Bits 0-16: Step count, useage is depending on CNT_MODE */ +#define GPC_STBY_CTRL_STBY_BANDGAP_IN_CTRL_STEP_CNT_SHIFT (0) /* Bits 0-16: Step count, usage is depending on CNT_MODE */ #define GPC_STBY_CTRL_STBY_BANDGAP_IN_CTRL_STEP_CNT_MASK (0xFFFF << GPC_STBY_CTRL_STBY_BANDGAP_IN_CTRL_STEP_CNT_SHIFT) #define GPC_STBY_CTRL_STBY_BANDGAP_IN_CTRL_STEP_CNT(n) (((n) << GPC_STBY_CTRL_STBY_BANDGAP_IN_CTRL_STEP_CNT_SHIFT) & GPC_STBY_CTRL_STBY_BANDGAP_IN_CTRL_STEP_CNT_MASK) #define GPC_STBY_CTRL_STBY_BANDGAP_IN_CTRL_CNT_MODE_SHIFT (28) /* Bits 28-30: Count mode */ @@ -1083,7 +1083,7 @@ #define GPC_STBY_CTRL_STBY_BANDGAP_IN_CTRL_DISABLE (1 << 31) /* Bit 31: Disable this step */ /* STBY ldo_in control (STBY_LDO_IN_CTRL) */ -#define GPC_STBY_CTRL_STBY_LDO_IN_CTRL_STEP_CNT_SHIFT (0) /* Bits 0-16: Step count, useage is depending on CNT_MODE */ +#define GPC_STBY_CTRL_STBY_LDO_IN_CTRL_STEP_CNT_SHIFT (0) /* Bits 0-16: Step count, usage is depending on CNT_MODE */ #define GPC_STBY_CTRL_STBY_LDO_IN_CTRL_STEP_CNT_MASK (0xFFFF << GPC_STBY_CTRL_STBY_LDO_IN_CTRL_STEP_CNT_SHIFT) #define GPC_STBY_CTRL_STBY_LDO_IN_CTRL_STEP_CNT(n) (((n) << GPC_STBY_CTRL_STBY_LDO_IN_CTRL_STEP_CNT_SHIFT) & GPC_STBY_CTRL_STBY_LDO_IN_CTRL_STEP_CNT_MASK) #define GPC_STBY_CTRL_STBY_LDO_IN_CTRL_CNT_MODE_SHIFT (28) /* Bits 28-30: Count mode */ @@ -1092,7 +1092,7 @@ #define GPC_STBY_CTRL_STBY_LDO_IN_CTRL_DISABLE (1 << 31) /* Bit 31: Disable this step */ /* STBY dcdc_in control (STBY_DCDC_IN_CTRL) */ -#define GPC_STBY_CTRL_STBY_DCDC_IN_CTRL_STEP_CNT_SHIFT (0) /* Bits 0-16: Step count, useage is depending on CNT_MODE */ +#define GPC_STBY_CTRL_STBY_DCDC_IN_CTRL_STEP_CNT_SHIFT (0) /* Bits 0-16: Step count, usage is depending on CNT_MODE */ #define GPC_STBY_CTRL_STBY_DCDC_IN_CTRL_STEP_CNT_MASK (0xFFFF << GPC_STBY_CTRL_STBY_DCDC_IN_CTRL_STEP_CNT_SHIFT) #define GPC_STBY_CTRL_STBY_DCDC_IN_CTRL_STEP_CNT(n) (((n) << GPC_STBY_CTRL_STBY_DCDC_IN_CTRL_STEP_CNT_SHIFT) & GPC_STBY_CTRL_STBY_DCDC_IN_CTRL_STEP_CNT_MASK) #define GPC_STBY_CTRL_STBY_DCDC_IN_CTRL_CNT_MODE_SHIFT (28) /* Bits 28-30: Count mode */ @@ -1101,7 +1101,7 @@ #define GPC_STBY_CTRL_STBY_DCDC_IN_CTRL_DISABLE (1 << 31) /* Bit 31: Disable this step */ /* STBY PMIC in control (STBY_PMIC_IN_CTRL) */ -#define GPC_STBY_CTRL_STBY_PMIC_IN_CTRL_STEP_CNT_SHIFT (0) /* Bits 0-16: Step count, useage is depending on CNT_MODE */ +#define GPC_STBY_CTRL_STBY_PMIC_IN_CTRL_STEP_CNT_SHIFT (0) /* Bits 0-16: Step count, usage is depending on CNT_MODE */ #define GPC_STBY_CTRL_STBY_PMIC_IN_CTRL_STEP_CNT_MASK (0xFFFF << GPC_STBY_CTRL_STBY_PMIC_IN_CTRL_STEP_CNT_SHIFT) #define GPC_STBY_CTRL_STBY_PMIC_IN_CTRL_STEP_CNT(n) (((n) << GPC_STBY_CTRL_STBY_PMIC_IN_CTRL_STEP_CNT_SHIFT) & GPC_STBY_CTRL_STBY_PMIC_IN_CTRL_STEP_CNT_MASK) #define GPC_STBY_CTRL_STBY_PMIC_IN_CTRL_CNT_MODE_SHIFT (28) /* Bits 28-30: Count mode */ @@ -1110,7 +1110,7 @@ #define GPC_STBY_CTRL_STBY_PMIC_IN_CTRL_DISABLE (1 << 31) /* Bit 31: Disable this step */ /* STBY PMIC out control (STBY_PMIC_OUT_CTRL) */ -#define GPC_STBY_CTRL_STBY_PMIC_OUT_CTRL_STEP_CNT_SHIFT (0) /* Bits 0-16: Step count, useage is depending on CNT_MODE */ +#define GPC_STBY_CTRL_STBY_PMIC_OUT_CTRL_STEP_CNT_SHIFT (0) /* Bits 0-16: Step count, usage is depending on CNT_MODE */ #define GPC_STBY_CTRL_STBY_PMIC_OUT_CTRL_STEP_CNT_MASK (0xFFFF << GPC_STBY_CTRL_STBY_PMIC_OUT_CTRL_STEP_CNT_SHIFT) #define GPC_STBY_CTRL_STBY_PMIC_OUT_CTRL_STEP_CNT(n) (((n) << GPC_STBY_CTRL_STBY_PMIC_OUT_CTRL_STEP_CNT_SHIFT) & GPC_STBY_CTRL_STBY_PMIC_OUT_CTRL_STEP_CNT_MASK) #define GPC_STBY_CTRL_STBY_PMIC_OUT_CTRL_CNT_MODE_SHIFT (28) /* Bits 28-30: Count mode */ @@ -1119,7 +1119,7 @@ #define GPC_STBY_CTRL_STBY_PMIC_OUT_CTRL_DISABLE (1 << 31) /* Bit 31: Disable this step */ /* STBY DCDC out control (STBY_DCDC_OUT_CTRL) */ -#define GPC_STBY_CTRL_STBY_DCDC_OUT_CTRL_STEP_CNT_SHIFT (0) /* Bits 0-16: Step count, useage is depending on CNT_MODE */ +#define GPC_STBY_CTRL_STBY_DCDC_OUT_CTRL_STEP_CNT_SHIFT (0) /* Bits 0-16: Step count, usage is depending on CNT_MODE */ #define GPC_STBY_CTRL_STBY_DCDC_OUT_CTRL_STEP_CNT_MASK (0xFFFF << GPC_STBY_CTRL_STBY_DCDC_OUT_CTRL_STEP_CNT_SHIFT) #define GPC_STBY_CTRL_STBY_DCDC_OUT_CTRL_STEP_CNT(n) (((n) << GPC_STBY_CTRL_STBY_DCDC_OUT_CTRL_STEP_CNT_SHIFT) & GPC_STBY_CTRL_STBY_DCDC_OUT_CTRL_STEP_CNT_MASK) #define GPC_STBY_CTRL_STBY_DCDC_OUT_CTRL_CNT_MODE_SHIFT (28) /* Bits 28-30: Count mode */ @@ -1128,7 +1128,7 @@ #define GPC_STBY_CTRL_STBY_DCDC_OUT_CTRL_DISABLE (1 << 31) /* Bit 31: Disable this step */ /* STBY LDO out control (STBY_LDO_OUT_CTRL) */ -#define GPC_STBY_CTRL_STBY_LDO_OUT_CTRL_STEP_CNT_SHIFT (0) /* Bits 0-16: Step count, useage is depending on CNT_MODE */ +#define GPC_STBY_CTRL_STBY_LDO_OUT_CTRL_STEP_CNT_SHIFT (0) /* Bits 0-16: Step count, usage is depending on CNT_MODE */ #define GPC_STBY_CTRL_STBY_LDO_OUT_CTRL_STEP_CNT_MASK (0xFFFF << GPC_STBY_CTRL_STBY_LDO_OUT_CTRL_STEP_CNT_SHIFT) #define GPC_STBY_CTRL_STBY_LDO_OUT_CTRL_STEP_CNT(n) (((n) << GPC_STBY_CTRL_STBY_LDO_OUT_CTRL_STEP_CNT_SHIFT) & GPC_STBY_CTRL_STBY_LDO_OUT_CTRL_STEP_CNT_MASK) #define GPC_STBY_CTRL_STBY_LDO_OUT_CTRL_CNT_MODE_SHIFT (28) /* Bits 28-30: Count mode */ @@ -1137,7 +1137,7 @@ #define GPC_STBY_CTRL_STBY_LDO_OUT_CTRL_DISABLE (1 << 31) /* Bit 31: Disable this step */ /* STBY bandgap out control (STBY_BANDGAP_OUT_CTRL) */ -#define GPC_STBY_CTRL_STBY_BANDGAP_OUT_CTRL_STEP_CNT_SHIFT (0) /* Bits 0-16: Step count, useage is depending on CNT_MODE */ +#define GPC_STBY_CTRL_STBY_BANDGAP_OUT_CTRL_STEP_CNT_SHIFT (0) /* Bits 0-16: Step count, usage is depending on CNT_MODE */ #define GPC_STBY_CTRL_STBY_BANDGAP_OUT_CTRL_STEP_CNT_MASK (0xFFFF << GPC_STBY_CTRL_STBY_BANDGAP_OUT_CTRL_STEP_CNT_SHIFT) #define GPC_STBY_CTRL_STBY_BANDGAP_OUT_CTRL_STEP_CNT(n) (((n) << GPC_STBY_CTRL_STBY_BANDGAP_OUT_CTRL_STEP_CNT_SHIFT) & GPC_STBY_CTRL_STBY_BANDGAP_OUT_CTRL_STEP_CNT_MASK) #define GPC_STBY_CTRL_STBY_BANDGAP_OUT_CTRL_CNT_MODE_SHIFT (28) /* Bits 28-30: Count mode */ @@ -1146,7 +1146,7 @@ #define GPC_STBY_CTRL_STBY_BANDGAP_OUT_CTRL_DISABLE (1 << 31) /* Bit 31: Disable this step */ /* STBY pldo out control (STBY_PLDO_OUT_CTRL) */ -#define GPC_STBY_CTRL_STBY_PLDO_OUT_CTRL_STEP_CNT_SHIFT (0) /* Bits 0-16: Step count, useage is depending on CNT_MODE */ +#define GPC_STBY_CTRL_STBY_PLDO_OUT_CTRL_STEP_CNT_SHIFT (0) /* Bits 0-16: Step count, usage is depending on CNT_MODE */ #define GPC_STBY_CTRL_STBY_PLDO_OUT_CTRL_STEP_CNT_MASK (0xFFFF << GPC_STBY_CTRL_STBY_PLDO_OUT_CTRL_STEP_CNT_SHIFT) #define GPC_STBY_CTRL_STBY_PLDO_OUT_CTRL_STEP_CNT(n) (((n) << GPC_STBY_CTRL_STBY_PLDO_OUT_CTRL_STEP_CNT_SHIFT) & GPC_STBY_CTRL_STBY_PLDO_OUT_CTRL_STEP_CNT_MASK) #define GPC_STBY_CTRL_STBY_PLDO_OUT_CTRL_CNT_MODE_SHIFT (28) /* Bits 28-30: Count mode */ @@ -1155,7 +1155,7 @@ #define GPC_STBY_CTRL_STBY_PLDO_OUT_CTRL_DISABLE (1 << 31) /* Bit 31: Disable this step */ /* STBY bias out control (STBY_BIAS_OUT_CTRL) */ -#define GPC_STBY_CTRL_STBY_BIAS_OUT_CTRL_STEP_CNT_SHIFT (0) /* Bits 0-16: Step count, useage is depending on CNT_MODE */ +#define GPC_STBY_CTRL_STBY_BIAS_OUT_CTRL_STEP_CNT_SHIFT (0) /* Bits 0-16: Step count, usage is depending on CNT_MODE */ #define GPC_STBY_CTRL_STBY_BIAS_OUT_CTRL_STEP_CNT_MASK (0xFFFF << GPC_STBY_CTRL_STBY_BIAS_OUT_CTRL_STEP_CNT_SHIFT) #define GPC_STBY_CTRL_STBY_BIAS_OUT_CTRL_STEP_CNT(n) (((n) << GPC_STBY_CTRL_STBY_BIAS_OUT_CTRL_STEP_CNT_SHIFT) & GPC_STBY_CTRL_STBY_BIAS_OUT_CTRL_STEP_CNT_MASK) #define GPC_STBY_CTRL_STBY_BIAS_OUT_CTRL_CNT_MODE_SHIFT (28) /* Bits 28-30: Count mode */ @@ -1164,7 +1164,7 @@ #define GPC_STBY_CTRL_STBY_BIAS_OUT_CTRL_DISABLE (1 << 31) /* Bit 31: Disable this step */ /* STBY PLL out control (STBY_PLL_OUT_CTRL) */ -#define GPC_STBY_CTRL_STBY_PLL_OUT_CTRL_STEP_CNT_SHIFT (0) /* Bits 0-16: Step count, useage is depending on CNT_MODE */ +#define GPC_STBY_CTRL_STBY_PLL_OUT_CTRL_STEP_CNT_SHIFT (0) /* Bits 0-16: Step count, usage is depending on CNT_MODE */ #define GPC_STBY_CTRL_STBY_PLL_OUT_CTRL_STEP_CNT_MASK (0xFFFF << GPC_STBY_CTRL_STBY_PLL_OUT_CTRL_STEP_CNT_SHIFT) #define GPC_STBY_CTRL_STBY_PLL_OUT_CTRL_STEP_CNT(n) (((n) << GPC_STBY_CTRL_STBY_PLL_OUT_CTRL_STEP_CNT_SHIFT) & GPC_STBY_CTRL_STBY_PLL_OUT_CTRL_STEP_CNT_MASK) #define GPC_STBY_CTRL_STBY_PLL_OUT_CTRL_CNT_MODE_SHIFT (28) /* Bits 28-30: Count mode */ @@ -1173,7 +1173,7 @@ #define GPC_STBY_CTRL_STBY_PLL_OUT_CTRL_DISABLE (1 << 31) /* Bit 31: Disable this step */ /* STBY LPCG out control (STBY_LPCG_OUT_CTRL) */ -#define GPC_STBY_CTRL_STBY_LPCG_OUT_CTRL_STEP_CNT_SHIFT (0) /* Bits 0-16: Step count, useage is depending on CNT_MODE */ +#define GPC_STBY_CTRL_STBY_LPCG_OUT_CTRL_STEP_CNT_SHIFT (0) /* Bits 0-16: Step count, usage is depending on CNT_MODE */ #define GPC_STBY_CTRL_STBY_LPCG_OUT_CTRL_STEP_CNT_MASK (0xFFFF << GPC_STBY_CTRL_STBY_LPCG_OUT_CTRL_STEP_CNT_SHIFT) #define GPC_STBY_CTRL_STBY_LPCG_OUT_CTRL_STEP_CNT(n) (((n) << GPC_STBY_CTRL_STBY_LPCG_OUT_CTRL_STEP_CNT_SHIFT) & GPC_STBY_CTRL_STBY_LPCG_OUT_CTRL_STEP_CNT_MASK) #define GPC_STBY_CTRL_STBY_LPCG_OUT_CTRL_CNT_MODE_SHIFT (28) /* Bits 28-30: Count mode */ diff --git a/arch/arm/src/imxrt/hardware/rt117x/imxrt117x_iomuxc.h b/arch/arm/src/imxrt/hardware/rt117x/imxrt117x_iomuxc.h index 799d030a57..64c3f270ae 100644 --- a/arch/arm/src/imxrt/hardware/rt117x/imxrt117x_iomuxc.h +++ b/arch/arm/src/imxrt/hardware/rt117x/imxrt117x_iomuxc.h @@ -3373,7 +3373,7 @@ # define GPR_GPR59_MIPI_CSI_RX_RCAL_15PL (0x02 << GPR_GPR59_MIPI_CSI_RX_RCAL_SHIFT) /* 15% lower than mid range */ # define GPR_GPR59_MIPI_CSI_RX_RCAL_25PL (0x03 << GPR_GPR59_MIPI_CSI_RX_RCAL_SHIFT) /* 25% lower than mid range */ -#define GPR_GPR59_MIPI_CSI_RXCDRP_SHIFT (8) /* Bits 8-9: Programming bits that adjust the treshold voltage of LP-CD (MIPI_CSI_RXCDRP) */ +#define GPR_GPR59_MIPI_CSI_RXCDRP_SHIFT (8) /* Bits 8-9: Programming bits that adjust the threshold voltage of LP-CD (MIPI_CSI_RXCDRP) */ #define GPR_GPR59_MIPI_CSI_RXCDRP_MASK (0x03 << GPR_GPR59_MIPI_CSI_RXCDRP_SHIFT) # define GPR_GPR59_MIPI_CSI_RXCDRP_344MV (0x00 << GPR_GPR59_MIPI_CSI_RXCDRP_SHIFT) /* 344 mV */ # define GPR_GPR59_MIPI_CSI_RXCDRP_325MV (0x01 << GPR_GPR59_MIPI_CSI_RXCDRP_SHIFT) /* 325 mV */ @@ -3382,10 +3382,10 @@ #define GPR_GPR59_MIPI_CSI_RXLPRP_SHIFT (10) /* Bits 10-11: Programming bits that adjust the threshold voltage of LP-RX (MIPI_CSI_RXLPRP) */ #define GPR_GPR59_MIPI_CSI_RXLPRP_MASK (0x03 << GPR_GPR59_MIPI_CSI_RXLPRP_SHIFT) -# define GPR_GPR59_MIPI_CSI_RXLPRP_B00 (0x00 << GPR_GPR59_MIPI_CSI_RXLPRP_SHIFT) /* High treshold: 782 mV, low treshold: 730 mV */ -# define GPR_GPR59_MIPI_CSI_RXLPRP_B01 (0x01 << GPR_GPR59_MIPI_CSI_RXLPRP_SHIFT) /* High treshold: 745 mV, low treshold: 692 mV */ -# define GPR_GPR59_MIPI_CSI_RXLPRP_B10 (0x02 << GPR_GPR59_MIPI_CSI_RXLPRP_SHIFT) /* High treshold: 708 mV, low treshold: 655 mV */ -# define GPR_GPR59_MIPI_CSI_RXLPRP_B11 (0x03 << GPR_GPR59_MIPI_CSI_RXLPRP_SHIFT) /* High treshold: invalid, low treshold: invalid */ +# define GPR_GPR59_MIPI_CSI_RXLPRP_B00 (0x00 << GPR_GPR59_MIPI_CSI_RXLPRP_SHIFT) /* High threshold: 782 mV, low threshold: 730 mV */ +# define GPR_GPR59_MIPI_CSI_RXLPRP_B01 (0x01 << GPR_GPR59_MIPI_CSI_RXLPRP_SHIFT) /* High threshold: 745 mV, low threshold: 692 mV */ +# define GPR_GPR59_MIPI_CSI_RXLPRP_B10 (0x02 << GPR_GPR59_MIPI_CSI_RXLPRP_SHIFT) /* High threshold: 708 mV, low threshold: 655 mV */ +# define GPR_GPR59_MIPI_CSI_RXLPRP_B11 (0x03 << GPR_GPR59_MIPI_CSI_RXLPRP_SHIFT) /* High threshold: invalid, low threshold: invalid */ #define GPR_GPR59_MIPI_CSI_S_PRG_RXHS_SETTLE_SHIFT (12) /* Bits 12-17: Bits used to program T_HS_SETTLE (MIPI_CSI_S_PRG_RXHS_SETTLE) */ #define GPR_GPR59_MIPI_CSI_S_PRG_RXHS_SETTLE_MASK (0x3f << GPR_GPR59_MIPI_CSI_S_PRG_RXHS_SETTLE_SHIFT) diff --git a/arch/arm/src/imxrt/hardware/rt117x/imxrt117x_ocotp.h b/arch/arm/src/imxrt/hardware/rt117x/imxrt117x_ocotp.h index fdb9419b61..9b1d197399 100644 --- a/arch/arm/src/imxrt/hardware/rt117x/imxrt117x_ocotp.h +++ b/arch/arm/src/imxrt/hardware/rt117x/imxrt117x_ocotp.h @@ -165,8 +165,8 @@ #define OCOTP_OUT_STATUS_FLAGSTATE_SHIFT (15) /* Bits 15-19: Flag state */ #define OCOTP_OUT_STATUS_FLAGSTATE_MASK (0xF << OCOTP_OUT_STATUS_FLAGSTATE_SHIFT) #define OCOTP_OUT_STATUS_FLAGSTATE(n) (((n) << OCOTP_OUT_STATUS_FLAGSTATE_SHIFT) & OCOTP_OUT_STATUS_FLAGSTATE_MASK) -#define OCOTP_OUT_STATUS_SEC_RELOAD (1 << 19) /* Bit 19: Indicates single error correction occured on reload */ -#define OCOTP_OUT_STATUS_DED_RELOAD (1 << 20) /* Bit 20: Indicates double error detection occured on reload */ +#define OCOTP_OUT_STATUS_SEC_RELOAD (1 << 19) /* Bit 19: Indicates single error correction occurred on reload */ +#define OCOTP_OUT_STATUS_DED_RELOAD (1 << 20) /* Bit 20: Indicates double error detection occurred on reload */ #define OCOTP_OUT_STATUS_CALIBRATED (1 << 21) /* Bit 21: Calibrated status */ #define OCOTP_OUT_STATUS_READ_DONE_INTR (1 << 22) /* Bit 22: Read fuse done */ #define OCOTP_OUT_STATUS_READ_ERROR_INTR (1 << 23) /* Bit 23: Fuse read error */ @@ -185,8 +185,8 @@ #define OCOTP_OUT_STATUS_SET_FLAGSTATE_SHIFT (15) /* Bits 15-19: Flag state */ #define OCOTP_OUT_STATUS_SET_FLAGSTATE_MASK (0xF << OCOTP_OUT_STATUS_SET_FLAGSTATE_SHIFT) #define OCOTP_OUT_STATUS_SET_FLAGSTATE(n) (((n) << OCOTP_OUT_STATUS_SET_FLAGSTATE_SHIFT) & OCOTP_OUT_STATUS_SET_FLAGSTATE_MASK) -#define OCOTP_OUT_STATUS_SET_SEC_RELOAD (1 << 19) /* Bit 19: Indicates single error correction occured on reload */ -#define OCOTP_OUT_STATUS_SET_DED_RELOAD (1 << 20) /* Bit 20: Indicates double error detection occured on reload */ +#define OCOTP_OUT_STATUS_SET_SEC_RELOAD (1 << 19) /* Bit 19: Indicates single error correction occurred on reload */ +#define OCOTP_OUT_STATUS_SET_DED_RELOAD (1 << 20) /* Bit 20: Indicates double error detection occurred on reload */ #define OCOTP_OUT_STATUS_SET_CALIBRATED (1 << 21) /* Bit 21: Calibrated status */ #define OCOTP_OUT_STATUS_SET_READ_DONE_INTR (1 << 22) /* Bit 22: Read fuse done */ #define OCOTP_OUT_STATUS_SET_READ_ERROR_INTR (1 << 23) /* Bit 23: Fuse read error */ @@ -205,8 +205,8 @@ #define OCOTP_OUT_STATUS_CLR_FLAGSTATE_SHIFT (15) /* Bits 15-19: Flag state */ #define OCOTP_OUT_STATUS_CLR_FLAGSTATE_MASK (0xF << OCOTP_OUT_STATUS_CLR_FLAGSTATE_SHIFT) #define OCOTP_OUT_STATUS_CLR_FLAGSTATE(n) (((n) << OCOTP_OUT_STATUS_CLR_FLAGSTATE_SHIFT) & OCOTP_OUT_STATUS_CLR_FLAGSTATE_MASK) -#define OCOTP_OUT_STATUS_CLR_SEC_RELOAD (1 << 19) /* Bit 19: Indicates single error correction occured on reload */ -#define OCOTP_OUT_STATUS_CLR_DED_RELOAD (1 << 20) /* Bit 20: Indicates double error detection occured on reload */ +#define OCOTP_OUT_STATUS_CLR_SEC_RELOAD (1 << 19) /* Bit 19: Indicates single error correction occurred on reload */ +#define OCOTP_OUT_STATUS_CLR_DED_RELOAD (1 << 20) /* Bit 20: Indicates double error detection occurred on reload */ #define OCOTP_OUT_STATUS_CLR_CALIBRATED (1 << 21) /* Bit 21: Calibrated status */ #define OCOTP_OUT_STATUS_CLR_READ_DONE_INTR (1 << 22) /* Bit 22: Read fuse done */ #define OCOTP_OUT_STATUS_CLR_READ_ERROR_INTR (1 << 23) /* Bit 23: Fuse read error */ @@ -225,8 +225,8 @@ #define OCOTP_OUT_STATUS_TOG_FLAGSTATE_SHIFT (15) /* Bits 15-19: Flag state */ #define OCOTP_OUT_STATUS_TOG_FLAGSTATE_MASK (0xF << OCOTP_OUT_STATUS_TOG_FLAGSTATE_SHIFT) #define OCOTP_OUT_STATUS_TOG_FLAGSTATE(n) (((n) << OCOTP_OUT_STATUS_TOG_FLAGSTATE_SHIFT) & OCOTP_OUT_STATUS_TOG_FLAGSTATE_MASK) -#define OCOTP_OUT_STATUS_TOG_SEC_RELOAD (1 << 19) /* Bit 19: Indicates single error correction occured on reload */ -#define OCOTP_OUT_STATUS_TOG_DED_RELOAD (1 << 20) /* Bit 20: Indicates double error detection occured on reload */ +#define OCOTP_OUT_STATUS_TOG_SEC_RELOAD (1 << 19) /* Bit 19: Indicates single error correction occurred on reload */ +#define OCOTP_OUT_STATUS_TOG_DED_RELOAD (1 << 20) /* Bit 20: Indicates double error detection occurred on reload */ #define OCOTP_OUT_STATUS_TOG_CALIBRATED (1 << 21) /* Bit 21: Calibrated status */ #define OCOTP_OUT_STATUS_TOG_READ_DONE_INTR (1 << 22) /* Bit 22: Read fuse done */ #define OCOTP_OUT_STATUS_TOG_READ_ERROR_INTR (1 << 23) /* Bit 23: Fuse read error */ diff --git a/arch/arm/src/imxrt/imxrt_adc_ver1.c b/arch/arm/src/imxrt/imxrt_adc_ver1.c index 9f4b16868c..4174409516 100644 --- a/arch/arm/src/imxrt/imxrt_adc_ver1.c +++ b/arch/arm/src/imxrt/imxrt_adc_ver1.c @@ -225,7 +225,7 @@ static void adc_modifyreg(struct imxrt_dev_s *priv, uint32_t offset, * Name: adc_reset_etc * * Description: - * Setup registers and channels/triggers for external trigering of ADC + * Setup registers and channels/triggers for external triggering of ADC * conversion. This functions also takes care of connecting XBARs. * ****************************************************************************/ @@ -525,7 +525,7 @@ static int adc_setup(struct adc_dev_s *dev) if (priv->trig_src != -1) { - /* Atach and enable ADCETC interrupt */ + /* Attach and enable ADCETC interrupt */ ret = irq_attach(priv->irq_etc, adc_interrupt, dev); if (ret < 0) diff --git a/arch/arm/src/imxrt/imxrt_clockconfig_ver2.c b/arch/arm/src/imxrt/imxrt_clockconfig_ver2.c index 31c82f1e43..e1fea76fa2 100644 --- a/arch/arm/src/imxrt/imxrt_clockconfig_ver2.c +++ b/arch/arm/src/imxrt/imxrt_clockconfig_ver2.c @@ -434,7 +434,7 @@ static void imxrt_pll2_pfd(void) putreg32(reg, IMXRT_ANADIG_PLL_SYS_PLL2_UPDATE); - /* Wait for stablizing */ + /* Wait for stabilizing */ reg = 0; @@ -604,7 +604,7 @@ static void imxrt_pll3_pfd(void) putreg32(reg, IMXRT_ANADIG_PLL_SYS_PLL3_UPDATE); - /* Wait for stablizing */ + /* Wait for stabilizing */ reg = 0; diff --git a/arch/arm/src/imxrt/imxrt_edma.h b/arch/arm/src/imxrt/imxrt_edma.h index aeb3df02fd..fba3530b78 100644 --- a/arch/arm/src/imxrt/imxrt_edma.h +++ b/arch/arm/src/imxrt/imxrt_edma.h @@ -80,7 +80,7 @@ * i mxrt_dmach_stop(handle); * * 7. The callback will be received when the DMA completes (or an error - * occurs). After that, you may free the DMA channel, or re-use it on + * occurs). After that, you may free the DMA channel, or reuse it on * subsequent DMAs. * * imxrt_dmach_free(handle); diff --git a/arch/arm/src/imxrt/imxrt_ehci.c b/arch/arm/src/imxrt/imxrt_ehci.c index 7663b57416..f7d881541c 100644 --- a/arch/arm/src/imxrt/imxrt_ehci.c +++ b/arch/arm/src/imxrt/imxrt_ehci.c @@ -1739,7 +1739,7 @@ static struct imxrt_qh_s *imxrt_qh_create(struct imxrt_rhport_s *rhport, * FIELD DESCRIPTION VALUE/SOURCE * -------- ------------------------------- -------------------- * DEVADDR Device address Endpoint structure - * I Inactivate on Next Transaction 0 + * I Deactivate on Next Transaction 0 * ENDPT Endpoint number Endpoint structure * EPS Endpoint speed Endpoint structure * DTC Data toggle control 1 @@ -3999,7 +3999,7 @@ static int imxrt_epalloc(struct usbhost_driver_s *drvr, * Input Parameters: * drvr - The USB host driver instance obtained as a parameter from the * call to the class create() method. - * ep - The endpint to be freed. + * ep - The endpoint to be freed. * * Returned Value: * On success, zero (OK) is returned. On a failure, a negated errno value diff --git a/arch/arm/src/imxrt/imxrt_enc.c b/arch/arm/src/imxrt/imxrt_enc.c index e34968fcad..a78bb70116 100644 --- a/arch/arm/src/imxrt/imxrt_enc.c +++ b/arch/arm/src/imxrt/imxrt_enc.c @@ -286,8 +286,8 @@ struct imxrt_qeconfig_s struct imxrt_qedata_s { - int32_t index_pos; /* Last position of index occurance */ - uint32_t index_cnt; /* Number of index occurance */ + int32_t index_pos; /* Last position of index occurrence */ + uint32_t index_cnt; /* Number of index occurrence */ }; /* ENC Device Private Data */ diff --git a/arch/arm/src/imxrt/imxrt_enet.c b/arch/arm/src/imxrt/imxrt_enet.c index 95617302e2..72efc465b6 100644 --- a/arch/arm/src/imxrt/imxrt_enet.c +++ b/arch/arm/src/imxrt/imxrt_enet.c @@ -2263,7 +2263,7 @@ static int imxrt_determine_phy(struct imxrt_driver_s *priv) * * Input Parameters: * priv - Reference to the private ENET driver state structure - * name - a pointer to comapre to. + * name - a pointer to compare to. * * Returned Value: * 1 on match, a 0 on no match. @@ -2286,7 +2286,7 @@ static int imxrt_phy_is(struct imxrt_driver_s *priv, const char *name) * phydata - last read phy data - may be ignored if there is no * status register defined by the current PHY. * mask - A value to and with phydata if a status register is - * defined. Or the value retunred if no status register is + * defined. Or the value returned if no status register is * defined. * * Returned Value: @@ -3088,7 +3088,7 @@ int imxrt_netinitialize(int intf) memset(priv, 0, sizeof(struct imxrt_driver_s)); - priv->base = IMXRT_ENETN_BASE; /* Assigne base address */ + priv->base = IMXRT_ENETN_BASE; /* Assign base address */ priv->dev.d_ifup = imxrt_ifup; /* I/F up (new IP address) callback */ priv->dev.d_ifdown = imxrt_ifdown; /* I/F down callback */ diff --git a/arch/arm/src/imxrt/imxrt_flexcan.c b/arch/arm/src/imxrt/imxrt_flexcan.c index 530e58b63e..ae794b5cb9 100644 --- a/arch/arm/src/imxrt/imxrt_flexcan.c +++ b/arch/arm/src/imxrt/imxrt_flexcan.c @@ -713,9 +713,9 @@ static int imxrt_transmit(struct imxrt_driver_s *priv) mb->cs = cs; /* Go. */ /* Errata ER005829 step 8: Write twice into the first TX MB - * Errata mentions writng 0x8 value, but this one couses + * Errata mentions writing 0x8 value, but this one causes * the ESR2_LPTM register to choose the reserved MB for - * transmiting the package, hence we write 0x3 + * transmitting the package, hence we write 0x3. */ struct mb_s *buffer = flexcan_get_mb(priv, RXMBCOUNT); @@ -1750,9 +1750,9 @@ static int imxrt_initialize(struct imxrt_driver_s *priv) } /* Errata ER005829 step 7: Reserve first TX MB - * Errata mentions writng 0x8 value, but this one couses + * Errata mentions writing 0x8 value, but this one causes * the ESR2_LPTM register to choose the reserved MB for - * transmiting the package, hence we write 0x3 + * transmitting the package, hence we write 0x3. */ struct mb_s *buffer = flexcan_get_mb(priv, RXMBCOUNT); diff --git a/arch/arm/src/imxrt/imxrt_flexspi.c b/arch/arm/src/imxrt/imxrt_flexspi.c index 864260d5c9..6af3c963ce 100644 --- a/arch/arm/src/imxrt/imxrt_flexspi.c +++ b/arch/arm/src/imxrt/imxrt_flexspi.c @@ -297,7 +297,7 @@ struct flexspi_config_s bool enable_ahb_bufferable; /* Enable/disable AHB bufferable write access support, when enabled, * FLEXSPI return before waiting for command execution finished */ - bool enable_ahb_cachable; /* Enable AHB bus cachable read access support */ + bool enable_ahb_cachable; /* Enable AHB bus cacheable read access support */ } ahb_config; }; @@ -1033,7 +1033,7 @@ static int imxrt_flexspi_read_blocking(struct flexspi_type_s *base, size = 0; } - /* Pop out a watermark level datas from IP RX FIFO */ + /* Pop out a watermark level data from IP RX FIFO */ base->INTR |= (uint32_t)FLEXSPI_IP_RX_FIFO_WATERMARK_AVAILABLE_FLAG; } diff --git a/arch/arm/src/imxrt/imxrt_iomuxc_ver1.c b/arch/arm/src/imxrt/imxrt_iomuxc_ver1.c index e47329f50c..d5e41f2c99 100644 --- a/arch/arm/src/imxrt/imxrt_iomuxc_ver1.c +++ b/arch/arm/src/imxrt/imxrt_iomuxc_ver1.c @@ -350,12 +350,12 @@ int imxrt_iomux_configure(uintptr_t padctl, iomux_pinset_t ioset) value = (ioset & IOMUX_DRIVE_MASK) >> IOMUX_DRIVE_SHIFT; regval |= PADCTL_DSE(value); - /* Select spped */ + /* Select speed */ value = (ioset & IOMUX_SPEED_MASK) >> IOMUX_SPEED_SHIFT; regval |= PADCTL_SPEED(value); - /* Select CMOS output or Open Drain outpout */ + /* Select CMOS output or Open Drain output */ if ((ioset & IOMUX_OPENDRAIN) != 0) { diff --git a/arch/arm/src/imxrt/imxrt_lowputc.c b/arch/arm/src/imxrt/imxrt_lowputc.c index fe1214cd99..b071f4b332 100644 --- a/arch/arm/src/imxrt/imxrt_lowputc.c +++ b/arch/arm/src/imxrt/imxrt_lowputc.c @@ -783,8 +783,8 @@ void imxrt_lowputc(int ch) { } - /* If the character to output is a newline, then pre-pend a carriage - * return + /* If the character to output is a newline, then prepend a carriage + * return. */ if (ch == '\n') diff --git a/arch/arm/src/imxrt/imxrt_lpi2c.c b/arch/arm/src/imxrt/imxrt_lpi2c.c index 0535470fb3..da1ccffe52 100644 --- a/arch/arm/src/imxrt/imxrt_lpi2c.c +++ b/arch/arm/src/imxrt/imxrt_lpi2c.c @@ -2098,7 +2098,7 @@ static int imxrt_lpi2c_dma_transfer(struct imxrt_lpi2c_priv_s *priv) LPI2C_MSR_ALF | LPI2C_MSR_FEF); - /* Enable the Iterrupts */ + /* Enable the Interrupts */ imxrt_lpi2c_putreg(priv, IMXRT_LPI2C_MIER_OFFSET, LPI2C_MIER_NDIE | LPI2C_MIER_ALIE | @@ -2390,7 +2390,7 @@ static int imxrt_lpi2c_reset(struct i2c_master_s *dev) out: - /* Release the port for re-use by other clients */ + /* Release the port for reuse by other clients */ nxmutex_unlock(&priv->lock); return ret; diff --git a/arch/arm/src/imxrt/imxrt_serial.c b/arch/arm/src/imxrt/imxrt_serial.c index e430cb9cd9..e92e3acd9a 100644 --- a/arch/arm/src/imxrt/imxrt_serial.c +++ b/arch/arm/src/imxrt/imxrt_serial.c @@ -763,7 +763,7 @@ struct imxrt_uart_s #ifdef SERIAL_HAVE_TXDMA const unsigned int dma_txreqsrc; /* DMAMUX source of TX DMA request */ - DMACH_HANDLE txdma; /* currently-open trasnmit DMA stream */ + DMACH_HANDLE txdma; /* currently-open transmit DMA stream */ #endif /* RX DMA state */ @@ -2133,7 +2133,7 @@ static int imxrt_dma_setup(struct uart_dev_s *dev) modifyreg32(priv->uartbase + IMXRT_LPUART_BAUD_OFFSET, 0, LPUART_BAUD_RDMAE); - /* Enable itnerrupt on Idel and erros */ + /* Enable interrupt on Idle and errors */ modifyreg32(priv->uartbase + IMXRT_LPUART_CTRL_OFFSET, 0, LPUART_CTRL_PEIE | @@ -3591,7 +3591,7 @@ static int up_pm_prepare(struct pm_callback_s *cb, int domain, * * Description: * Performs the low level UART initialization early in debug so that the - * serial console will be available during bootup. This must be called + * serial console will be available during boot up. This must be called * before arm_serialinit. * ****************************************************************************/ diff --git a/arch/arm/src/imxrt/imxrt_serial.h b/arch/arm/src/imxrt/imxrt_serial.h index 95806a036f..c977b84848 100644 --- a/arch/arm/src/imxrt/imxrt_serial.h +++ b/arch/arm/src/imxrt/imxrt_serial.h @@ -308,7 +308,7 @@ extern "C" * * Description: * Performs the low level UART initialization early in debug so that the - * serial console will be available during bootup. This must be called + * serial console will be available during boot up. This must be called * before arm_serialinit. * ****************************************************************************/ diff --git a/arch/arm/src/imxrt/imxrt_start.h b/arch/arm/src/imxrt/imxrt_start.h index 547a7c5a61..cb70640067 100644 --- a/arch/arm/src/imxrt/imxrt_start.h +++ b/arch/arm/src/imxrt/imxrt_start.h @@ -119,7 +119,7 @@ void imxrt_ocram_initialize(void); * Name: imxrt_flexram_initialize * * Description: - * Sets FlexRAM paritioning + * Sets FlexRAM partitioning * ****************************************************************************/ diff --git a/arch/arm/src/imxrt/imxrt_tickless.c b/arch/arm/src/imxrt/imxrt_tickless.c index 2e68a779a3..038bf29dbf 100644 --- a/arch/arm/src/imxrt/imxrt_tickless.c +++ b/arch/arm/src/imxrt/imxrt_tickless.c @@ -43,7 +43,7 @@ * * NOTE * Only alarm option selected by CONFIG_SCHED_TICKLESS_ALARM is currently - * suported for iMXRT. + * supported for iMXRT. * ****************************************************************************/ @@ -98,7 +98,7 @@ * PRECLK_CLOCK_ROOT = IPG_CLOCK_ROOT / IMXRT_PERCLK_PODF_DIVIDER * where IPG_CLOCK_ROOT = 150 MHz and IMXRT_PERCLK_PODF_DIVIDER = 9 * - * Those clocks are set in imxrt_clockconfig, but makros are defined in + * Those clocks are set in imxrt_clockconfig, but macros are defined in * board level section (file board.h) so clock settings may actually vary * when using different boards. * @@ -373,7 +373,7 @@ void up_timer_initialize(void) regval |= GPT_CR_ENMOD; putreg32(regval, g_tickless.base + IMXRT_GPT_CR_OFFSET); - /* Eneable the timer */ + /* Enable the timer */ regval = getreg32(g_tickless.base + IMXRT_GPT_CR_OFFSET); regval |= GPT_CR_EN; diff --git a/arch/arm/src/imxrt/imxrt_usbdev.c b/arch/arm/src/imxrt/imxrt_usbdev.c index e4de158199..a3eb705bc5 100644 --- a/arch/arm/src/imxrt/imxrt_usbdev.c +++ b/arch/arm/src/imxrt/imxrt_usbdev.c @@ -222,7 +222,7 @@ const struct trace_msg_t g_usb_trace_strings_intdecode[] = struct imxrt_dtd_s { - volatile uint32_t nextdesc; /* Address of the next DMA descripto in RAM */ + volatile uint32_t nextdesc; /* Address of the next DMA descriptor in RAM */ volatile uint32_t config; /* Misc. bit encoded configuration information */ uint32_t buffer0; /* Buffer start address */ uint32_t buffer1; /* Buffer start address */ @@ -303,7 +303,7 @@ struct imxrt_dqh_s #define IMXRT_EP0MAXPACKET (64) /* EP0 max packet size (1-64) */ #define IMXRT_BULKMAXPACKET (512) /* Bulk endpoint max packet (8/16/32/64/512) */ #define IMXRT_INTRMAXPACKET (1024) /* Interrupt endpoint max packet (1 to 1024) */ -#define IMXRT_ISOCMAXPACKET (512) /* Acutally 1..1023 */ +#define IMXRT_ISOCMAXPACKET (512) /* Actually 1..1023 */ /* Endpoint bit position in SETUPSTAT, PRIME, FLUSH, STAT, COMPLETE * registers @@ -1224,7 +1224,7 @@ static void imxrt_usbreset(struct imxrt_usbdev_s *priv) imxrt_set_address(priv, 0); - /* Initialise the Enpoint List Address */ + /* Initialise the Endpoint List Address */ imxrt_putreg((uint32_t)g_qh, IMXRT_USBDEV_ENDPOINTLIST); diff --git a/arch/arm/src/imxrt/imxrt_usdhc.c b/arch/arm/src/imxrt/imxrt_usdhc.c index 3f76e7f358..6f88193395 100644 --- a/arch/arm/src/imxrt/imxrt_usdhc.c +++ b/arch/arm/src/imxrt/imxrt_usdhc.c @@ -3003,11 +3003,11 @@ static int imxrt_dmarecvsetup(struct sdio_dev_s *dev, struct imxrt_dev_s *priv = (struct imxrt_dev_s *)dev; DEBUGASSERT(priv != NULL && buffer != NULL && buflen > 0); #if defined(CONFIG_ARCH_HAVE_SDIO_PREFLIGHT) - /* Normaly imxrt_dmapreflight is called prior to imxrt_dmarecvsetup - * except for the case where the CSR read is done at initalization + /* Normally imxrt_dmapreflight is called prior to imxrt_dmarecvsetup + * except for the case where the CSR read is done at initialization. * * With a total read size of less then priv->rxbuffer we can - * handel the unaligned case herein, using the rxbuffer. + * handle the unaligned case herein, using the rxbuffer. * * Any other case is a falult. */ diff --git a/arch/arm/src/kinetis/hardware/kinetis_enet.h b/arch/arm/src/kinetis/hardware/kinetis_enet.h index 21ab0715e5..b04b0b285f 100644 --- a/arch/arm/src/kinetis/hardware/kinetis_enet.h +++ b/arch/arm/src/kinetis/hardware/kinetis_enet.h @@ -287,7 +287,7 @@ #define ENET_OPD_OPCODE_SHIFT (16) /* Bits 16-31: Opcode field in PAUSE frames */ #define ENET_OPD_OPCODE_MASK (0xffff << ENET_OPD_OPCODE_SHIFT) -/* Descriptor Individual Uupper/Lower Address Register +/* Descriptor Individual Upper/Lower Address Register * (64-bit address in two 32-bit registers) */ diff --git a/arch/arm/src/kinetis/hardware/kinetis_usbhs.h b/arch/arm/src/kinetis/hardware/kinetis_usbhs.h index 2106871913..10c84e7324 100644 --- a/arch/arm/src/kinetis/hardware/kinetis_usbhs.h +++ b/arch/arm/src/kinetis/hardware/kinetis_usbhs.h @@ -760,7 +760,7 @@ #define USBPHY_CTRLN_SFTRST (1 << 31) /* Bit 31: Soft-reset the USBPHY_PWD, USBPHY_TX, USBPHY_RX, and USBPHY_CTRL */ #define USBPHY_CTRLN_CLKGATE (1 << 30) /* Bit 30: Gate UTMI Clocks */ -#define USBPHY_CTRLN_UTMI_SUSPENDM (1 << 29) /* Bit 29: Indicats powered-down state */ +#define USBPHY_CTRLN_UTMI_SUSPENDM (1 << 29) /* Bit 29: Indicates powered-down state */ #define USBPHY_CTRLN_HOST_FORCE_LS_SE0 (1 << 28) /* Bit 28: Forces next FS packet tohave a EOP with low-speed timing */ #define USBPHY_CTRLN_OTG_ID_VALUE (1 << 27) /* Bit 27: Indicates the results of USB_ID pin */ /* Bit 25-26: Reserved */ diff --git a/arch/arm/src/kinetis/hardware/kinetis_usbotg.h b/arch/arm/src/kinetis/hardware/kinetis_usbotg.h index 692bb4f691..b307e03f46 100644 --- a/arch/arm/src/kinetis/hardware/kinetis_usbotg.h +++ b/arch/arm/src/kinetis/hardware/kinetis_usbotg.h @@ -88,7 +88,7 @@ # define KINETIS_USB_USBFRMADJUST_OFFSET 0x114 /* Frame Adjust Register */ # define KINETIS_USB_USB0_CLK_RECOVER_CTRL_OFFSET 0x140 /* USB Clock recovery control */ # define KINETIS_USB_USB0_CLK_RECOVER_IRC_EN_OFFSET 0x144 /* IRC48M oscillator enable register */ -# define KINETIS_USB_USB0_CLK_RECOVER_INT_STATUS_OFFSET 0x15c /* Clock recovery sperated interrupt status */ +# define KINETIS_USB_USB0_CLK_RECOVER_INT_STATUS_OFFSET 0x15c /* Clock recovery separated interrupt status */ #endif /* Register Addresses *******************************************************/ diff --git a/arch/arm/src/kinetis/kinetis.h b/arch/arm/src/kinetis/kinetis.h index b352f8614a..cd406a91f5 100644 --- a/arch/arm/src/kinetis/kinetis.h +++ b/arch/arm/src/kinetis/kinetis.h @@ -350,8 +350,8 @@ void kinetis_clockconfig(void); * * Description: * Performs the low level UART/LPUART initialization early in debug so that - * the serial console will be available during bootup. This must be called - * before arm_serialinit. + * the serial console will be available during boot up. This must be + * called before arm_serialinit. * ****************************************************************************/ @@ -364,7 +364,7 @@ void kinetis_earlyserialinit(void); * * Description: * Performs the low level UART initialization early in debug so that the - * serial console will be available during bootup. This must be called + * serial console will be available during boot up. This must be called * before arm_serialinit. * ****************************************************************************/ @@ -378,7 +378,7 @@ void kinetis_uart_earlyserialinit(void); * * Description: * Performs the low level LPUART initialization early in debug so that the - * serial console will be available during bootup. This must be called + * serial console will be available during boot up. This must be called * before arm_serialinit. * ****************************************************************************/ diff --git a/arch/arm/src/kinetis/kinetis_edma.h b/arch/arm/src/kinetis/kinetis_edma.h index 3134ef012a..d1d96dcf0e 100644 --- a/arch/arm/src/kinetis/kinetis_edma.h +++ b/arch/arm/src/kinetis/kinetis_edma.h @@ -80,7 +80,7 @@ * i mxrt_dmach_stop(handle); * * 7. The callback will be received when the DMA completes (or an error - * occurs). After that, you may free the DMA channel, or re-use it on + * occurs). After that, you may free the DMA channel, or reuse it on * subsequent DMAs. * * kinetis_dmach_free(handle); diff --git a/arch/arm/src/kinetis/kinetis_i2c.c b/arch/arm/src/kinetis/kinetis_i2c.c index 7267c7dac0..d9e25871e0 100644 --- a/arch/arm/src/kinetis/kinetis_i2c.c +++ b/arch/arm/src/kinetis/kinetis_i2c.c @@ -1286,7 +1286,7 @@ out: kinetis_i2c_setfrequency(priv, frequency); - /* Release the port for re-use by other clients */ + /* Release the port for reuse by other clients */ nxmutex_unlock(&priv->lock); return ret; diff --git a/arch/arm/src/kinetis/kinetis_lpserial.c b/arch/arm/src/kinetis/kinetis_lpserial.c index b8274b7f57..36c0a83a29 100644 --- a/arch/arm/src/kinetis/kinetis_lpserial.c +++ b/arch/arm/src/kinetis/kinetis_lpserial.c @@ -1788,7 +1788,7 @@ static void kinetis_dma_rxcallback(DMACH_HANDLE handle, void *arg, bool done, * * Description: * Performs the low level LPUART initialization early in debug so that the - * serial console will be available during bootup. This must be called + * serial console will be available during boot up. This must be called * before arm_serialinit. NOTE: This function depends on GPIO pin * configuration performed in kinetis_lowsetup() and main clock * initialization performed in up_clkinitialize(). diff --git a/arch/arm/src/kinetis/kinetis_rtc.c b/arch/arm/src/kinetis/kinetis_rtc.c index 7bb69d9331..96cad99df0 100644 --- a/arch/arm/src/kinetis/kinetis_rtc.c +++ b/arch/arm/src/kinetis/kinetis_rtc.c @@ -354,7 +354,7 @@ int up_rtc_initialize(void) putreg32(0, KINETIS_RTC_SR); - /* Enable oscilator - must have Vbat else hard fault */ + /* Enable oscillator - must have Vbat else hard fault */ putreg32((BOARD_RTC_CAP | RTC_CR_OSCE), KINETIS_RTC_CR); diff --git a/arch/arm/src/kinetis/kinetis_sdhc.c b/arch/arm/src/kinetis/kinetis_sdhc.c index c8bf9e86fc..06f88932c6 100644 --- a/arch/arm/src/kinetis/kinetis_sdhc.c +++ b/arch/arm/src/kinetis/kinetis_sdhc.c @@ -2184,7 +2184,7 @@ static int kinetis_waitresponse(struct sdio_dev_s *dev, uint32_t cmd) * * Returned Value: * Number of bytes sent on success; a negated errno on failure. Here a - * failure means only a faiure to obtain the requested response (due to + * failure means only a failure to obtain the requested response (due to * transport problem -- timeout, CRC, etc.). The implementation only * assures that the response is returned intacta and does not check errors * within the response itself. diff --git a/arch/arm/src/kinetis/kinetis_serial.c b/arch/arm/src/kinetis/kinetis_serial.c index 1921a09045..72d648e390 100644 --- a/arch/arm/src/kinetis/kinetis_serial.c +++ b/arch/arm/src/kinetis/kinetis_serial.c @@ -1988,7 +1988,7 @@ static void up_dma_rxcallback(DMACH_HANDLE handle, void *arg, bool done, * * Description: * Performs the low level UART initialization early in debug so that the - * serial console will be available during bootup. This must be called + * serial console will be available during boot up. This must be called * before arm_serialinit. NOTE: This function depends on GPIO pin * configuration performed in up_consoleinit() and main clock * initialization performed in up_clkinitialize(). diff --git a/arch/arm/src/kinetis/kinetis_serialinit.c b/arch/arm/src/kinetis/kinetis_serialinit.c index 4cfdd5cb09..73da8071ef 100644 --- a/arch/arm/src/kinetis/kinetis_serialinit.c +++ b/arch/arm/src/kinetis/kinetis_serialinit.c @@ -48,7 +48,7 @@ * * Description: * Performs the low level UART and LPUART initialization early in debug - * so that the serial console will be available during bootup. This must + * so that the serial console will be available during boot up. This must * be called before arm_serialinit. NOTE: This function depends on GPIO * pin configuration performed in up_consoleinit() and main clock * initialization performed in up_clkinitialize(). diff --git a/arch/arm/src/kinetis/kinetis_usbhshost.c b/arch/arm/src/kinetis/kinetis_usbhshost.c index 386071e118..d7d5b140d2 100644 --- a/arch/arm/src/kinetis/kinetis_usbhshost.c +++ b/arch/arm/src/kinetis/kinetis_usbhshost.c @@ -1788,7 +1788,7 @@ kinetis_qh_s *kinetis_qh_create(struct kinetis_rhport_s *rhport, * FIELD DESCRIPTION VALUE/SOURCE * -------- ------------------------------- -------------------- * DEVADDR Device address Endpoint structure - * I Inactivate on Next Transaction 0 + * I Deactivate on Next Transaction 0 * ENDPT Endpoint number Endpoint structure * EPS Endpoint speed Endpoint structure * DTC Data toggle control 1 @@ -4068,7 +4068,7 @@ static int kinetis_epalloc(struct usbhost_driver_s *drvr, * Input Parameters: * drvr - The USB host driver instance obtained as a parameter from the * call to the class create() method. - * ep - The endpint to be freed. + * ep - The endpoint to be freed. * * Returned Value: * On success, zero (OK) is returned. On a failure, a negated errno value diff --git a/arch/arm/src/kl/kl_serial.c b/arch/arm/src/kl/kl_serial.c index d9c76bd039..d2a6ff7f09 100644 --- a/arch/arm/src/kl/kl_serial.c +++ b/arch/arm/src/kl/kl_serial.c @@ -810,7 +810,7 @@ static bool up_txready(struct uart_dev_s *dev) * * Description: * Performs the low level UART initialization early in debug so that the - * serial console will be available during bootup. This must be called + * serial console will be available during boot up. This must be called * before arm_serialinit. NOTE: This function depends on GPIO pin * configuration performed in up_consoleinit() and main clock * initialization performed in up_clkinitialize(). diff --git a/arch/arm/src/kl/kl_spi.c b/arch/arm/src/kl/kl_spi.c index 0a13576745..56cca4e3c9 100644 --- a/arch/arm/src/kl/kl_spi.c +++ b/arch/arm/src/kl/kl_spi.c @@ -274,7 +274,7 @@ static uint32_t spi_setfrequency(struct spi_dev_s *dev, unsigned int spr; unsigned int sppr; - /* Check if the requested frequence is the same as the frequency + /* Check if the requested frequency is the same as the frequency * selection. */ diff --git a/arch/arm/src/kl/kl_start.c b/arch/arm/src/kl/kl_start.c index 271ec005d6..e2f45890f9 100644 --- a/arch/arm/src/kl/kl_start.c +++ b/arch/arm/src/kl/kl_start.c @@ -51,7 +51,7 @@ * 0x0000:0000 - Beginning of FLASH. Address of exception vectors. * 0x0001:ffff - End of flash (assuming 128KB of FLASH) * 0x2000:0000 - Start of SRAM and start of .data (_sdata) - * - End of .data (_edata) abd start of .bss (_sbss) + * - End of .data (_edata) and start of .bss (_sbss) * - End of .bss (_ebss) and bottom of idle stack * - _ebss + CONFIG_IDLETHREAD_STACKSIZE = end of idle stack, * start of heap diff --git a/arch/arm/src/lc823450/lc823450_adc.c b/arch/arm/src/lc823450/lc823450_adc.c index 0fa988693b..696d6a6cea 100644 --- a/arch/arm/src/lc823450/lc823450_adc.c +++ b/arch/arm/src/lc823450/lc823450_adc.c @@ -521,7 +521,7 @@ struct adc_dev_s *lc823450_adcinitialize(void) return NULL; } - /* enable clock & unreset (include exitting standby mode) */ + /* enable clock & unreset (include exiting standby mode) */ modifyreg32(MCLKCNTAPB, 0, MCLKCNTAPB_ADC_CLKEN); modifyreg32(MRSTCNTAPB, MRSTCNTAPB_ADC_RSTB, 0); diff --git a/arch/arm/src/lc823450/lc823450_dma.c b/arch/arm/src/lc823450/lc823450_dma.c index 61b9ffd5b4..82bb589c5b 100644 --- a/arch/arm/src/lc823450/lc823450_dma.c +++ b/arch/arm/src/lc823450/lc823450_dma.c @@ -448,7 +448,7 @@ void lc823450_dmarequest(DMA_HANDLE handle, uint8_t dmarequest) val |= DMACCFG_FLOWCTRL_M2P_DMA; break; default: - dmaerr("ERROR: Not implemetned\n"); + dmaerr("ERROR: Not implemented\n"); DEBUGPANIC(); } diff --git a/arch/arm/src/lc823450/lc823450_i2c.c b/arch/arm/src/lc823450/lc823450_i2c.c index 5632b5ea6b..82a2891c92 100644 --- a/arch/arm/src/lc823450/lc823450_i2c.c +++ b/arch/arm/src/lc823450/lc823450_i2c.c @@ -1020,7 +1020,7 @@ static int lc823450_i2c_transfer(struct i2c_master_s *dev, leave_critical_section(irqs); /* Wait for irq handler completion. 10msec wait is probably enough - * to terminate i2c transaction, NACK and STOP contition for read + * to terminate i2c transaction, NACK and STOP condition for read * transaction, STOP condition for write transaction */ diff --git a/arch/arm/src/lc823450/lc823450_serial.c b/arch/arm/src/lc823450/lc823450_serial.c index 0ddea2c79b..240793ab47 100644 --- a/arch/arm/src/lc823450/lc823450_serial.c +++ b/arch/arm/src/lc823450/lc823450_serial.c @@ -1259,7 +1259,7 @@ retry: * Description: * Performs the low level UART initialization early in * debug so that the serial console will be available - * during bootup. This must be called before arm_serialinit. + * during boot up. This must be called before arm_serialinit. * ****************************************************************************/ diff --git a/arch/arm/src/lc823450/lc823450_spi.h b/arch/arm/src/lc823450/lc823450_spi.h index f012b8dd76..bf48748f18 100644 --- a/arch/arm/src/lc823450/lc823450_spi.h +++ b/arch/arm/src/lc823450/lc823450_spi.h @@ -94,7 +94,7 @@ #define SPI_ISR_OVE (1 << 1) /* Bit 1: overrun */ #define SPI_ISR_SPIF (1 << 0) /* Bit 0: Frame transfer completion */ -/* SPI FIFO contorl Register */ +/* SPI FIFO control Register */ #define SPI_TXFF_EN (1 << 0) #define SPI_TXFF_WL2 (0 << 4) diff --git a/arch/arm/src/lc823450/lc823450_timer.c b/arch/arm/src/lc823450/lc823450_timer.c index 926eeb828f..badfa91595 100644 --- a/arch/arm/src/lc823450/lc823450_timer.c +++ b/arch/arm/src/lc823450/lc823450_timer.c @@ -198,7 +198,7 @@ static void hrt_queue_refresh(void) cont: - /* serch for expired */ + /* search for expired */ for (pent = hrt_timer_queue.head; pent; pent = dq_next(pent)) { @@ -707,7 +707,7 @@ int up_rtc_gettime(struct timespec *tp) elapsed = NSEC_PER_TICK * (uint64_t)g_system_ticks; - /* Add the tiemr fraction in nanoseconds */ + /* Add the timer fraction in nanoseconds */ f = up_get_timer_fraction(); elapsed += f; diff --git a/arch/arm/src/lpc17xx_40xx/hardware/lpc17_40_can.h b/arch/arm/src/lpc17xx_40xx/hardware/lpc17_40_can.h index 8f932401a7..d710d7a45f 100644 --- a/arch/arm/src/lpc17xx_40xx/hardware/lpc17_40_can.h +++ b/arch/arm/src/lpc17xx_40xx/hardware/lpc17_40_can.h @@ -440,7 +440,7 @@ #define CAN_RID_ID11_MASK (0x7ff) /* Bits 0-10: 11-bit Identifier (FF=0) */ /* Bits 11-31: Reserved */ -#define CAN_RID_ID29_MASK (0x1fffffff) /* Bits 0-28: 29-bit Identifiter (FF=1) */ +#define CAN_RID_ID29_MASK (0x1fffffff) /* Bits 0-28: 29-bit Identifier (FF=1) */ /* Bits 29-31: Reserved */ /* Received data bytes 1-4 */ @@ -487,7 +487,7 @@ #define CAN_TID_ID11_MASK (0x7ff) /* Bits 0-10: 11-bit Identifier (FF=0) */ /* Bits 11-31: Reserved */ -#define CAN_TID_ID29_MASK (0x1fffffff) /* Bits 0-28: 29-bit Identifiter (FF=1) */ +#define CAN_TID_ID29_MASK (0x1fffffff) /* Bits 0-28: 29-bit Identifier (FF=1) */ /* Bits 29-31: Reserved */ /* Transmit data bytes 1-4 (Tx Buffer 1), diff --git a/arch/arm/src/lpc17xx_40xx/hardware/lpc17_40_lcd.h b/arch/arm/src/lpc17xx_40xx/hardware/lpc17_40_lcd.h index 1aa34b8ad5..f05df0efc2 100644 --- a/arch/arm/src/lpc17xx_40xx/hardware/lpc17_40_lcd.h +++ b/arch/arm/src/lpc17xx_40xx/hardware/lpc17_40_lcd.h @@ -206,7 +206,7 @@ /* Bits 0: Reserved */ #define LCD_INTRAW_FUFRIS (1 << 1) /* Bit 1: FIFO Underflow raw interrupt status */ -#define LCD_INTRAW_LNBURIS (1 << 2) /* Bit 2: LCD Next address base update intterupt */ +#define LCD_INTRAW_LNBURIS (1 << 2) /* Bit 2: LCD Next address base update interrupt */ #define LCD_INTRAW_VCOMPRIS (1 << 3) /* Bit 3: Vertical compare interrupt status */ #define LCD_INTRAW_BERRAW (1 << 4) /* Bit 4: AHB Master bus error interrupt status */ /* Bits 5-31: Reserved */ @@ -216,7 +216,7 @@ /* Bits 0: Reserved */ #define LCD_INTSTAT_FUFMIS (1 << 1) /* Bit 1: FIFO Underflow raw interrupt status */ -#define LCD_INTSTAT_LNBUMIS (1 << 2) /* Bit 2: LCD Next address base update intterupt */ +#define LCD_INTSTAT_LNBUMIS (1 << 2) /* Bit 2: LCD Next address base update interrupt */ #define LCD_INTSTAT_VCOMPMIS (1 << 3) /* Bit 3: Vertical compare interrupt status */ #define LCD_INTSTAT_BERMIS (1 << 4) /* Bit 4: AHB Master bus error interrupt status */ /* Bits 15-31: Reserved */ @@ -226,7 +226,7 @@ /* Bits 0: Reserved */ #define LCD_INTCLR_FUFIC (1 << 1) /* Bit 1: FIFO Underflow raw interrupt clear */ -#define LCD_INTCLR_LNBUIC (1 << 2) /* Bit 2: LCD Next address base update intterupt */ +#define LCD_INTCLR_LNBUIC (1 << 2) /* Bit 2: LCD Next address base update interrupt */ #define LCD_INTCLR_VCOMPIC (1 << 3) /* Bit 3: Vertical compare interrupt clear */ #define LCD_INTCLR_BERIC (1 << 4) /* Bit 4: AHB Master bus error interrupt clear */ /* Bits 15-31: Reserved */ @@ -289,7 +289,7 @@ /* LCD CRSR_PAL0/1 - Cursor Palette Registers */ -#define LCD_CRSR_PAL_RED_SHIFT (0) /* Bits 0-7: Red color componnent */ +#define LCD_CRSR_PAL_RED_SHIFT (0) /* Bits 0-7: Red color component */ #define LCD_CRSR_PAL_RED_MASK (0xff << LCD_CRSR_PAL0_RED_SHIFT) #define LCD_CRSR_PAL_GREEN_SHIFT (8) /* Bits 8-15: Green color component */ #define LCD_CRSR_PAL_GREEN_MASK (0xff << LCD_CRSR_PAL0_GREEN_SHIFT) diff --git a/arch/arm/src/lpc17xx_40xx/hardware/lpc17_40_usb.h b/arch/arm/src/lpc17xx_40xx/hardware/lpc17_40_usb.h index 142ca7175c..179da73c0d 100644 --- a/arch/arm/src/lpc17xx_40xx/hardware/lpc17_40_usb.h +++ b/arch/arm/src/lpc17xx_40xx/hardware/lpc17_40_usb.h @@ -346,7 +346,7 @@ #define USBDEV_INT_CCEMPTY (1 << 4) /* Bit 4: Command code register empty */ #define USBDEV_INT_CDFULL (1 << 5) /* Bit 5: Command data register full */ #define USBDEV_INT_RXENDPKT (1 << 6) /* Bit 6: RX endpoint data transferred */ -#define USBDEV_INT_TXENDPKT (1 << 7) /* Bit 7: TX endpoint data tansferred */ +#define USBDEV_INT_TXENDPKT (1 << 7) /* Bit 7: TX endpoint data transferred */ #define USBDEV_INT_EPRLZED (1 << 8) /* Bit 8: Endpoints realized */ #define USBDEV_INT_ERRINT (1 << 9) /* Bit 9: Error Interrupt */ /* Bits 10-31: Reserved */ diff --git a/arch/arm/src/lpc17xx_40xx/lpc176x_clockconfig.c b/arch/arm/src/lpc17xx_40xx/lpc176x_clockconfig.c index bbf4c5fc2f..d0b6fa6576 100644 --- a/arch/arm/src/lpc17xx_40xx/lpc176x_clockconfig.c +++ b/arch/arm/src/lpc17xx_40xx/lpc176x_clockconfig.c @@ -197,7 +197,7 @@ void lpc17_40_clockconfig(void) putreg32(0, LPC17_40_SYSCON_PCLKSEL0); putreg32(0, LPC17_40_SYSCON_PCLKSEL1); - /* Disable power to all peripherals (execpt GPIO). Peripherals must be + /* Disable power to all peripherals (except GPIO). Peripherals must be * re-powered one at a time by each device driver when the driver is * initialized. */ diff --git a/arch/arm/src/lpc17xx_40xx/lpc176x_gpio.c b/arch/arm/src/lpc17xx_40xx/lpc176x_gpio.c index 4d7283a67f..66c2db43e0 100644 --- a/arch/arm/src/lpc17xx_40xx/lpc176x_gpio.c +++ b/arch/arm/src/lpc17xx_40xx/lpc176x_gpio.c @@ -589,7 +589,7 @@ int lpc17_40_configgpio(lpc17_40_pinset_t cfgset) ret = lpc17_40_configinterrupt(cfgset, port, pin); break; - case GPIO_OUTPUT: /* GPIO outpout pin */ + case GPIO_OUTPUT: /* GPIO output pin */ ret = lpc17_40_configoutput(cfgset, port, pin); break; diff --git a/arch/arm/src/lpc17xx_40xx/lpc176x_gpio.h b/arch/arm/src/lpc17xx_40xx/lpc176x_gpio.h index 7259f78920..d1291c0a1a 100644 --- a/arch/arm/src/lpc17xx_40xx/lpc176x_gpio.h +++ b/arch/arm/src/lpc17xx_40xx/lpc176x_gpio.h @@ -53,7 +53,7 @@ # define GPIO_INTFE (1 << GPIO_FUNC_SHIFT) /* 001 GPIO interrupt falling edge */ # define GPIO_INTRE (2 << GPIO_FUNC_SHIFT) /* 010 GPIO interrupt rising edge */ # define GPIO_INTBOTH (3 << GPIO_FUNC_SHIFT) /* 011 GPIO interrupt both edges */ -# define GPIO_OUTPUT (4 << GPIO_FUNC_SHIFT) /* 100 GPIO outpout pin */ +# define GPIO_OUTPUT (4 << GPIO_FUNC_SHIFT) /* 100 GPIO output pin */ # define GPIO_ALT1 (5 << GPIO_FUNC_SHIFT) /* 101 Alternate function 1 */ # define GPIO_ALT2 (6 << GPIO_FUNC_SHIFT) /* 110 Alternate function 2 */ # define GPIO_ALT3 (7 << GPIO_FUNC_SHIFT) /* 111 Alternate function 3 */ diff --git a/arch/arm/src/lpc17xx_40xx/lpc178x_40xx_gpio.c b/arch/arm/src/lpc17xx_40xx/lpc178x_40xx_gpio.c index b31233094d..d2b5f489d0 100644 --- a/arch/arm/src/lpc17xx_40xx/lpc178x_40xx_gpio.c +++ b/arch/arm/src/lpc17xx_40xx/lpc178x_40xx_gpio.c @@ -827,7 +827,7 @@ int lpc17_40_configgpio(lpc17_40_pinset_t cfgset) ret = lpc17_40_configinterrupt(cfgset, port, pin); break; - case GPIO_OUTPUT: /* GPIO outpout pin */ + case GPIO_OUTPUT: /* GPIO output pin */ ret = lpc17_40_configoutput(cfgset, port, pin); break; diff --git a/arch/arm/src/lpc17xx_40xx/lpc178x_40xx_gpio.h b/arch/arm/src/lpc17xx_40xx/lpc178x_40xx_gpio.h index fae33b791f..6efce0d511 100644 --- a/arch/arm/src/lpc17xx_40xx/lpc178x_40xx_gpio.h +++ b/arch/arm/src/lpc17xx_40xx/lpc178x_40xx_gpio.h @@ -86,7 +86,7 @@ # define GPIO_INTFE (1 << GPIO_FUNC_SHIFT) /* 0001 GPIO interrupt falling edge */ # define GPIO_INTRE (2 << GPIO_FUNC_SHIFT) /* 0010 GPIO interrupt rising edge */ # define GPIO_INTBOTH (3 << GPIO_FUNC_SHIFT) /* 0011 GPIO interrupt both edges */ -# define GPIO_OUTPUT (4 << GPIO_FUNC_SHIFT) /* 0100 GPIO outpout pin */ +# define GPIO_OUTPUT (4 << GPIO_FUNC_SHIFT) /* 0100 GPIO output pin */ # define GPIO_ALT1 (5 << GPIO_FUNC_SHIFT) /* 0101 Alternate function 1 */ # define GPIO_ALT2 (6 << GPIO_FUNC_SHIFT) /* 0110 Alternate function 2 */ # define GPIO_ALT3 (7 << GPIO_FUNC_SHIFT) /* 0111 Alternate function 3 */ diff --git a/arch/arm/src/lpc17xx_40xx/lpc17_40_gpdma.h b/arch/arm/src/lpc17xx_40xx/lpc17_40_gpdma.h index 7e1d2d6b7f..3c40293a01 100644 --- a/arch/arm/src/lpc17xx_40xx/lpc17_40_gpdma.h +++ b/arch/arm/src/lpc17xx_40xx/lpc17_40_gpdma.h @@ -48,7 +48,7 @@ typedef void *DMA_HANDLE; * same 'arg' value that was provided when lpc17_40_dmastart() was called and * result indicates the result of the transfer: Zero indicates a successful * transfers. On failure, a negated errno is returned indicating the general - * nature of the DMA faiure. + * nature of the DMA failure. */ typedef void (*dma_callback_t)(DMA_HANDLE handle, void *arg, int result); diff --git a/arch/arm/src/lpc17xx_40xx/lpc17_40_sdcard.c b/arch/arm/src/lpc17xx_40xx/lpc17_40_sdcard.c index 7eb758a599..4057867e8d 100644 --- a/arch/arm/src/lpc17xx_40xx/lpc17_40_sdcard.c +++ b/arch/arm/src/lpc17xx_40xx/lpc17_40_sdcard.c @@ -1962,7 +1962,7 @@ static int lpc17_40_waitresponse(struct sdio_dev_s *dev, uint32_t cmd) * * Returned Value: * Number of bytes sent on success; a negated errno on failure. Here a - * failure means only a faiure to obtain the requested response (due to + * failure means only a failure to obtain the requested response (due to * transport problem -- timeout, CRC, etc.). The implementation only * assures that the response is returned intacta and does not check errors * within the response itself. diff --git a/arch/arm/src/lpc17xx_40xx/lpc17_40_serial.c b/arch/arm/src/lpc17xx_40xx/lpc17_40_serial.c index 55bc869117..616de21ef3 100644 --- a/arch/arm/src/lpc17xx_40xx/lpc17_40_serial.c +++ b/arch/arm/src/lpc17xx_40xx/lpc17_40_serial.c @@ -1586,7 +1586,7 @@ static bool up_txempty(struct uart_dev_s *dev) * * Description: * Performs the low level UART initialization early in debug so that the - * serial console will be available during bootup. This must be called + * serial console will be available during boot up. This must be called * before arm_serialinit. * * NOTE: Configuration of the CONSOLE UART was performed by up_lowsetup() diff --git a/arch/arm/src/lpc17xx_40xx/lpc17_40_spi.c b/arch/arm/src/lpc17xx_40xx/lpc17_40_spi.c index c9a893a5f7..af5e4d3934 100644 --- a/arch/arm/src/lpc17xx_40xx/lpc17_40_spi.c +++ b/arch/arm/src/lpc17xx_40xx/lpc17_40_spi.c @@ -217,7 +217,7 @@ static uint32_t spi_setfrequency(struct spi_dev_s *dev, DEBUGASSERT(priv && frequency <= SPI_CLOCK / 2); - /* Check if the requested frequence is the same as the frequency + /* Check if the requested frequency is the same as the frequency * selection. */ diff --git a/arch/arm/src/lpc17xx_40xx/lpc17_40_usbdev.c b/arch/arm/src/lpc17xx_40xx/lpc17_40_usbdev.c index fa433c4acb..c7ce7cfce0 100644 --- a/arch/arm/src/lpc17xx_40xx/lpc17_40_usbdev.c +++ b/arch/arm/src/lpc17xx_40xx/lpc17_40_usbdev.c @@ -306,7 +306,7 @@ struct lpc17_40_dmadesc_s uint32_t nextdesc; /* Address of the next DMA descriptor in RAM */ uint32_t config; /* Misc. bit encoded configuration information */ uint32_t start; /* DMA start address */ - uint32_t status; /* Misc. bit encoded status inforamation */ + uint32_t status; /* Misc. bit encoded status information */ #ifdef CONFIG_USBDEV_ISOCHRONOUS uint32_t size; /* Isochronous packet size address */ #endif diff --git a/arch/arm/src/lpc17xx_40xx/lpc17_40_usbhost.c b/arch/arm/src/lpc17xx_40xx/lpc17_40_usbhost.c index 94c61457b5..14606efe30 100644 --- a/arch/arm/src/lpc17xx_40xx/lpc17_40_usbhost.c +++ b/arch/arm/src/lpc17xx_40xx/lpc17_40_usbhost.c @@ -2369,7 +2369,7 @@ static int lpc17_40_epalloc(struct usbhost_driver_s *drvr, * Input Parameters: * drvr - The USB host driver instance obtained as a parameter from the * call to the class create() method. - * ep - The endpint to be freed. + * ep - The endpoint to be freed. * * Returned Value: * On success, zero (OK) is returned. On a failure, a negated errno value diff --git a/arch/arm/src/lpc214x/lpc214x_serial.c b/arch/arm/src/lpc214x/lpc214x_serial.c index 6fc923d6b5..f669aa5456 100644 --- a/arch/arm/src/lpc214x/lpc214x_serial.c +++ b/arch/arm/src/lpc214x/lpc214x_serial.c @@ -243,7 +243,7 @@ static inline void up_waittxready(struct up_dev_s *priv) for (tmp = 1000 ; tmp > 0 ; tmp--) { - /* Check if the tranmitter holding register (THR) is empty */ + /* Check if the transmitter holding register (THR) is empty */ if ((up_serialin(priv, LPC214X_UART_LSR_OFFSET) & LPC214X_LSR_THRE) != 0) @@ -736,7 +736,7 @@ static bool up_txempty(struct uart_dev_s *dev) * Description: * Performs the low level UART initialization early in * debug so that the serial console will be available - * during bootup. This must be called before arm_serialinit. + * during boot up. This must be called before arm_serialinit. * ****************************************************************************/ diff --git a/arch/arm/src/lpc214x/lpc214x_spi.h b/arch/arm/src/lpc214x/lpc214x_spi.h index e4b6131893..7c643a6234 100644 --- a/arch/arm/src/lpc214x/lpc214x_spi.h +++ b/arch/arm/src/lpc214x/lpc214x_spi.h @@ -110,7 +110,7 @@ #define LPC214X_SPI1CR0_FRFMW (0x0020) /* Microwire */ #define LPC214X_SPI1CR0_CPOL (0x0040) /* Bit 6: Clock polarity control */ #define LPC214X_SPI1CR0_CPHA (0x0080) /* Bit 7: Clock phase control */ -#define LPC214X_SPI1CR0_SCR (0xff00) /* Bits 8-15: Serial clock reate */ +#define LPC214X_SPI1CR0_SCR (0xff00) /* Bits 8-15: Serial clock rate */ /* Control Register 1 (CR1) */ diff --git a/arch/arm/src/lpc214x/lpc214x_usbdev.c b/arch/arm/src/lpc214x/lpc214x_usbdev.c index 1496d563ce..8542379000 100644 --- a/arch/arm/src/lpc214x/lpc214x_usbdev.c +++ b/arch/arm/src/lpc214x/lpc214x_usbdev.c @@ -313,7 +313,7 @@ struct lpc214x_dmadesc_s uint32_t nextdesc; /* Address of the next DMA descriptor in RAM */ uint32_t config; /* Misc. bit encoded configuration information */ uint32_t start; /* DMA start address */ - uint32_t status; /* Misc. bit encoded status inforamation */ + uint32_t status; /* Misc. bit encoded status information */ #ifdef CONFIG_USBDEV_ISOCHRONOUS uint32_t size; /* Isochronous packet size address */ #endif diff --git a/arch/arm/src/lpc2378/chip.h b/arch/arm/src/lpc2378/chip.h index cbfd019620..864b02bc74 100644 --- a/arch/arm/src/lpc2378/chip.h +++ b/arch/arm/src/lpc2378/chip.h @@ -422,7 +422,7 @@ #define CAN2TDA3_OFFSET 0x58 #define CAN2TDB3_OFFSET 0x5C -/* MultiMedia Card Interface(MCI) ontroller */ +/* MultiMedia Card Interface(MCI) controller */ /* MCI_BASE_ADDR 0xE008C000 */ #define MCI_POWER_OFFSET 0x00 diff --git a/arch/arm/src/lpc2378/lpc23xx_pllsetup.c b/arch/arm/src/lpc2378/lpc23xx_pllsetup.c index 4d172acdd0..09938b8153 100644 --- a/arch/arm/src/lpc2378/lpc23xx_pllsetup.c +++ b/arch/arm/src/lpc2378/lpc23xx_pllsetup.c @@ -244,7 +244,7 @@ void configure_pll(void) while ((SCB_PLLSTAT & (1 << 25)) == 0); - /* Set memory accelerater module */ + /* Set memory accelerator module */ SCB_MAMCR = 0; SCB_MAMTIM = CONFIG_LPC2378_MAMTIM_VALUE; diff --git a/arch/arm/src/lpc2378/lpc23xx_serial.c b/arch/arm/src/lpc2378/lpc23xx_serial.c index 6468ae8c8a..ece1496658 100644 --- a/arch/arm/src/lpc2378/lpc23xx_serial.c +++ b/arch/arm/src/lpc2378/lpc23xx_serial.c @@ -269,7 +269,7 @@ static inline void up_waittxready(struct up_dev_s *priv) for (tmp = 1000; tmp > 0; tmp--) { - /* Check if the tranmitter holding register (THR) is empty */ + /* Check if the transmitter holding register (THR) is empty */ if ((up_serialin(priv, UART_LSR_OFFSET) & LSR_THRE) != 0) { @@ -865,7 +865,7 @@ static bool up_txempty(struct uart_dev_s *dev) * Description: * Performs the low level UART initialization early in * debug so that the serial console will be available - * during bootup. This must be called before arm_serialinit. + * during boot up. This must be called before arm_serialinit. * ****************************************************************************/ diff --git a/arch/arm/src/lpc31xx/lpc31_cgudrvr.h b/arch/arm/src/lpc31xx/lpc31_cgudrvr.h index 5db81b8891..33dc9016c5 100644 --- a/arch/arm/src/lpc31xx/lpc31_cgudrvr.h +++ b/arch/arm/src/lpc31xx/lpc31_cgudrvr.h @@ -717,7 +717,7 @@ enum lpc31_domainid_e lpc31_clkdomain(enum lpc31_clockid_e clkid); * Given a clock ID, return the index of the corresponding ESR register * (or ESRNDX_INVALID if there is no ESR associated with this clock ID). * Indexing of ESRs differs slightly from the clock ID: - * There are 92 clock IDs but only 89 ESR regisers. There are no ESR + * There are 92 clock IDs but only 89 ESR registers. There are no ESR * registers for : * * diff --git a/arch/arm/src/lpc31xx/lpc31_ehci.c b/arch/arm/src/lpc31xx/lpc31_ehci.c index 9d0cfc9760..cc2469d243 100644 --- a/arch/arm/src/lpc31xx/lpc31_ehci.c +++ b/arch/arm/src/lpc31xx/lpc31_ehci.c @@ -1736,7 +1736,7 @@ static struct lpc31_qh_s *lpc31_qh_create(struct lpc31_rhport_s *rhport, * FIELD DESCRIPTION VALUE/SOURCE * -------- ------------------------------- -------------------- * DEVADDR Device address Endpoint structure - * I Inactivate on Next Transaction 0 + * I Deactivate on Next Transaction 0 * ENDPT Endpoint number Endpoint structure * EPS Endpoint speed Endpoint structure * DTC Data toggle control 1 @@ -4019,7 +4019,7 @@ static int lpc31_epalloc(struct usbhost_driver_s *drvr, * Input Parameters: * drvr - The USB host driver instance obtained as a parameter from the * call to the class create() method. - * ep - The endpint to be freed. + * ep - The endpoint to be freed. * * Returned Value: * On success, zero (OK) is returned. On a failure, a negated errno value diff --git a/arch/arm/src/lpc31xx/lpc31_esrndx.c b/arch/arm/src/lpc31xx/lpc31_esrndx.c index 1c04838fa5..f8ec2e0455 100644 --- a/arch/arm/src/lpc31xx/lpc31_esrndx.c +++ b/arch/arm/src/lpc31xx/lpc31_esrndx.c @@ -46,7 +46,7 @@ * Given a clock ID, return the index of the corresponding ESR * register (or ESRNDX_INVALID if there is no ESR associated with * this clock ID). Indexing of ESRs differs slightly from the clock - * ID: There are 92 clock IDs but only 89 ESR regisers. There are no + * ID: There are 92 clock IDs but only 89 ESR registers. There are no * ESR registers for: * * CLKID_I2SRXBCK0 Clock ID 87: I2SRX_BCK0 diff --git a/arch/arm/src/lpc31xx/lpc31_i2s.h b/arch/arm/src/lpc31xx/lpc31_i2s.h index e7d4a5e077..b3acfa3dd3 100644 --- a/arch/arm/src/lpc31xx/lpc31_i2s.h +++ b/arch/arm/src/lpc31xx/lpc31_i2s.h @@ -288,8 +288,8 @@ /* II2SCONFIG_CFGMUX address 0x16000004 */ -#define I2SCONFIG_CFGMUX_I2SRX1OEN (1 << 2) /* Bit 2: Selects faster mode for I2SRX1 */ -#define I2SCONFIG_CFGMUX_I2SRX0OEN (1 << 1) /* Bit 1: Slects master mode for I2SRX0 */ +#define I2SCONFIG_CFGMUX_I2SRX1OEN (1 << 2) /* Bit 2: Selects master mode for I2SRX1 */ +#define I2SCONFIG_CFGMUX_I2SRX0OEN (1 << 1) /* Bit 1: Selects master mode for I2SRX0 */ /* I2SCONFIG_NSOFCNT address 0x16000010 */ diff --git a/arch/arm/src/lpc31xx/lpc31_lowputc.c b/arch/arm/src/lpc31xx/lpc31_lowputc.c index 22a1200fd5..81213c1aa3 100644 --- a/arch/arm/src/lpc31xx/lpc31_lowputc.c +++ b/arch/arm/src/lpc31xx/lpc31_lowputc.c @@ -97,7 +97,7 @@ static inline void up_waittxready(void) for (tmp = 1000 ; tmp > 0 ; tmp--) { - /* Check if the tranmitter holding register (THR) is empty */ + /* Check if the transmitter holding register (THR) is empty */ if ((getreg32(LPC31_UART_LSR) & UART_LSR_THRE) != 0) { diff --git a/arch/arm/src/lpc31xx/lpc31_serial.c b/arch/arm/src/lpc31xx/lpc31_serial.c index 263531684c..a2602557ae 100644 --- a/arch/arm/src/lpc31xx/lpc31_serial.c +++ b/arch/arm/src/lpc31xx/lpc31_serial.c @@ -749,8 +749,8 @@ static bool up_txempty(struct uart_dev_s *dev) * * Description: * Performs the low level UART initialization early in debug so that the - * serial console will be available during bootup (via up_putc). This must - * be called before arm_serialinit. + * serial console will be available during boot up (via up_putc). This + * must be called before arm_serialinit. * ****************************************************************************/ diff --git a/arch/arm/src/lpc31xx/lpc31_spi.c b/arch/arm/src/lpc31xx/lpc31_spi.c index eb7f1cd098..7a1e14b74c 100644 --- a/arch/arm/src/lpc31xx/lpc31_spi.c +++ b/arch/arm/src/lpc31xx/lpc31_spi.c @@ -190,7 +190,7 @@ static int g_ntimes; * * Returned Value: * true: This is the first register access of this type. - * flase: This is the same as the preceding register access. + * false: This is the same as the preceding register access. * ****************************************************************************/ diff --git a/arch/arm/src/lpc43xx/hardware/lpc4310203050_pinconfig.h b/arch/arm/src/lpc43xx/hardware/lpc4310203050_pinconfig.h index fe1469fb00..406e0aa6ba 100644 --- a/arch/arm/src/lpc43xx/hardware/lpc4310203050_pinconfig.h +++ b/arch/arm/src/lpc43xx/hardware/lpc4310203050_pinconfig.h @@ -39,8 +39,8 @@ * not be applicable to any other family members. * * 2. Settings taken from the data sheet include only function, pin set, and - * pin number. Additional settings must be verfied before using these pin - * configurations (like pull-ups, open-drain, drive strength, input + * pin number. Additional settings must be verified before using these + * pin configurations (like pull-ups, open-drain, drive strength, input * buffering, etc.). * * 3. Alternative pin selections are provided with a numeric suffix like _1, diff --git a/arch/arm/src/lpc43xx/lpc43_ehci.c b/arch/arm/src/lpc43xx/lpc43_ehci.c index b99cbfb7b1..96af92c566 100644 --- a/arch/arm/src/lpc43xx/lpc43_ehci.c +++ b/arch/arm/src/lpc43xx/lpc43_ehci.c @@ -1630,7 +1630,7 @@ static struct lpc43_qh_s *lpc43_qh_create(struct lpc43_rhport_s *rhport, * FIELD DESCRIPTION VALUE/SOURCE * -------- ------------------------------- -------------------- * DEVADDR Device address Endpoint structure - * I Inactivate on Next Transaction 0 + * I Deactivate on Next Transaction 0 * ENDPT Endpoint number Endpoint structure * EPS Endpoint speed Endpoint structure * DTC Data toggle control 1 @@ -3856,7 +3856,7 @@ static int lpc43_epalloc(struct usbhost_driver_s *drvr, * Input Parameters: * drvr - The USB host driver instance obtained as a parameter from the * call to the class create() method. - * ep - The endpint to be freed. + * ep - The endpoint to be freed. * * Returned Value: * On success, zero (OK) is returned. On a failure, a negated errno value diff --git a/arch/arm/src/lpc43xx/lpc43_ethernet.c b/arch/arm/src/lpc43xx/lpc43_ethernet.c index cbb1f9d9f6..dae1dab96f 100644 --- a/arch/arm/src/lpc43xx/lpc43_ethernet.c +++ b/arch/arm/src/lpc43xx/lpc43_ethernet.c @@ -1660,7 +1660,7 @@ static void lpc43_receive(struct lpc43_ethmac_s *priv) } /* We are finished with the RX buffer. NOTE: If the buffer is - * re-used for transmission, the dev->d_buf field will have been + * reused for transmission, the dev->d_buf field will have been * nullified. */ @@ -1891,7 +1891,7 @@ static void lpc43_interrupt_work(void *arg) lpc43_putreg(ETH_DMAINT_NIS, LPC43_ETH_DMASTAT); } - /* Handle error interrupt only if CONFIG_DEBUG_NET is eanbled */ + /* Handle error interrupt only if CONFIG_DEBUG_NET is enabled */ #ifdef CONFIG_DEBUG_NET /* Check if there are pending "abnormal" interrupts */ diff --git a/arch/arm/src/lpc43xx/lpc43_sdmmc.c b/arch/arm/src/lpc43xx/lpc43_sdmmc.c index a93d6fcc20..e1d7649a9c 100644 --- a/arch/arm/src/lpc43xx/lpc43_sdmmc.c +++ b/arch/arm/src/lpc43xx/lpc43_sdmmc.c @@ -1946,7 +1946,7 @@ static int lpc43_waitresponse(struct sdio_dev_s *dev, uint32_t cmd) * * Returned Value: * Number of bytes sent on success; a negated errno on failure. Here a - * failure means only a faiure to obtain the requested response (due to + * failure means only a failure to obtain the requested response (due to * transport problem -- timeout, CRC, etc.). The implementation only * assures that the response is returned intacta and does not check errors * within the response itself. diff --git a/arch/arm/src/lpc43xx/lpc43_serial.c b/arch/arm/src/lpc43xx/lpc43_serial.c index 9d0c79cb00..28f1db3da2 100644 --- a/arch/arm/src/lpc43xx/lpc43_serial.c +++ b/arch/arm/src/lpc43xx/lpc43_serial.c @@ -1264,7 +1264,7 @@ static bool up_txempty(struct uart_dev_s *dev) * * Description: * Performs the low level UART initialization early in debug so that the - * serial console will be available during bootup. This must be called + * serial console will be available during boot up. This must be called * before arm_serialinit. * * NOTE: Configuration of the CONSOLE UART was performed by up_lowsetup() diff --git a/arch/arm/src/lpc43xx/lpc43_spi.c b/arch/arm/src/lpc43xx/lpc43_spi.c index 42a71467ac..98768e8c56 100644 --- a/arch/arm/src/lpc43xx/lpc43_spi.c +++ b/arch/arm/src/lpc43xx/lpc43_spi.c @@ -206,7 +206,7 @@ static uint32_t spi_setfrequency(struct spi_dev_s *dev, uint32_t divisor; uint32_t actual; - /* Check if the requested frequence is the same as the frequency + /* Check if the requested frequency is the same as the frequency * selection. */ diff --git a/arch/arm/src/lpc54xx/hardware/lpc54_gpio.h b/arch/arm/src/lpc54xx/hardware/lpc54_gpio.h index bb016e2883..00c610b4ca 100644 --- a/arch/arm/src/lpc54xx/hardware/lpc54_gpio.h +++ b/arch/arm/src/lpc54xx/hardware/lpc54_gpio.h @@ -50,7 +50,7 @@ #define LPC54_GPIO_B_OFFSET(p) (0x0000 + (p)) #define LPC54_GPIO_W_OFFSET(p) (0x1000 + ((p) << 2)) -/* Word access to individual port regisers */ +/* Word access to individual port registers */ #define LPC54_GPIO_PORT_OFFSET(n) ((n) << 2) #define LPC54_GPIO_DIR_OFFSET(n) (0x2000 + LPC54_GPIO_PORT_OFFSET(n)) @@ -71,7 +71,7 @@ #define LPC54_GPIO_B(p) (LPC54_GPIO_BASE + LPC54_GPIO_B_OFFSET(p)) #define LPC54_GPIO_W(p) (LPC54_GPIO_BASE + LPC54_GPIO_W_OFFSET(p)) -/* Word access to individual port regisers */ +/* Word access to individual port registers */ #define LPC54_GPIO_PORT(n) (LPC54_GPIO_BASE + LPC54_GPIO_PORT_OFFSET(n)) #define LPC54_GPIO_DIR(n) (LPC54_GPIO_BASE + LPC54_GPIO_DIR_OFFSET(n)) diff --git a/arch/arm/src/lpc54xx/hardware/lpc54_lcd.h b/arch/arm/src/lpc54xx/hardware/lpc54_lcd.h index 3d80c2c88d..09ccf20028 100644 --- a/arch/arm/src/lpc54xx/hardware/lpc54_lcd.h +++ b/arch/arm/src/lpc54xx/hardware/lpc54_lcd.h @@ -207,7 +207,7 @@ /* Bits 0: Reserved */ #define LCD_INTRAW_FUFRIS (1 << 1) /* Bit 1: FIFO Underflow raw interrupt status */ -#define LCD_INTRAW_LNBURIS (1 << 2) /* Bit 2: LCD Next address base update intterupt */ +#define LCD_INTRAW_LNBURIS (1 << 2) /* Bit 2: LCD Next address base update interrupt */ #define LCD_INTRAW_VCOMPRIS (1 << 3) /* Bit 3: Vertical compare interrupt status */ #define LCD_INTRAW_BERRAW (1 << 4) /* Bit 4: AHB Master bus error interrupt status */ /* Bits 5-31: Reserved */ @@ -217,7 +217,7 @@ /* Bits 0: Reserved */ #define LCD_INTSTAT_FUFMIS (1 << 1) /* Bit 1: FIFO Underflow raw interrupt status */ -#define LCD_INTSTAT_LNBUMIS (1 << 2) /* Bit 2: LCD Next address base update intterupt */ +#define LCD_INTSTAT_LNBUMIS (1 << 2) /* Bit 2: LCD Next address base update interrupt */ #define LCD_INTSTAT_VCOMPMIS (1 << 3) /* Bit 3: Vertical compare interrupt status */ #define LCD_INTSTAT_BERMIS (1 << 4) /* Bit 4: AHB Master bus error interrupt status */ /* Bits 15-31: Reserved */ @@ -227,7 +227,7 @@ /* Bits 0: Reserved */ #define LCD_INTCLR_FUFIC (1 << 1) /* Bit 1: FIFO Underflow raw interrupt clear */ -#define LCD_INTCLR_LNBUIC (1 << 2) /* Bit 2: LCD Next address base update intterupt */ +#define LCD_INTCLR_LNBUIC (1 << 2) /* Bit 2: LCD Next address base update interrupt */ #define LCD_INTCLR_VCOMPIC (1 << 3) /* Bit 3: Vertical compare interrupt clear */ #define LCD_INTCLR_BERIC (1 << 4) /* Bit 4: AHB Master bus error interrupt clear */ /* Bits 15-31: Reserved */ @@ -290,7 +290,7 @@ /* LCD CRSR_PAL0/1 - Cursor Palette Registers */ -#define LCD_CRSR_PAL_RED_SHIFT (0) /* Bits 0-7: Red color componnent */ +#define LCD_CRSR_PAL_RED_SHIFT (0) /* Bits 0-7: Red color component */ #define LCD_CRSR_PAL_RED_MASK (0xff << LCD_CRSR_PAL0_RED_SHIFT) #define LCD_CRSR_PAL_GREEN_SHIFT (8) /* Bits 8-15: Green color component */ #define LCD_CRSR_PAL_GREEN_MASK (0xff << LCD_CRSR_PAL0_GREEN_SHIFT) diff --git a/arch/arm/src/lpc54xx/lpc54_emc.h b/arch/arm/src/lpc54xx/lpc54_emc.h index 392d3a79d8..c9725bbf9c 100644 --- a/arch/arm/src/lpc54xx/lpc54_emc.h +++ b/arch/arm/src/lpc54xx/lpc54_emc.h @@ -167,7 +167,7 @@ struct emc_static_chip_config_s * emc_static_special_config_e settings */ uint32_t waitwriteen; /* The delay form chip select to write enable in * units of nanoseconds */ - uint32_t waitouten; /* The delay from chip selcet to output enable in + uint32_t waitouten; /* The delay from chip select to output enable in * units of nanoseconds */ uint32_t waitread; /* In No-page mode, the delay from chip select to * read access in units of nanoseconds */ diff --git a/arch/arm/src/lpc54xx/lpc54_ethernet.c b/arch/arm/src/lpc54xx/lpc54_ethernet.c index c2343ecbf9..3cd62bc336 100644 --- a/arch/arm/src/lpc54xx/lpc54_ethernet.c +++ b/arch/arm/src/lpc54xx/lpc54_ethernet.c @@ -2651,7 +2651,7 @@ static void lpc54_phy_write(struct lpc54_ethdriver_s *priv, * Name: lpc54_phy_linkstatus * * Description: - * Read the MII status register and return tru if the link is up. + * Read the MII status register and return true if the link is up. * * Input Parameters: * priv - Reference to the driver state structure @@ -2663,7 +2663,7 @@ static void lpc54_phy_write(struct lpc54_ethdriver_s *priv, static inline bool lpc54_phy_linkstatus(struct lpc54_ethdriver_s *priv) { - /* Read the status register and return tru of the linkstatus bit is set. */ + /* Read the status register and return true if the linkstatus bit is set. */ return ((lpc54_phy_read(priv, MII_MSR) & MII_MSR_LINKSTATUS) != 0); } diff --git a/arch/arm/src/lpc54xx/lpc54_gpio.c b/arch/arm/src/lpc54xx/lpc54_gpio.c index 19cf128bde..f7b8970d7a 100644 --- a/arch/arm/src/lpc54xx/lpc54_gpio.c +++ b/arch/arm/src/lpc54xx/lpc54_gpio.c @@ -376,7 +376,7 @@ int lpc54_gpio_config(lpc54_pinset_t cfgset) break; #endif - case GPIO_OUTPUT: /* GPIO outpout pin */ + case GPIO_OUTPUT: /* GPIO output pin */ lpc54_gpio_output(cfgset, port, pin); break; diff --git a/arch/arm/src/lpc54xx/lpc54_gpio.h b/arch/arm/src/lpc54xx/lpc54_gpio.h index fc8d3464d4..5134f8d75a 100644 --- a/arch/arm/src/lpc54xx/lpc54_gpio.h +++ b/arch/arm/src/lpc54xx/lpc54_gpio.h @@ -249,7 +249,7 @@ extern "C" * * Description: * Initialize logic to support interrupting GPIO pins. - * This function is called by the OS inialization logic and is not a + * This function is called by the OS initialization logic and is not a * user interface. * ****************************************************************************/ diff --git a/arch/arm/src/lpc54xx/lpc54_gpioirq.c b/arch/arm/src/lpc54xx/lpc54_gpioirq.c index c103dbc947..7f34a9433b 100644 --- a/arch/arm/src/lpc54xx/lpc54_gpioirq.c +++ b/arch/arm/src/lpc54xx/lpc54_gpioirq.c @@ -80,7 +80,7 @@ static const uint8_t g_pinirq[MAX_PININT] = * * Description: * Initialize logic to support interrupting GPIO pins. This function is - * called by the OS inialization logic and is not a user interface. + * called by the OS initialization logic and is not a user interface. * ****************************************************************************/ @@ -120,7 +120,7 @@ static int lpc54_alloc_pinint(lpc54_pinset_t pinset) * * Description: * Initialize logic to support interrupting GPIO pins. This function is - * called by the OS inialization logic and is not a user interface. + * called by the OS initialization logic and is not a user interface. * ****************************************************************************/ diff --git a/arch/arm/src/lpc54xx/lpc54_i2c_master.c b/arch/arm/src/lpc54xx/lpc54_i2c_master.c index 0e61e4af8f..bcf0cd6d12 100644 --- a/arch/arm/src/lpc54xx/lpc54_i2c_master.c +++ b/arch/arm/src/lpc54xx/lpc54_i2c_master.c @@ -905,7 +905,7 @@ struct i2c_master_s *lpc54_i2cbus_initialize(int port) flags = enter_critical_section(); - /* Configure the requestin I2C peripheral */ + /* Configure the requesting I2C peripheral */ /* NOTE: The basic FLEXCOMM initialization was performed in * lpc54_lowputc.c. diff --git a/arch/arm/src/lpc54xx/lpc54_rng.c b/arch/arm/src/lpc54xx/lpc54_rng.c index 315065ee00..60c7c7b646 100644 --- a/arch/arm/src/lpc54xx/lpc54_rng.c +++ b/arch/arm/src/lpc54xx/lpc54_rng.c @@ -97,7 +97,7 @@ static ssize_t lpc54_read(struct file *filep, char *buffer, size_t buflen) return ret; } - /* Copy the requested number of randome bytes. */ + /* Copy the requested number of random bytes. */ for (remaining = buflen; remaining > 0; diff --git a/arch/arm/src/lpc54xx/lpc54_sdmmc.c b/arch/arm/src/lpc54xx/lpc54_sdmmc.c index 84109a8d99..66af795aa3 100644 --- a/arch/arm/src/lpc54xx/lpc54_sdmmc.c +++ b/arch/arm/src/lpc54xx/lpc54_sdmmc.c @@ -1942,7 +1942,7 @@ static int lpc54_waitresponse(struct sdio_dev_s *dev, uint32_t cmd) * * Returned Value: * Number of bytes sent on success; a negated errno on failure. Here a - * failure means only a faiure to obtain the requested response (due to + * failure means only a failure to obtain the requested response (due to * transport problem -- timeout, CRC, etc.). The implementation only * assures that the response is returned intacta and does not check errors * within the response itself. diff --git a/arch/arm/src/lpc54xx/lpc54_serial.c b/arch/arm/src/lpc54xx/lpc54_serial.c index d960821620..8d3c2d9938 100644 --- a/arch/arm/src/lpc54xx/lpc54_serial.c +++ b/arch/arm/src/lpc54xx/lpc54_serial.c @@ -1340,7 +1340,7 @@ static bool lpc54_txempty(struct uart_dev_s *dev) * * Description: * Performs the low level USART initialization early in debug so that the - * serial console will be available during bootup. This must be called + * serial console will be available during boot up. This must be called * before lpc54_serialinit. NOTE: This function depends on GPIO pin * configuration performed in lpc54_lowsetup() and main clock * initialization performed in lpc54_clockconfig(). diff --git a/arch/arm/src/lpc54xx/lpc54_serial.h b/arch/arm/src/lpc54xx/lpc54_serial.h index 5a33ede1e6..0050647dca 100644 --- a/arch/arm/src/lpc54xx/lpc54_serial.h +++ b/arch/arm/src/lpc54xx/lpc54_serial.h @@ -39,7 +39,7 @@ * * Description: * Performs the low level USART initialization early in debug so that the - * serial console will be available during bootup. This must be called + * serial console will be available during boot up. This must be called * before lpc54_serialinit. NOTE: This function depends on GPIO pin * configuration performed in lpc54_lowsetup() and main clock * initialization performed in lpc54_clockconfig(). diff --git a/arch/arm/src/lpc54xx/lpc54_usb0_ohci.c b/arch/arm/src/lpc54xx/lpc54_usb0_ohci.c index 2e862240d2..c2b1db2f83 100644 --- a/arch/arm/src/lpc54xx/lpc54_usb0_ohci.c +++ b/arch/arm/src/lpc54xx/lpc54_usb0_ohci.c @@ -2463,7 +2463,7 @@ static int lpc54_epalloc(struct usbhost_driver_s *drvr, * Input Parameters: * drvr - The USB host driver instance obtained as a parameter from the * call to the class create() method. - * ep - The endpint to be freed. + * ep - The endpoint to be freed. * * Returned Value: * On success, zero (OK) is returned. On a failure, a negated errno value diff --git a/arch/arm/src/max326xx/common/max326_start.c b/arch/arm/src/max326xx/common/max326_start.c index 44628e0815..fff5281f69 100644 --- a/arch/arm/src/max326xx/common/max326_start.c +++ b/arch/arm/src/max326xx/common/max326_start.c @@ -53,7 +53,7 @@ * 0x0000:0000 - Beginning of FLASH. Address of exception vectors. * 0x0003:ffff - End of flash (assuming 256KB of FLASH) * 0x2000:0000 - Start of SRAM and start of .data (_sdata) - * - End of .data (_edata) abd start of .bss (_sbss) + * - End of .data (_edata) and start of .bss (_sbss) * - End of .bss (_ebss) and bottom of idle stack * - _ebss + CONFIG_IDLETHREAD_STACKSIZE = end of idle stack, * start of heap diff --git a/arch/arm/src/max326xx/max32660/max32660_serial.c b/arch/arm/src/max326xx/max32660/max32660_serial.c index 2690c39f85..1bd45dbabe 100644 --- a/arch/arm/src/max326xx/max32660/max32660_serial.c +++ b/arch/arm/src/max326xx/max32660/max32660_serial.c @@ -763,7 +763,7 @@ static bool max326_txempty(struct uart_dev_s *dev) * * Description: * Performs the low level UART initialization early in debug so that the - * serial console will be available during bootup. This must be called + * serial console will be available during boot up. This must be called * before max326_serialinit. NOTE: This function depends on GPIO pin * configuration performed in max326_lowsetup() and main clock * initialization performed in max326_clockconfig(). diff --git a/arch/arm/src/max326xx/max32690/max32690_gpioirq.c b/arch/arm/src/max326xx/max32690/max32690_gpioirq.c index 270bd52bd4..d43a7d63aa 100644 --- a/arch/arm/src/max326xx/max32690/max32690_gpioirq.c +++ b/arch/arm/src/max326xx/max32690/max32690_gpioirq.c @@ -163,7 +163,7 @@ void max32690_gpio_irq_enable(max32690_pinconfig_t pinconf) int bank = pinconf.gpio_bank; irq_infos[bank].irq_handler[pinconf.pin] = pinconf.irq_handler; - /* enable the interupt for the gpio bank */ + /* enable the interrupt for the gpio bank */ if (irq_infos[pinconf.gpio_bank].int_enabled == 0) { diff --git a/arch/arm/src/max326xx/max326_serial.h b/arch/arm/src/max326xx/max326_serial.h index 201891804f..a62ee0ae2f 100644 --- a/arch/arm/src/max326xx/max326_serial.h +++ b/arch/arm/src/max326xx/max326_serial.h @@ -39,7 +39,7 @@ * * Description: * Performs the low level USART initialization early in debug so that the - * serial console will be available during bootup. This must be called + * serial console will be available during boot up. This must be called * before max326_serialinit. NOTE: This function depends on GPIO pin * configuration performed in xmc_lowsetup() and main clock initialization * performed in xmc_clock_configure(). diff --git a/arch/arm/src/mcx-nxxx/nxxx_lowputc.c b/arch/arm/src/mcx-nxxx/nxxx_lowputc.c index 6b696e9c29..ab6133760e 100644 --- a/arch/arm/src/mcx-nxxx/nxxx_lowputc.c +++ b/arch/arm/src/mcx-nxxx/nxxx_lowputc.c @@ -563,7 +563,7 @@ void arm_lowputc(char ch) } /* If the character to output is a newline, - * then pre-pend a carriage return + * then prepend a carriage return. */ if (ch == '\n') diff --git a/arch/arm/src/mcx-nxxx/nxxx_lpuart.c b/arch/arm/src/mcx-nxxx/nxxx_lpuart.c index 4f3a31dcc3..767fc52555 100644 --- a/arch/arm/src/mcx-nxxx/nxxx_lpuart.c +++ b/arch/arm/src/mcx-nxxx/nxxx_lpuart.c @@ -1271,7 +1271,7 @@ static int nxxx_dma_setup(struct uart_dev_s *dev) modifyreg32(priv->uartbase + NXXX_LPUART_BAUD_OFFSET, 0, LPUART_BAUD_RDMAE); - /* Enable interrupt on idle and erros */ + /* Enable interrupt on idle and errors */ modifyreg32(priv->uartbase + NXXX_LPUART_CTRL_OFFSET, 0, LPUART_CTRL_PEIE | @@ -2547,7 +2547,7 @@ static int up_pm_prepare(struct pm_callback_s *cb, int domain, * * Description: * Performs the low level UART initialization early in debug so that the - * serial console will be available during bootup. This must be called + * serial console will be available during boot up. This must be called * before arm_serialinit. * ****************************************************************************/ diff --git a/arch/arm/src/mps/mps_serial.c b/arch/arm/src/mps/mps_serial.c index 38858841a7..fefe125c4b 100644 --- a/arch/arm/src/mps/mps_serial.c +++ b/arch/arm/src/mps/mps_serial.c @@ -53,7 +53,7 @@ void arm_serialinit(void) * * Description: * Performs the low level UART initialization early in debug so that the - * serial console will be available during bootup. This must be called + * serial console will be available during boot up. This must be called * before arm_serialinit. * ***************************************************************************/ diff --git a/arch/arm/src/mx8mp/hardware/mx8mp_ccm.h b/arch/arm/src/mx8mp/hardware/mx8mp_ccm.h index a8a4867375..0bff24ba83 100644 --- a/arch/arm/src/mx8mp/hardware/mx8mp_ccm.h +++ b/arch/arm/src/mx8mp/hardware/mx8mp_ccm.h @@ -348,9 +348,9 @@ #define AUDIO_PLL2_CLK 36 #define VIDEO_PLL_CLK 37 -/* Theses definitions values are arbitrary: previous definitions +/* These definitions values are arbitrary: previous definitions * are used in both PLL_CTRL and clock tree mapping while - * theses definitions have no meaning for PLL_CTR (since they are + * these definitions have no meaning for PLL_CTR (since they are * external clock source) but are still use in clock tree mapping. */ diff --git a/arch/arm/src/mx8mp/mx8mp_config.h b/arch/arm/src/mx8mp/mx8mp_config.h index 75a3e80839..0ea98251f8 100644 --- a/arch/arm/src/mx8mp/mx8mp_config.h +++ b/arch/arm/src/mx8mp/mx8mp_config.h @@ -66,10 +66,10 @@ # undef HAVE_UART_CONSOLE #endif -/* Ensure that the MPU is enabled: it is requiered to access devices */ +/* Ensure that the MPU is enabled: it is required to access devices */ #ifndef CONFIG_ARM_MPU -#error "MPU is requiered for proper behavior" +#error "MPU is required for proper behavior" #endif #endif /* __ARCH_ARM_SRC_MX8MP_MX8MP_CONFIG_H */ diff --git a/arch/arm/src/mx8mp/mx8mp_ecspi.c b/arch/arm/src/mx8mp/mx8mp_ecspi.c index d2d3bd1ad8..4126ba5588 100644 --- a/arch/arm/src/mx8mp/mx8mp_ecspi.c +++ b/arch/arm/src/mx8mp/mx8mp_ecspi.c @@ -332,7 +332,7 @@ static int mx8mp_spi_transfer(struct mx8mp_spi_s *priv, return ret; } - /* 6. Unload RX FIFO (even if an error occured to empty the queue) */ + /* 6. Unload RX FIFO (even if an error occurred to empty the queue) */ if (remaining_bytes) { diff --git a/arch/arm/src/mx8mp/mx8mp_i2c.c b/arch/arm/src/mx8mp/mx8mp_i2c.c index 1f081d6f37..7c315b9651 100644 --- a/arch/arm/src/mx8mp/mx8mp_i2c.c +++ b/arch/arm/src/mx8mp/mx8mp_i2c.c @@ -707,7 +707,7 @@ static int mx8mp_i2c_reset(struct i2c_master_s *dev) mx8mp_i2c_reset_bus(priv); - /* Release the port for re-use by other clients */ + /* Release the port for reuse by other clients */ nxmutex_unlock(&priv->lock); diff --git a/arch/arm/src/mx8mp/mx8mp_iomuxc.h b/arch/arm/src/mx8mp/mx8mp_iomuxc.h index 922660ec7d..fc430bbb6f 100644 --- a/arch/arm/src/mx8mp/mx8mp_iomuxc.h +++ b/arch/arm/src/mx8mp/mx8mp_iomuxc.h @@ -39,7 +39,7 @@ * Name: mx8mp_iomuxc_set_pin_config * * Description: - * Congigure the IOMUXC pin configuration. + * Configure the IOMUXC pin configuration. * The first five parameters can be filled with the pin function ID macros. * ****************************************************************************/ diff --git a/arch/arm/src/mx8mp/mx8mp_serial.c b/arch/arm/src/mx8mp/mx8mp_serial.c index c9420266f3..05db0d07f4 100644 --- a/arch/arm/src/mx8mp/mx8mp_serial.c +++ b/arch/arm/src/mx8mp/mx8mp_serial.c @@ -997,7 +997,7 @@ static bool mx8mp_txempty(struct uart_dev_s *dev) * Description: * Performs the low level UART initialization early in * debug so that the serial console will be available - * during bootup. This must be called before arm_serialinit. + * during boot up. This must be called before arm_serialinit. * ****************************************************************************/ diff --git a/arch/arm/src/nrf52/hardware/nrf52_clock.h b/arch/arm/src/nrf52/hardware/nrf52_clock.h index 00fe3deeb7..ed0c37ce14 100644 --- a/arch/arm/src/nrf52/hardware/nrf52_clock.h +++ b/arch/arm/src/nrf52/hardware/nrf52_clock.h @@ -122,7 +122,7 @@ #define CLOCK_HFCLKSTAT_SRC_SHIFT (0) /* Bit 0: Source of HFCLK */ #define CLOCK_HFCLKSTAT_SRC_MASK (1 << CLOCK_HFCLKSTAT_SRC_SHIFT) # define CLOCK_HFCLKSTAT_SRC_RC (0 << CLOCK_HFCLKSTAT_SRC_SHIFT) /* 0b0: 64 MHz internal oscillator (HFINT) */ -# define CLOCK_HFCLKSTAT_SRC_XTAL (1 << CLOCK_HFCLKSTAT_SRC_SHIFT) /* 0b1: 64 MHz crystal oscilator (HFXO) */ +# define CLOCK_HFCLKSTAT_SRC_XTAL (1 << CLOCK_HFCLKSTAT_SRC_SHIFT) /* 0b1: 64 MHz crystal oscillator (HFXO) */ #define CLOCK_HFCLKSTAT_STATE (1 << 16) /* Bit 16: HFCLK state */ /* LFCLKRUN Register */ diff --git a/arch/arm/src/nrf52/nrf52_adc.c b/arch/arm/src/nrf52/nrf52_adc.c index c0502a9e74..19e32ac3e0 100644 --- a/arch/arm/src/nrf52/nrf52_adc.c +++ b/arch/arm/src/nrf52/nrf52_adc.c @@ -936,7 +936,7 @@ struct adc_dev_s *nrf52_adcinitialize( #ifdef CONFIG_NRF52_SAADC_TIMER if (channels > 1) { - aerr("ERORR: timer trigger works only for 1 channel!\n"); + aerr("ERROR: timer trigger works only for 1 channel!\n"); goto errout; } #endif diff --git a/arch/arm/src/nrf52/nrf52_gpio.c b/arch/arm/src/nrf52/nrf52_gpio.c index c650a8ce3b..61894872b6 100644 --- a/arch/arm/src/nrf52/nrf52_gpio.c +++ b/arch/arm/src/nrf52/nrf52_gpio.c @@ -308,7 +308,7 @@ int nrf52_gpio_config(nrf52_pinset_t cfgset) nrf52_gpio_sense(cfgset, port, pin); break; - case GPIO_OUTPUT: /* GPIO outpout pin */ + case GPIO_OUTPUT: /* GPIO output pin */ nrf52_gpio_output(cfgset, port, pin); break; diff --git a/arch/arm/src/nrf52/nrf52_gpiote.c b/arch/arm/src/nrf52/nrf52_gpiote.c index 7271157828..c0d637fa82 100644 --- a/arch/arm/src/nrf52/nrf52_gpiote.c +++ b/arch/arm/src/nrf52/nrf52_gpiote.c @@ -440,7 +440,7 @@ void nrf52_gpiote_set_ch_event(uint32_t pinset, int channel, * * Description: * Configures a GPIOTE channel in EVENT mode, assigns it to a given pin - * and sets a handler for the first availalbe GPIOTE channel + * and sets a handler for the first available GPIOTE channel. * * Input Parameters: * - pinset: GPIO pin configuration diff --git a/arch/arm/src/nrf52/nrf52_gpiote.h b/arch/arm/src/nrf52/nrf52_gpiote.h index 4fe76bc9d5..b36bd0ec45 100644 --- a/arch/arm/src/nrf52/nrf52_gpiote.h +++ b/arch/arm/src/nrf52/nrf52_gpiote.h @@ -76,7 +76,7 @@ void nrf52_gpiote_set_ch_event(uint32_t pinset, int channel, * * Description: * Configures a GPIOTE channel in EVENT mode, assigns it to a given pin - * and sets a handler for the first availalbe GPIOTE channel + * and sets a handler for the first available GPIOTE channel. * * Input Parameters: * - pinset: GPIO pin configuration diff --git a/arch/arm/src/nrf52/nrf52_ieee802154.c b/arch/arm/src/nrf52/nrf52_ieee802154.c index ed032dbd1b..2089e9e506 100644 --- a/arch/arm/src/nrf52/nrf52_ieee802154.c +++ b/arch/arm/src/nrf52/nrf52_ieee802154.c @@ -587,7 +587,7 @@ static int nrf52_radioi8_txdelayed(struct ieee802154_radio_s *radio, return -EBUSY; } - /* Wait for ACKTX done - we start transmition in + /* Wait for ACKTX done - we start transmission in * nrf52_radioi8_state_acktx() */ @@ -759,7 +759,7 @@ nrf52_radioi8_beaconstart(struct ieee802154_radio_s *radio, memcpy(&dev->state.sf, (void *)sfspec, sizeof(struct ieee802154_superframespec_s)); - /* Setup beacon transmition */ + /* Setup beacon transmission */ dev->radio->ops->beacon_setup(dev, beacon->bf_data, beacon->bf_len); diff --git a/arch/arm/src/nrf52/nrf52_ieee802154_radio.c b/arch/arm/src/nrf52/nrf52_ieee802154_radio.c index 1898a7e252..2ad3a538ea 100644 --- a/arch/arm/src/nrf52/nrf52_ieee802154_radio.c +++ b/arch/arm/src/nrf52/nrf52_ieee802154_radio.c @@ -397,7 +397,7 @@ static void nrf52_radioi8_ack_transmit(struct nrf52_radioi8_dev_s *dev) pending = true; } - /* Set frame pedning flag for this ACK */ + /* Set frame pending flag for this ACK */ if (pending) { @@ -582,7 +582,7 @@ static void nrf52_radioi8_dopoll_gts(void *arg) * Name: nrf52_radioi8_txstart * * Description: - * Start transmition, TX must be armed (TXEN must be set). + * Start transmission, TX must be armed (TXEN must be set). * ****************************************************************************/ @@ -692,7 +692,7 @@ static int nrf52_radioi8_rxenable(struct nrf52_radioi8_dev_s *dev, { nrf52_radioi8_trace_put(RADIO_TRACE_RXDISABLE, 0); - /* Disalbe interrups and shorts */ + /* Disable interrupts and shorts */ NRF52_RADIO_INTCLR(lower, IEEE802154_RX_INT); NRF52_RADIO_SHRTSET(lower, 0); @@ -792,7 +792,7 @@ static int nrf52_radioi8_setcca(struct nrf52_radioi8_dev_s *dev, DEBUGASSERT(dev); lower = dev->radio->lower; - /* Fill radio sturcture */ + /* Fill radio structure */ memset(&c, 0, sizeof(struct nrf52_radio_cca_s)); @@ -839,7 +839,7 @@ static void nrf52_radioi8_norm_setup_buf(struct nrf52_radioi8_dev_s *dev, nrf52_radioi8_trace_put(RADIO_TRACE_CSMASETUP, csma); - /* If RX is enabled - we have to temporarly disable it */ + /* If RX is enabled - we have to temporarily disable it */ if (dev->radio->state.rxenabled) { @@ -1054,14 +1054,14 @@ static void nrf52_radioi8_norm_trigger(struct nrf52_radioi8_dev_s *dev) dev->radio->state.waitack = true; } - /* CSMA transmition */ + /* CSMA transmission */ if (dev->radio->state.state == NRF52_RADIO_STATE_TX_CSMA) { nrf52_radioi8_trg_csma(dev); } - /* No-CSMA transmition */ + /* No-CSMA transmission */ else if (dev->radio->state.state == NRF52_RADIO_STATE_TX_NOCSMA) { @@ -1145,7 +1145,7 @@ static int nrf52_radioi8_reset(struct nrf52_radioi8_radio_s *dev) NRF52_RADIO_RESET(radio); - /* MAC prameters */ + /* MAC parameters */ dev->state.max_frame_waittime = IEEE802154_MAX_FRAME_WAITTIME; dev->state.max_csma_backoffs = IEEE802154_MAX_CSMA_BACKOFFS; @@ -1705,7 +1705,7 @@ static void nrf52_radioi8_state_rx(struct nrf52_radioi8_dev_s *dev) dev->radio->state.waitack = false; - /* Get frame pedning flag */ + /* Get frame pending flag */ dev->radio->state.framepending = rxbuf[1] & 0x10; @@ -1796,7 +1796,7 @@ static void nrf52_radioi8_state_tx(struct nrf52_radioi8_dev_s *dev) if (dev->radio->state.NB > dev->radio->state.max_csma_backoffs) { - /* Return fauilure to MAC */ + /* Return failure to MAC */ if (work_available(&dev->radio->irqwork)) { @@ -1832,7 +1832,7 @@ static void nrf52_radioi8_state_tx(struct nrf52_radioi8_dev_s *dev) if (dev->radio->state.NB > dev->radio->state.max_csma_backoffs) { - /* Return fauilure to MAC */ + /* Return failure to MAC */ if (work_available(&dev->radio->irqwork)) { @@ -2010,7 +2010,7 @@ static int nrf52_radioi8_isr_radio(int irq, void *context, void *arg) NRF52_RADIO_PUTREG(lower, NRF52_RADIO_TASKS_DISABLE_OFFSET, 1); /* Don't wait for the DISABLED event, hopefully the radio will be - * disabled by the time we use it again. Max delay is TX->DSIABLED + * disabled by the time we use it again. Max delay is TX->DISABLED * and takes 21us. */ } diff --git a/arch/arm/src/nrf52/nrf52_ieee802154_radio.h b/arch/arm/src/nrf52/nrf52_ieee802154_radio.h index 76960aa466..7bb4577425 100644 --- a/arch/arm/src/nrf52/nrf52_ieee802154_radio.h +++ b/arch/arm/src/nrf52/nrf52_ieee802154_radio.h @@ -66,7 +66,7 @@ enum nrf52_radioi8_state_e NRF52_RADIO_STATE_TX_NOCSMA, /* Non CSMA TX armed */ NRF52_RADIO_STATE_TX, /* TX on the air */ NRF52_RADIO_STATE_RX, /* RX active */ - NRF52_RADIO_STATE_ACKTX, /* Transmiting ACK now */ + NRF52_RADIO_STATE_ACKTX, /* Transmitting ACK now */ NRF52_RADIO_STATE_ED, /* Energy detection now */ }; @@ -123,7 +123,7 @@ struct ieee802154_cca_s; struct nrf52_radioi8_radio_ops_s { - /* Start transmition - TX must be armed (TXEN set) */ + /* Start transmission - TX must be armed (TXEN set) */ void (*txstart)(struct nrf52_radioi8_dev_s *dev); diff --git a/arch/arm/src/nrf52/nrf52_ieee802154_rtc.c b/arch/arm/src/nrf52/nrf52_ieee802154_rtc.c index bdfd92c371..ce33257851 100644 --- a/arch/arm/src/nrf52/nrf52_ieee802154_rtc.c +++ b/arch/arm/src/nrf52/nrf52_ieee802154_rtc.c @@ -157,7 +157,7 @@ static int nrf52_radioi8_rtc(struct nrf52_radioi8_dev_s *dev, dev->rtc->rtc_timeslot = NRF52_RTC_TIMESLOT_CC; NRF52_RTC_SETCC(dev->rtc->rtc, NRF52_RTC_TIMESLOT, dev->rtc->rtc_timeslot); - /* Configure interupts */ + /* Configure interrupts */ NRF52_RTC_ENABLEINT(dev->rtc->rtc, NRF52_RTC_BI); NRF52_RTC_ENABLEINT(dev->rtc->rtc, NRF52_RTC_SD); @@ -328,7 +328,7 @@ static int nrf52_radioi8_isr_rtc(int irq, void *context, void *arg) { nrf52_radioi8_trace_put(RADIO_TRACE_IRQ_RTCTIMESLOT, 0); - /* TODO: how to sync transmition with timeslot ? + /* TODO: how to sync transmission with timeslot ? * do we need count every timeslot here ? * or wait for the timeslot we are interested in ? * or just use txdelay ? @@ -357,7 +357,7 @@ static int nrf52_radioi8_isr_rtc(int irq, void *context, void *arg) * Name: nrf52_radioi8_rtc_init * * Description: - * Initialize low resoluton, low power timer for IEEE802154 operations. + * Initialize low resolution, low power timer for IEEE802154 operations. * Used to handle superframe timings. * ****************************************************************************/ @@ -376,7 +376,7 @@ nrf52_radioi8_rtc_init(struct nrf52_radioi8_dev_s *dev) return NULL; } - /* Atach RTC interrupt */ + /* Attach RTC interrupt */ NRF52_RTC_SETISR(rtc, nrf52_radioi8_isr_rtc, dev); diff --git a/arch/arm/src/nrf52/nrf52_ieee802154_rtc.h b/arch/arm/src/nrf52/nrf52_ieee802154_rtc.h index f011a28977..21767c9e02 100644 --- a/arch/arm/src/nrf52/nrf52_ieee802154_rtc.h +++ b/arch/arm/src/nrf52/nrf52_ieee802154_rtc.h @@ -107,7 +107,7 @@ struct nrf52_radioi8_rtc_s * Name: nrf52_radioi8_rtc_init * * Description: - * Initialize low resoluton, low power timer for IEEE802154 operations. + * Initialize low resolution, low power timer for IEEE802154 operations. * Used to handle superframe timings. * ****************************************************************************/ diff --git a/arch/arm/src/nrf52/nrf52_ieee802154_tim.c b/arch/arm/src/nrf52/nrf52_ieee802154_tim.c index f2abcb495d..b25747d5c0 100644 --- a/arch/arm/src/nrf52/nrf52_ieee802154_tim.c +++ b/arch/arm/src/nrf52/nrf52_ieee802154_tim.c @@ -133,7 +133,7 @@ static int nrf52_radioi8_tim(struct nrf52_radioi8_dev_s *dev, uint8_t chan, NRF52_TIM_SETCC(tim->tim, chan, val); - /* Configure interupt */ + /* Configure interrupt */ NRF52_TIM_ENABLEINT(tim->tim, chan); @@ -311,9 +311,9 @@ static int nrf52_radioi8_isr_tim(int irq, void *context, void *arg) * Name: nrf52_radioi8_tim_init * * Description: - * Initialize high resoluton timer for IEEE802154 operations. + * Initialize high resolution timer for IEEE802154 operations. * Used to handle short radio timeouts like ACK, IFS or delayed - * transmitions. + * transmissions. * ****************************************************************************/ @@ -331,7 +331,7 @@ nrf52_radioi8_tim_init(struct nrf52_radioi8_dev_s *dev) return NULL; } - /* Atach TIMER interrupt */ + /* Attach TIMER interrupt */ NRF52_TIM_SETISR(tim, nrf52_radioi8_isr_tim, dev); diff --git a/arch/arm/src/nrf52/nrf52_ieee802154_tim.h b/arch/arm/src/nrf52/nrf52_ieee802154_tim.h index 714d034b97..3257a9eead 100644 --- a/arch/arm/src/nrf52/nrf52_ieee802154_tim.h +++ b/arch/arm/src/nrf52/nrf52_ieee802154_tim.h @@ -95,9 +95,9 @@ struct nrf52_radioi8_tim_s * Name: nrf52_radioi8_tim_init * * Description: - * Initialize high resoluton timer for IEEE802154 operations. + * Initialize high resolution timer for IEEE802154 operations. * Used to handle short radio timeouts like ACK, IFS or delayed - * transmitions. + * transmissions. * ****************************************************************************/ diff --git a/arch/arm/src/nrf52/nrf52_ieee802154_trace.h b/arch/arm/src/nrf52/nrf52_ieee802154_trace.h index ca0939f6cb..c3e553bd15 100644 --- a/arch/arm/src/nrf52/nrf52_ieee802154_trace.h +++ b/arch/arm/src/nrf52/nrf52_ieee802154_trace.h @@ -50,7 +50,7 @@ struct radio_trace_s enum radio_trace_type_e { - /* Radio interupts */ + /* Radio interrupts */ RADIO_TRACE_IRQ_RADIO, RADIO_TRACE_IRQ_RXDONE, diff --git a/arch/arm/src/nrf52/nrf52_radio.c b/arch/arm/src/nrf52/nrf52_radio.c index d7a8d8c3e5..646e0374b9 100644 --- a/arch/arm/src/nrf52/nrf52_radio.c +++ b/arch/arm/src/nrf52/nrf52_radio.c @@ -338,7 +338,7 @@ static int nrf52_radio_rssi_get(struct nrf52_radio_dev_s *dev, { uint32_t regval = 0; - /* Start the RSSI meassurement */ + /* Start the RSSI measurement */ nrf52_radio_putreg(dev, NRF52_RADIO_TASKS_RSSISTART_OFFSET, 1); @@ -925,7 +925,7 @@ static void nrf52_radio_cca_cfg(struct nrf52_radio_dev_s *dev, regval |= ((cca->corrthres << RADIO_CCACTRL_CCACORRTHRES_SHIFT) & RADIO_CCACTRL_CCACORRTHRES_MASK); - /* Limit for occurances above CCACORRTHRES */ + /* Limit for occurrences above CCACORRTHRES */ regval |= ((cca->corrcnt << RADIO_CCACTRL_CCACORRCNT_SHIFT) & RADIO_CCACTRL_CCACORRCNT_MASK); diff --git a/arch/arm/src/nrf52/nrf52_radio.h b/arch/arm/src/nrf52/nrf52_radio.h index e8b3409ed0..e4fb0d603c 100644 --- a/arch/arm/src/nrf52/nrf52_radio.h +++ b/arch/arm/src/nrf52/nrf52_radio.h @@ -160,7 +160,7 @@ enum nrf52_radio_cca_mode_e * +--------------------------------------------------------------------+ * | PHY protocol data unit (PPDU) | * +--------------------+-----+---------+-------------------------------+ - * | Preamble sequence | SFD | Lenght | PHY payload | + * | Preamble sequence | SFD | Length | PHY payload | * |--------------------+-----+---------+-------------------------------+ * | 5 octets synchronization | 1 octet | Maximum 127 octets (PSDU) | * | header (SHR) | (PHR) +-------------------------------+ @@ -222,7 +222,7 @@ struct nrf52_radio_cca_s uint8_t mode; /* CCA mode of operation */ uint8_t edthres; /* CCA energy busy threshold */ uint8_t corrthres; /* CCA correlator busy threshold */ - uint8_t corrcnt; /* Limit for occurances above CCACORRTHRES */ + uint8_t corrcnt; /* Limit for occurrences above CCACORRTHRES */ }; #endif diff --git a/arch/arm/src/nrf52/nrf52_serial.c b/arch/arm/src/nrf52/nrf52_serial.c index bd7935d9e5..51c0a197db 100644 --- a/arch/arm/src/nrf52/nrf52_serial.c +++ b/arch/arm/src/nrf52/nrf52_serial.c @@ -731,7 +731,7 @@ static bool nrf52_txempty(struct uart_dev_s *dev) * * Description: * Performs the low level UART initialization early in debug so that the - * serial console will be available during bootup. This must be called + * serial console will be available during boot up. This must be called * before nrf52_serialinit. NOTE: This function depends on GPIO pin * configuration performed in nrf52_lowsetup() and main clock * initialization performed in nrf_clock_configure(). diff --git a/arch/arm/src/nrf52/nrf52_serial.h b/arch/arm/src/nrf52/nrf52_serial.h index a8a01811fd..1466f35b05 100644 --- a/arch/arm/src/nrf52/nrf52_serial.h +++ b/arch/arm/src/nrf52/nrf52_serial.h @@ -39,7 +39,7 @@ * * Description: * Performs the low level UART initialization early in debug so that the - * serial console will be available during bootup. This must be called + * serial console will be available during boot up. This must be called * before nrf52_serialinit. NOTE: This function depends on GPIO pin * configuration performed in xmc_lowsetup() and main clock initialization * performed in xmc_clock_configure(). diff --git a/arch/arm/src/nrf52/nrf52_usbd.c b/arch/arm/src/nrf52/nrf52_usbd.c index 9435d66dc7..26d859d16f 100644 --- a/arch/arm/src/nrf52/nrf52_usbd.c +++ b/arch/arm/src/nrf52/nrf52_usbd.c @@ -698,8 +698,8 @@ static bool nrf52_req_addlast(struct nrf52_ep_s *privep, * Name: nrf52_ep0out_stdrequest * * Description: - * Handle a stanard request on EP0. Pick off the things of interest to the - * USB device controller driver; pass what is left to the class driver. + * Handle a standard request on EP0. Pick off the things of interest to + * the USB device controller driver; pass what is left to the class driver. * ****************************************************************************/ @@ -1060,7 +1060,7 @@ static void nrf52_epin_transfer(struct nrf52_ep_s *privep, uint8_t *buf, * Name: nrf52_epout_allow * * Description: - * Allow OUT trafic on this endpoint + * Allow OUT traffic on this endpoint * ****************************************************************************/ @@ -1623,7 +1623,7 @@ static void nrf52_usbreset(struct nrf52_usbdev_s *priv) privep->stalled = false; - /* Stop EPIN taks */ + /* Stop EPIN task */ nrf52_epin_stop(priv, i); @@ -1636,7 +1636,7 @@ static void nrf52_usbreset(struct nrf52_usbdev_s *priv) privep->stalled = false; - /* Stop EPOUT taks */ + /* Stop EPOUT task */ nrf52_epout_stop(priv, i); } @@ -2572,7 +2572,7 @@ static int nrf52_ep_submit(struct usbdev_ep_s *ep, struct usbdev_req_s *req) { usbtrace(TRACE_OUTREQQUEUED(privep->epphy), privreq->req.len); - /* Allow OUT trafic on this endpoint */ + /* Allow OUT traffic on this endpoint */ nrf52_epout_allow(privep); } @@ -2635,7 +2635,7 @@ static int nrf52_ep_setstall(struct nrf52_ep_s *privep) regval |= USBD_EPSTALL_IO_OUT; } - /* Unstall a given EP */ + /* Un-stall a given EP */ regval |= USBD_EPSTALL_EP(privep->epphy) | USBD_EPSTALL_IO_STALL; nrf52_putreg(regval, NRF52_USBD_EPSTALL); @@ -2669,7 +2669,7 @@ static int nrf52_ep_clrstall(struct nrf52_ep_s *privep) regval |= USBD_EPSTALL_IO_OUT; } - /* Unstall a given EP */ + /* Un-stall a given EP */ regval |= USBD_EPSTALL_EP(privep->epphy) | USBD_EPSTALL_IO_UNSTALL; nrf52_putreg(regval, NRF52_USBD_EPSTALL); @@ -3105,7 +3105,7 @@ void arm_usbinitialize(void) arm_usbuninitialize(); - /* Initialie the driver data structure */ + /* Initialize the driver data structure */ nrf52_swinitialize(priv); diff --git a/arch/arm/src/nrf53/hardware/nrf53_clock.h b/arch/arm/src/nrf53/hardware/nrf53_clock.h index c466133b10..494679058d 100644 --- a/arch/arm/src/nrf53/hardware/nrf53_clock.h +++ b/arch/arm/src/nrf53/hardware/nrf53_clock.h @@ -127,7 +127,7 @@ #define CLOCK_HFCLKSTAT_SRC_SHIFT (0) /* Bit 0: Source of HFCLK */ #define CLOCK_HFCLKSTAT_SRC_MASK (1 << CLOCK_HFCLKSTAT_SRC_SHIFT) # define CLOCK_HFCLKSTAT_SRC_HFINT (0 << CLOCK_HFCLKSTAT_SRC_SHIFT) /* 0b0: 128 MHz internal oscillator (HFINT) */ -# define CLOCK_HFCLKSTAT_SRC_HFXO (1 << CLOCK_HFCLKSTAT_SRC_SHIFT) /* 0b1: 128 MHz crystal oscilator (HFXO) */ +# define CLOCK_HFCLKSTAT_SRC_HFXO (1 << CLOCK_HFCLKSTAT_SRC_SHIFT) /* 0b1: 128 MHz crystal oscillator (HFXO) */ #define CLOCK_HFCLKSTAT_ALWAYSRUNNING (1 << 4) /* Bit 4: Oscillator is always running */ #define CLOCK_HFCLKSTAT_STATE (1 << 16) /* Bit 16: HFCLK state */ diff --git a/arch/arm/src/nrf53/hardware/nrf53_usbreg.h b/arch/arm/src/nrf53/hardware/nrf53_usbreg.h index 1baa10daf8..f43d0e899f 100644 --- a/arch/arm/src/nrf53/hardware/nrf53_usbreg.h +++ b/arch/arm/src/nrf53/hardware/nrf53_usbreg.h @@ -39,9 +39,9 @@ #define NRF53_USBREG_EVENTS_USBDETECTED_OFFSET 0x000100 /* Voltage supply detected on VBUS */ #define NRF53_USBREG_EVENTS_USBREMOVED_OFFSET 0x000104 /* Voltage supply removed from VBUS*/ #define NRF53_USBREG_EVENTS_USBPWRRDY_OFFSET 0x000108 /* USB 3.3 V supply ready */ -#define NRF53_USBREG_INTEN_OFFSET 0x000300 /* Enable or disable interrrupt */ -#define NRF53_USBREG_INTENSET_OFFSET 0x000304 /* Enable interrrupt */ -#define NRF53_USBREG_INTENCLR_OFFSET 0x000308 /* Disable interrrupt */ +#define NRF53_USBREG_INTEN_OFFSET 0x000300 /* Enable or disable interrupt */ +#define NRF53_USBREG_INTENSET_OFFSET 0x000304 /* Enable interrupt */ +#define NRF53_USBREG_INTENCLR_OFFSET 0x000308 /* Disable interrupt */ #define NRF53_USBREG_USBREGSTATUS_OFFSET 0x000400 /* USB supply status */ /* Register definitions *****************************************************/ diff --git a/arch/arm/src/nrf53/nrf53_adc.c b/arch/arm/src/nrf53/nrf53_adc.c index 3a42f22f53..5282c3c9de 100644 --- a/arch/arm/src/nrf53/nrf53_adc.c +++ b/arch/arm/src/nrf53/nrf53_adc.c @@ -936,7 +936,7 @@ struct adc_dev_s *nrf53_adcinitialize( #ifdef CONFIG_NRF53_SAADC_TIMER if (channels > 1) { - aerr("ERORR: timer trigger works only for 1 channel!\n"); + aerr("ERROR: timer trigger works only for 1 channel!\n"); goto errout; } #endif diff --git a/arch/arm/src/nrf53/nrf53_flash.c b/arch/arm/src/nrf53/nrf53_flash.c index 42ef436ada..bf795c255b 100644 --- a/arch/arm/src/nrf53/nrf53_flash.c +++ b/arch/arm/src/nrf53/nrf53_flash.c @@ -220,8 +220,8 @@ ssize_t up_progmem_eraseblock(size_t block) UP_MB(); - /* Erase the page by writting 0xffffffff into the first 32-bit word of - * the flash page + /* Erase the page by writing 0xffffffff into the first 32-bit word of + * the flash page. */ putreg32(0xffffffff, page_address); diff --git a/arch/arm/src/nrf53/nrf53_gpio.c b/arch/arm/src/nrf53/nrf53_gpio.c index ff4832f3a6..c6fdb95571 100644 --- a/arch/arm/src/nrf53/nrf53_gpio.c +++ b/arch/arm/src/nrf53/nrf53_gpio.c @@ -371,7 +371,7 @@ int nrf53_gpio_config(nrf53_pinset_t cfgset) nrf53_gpio_sense(cfgset, port, pin); break; - case GPIO_OUTPUT: /* GPIO outpout pin */ + case GPIO_OUTPUT: /* GPIO output pin */ nrf53_gpio_output(cfgset, port, pin); break; @@ -515,7 +515,7 @@ void nrf53_gpio_detectmode(int port, enum nrf53_gpio_detectmode_e mode) * * Description: * Allow GPIO to be used by the net core. - * Can be used only with te app core. + * Can be used only with the app core. * ****************************************************************************/ diff --git a/arch/arm/src/nrf53/nrf53_gpio.h b/arch/arm/src/nrf53/nrf53_gpio.h index a4b4899eaa..7b3637f394 100644 --- a/arch/arm/src/nrf53/nrf53_gpio.h +++ b/arch/arm/src/nrf53/nrf53_gpio.h @@ -277,7 +277,7 @@ int nrf53_gpio_dump(nrf53_pinset_t pinset, const char *msg); * * Description: * Allow GPIO to be used by the net core. - * Can be used only with te app core. + * Can be used only with the app core. * ****************************************************************************/ diff --git a/arch/arm/src/nrf53/nrf53_gpiote.c b/arch/arm/src/nrf53/nrf53_gpiote.c index bfa0c9315c..864671b149 100644 --- a/arch/arm/src/nrf53/nrf53_gpiote.c +++ b/arch/arm/src/nrf53/nrf53_gpiote.c @@ -154,7 +154,7 @@ static int nrf53_gpiote_isr(int irq, void *context, void *arg) int j = 0; #endif - /* Get GPIOTE instnace */ + /* Get GPIOTE instance */ #ifdef CONFIG_NRF53_HAVE_GPIOTE1 inst = (irq == NRF53_IRQ_GPIOTE0) ? 0 : 1; @@ -397,7 +397,7 @@ void nrf53_gpiote_set_ch_event(uint32_t pinset, int channel, DEBUGASSERT(channel < GPIOTE_CHANNELS); - /* Get GPIOTE instnace */ + /* Get GPIOTE instance */ #ifdef CONFIG_NRF53_HAVE_GPIOTE1 inst = (channel < GPIOTE_PER_CHANNEL) ? 0 : 1; @@ -479,7 +479,7 @@ void nrf53_gpiote_set_ch_event(uint32_t pinset, int channel, * * Description: * Configures a GPIOTE channel in EVENT mode, assigns it to a given pin - * and sets a handler for the first availalbe GPIOTE channel + * and sets a handler for the first available GPIOTE channel. * * Input Parameters: * - pinset: GPIO pin configuration @@ -559,7 +559,7 @@ void nrf53_gpiote_set_task(uint32_t pinset, int channel, int port; int inst; - /* Get GPIOTE instnace */ + /* Get GPIOTE instance */ #ifdef CONFIG_NRF53_HAVE_GPIOTE1 inst = (channel < GPIOTE_PER_CHANNEL) ? 0 : 1; diff --git a/arch/arm/src/nrf53/nrf53_gpiote.h b/arch/arm/src/nrf53/nrf53_gpiote.h index e145f6a74c..630727ff0b 100644 --- a/arch/arm/src/nrf53/nrf53_gpiote.h +++ b/arch/arm/src/nrf53/nrf53_gpiote.h @@ -76,7 +76,7 @@ void nrf53_gpiote_set_ch_event(uint32_t pinset, int channel, * * Description: * Configures a GPIOTE channel in EVENT mode, assigns it to a given pin - * and sets a handler for the first availalbe GPIOTE channel + * and sets a handler for the first available GPIOTE channel. * * Input Parameters: * - pinset: GPIO pin configuration diff --git a/arch/arm/src/nrf53/nrf53_oscconfig.c b/arch/arm/src/nrf53/nrf53_oscconfig.c index 77a9facbaf..078a53a24e 100644 --- a/arch/arm/src/nrf53/nrf53_oscconfig.c +++ b/arch/arm/src/nrf53/nrf53_oscconfig.c @@ -42,7 +42,7 @@ ****************************************************************************/ #ifdef CONFIG_NRF53_NETCORE -# error Oscillators configuration availalbe only for the App core +# error Oscillators configuration available only for the App core #endif /* LFXO pins */ diff --git a/arch/arm/src/nrf53/nrf53_rptun.c b/arch/arm/src/nrf53/nrf53_rptun.c index ebbbae92db..9091d00ff5 100644 --- a/arch/arm/src/nrf53/nrf53_rptun.c +++ b/arch/arm/src/nrf53/nrf53_rptun.c @@ -48,7 +48,7 @@ ****************************************************************************/ #ifdef CONFIG_NRF53_FLASH_PREFETCH -# warning rptun doesnt seem to work correctly with FLASH cache enabled +# warning rptun does not seem to work correctly with FLASH cache enabled #endif /* Vring configuration parameters */ diff --git a/arch/arm/src/nrf53/nrf53_serial.c b/arch/arm/src/nrf53/nrf53_serial.c index fdd214c61f..4df9169775 100644 --- a/arch/arm/src/nrf53/nrf53_serial.c +++ b/arch/arm/src/nrf53/nrf53_serial.c @@ -731,7 +731,7 @@ static bool nrf53_txempty(struct uart_dev_s *dev) * * Description: * Performs the low level UART initialization early in debug so that the - * serial console will be available during bootup. This must be called + * serial console will be available during boot up. This must be called * before nrf53_serialinit. NOTE: This function depends on GPIO pin * configuration performed in nrf53_lowsetup() and main clock * initialization performed in nrf_clock_configure(). diff --git a/arch/arm/src/nrf53/nrf53_serial.h b/arch/arm/src/nrf53/nrf53_serial.h index e0b26fc0f1..6978a36639 100644 --- a/arch/arm/src/nrf53/nrf53_serial.h +++ b/arch/arm/src/nrf53/nrf53_serial.h @@ -40,7 +40,7 @@ * * Description: * Performs the low level UART initialization early in debug so that the - * serial console will be available during bootup. This must be called + * serial console will be available during boot up. This must be called * before nrf53_serialinit. NOTE: This function depends on GPIO pin * configuration performed in xmc_lowsetup() and main clock initialization * performed in xmc_clock_configure(). diff --git a/arch/arm/src/nrf53/nrf53_usbd.c b/arch/arm/src/nrf53/nrf53_usbd.c index 9ec9d42449..9826895b62 100644 --- a/arch/arm/src/nrf53/nrf53_usbd.c +++ b/arch/arm/src/nrf53/nrf53_usbd.c @@ -698,8 +698,8 @@ static bool nrf53_req_addlast(struct nrf53_ep_s *privep, * Name: nrf53_ep0out_stdrequest * * Description: - * Handle a stanard request on EP0. Pick off the things of interest to the - * USB device controller driver; pass what is left to the class driver. + * Handle a standard request on EP0. Pick off the things of interest to + * the USB device controller driver; pass what is left to the class driver. * ****************************************************************************/ @@ -1060,7 +1060,7 @@ static void nrf53_epin_transfer(struct nrf53_ep_s *privep, uint8_t *buf, * Name: nrf53_epout_allow * * Description: - * Allow OUT trafic on this endpoint + * Allow OUT traffic on this endpoint * ****************************************************************************/ @@ -1623,7 +1623,7 @@ static void nrf53_usbreset(struct nrf53_usbdev_s *priv) privep->stalled = false; - /* Stop EPIN taks */ + /* Stop EPIN task */ nrf53_epin_stop(priv, i); @@ -1636,7 +1636,7 @@ static void nrf53_usbreset(struct nrf53_usbdev_s *priv) privep->stalled = false; - /* Stop EPOUT taks */ + /* Stop EPOUT task */ nrf53_epout_stop(priv, i); } @@ -2572,7 +2572,7 @@ static int nrf53_ep_submit(struct usbdev_ep_s *ep, struct usbdev_req_s *req) { usbtrace(TRACE_OUTREQQUEUED(privep->epphy), privreq->req.len); - /* Allow OUT trafic on this endpoint */ + /* Allow OUT traffic on this endpoint */ nrf53_epout_allow(privep); } @@ -2635,7 +2635,7 @@ static int nrf53_ep_setstall(struct nrf53_ep_s *privep) regval |= USBD_EPSTALL_IO_OUT; } - /* Unstall a given EP */ + /* Un-stall a given EP */ regval |= USBD_EPSTALL_EP(privep->epphy) | USBD_EPSTALL_IO_STALL; nrf53_putreg(regval, NRF53_USBD_EPSTALL); @@ -2669,7 +2669,7 @@ static int nrf53_ep_clrstall(struct nrf53_ep_s *privep) regval |= USBD_EPSTALL_IO_OUT; } - /* Unstall a given EP */ + /* Un-stall a given EP */ regval |= USBD_EPSTALL_EP(privep->epphy) | USBD_EPSTALL_IO_UNSTALL; nrf53_putreg(regval, NRF53_USBD_EPSTALL); @@ -3095,7 +3095,7 @@ void arm_usbinitialize(void) arm_usbuninitialize(); - /* Initialie the driver data structure */ + /* Initialize the driver data structure */ nrf53_swinitialize(priv); diff --git a/arch/arm/src/nrf91/Kconfig b/arch/arm/src/nrf91/Kconfig index f129615954..57048b5fb8 100644 --- a/arch/arm/src/nrf91/Kconfig +++ b/arch/arm/src/nrf91/Kconfig @@ -763,8 +763,8 @@ config NRF91_MODEM_PREFERENCE 0 - No preference. Initial system selection is based on history data and USIM 1 - LTE-M preferred 2 - NB-IoT preferred - 3 - Network selection priorities override system priority, but LTE-M is prefered - 4 - Network selection priorities override system priority, but NB-IoT is prefered + 3 - Network selection priorities override system priority, but LTE-M is preferred + 4 - Network selection priorities override system priority, but NB-IoT is preferred For details look at "nRF9160 AT Commands Command Reference Guid" from Nordic, section "5.27 System mode" diff --git a/arch/arm/src/nrf91/hardware/nrf91_clock.h b/arch/arm/src/nrf91/hardware/nrf91_clock.h index a0920965b4..dd68a5e3b7 100644 --- a/arch/arm/src/nrf91/hardware/nrf91_clock.h +++ b/arch/arm/src/nrf91/hardware/nrf91_clock.h @@ -85,7 +85,7 @@ #define CLOCK_HFCLKSTAT_SRC_SHIFT (0) /* Bit 0: Source of HFCLK */ #define CLOCK_HFCLKSTAT_SRC_MASK (1 << CLOCK_HFCLKSTAT_SRC_SHIFT) # define CLOCK_HFCLKSTAT_SRC_HFINT (0 << CLOCK_HFCLKSTAT_SRC_SHIFT) /* 0b0: 128 MHz internal oscillator (HFINT) */ -# define CLOCK_HFCLKSTAT_SRC_HFXO (1 << CLOCK_HFCLKSTAT_SRC_SHIFT) /* 0b1: 128 MHz crystal oscilator (HFXO) */ +# define CLOCK_HFCLKSTAT_SRC_HFXO (1 << CLOCK_HFCLKSTAT_SRC_SHIFT) /* 0b1: 128 MHz crystal oscillator (HFXO) */ #define CLOCK_HFCLKSTAT_STATE (1 << 16) /* Bit 16: HFCLK state */ /* LFCLKRUN Register */ diff --git a/arch/arm/src/nrf91/nrf91_flash.c b/arch/arm/src/nrf91/nrf91_flash.c index bbf1d8f833..9d388af5fd 100644 --- a/arch/arm/src/nrf91/nrf91_flash.c +++ b/arch/arm/src/nrf91/nrf91_flash.c @@ -220,8 +220,8 @@ ssize_t up_progmem_eraseblock(size_t block) UP_MB(); - /* Erase the page by writting 0xffffffff into the first 32-bit word of - * the flash page + /* Erase the page by writing 0xffffffff into the first 32-bit word of + * the flash page. */ putreg32(0xffffffff, page_address); diff --git a/arch/arm/src/nrf91/nrf91_gpio.c b/arch/arm/src/nrf91/nrf91_gpio.c index 2b165a7b3c..31ccec1d99 100644 --- a/arch/arm/src/nrf91/nrf91_gpio.c +++ b/arch/arm/src/nrf91/nrf91_gpio.c @@ -304,7 +304,7 @@ int nrf91_gpio_config(nrf91_pinset_t cfgset) nrf91_gpio_sense(cfgset, port, pin); break; - case GPIO_OUTPUT: /* GPIO outpout pin */ + case GPIO_OUTPUT: /* GPIO output pin */ nrf91_gpio_output(cfgset, port, pin); break; diff --git a/arch/arm/src/nrf91/nrf91_modem_at.c b/arch/arm/src/nrf91/nrf91_modem_at.c index 03d733fd61..30bc888fdd 100644 --- a/arch/arm/src/nrf91/nrf91_modem_at.c +++ b/arch/arm/src/nrf91/nrf91_modem_at.c @@ -296,7 +296,7 @@ static void nrf91_modem_at_send(struct uart_dev_s *dev, int ch) priv->txbuf[priv->tx_i] = (char)ch; priv->tx_i += 1; - /* Special formating Nordic AT interface (escape charactes) */ + /* Special formatting Nordic AT interface (escape characters) */ if (ch == '%') { diff --git a/arch/arm/src/nrf91/nrf91_serial.c b/arch/arm/src/nrf91/nrf91_serial.c index 450056f9a4..687a7d7975 100644 --- a/arch/arm/src/nrf91/nrf91_serial.c +++ b/arch/arm/src/nrf91/nrf91_serial.c @@ -731,7 +731,7 @@ static bool nrf91_txempty(struct uart_dev_s *dev) * * Description: * Performs the low level UART initialization early in debug so that the - * serial console will be available during bootup. This must be called + * serial console will be available during boot up. This must be called * before nrf91_serialinit. NOTE: This function depends on GPIO pin * configuration performed in nrf91_lowsetup() and main clock * initialization performed in nrf_clock_configure(). diff --git a/arch/arm/src/nrf91/nrf91_serial.h b/arch/arm/src/nrf91/nrf91_serial.h index a68eb4a689..3cabeaa739 100644 --- a/arch/arm/src/nrf91/nrf91_serial.h +++ b/arch/arm/src/nrf91/nrf91_serial.h @@ -40,7 +40,7 @@ * * Description: * Performs the low level UART initialization early in debug so that the - * serial console will be available during bootup. This must be called + * serial console will be available during boot up. This must be called * before nrf91_serialinit. NOTE: This function depends on GPIO pin * configuration performed in xmc_lowsetup() and main clock initialization * performed in xmc_clock_configure(). diff --git a/arch/arm/src/nuc1xx/nuc_serial.c b/arch/arm/src/nuc1xx/nuc_serial.c index 27529b345a..3aede14a81 100644 --- a/arch/arm/src/nuc1xx/nuc_serial.c +++ b/arch/arm/src/nuc1xx/nuc_serial.c @@ -999,7 +999,7 @@ static bool up_txempty(struct uart_dev_s *dev) * * Description: * Performs the low level UART initialization early in debug so that the - * serial console will be available during bootup. This must be called + * serial console will be available during boot up. This must be called * before arm_serialinit. * * NOTE: Configuration of the CONSOLE UART was performed by up_lowsetup() diff --git a/arch/arm/src/nuc1xx/nuc_start.c b/arch/arm/src/nuc1xx/nuc_start.c index a704d3b9bb..1dabf43083 100644 --- a/arch/arm/src/nuc1xx/nuc_start.c +++ b/arch/arm/src/nuc1xx/nuc_start.c @@ -48,7 +48,7 @@ * 0x0000:0000 - Beginning of FLASH. Address of exception vectors. * 0x0001:ffff - End of flash (assuming 128KB of FLASH) * 0x2000:0000 - Start of SRAM and start of .data (_sdata) - * - End of .data (_edata) abd start of .bss (_sbss) + * - End of .data (_edata) and start of .bss (_sbss) * - End of .bss (_ebss) and bottom of idle stack * - _ebss + CONFIG_IDLETHREAD_STACKSIZE = end of idle stack, * start of heap diff --git a/arch/arm/src/phy62xx/ble/ble_controller.h b/arch/arm/src/phy62xx/ble/ble_controller.h index d13674b9b9..c3dc54dd81 100644 --- a/arch/arm/src/phy62xx/ble/ble_controller.h +++ b/arch/arm/src/phy62xx/ble/ble_controller.h @@ -402,7 +402,7 @@ typedef struct uint8_t allocConn; /* flag to indicate if this connection is allocated */ uint8_t active; /* flag to indicate if this connection is active */ uint8_t connId; /* connection ID */ - uint8_t firstPacket; /* flag to indicate when the first packet has been received. 0 means TURE, 1 means FALSE */ + uint8_t firstPacket; /* flag to indicate when the first packet has been received. 0 means TRUE, 1 means FALSE */ uint16_t currentEvent; /* current event number */ uint16_t nextEvent; /* next active event number */ @@ -519,7 +519,7 @@ typedef struct /* =============== A2 multi connection */ - uint8_t ctrlDataIsProcess ; /* seding a control packet or not */ + uint8_t ctrlDataIsProcess ; /* sending a control packet or not */ uint8_t ctrlDataIsPending ; /* control packet is pending to be sent */ diff --git a/arch/arm/src/phy62xx/error.h b/arch/arm/src/phy62xx/error.h index 073c82891e..60cdc79f41 100644 --- a/arch/arm/src/phy62xx/error.h +++ b/arch/arm/src/phy62xx/error.h @@ -53,11 +53,11 @@ #define PPlus_ERR_FORBIDDEN (15) /* Forbidden Operation */ #define PPlus_ERR_INVALID_ADDR (16) /* Bad Memory Address */ #define PPlus_ERR_BUSY (17) /* Busy */ -#define PPlus_ERR_NOT_REGISTED (18) /* not registed */ +#define PPlus_ERR_NOT_REGISTED (18) /* not registered */ #define PPlus_ERR_IO_CONFILCT (19) /* IO config error */ #define PPlus_ERR_IO_FAIL (20) /* IO fail error */ #define PPlus_ERR_NOT_IMPLEMENTED (22) /* Function is not provide now */ -#define PPlus_ERR_SPI_FLASH (23) /* spi falsh operation error */ +#define PPlus_ERR_SPI_FLASH (23) /* spi flash operation error */ #define PPlus_ERR_UNINITIALIZED (24) #define PPlus_ERR_FS_WRITE_FAILED (31) #define PPlus_ERR_FS_CONTEXT (32) @@ -78,7 +78,7 @@ #define PPlus_ERR_ACCESS_REJECTED (51) #define PPlus_ERR_BLE_NOT_READY (80) /* BLE not ready error */ -#define PPlus_ERR_BLE_BUSY (81) /* BLE operation failed becuase of busy */ +#define PPlus_ERR_BLE_BUSY (81) /* BLE operation failed because of busy */ #define PPlus_ERR_BLE_FAIL (82) /* BLE operation failed */ #define PPlus_ERR_OTA_INVALID_STATE (100) /* state machine error when OTA */ @@ -86,7 +86,7 @@ #define PPlus_ERR_OTA_CRC (102) /* bad checksum(crc) */ #define PPlus_ERR_OTA_NO_APP (103) /* No application data */ #define PPlus_ERR_OTA_BAD_DATA (104) /* bad application data */ -#define PPlus_ERR_OTA_UNKNOW_CMD (105) /* unknow command */ +#define PPlus_ERR_OTA_UNKNOW_CMD (105) /* unknown command */ #define PPlus_ERR_OTA_CRYPTO (106) /* crypto verify error */ #define PPlus_ERR_KEY_VERIFY (107) /* security boot key verify fail */ #define PPlus_ERR_DOUBLE_CONFIRM (108) /* security boot double key verify fail */ diff --git a/arch/arm/src/phy62xx/flash.h b/arch/arm/src/phy62xx/flash.h index da1a89fbaf..957ac17293 100644 --- a/arch/arm/src/phy62xx/flash.h +++ b/arch/arm/src/phy62xx/flash.h @@ -70,7 +70,7 @@ #define CHIP_MADDR_LEN 6 -/* xip flash read instrcution */ +/* xip flash read instruction */ #define XFRD_FCMD_READ 0x0000003 #define XFRD_FCMD_READ_DUAL 0x801003B diff --git a/arch/arm/src/phy62xx/gpio.c b/arch/arm/src/phy62xx/gpio.c index 36a6ecf14d..b4c5a26c63 100644 --- a/arch/arm/src/phy62xx/gpio.c +++ b/arch/arm/src/phy62xx/gpio.c @@ -628,7 +628,7 @@ int hal_gpioin_enable(gpio_pin_e pin) p_irq_ctx[pin].enable = TRUE; hal_gpio_pin_init(pin, GPIO_INPUT); - /* hal_gpio_pull_set(pin, PULL_DOWN); fixme: need disccuss */ + /* hal_gpio_pull_set(pin, PULL_DOWN); fixme: need discuss */ if (p_irq_ctx[pin].posedgeHdl && p_irq_ctx[pin].negedgeHdl) /* both raise and fall */ { diff --git a/arch/arm/src/phy62xx/jump_table.c b/arch/arm/src/phy62xx/jump_table.c index d498ad7a21..813bdcf329 100644 --- a/arch/arm/src/phy62xx/jump_table.c +++ b/arch/arm/src/phy62xx/jump_table.c @@ -25,7 +25,7 @@ * Revised: * Revision: * - * Description: Jump table that holds function pointers and veriables + * Description: Jump table that holds function pointers and variables * used in ROM code. ****************************************************************************/ diff --git a/arch/arm/src/phy62xx/phy62xx_ble.c b/arch/arm/src/phy62xx/phy62xx_ble.c index fda53e479a..613c7777b0 100644 --- a/arch/arm/src/phy62xx/phy62xx_ble.c +++ b/arch/arm/src/phy62xx/phy62xx_ble.c @@ -191,8 +191,8 @@ uint8 pplus_ble_recv_msg(uint8 destination_task, uint8 *msg_ptr) * Input Parameters: * drv - BT driver pointer * type - BT packet type - * data - BT packte data buffer pointer - * len - BT packte length + * data - BT packet data buffer pointer + * len - BT packet length * * Returned Value: * Sent bytes on success or a negated value on failure. diff --git a/arch/arm/src/phy62xx/phyplus_gpio.c b/arch/arm/src/phy62xx/phyplus_gpio.c index a3160d38ca..a7295f9809 100644 --- a/arch/arm/src/phy62xx/phyplus_gpio.c +++ b/arch/arm/src/phy62xx/phyplus_gpio.c @@ -272,7 +272,7 @@ static int phyplus_gpint_attach(struct gpio_dev_s *dev, pin_interrupt_t callback) { #if 0 - /* do the regist callback things... */ + /* do the register callback things... */ struct stm32gpint_dev_s *stm32gpint = (struct stm32gpint_dev_s *)dev; diff --git a/arch/arm/src/phy62xx/phyplus_tim.h b/arch/arm/src/phy62xx/phyplus_tim.h index 04947e805c..f32054eb85 100644 --- a/arch/arm/src/phy62xx/phyplus_tim.h +++ b/arch/arm/src/phy62xx/phyplus_tim.h @@ -67,7 +67,7 @@ extern "C" #define EXTERN extern #endif -/* register informations... */ +/* register information... */ #define TIM_COUNT_OFFSET 0x0000 #define TIM_CURRENT_OFFSET 0x0004 diff --git a/arch/arm/src/phy62xx/pplus_mtd_flash.c b/arch/arm/src/phy62xx/pplus_mtd_flash.c index bb6d0090c6..9856ad3201 100644 --- a/arch/arm/src/phy62xx/pplus_mtd_flash.c +++ b/arch/arm/src/phy62xx/pplus_mtd_flash.c @@ -65,7 +65,7 @@ struct pplus_fls_dev_s { struct mtd_dev_s mtd; /* MTD interface */ uint32_t offset; /* offset from flash start address */ - uint32_t size; /* avaliable size for MTD */ + uint32_t size; /* available size for MTD */ uint16_t nsectors; /* Number of erase sectors */ uint8_t sectorshift; /* Log2 of sector size */ uint8_t pageshift; /* Log2 of page size */ @@ -354,7 +354,7 @@ static int pplus_fls_ioctl(struct mtd_dev_s *dev, * character driver front end). * Parameter: * offset: offset from 0 of internal flash - * size: avaiable size for NVM + * size: available size for NVM ****************************************************************************/ struct mtd_dev_s *pplus_fls_initialize(uint32_t offset, uint32_t size) diff --git a/arch/arm/src/phy62xx/pwrmgr.c b/arch/arm/src/phy62xx/pwrmgr.c index df2f19cd60..5c191a977d 100644 --- a/arch/arm/src/phy62xx/pwrmgr.c +++ b/arch/arm/src/phy62xx/pwrmgr.c @@ -432,7 +432,7 @@ void hal_pwrmgr_poweroff(pwroff_cfg_t *pcfg, uint8_t wakeup_pin_num) * } */ - /* config reset casue as RSTC_OFF_MODE + /* config reset cause as RSTC_OFF_MODE * reset path walkaround dwc */ diff --git a/arch/arm/src/qemu/chip.h b/arch/arm/src/qemu/chip.h index 0ef01e082d..68392950af 100644 --- a/arch/arm/src/qemu/chip.h +++ b/arch/arm/src/qemu/chip.h @@ -68,7 +68,7 @@ * Name: cpuindex * * Description: - * Return an index idenifying the current CPU. + * Return an index identifying the current CPU. * ****************************************************************************/ diff --git a/arch/arm/src/ra4/ra_serial.c b/arch/arm/src/ra4/ra_serial.c index 3e746850b3..699804faf6 100644 --- a/arch/arm/src/ra4/ra_serial.c +++ b/arch/arm/src/ra4/ra_serial.c @@ -908,7 +908,7 @@ static bool up_txempty(struct uart_dev_s *dev) * * Description: * Performs the low level SCI initialization early in debug so that the - * serial console will be available during bootup. This must be called + * serial console will be available during boot up. This must be called * before arm_serialinit. * ****************************************************************************/ diff --git a/arch/arm/src/rp2040/rp2040_config.h b/arch/arm/src/rp2040/rp2040_config.h index caf58e92a7..fa9bc9b497 100644 --- a/arch/arm/src/rp2040/rp2040_config.h +++ b/arch/arm/src/rp2040/rp2040_config.h @@ -42,8 +42,8 @@ # define HAVE_UART 1 #endif -/* Make sure all features are disabled for diabled U[S]ARTs. This simplifies - * checking later. +/* Make sure all features are disabled for disabled U[S]ARTs. + * This simplifies checking later. */ #ifndef CONFIG_RP2040_UART0 diff --git a/arch/arm/src/rp2040/rp2040_pio.h b/arch/arm/src/rp2040/rp2040_pio.h index 3701aa9689..f479baff45 100644 --- a/arch/arm/src/rp2040/rp2040_pio.h +++ b/arch/arm/src/rp2040/rp2040_pio.h @@ -876,7 +876,7 @@ static inline void rp2040_pio_sm_clkdiv_restart(uint32_t pio, uint32_t sm) * machines and wish to resynchronise them), and that disabling a state * machine does not halt its clock divider: that is, if multiple state * machines have their clocks synchronised, you can safely disable and - * reenable one of the state machines without losing synchronisation. + * re-enable one of the state machines without losing synchronisation. * * Input Parameters: * pio - PIO index (0..1) diff --git a/arch/arm/src/rp2040/rp2040_serial.c b/arch/arm/src/rp2040/rp2040_serial.c index 686af616eb..9d50fb1014 100644 --- a/arch/arm/src/rp2040/rp2040_serial.c +++ b/arch/arm/src/rp2040/rp2040_serial.c @@ -967,7 +967,7 @@ static bool up_txempty(struct uart_dev_s *dev) * * Description: * Performs the low level UART initialization early in debug so that the - * serial console will be available during bootup. This must be called + * serial console will be available during boot up. This must be called * before arm_serialinit. * * NOTE: Configuration of the CONSOLE UART was performed by up_lowsetup() diff --git a/arch/arm/src/rp2040/rp2040_ws2812.pio b/arch/arm/src/rp2040/rp2040_ws2812.pio index 99f106a4a2..fb5605c191 100644 --- a/arch/arm/src/rp2040/rp2040_ws2812.pio +++ b/arch/arm/src/rp2040/rp2040_ws2812.pio @@ -7,7 +7,7 @@ ; in "arch/arm/src/rp2040/rp2040_ws2812.c". This file is ; supplied for documentation purposes only ; -; Each bit of the input word generaes one of two patterns for output: +; Each bit of the input word generates one of two patterns for output: ; ; clock +-----+-----+-----+-----+-----+-----+-----+-----+-----+ | | T1 | T2 | T3 | diff --git a/arch/arm/src/rp23xx/hardware/rp23xx_usbctrl_regs.h b/arch/arm/src/rp23xx/hardware/rp23xx_usbctrl_regs.h index d6edd05f08..3c58e33788 100644 --- a/arch/arm/src/rp23xx/hardware/rp23xx_usbctrl_regs.h +++ b/arch/arm/src/rp23xx/hardware/rp23xx_usbctrl_regs.h @@ -62,7 +62,7 @@ #define RP23XX_USBCTRL_REGS_INTF_OFFSET 0x000094 /* Interrupt Force */ #define RP23XX_USBCTRL_REGS_INTS_OFFSET 0x000098 /* Interrupt status after masking & forcing */ #define RP23XX_USBCTRL_REGS_SOF_TIMESTAMP_RAW_OFFSET 0x000100 /* Device only. Raw value of free-running PHY clock counter @48MHz. Used to calculate time between SOF events */ -#define RP23XX_USBCTRL_REGS_SOF_TIMESTAMP_LAST_OFFSET 0x000104 /* Device only. Value of free-running PHY clock counter @48MHz when last SOF event occured */ +#define RP23XX_USBCTRL_REGS_SOF_TIMESTAMP_LAST_OFFSET 0x000104 /* Device only. Value of free-running PHY clock counter @48MHz when last SOF event occurred */ #define RP23XX_USBCTRL_REGS_SM_STATE_OFFSET 0x000108 #define RP23XX_USBCTRL_REGS_EP_TX_ERROR_OFFSET 0x00010c /* TX error count for each endpoint. Write to each field to reset the counter to 0 */ #define RP23XX_USBCTRL_REGS_EP_RX_ERROR_OFFSET 0x000110 /* RX error count for each endpoint. Write to each field to reset the counter to 0 */ @@ -158,12 +158,12 @@ #define RP23XX_USBCTRL_REGS_SIE_STATUS_RX_OVERFLOW (1 << 26) /* RX overflow is raised by the Serial RX engine if the incoming data is too fast. */ #define RP23XX_USBCTRL_REGS_SIE_STATUS_BIT_STUFF_ERROR (1 << 25) /* Bit Stuff Error. Raised by the Serial RX engine. */ #define RP23XX_USBCTRL_REGS_SIE_STATUS_CRC_ERROR (1 << 24) /* CRC Error. Raised by the Serial RX engine. */ -#define RP23XX_USBCTRL_REGS_SIE_STATUS_ENDPOINT_ERROR (1 << 23) /* An endpoint has encounted an error. Read the ep_rx_error and ep_tx_error registers to find out which endpoint had an error */ +#define RP23XX_USBCTRL_REGS_SIE_STATUS_ENDPOINT_ERROR (1 << 23) /* An endpoint has encountered an error. Read the ep_rx_error and ep_tx_error registers to find out which endpoint had an error */ #define RP23XX_USBCTRL_REGS_SIE_STATUS_BUS_RESET (1 << 19) /* Device: bus reset received */ #define RP23XX_USBCTRL_REGS_SIE_STATUS_TRANS_COMPLETE (1 << 18) /* Transaction complete. */ #define RP23XX_USBCTRL_REGS_SIE_STATUS_SETUP_REC (1 << 17) /* Device: Setup packet received */ #define RP23XX_USBCTRL_REGS_SIE_STATUS_CONNECTED (1 << 16) /* Device: connected */ -#define RP23XX_USBCTRL_REGS_SIE_STATUS_RX_SHORT_PACKET (1 << 12) /* Device or Host has received a short packet. This is when the data recieved is less than configured in the buffer control register. Device: If using double buffered mode on device the buffer select will not be toggled after writing status back to the buffer control register. This is to prevent any further transactions on that endpoint until the user has reset the buffer control registers. Host: the current transfer will be stopped early */ +#define RP23XX_USBCTRL_REGS_SIE_STATUS_RX_SHORT_PACKET (1 << 12) /* Device or Host has received a short packet. This is when the data received is less than configured in the buffer control register. Device: If using double buffered mode on device the buffer select will not be toggled after writing status back to the buffer control register. This is to prevent any further transactions on that endpoint until the user has reset the buffer control registers. Host: the current transfer will be stopped early */ #define RP23XX_USBCTRL_REGS_SIE_STATUS_RESUME (1 << 11) /* Host: Device has initiated a remote resume. Device: host has initiated a resume. */ #define RP23XX_USBCTRL_REGS_SIE_STATUS_VBUS_OVER_CURR (1 << 10) /* VBUS over current detected */ #define RP23XX_USBCTRL_REGS_SIE_STATUS_SPEED_SHIFT (8) /* Host: device speed. Disconnected = 00, LS = 01, FS = 10 */ @@ -511,7 +511,7 @@ #define RP23XX_USBCTRL_REGS_INTS_HOST_CONN_DIS (1 << 0) /* Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED */ #define RP23XX_USBCTRL_REGS_SOF_TIMESTAMP_RAW_MASK (0x1fffff) /* Device only. Raw value of free-running PHY clock counter @48MHz. Used to calculate time between SOF events */ -#define RP23XX_USBCTRL_REGS_SOF_TIMESTAMP_LAST_MASK (0x1fffff) /* Device only. Value of free-running PHY clock counter @48MHz when last SOF event occured */ +#define RP23XX_USBCTRL_REGS_SOF_TIMESTAMP_LAST_MASK (0x1fffff) /* Device only. Value of free-running PHY clock counter @48MHz when last SOF event occurred */ #define RP23XX_USBCTRL_REGS_SM_STATE_RX_DASM_SHIFT (8) #define RP23XX_USBCTRL_REGS_SM_STATE_RX_DASM_MASK (0xf << RP23XX_USBCTRL_REGS_SM_STATE_RX_DASM_SHIFT) #define RP23XX_USBCTRL_REGS_SM_STATE_BC_STATE_SHIFT (5) diff --git a/arch/arm/src/rp23xx/rp23xx_config.h b/arch/arm/src/rp23xx/rp23xx_config.h index 3c5683ea05..ca59dfc930 100644 --- a/arch/arm/src/rp23xx/rp23xx_config.h +++ b/arch/arm/src/rp23xx/rp23xx_config.h @@ -42,8 +42,8 @@ # define HAVE_UART 1 #endif -/* Make sure all features are disabled for diabled U[S]ARTs. This simplifies - * checking later. +/* Make sure all features are disabled for disabled U[S]ARTs. + * This simplifies checking later. */ #ifndef CONFIG_RP23XX_UART0 diff --git a/arch/arm/src/rp23xx/rp23xx_pio.h b/arch/arm/src/rp23xx/rp23xx_pio.h index f0e76fc967..6327910109 100644 --- a/arch/arm/src/rp23xx/rp23xx_pio.h +++ b/arch/arm/src/rp23xx/rp23xx_pio.h @@ -870,7 +870,7 @@ static inline void rp23xx_pio_sm_clkdiv_restart(uint32_t pio, uint32_t sm) * machines and wish to resynchronise them), and that disabling a state * machine does not halt its clock divider: that is, if multiple state * machines have their clocks synchronised, you can safely disable and - * reenable one of the state machines without losing synchronisation. + * re-enable one of the state machines without losing synchronisation. * * Input Parameters: * pio - PIO index (0..2) diff --git a/arch/arm/src/rp23xx/rp23xx_ws2812.pio b/arch/arm/src/rp23xx/rp23xx_ws2812.pio index 2bd3f8d1a0..7b5632bfc1 100644 --- a/arch/arm/src/rp23xx/rp23xx_ws2812.pio +++ b/arch/arm/src/rp23xx/rp23xx_ws2812.pio @@ -7,7 +7,7 @@ ; in "arch/arm/src/rp23xx/rp23xx_ws2812.c". This file is ; supplied for documentation purposes only ; -; Each bit of the input word generaes one of two patterns for output: +; Each bit of the input word generates one of two patterns for output: ; ; clock +-----+-----+-----+-----+-----+-----+-----+-----+-----+ ; | T1 | T2 | T3 | diff --git a/arch/arm/src/rtl8720c/ameba_uart.c b/arch/arm/src/rtl8720c/ameba_uart.c index ab8ab6a829..0833dc2254 100644 --- a/arch/arm/src/rtl8720c/ameba_uart.c +++ b/arch/arm/src/rtl8720c/ameba_uart.c @@ -1019,7 +1019,7 @@ static void ameba_putc(struct ameba_s *priv, int ch) * * Description: * Performs the low level UART initialization early in debug so that the - * serial console will be available during bootup. This must be called + * serial console will be available during boot up. This must be called * before uart_serialinit. * * NOTE: Configuration of the CONSOLE UART was performed by uart_lowsetup() diff --git a/arch/arm/src/rtl8720c/amebaz_hci_board.c b/arch/arm/src/rtl8720c/amebaz_hci_board.c index f540cf8c75..720be4dcc5 100644 --- a/arch/arm/src/rtl8720c/amebaz_hci_board.c +++ b/arch/arm/src/rtl8720c/amebaz_hci_board.c @@ -171,9 +171,9 @@ static uint8_t rtl_vendor_init_config[] = 0x94, 0x01, 0x06, 0x0a, 0x08, 0x00, 0x00, 0x2e, 0x07, /* phy flatk */ - 0x9f, 0x01, 0x05, 0x2a, 0x2a, 0x2a, 0x2a, 0x1c, /* unknow 1 */ + 0x9f, 0x01, 0x05, 0x2a, 0x2a, 0x2a, 0x2a, 0x1c, /* unknown 1 */ - 0xa4, 0x01, 0x04, 0xfe, 0xfe, 0xfe, 0xfe, /* unknow 2 */ + 0xa4, 0x01, 0x04, 0xfe, 0xfe, 0xfe, 0xfe, /* unknown 2 */ }; /**************************************************************************** @@ -418,7 +418,7 @@ int hci_find_fw_patch(uint8_t chipid) phal_spic_adaptor_t flash; - /* FIXME: Distiguish Normal and MP Ptach (rltk_bt_get_patch_code) */ + /* FIXME: Distinguish Normal and MP Ptach (rltk_bt_get_patch_code) */ const uint8_t *fw_patch = rtl_vendor_command; uint32_t fw_patch_len = rtl_vendor_command_size; @@ -681,7 +681,7 @@ static int hci_parse_config(void) if (payload_len != sizeof(rtl_vendor_init_config) - BT_CONFIG_HEADER_LEN) { - /* Fix the len, just avoid the length is not corect */ + /* Fix the len, just avoid the length is not correct */ LE_UINT16_TO_STREAM(p_len, sizeof(rtl_vendor_init_config) - BT_CONFIG_HEADER_LEN); diff --git a/arch/arm/src/s32k1xx/Kconfig b/arch/arm/src/s32k1xx/Kconfig index 2bd964fa5c..b71c5d1412 100644 --- a/arch/arm/src/s32k1xx/Kconfig +++ b/arch/arm/src/s32k1xx/Kconfig @@ -701,7 +701,7 @@ config S32K1XX_LPI2C_DMA_MAXMSG default 8 depends on S32K1XX_LPI2C_DMA ---help--- - This option set the mumber of mesg that can be in a transfer. + This option set the number of mesg that can be in a transfer. It is used to allocate space for the 16 bit LPI2C commands that will be DMA-ed to the LPI2C device. diff --git a/arch/arm/src/s32k1xx/hardware/s32k1xx_enet.h b/arch/arm/src/s32k1xx/hardware/s32k1xx_enet.h index 5e6e3c1556..8c5d2129e4 100644 --- a/arch/arm/src/s32k1xx/hardware/s32k1xx_enet.h +++ b/arch/arm/src/s32k1xx/hardware/s32k1xx_enet.h @@ -304,7 +304,7 @@ #define ENET_TXIC_ICFT_SHIFT (20) /* Bits 0-15: Interrupt coalescing timer threshold */ #define ENET_TXIC_ICFT_SHIFT_MASK (0xff << ENET_TXIC_ICFT_SHIFT) #define ENET_TXIC_ICTT_ICCS (1 << 30) /* Bit 30: Interrupt Coalescing Timer Clock Source Select */ -#define ENET_TXIC_ICTT_ICEN (1 << 31) /* Bit 31: Eable/disabel Interrupt Coalescing */ +#define ENET_TXIC_ICTT_ICEN (1 << 31) /* Bit 31: Enable/disable Interrupt Coalescing */ /* Receive Interrupt Coalescing Register */ @@ -314,7 +314,7 @@ #define ENET_RXIC_ICFT_SHIFT (20) /* Bits 0-15: Interrupt coalescing timer threshold */ #define ENET_RXIC_ICFT_SHIFT_MASK (0xff << ENET_TXIC_ICFT_SHIFT) #define ENET_RXIC_ICTT_ICCS (1 << 30) /* Bit 30: Interrupt Coalescing Timer Clock Source Select */ -#define ENET_RXIC_ICTT_ICEN (1 << 31) /* Bit 31: Eable/disabel Interrupt Coalescing */ +#define ENET_RXIC_ICTT_ICEN (1 << 31) /* Bit 31: Enable/disable Interrupt Coalescing */ /* Transmit FIFO Watermark Register */ diff --git a/arch/arm/src/s32k1xx/hardware/s32k1xx_ftm.h b/arch/arm/src/s32k1xx/hardware/s32k1xx_ftm.h index f860a0cafa..bd9efdc473 100644 --- a/arch/arm/src/s32k1xx/hardware/s32k1xx_ftm.h +++ b/arch/arm/src/s32k1xx/hardware/s32k1xx_ftm.h @@ -717,14 +717,14 @@ /* Output Mask register */ -#define FTM_OUTMASK_CH0OM (1 << 0) /* Bit 0: Channel 0 Ouput Mask */ -#define FTM_OUTMASK_CH1OM (1 << 1) /* Bit 1: Channel 1 Ouput Mask */ -#define FTM_OUTMASK_CH2OM (1 << 2) /* Bit 2: Channel 2 Ouput Mask */ -#define FTM_OUTMASK_CH3OM (1 << 3) /* Bit 3: Channel 3 Ouput Mask */ -#define FTM_OUTMASK_CH4OM (1 << 4) /* Bit 4: Channel 4 Ouput Mask */ -#define FTM_OUTMASK_CH5OM (1 << 5) /* Bit 5: Channel 5 Ouput Mask */ -#define FTM_OUTMASK_CH6OM (1 << 6) /* Bit 6: Channel 6 Ouput Mask */ -#define FTM_OUTMASK_CH7OM (1 << 7) /* Bit 7: Channel 7 Ouput Mask */ +#define FTM_OUTMASK_CH0OM (1 << 0) /* Bit 0: Channel 0 Output Mask */ +#define FTM_OUTMASK_CH1OM (1 << 1) /* Bit 1: Channel 1 Output Mask */ +#define FTM_OUTMASK_CH2OM (1 << 2) /* Bit 2: Channel 2 Output Mask */ +#define FTM_OUTMASK_CH3OM (1 << 3) /* Bit 3: Channel 3 Output Mask */ +#define FTM_OUTMASK_CH4OM (1 << 4) /* Bit 4: Channel 4 Output Mask */ +#define FTM_OUTMASK_CH5OM (1 << 5) /* Bit 5: Channel 5 Output Mask */ +#define FTM_OUTMASK_CH6OM (1 << 6) /* Bit 6: Channel 6 Output Mask */ +#define FTM_OUTMASK_CH7OM (1 << 7) /* Bit 7: Channel 7 Output Mask */ /* Bit 8-31: Reserved */ diff --git a/arch/arm/src/s32k1xx/s32k1xx_clockconfig.c b/arch/arm/src/s32k1xx/s32k1xx_clockconfig.c index edb7a23a63..bd2b4ba6e5 100644 --- a/arch/arm/src/s32k1xx/s32k1xx_clockconfig.c +++ b/arch/arm/src/s32k1xx/s32k1xx_clockconfig.c @@ -2030,8 +2030,8 @@ static void up_pm_notify(struct pm_callback_s *cb, int domain, /* set the system clock to the SIRC 8MHz freq */ - /* this freq will change to the predefined vccr settings - * when the mode change occures + /* This freq will change to the predefined vccr settings + * when the mode change occurs. */ /* and wait until system clock changed */ @@ -2228,8 +2228,8 @@ static void up_pm_notify(struct pm_callback_s *cb, int domain, /* set the system clock to the SIRC 8MHz freq */ - /* this freq will change to the predefined vccr settings - * when the mode change occures + /* This freq will change to the predefined vccr settings + * when the mode change occurs. */ /* and wait until system clock changed */ diff --git a/arch/arm/src/s32k1xx/s32k1xx_edma.h b/arch/arm/src/s32k1xx/s32k1xx_edma.h index f0dcc8178b..c314b4ecf9 100644 --- a/arch/arm/src/s32k1xx/s32k1xx_edma.h +++ b/arch/arm/src/s32k1xx/s32k1xx_edma.h @@ -79,7 +79,7 @@ * i mxrt_dmach_stop(handle); * * 7. The callback will be received when the DMA completes (or an error - * occurs). After that, you may free the DMA channel, or re-use it on + * occurs). After that, you may free the DMA channel, or reuse it on * subsequent DMAs. * * s32k1xx_dmach_free(handle); diff --git a/arch/arm/src/s32k1xx/s32k1xx_eeeprom.c b/arch/arm/src/s32k1xx/s32k1xx_eeeprom.c index 73e583f149..78a3a29792 100644 --- a/arch/arm/src/s32k1xx/s32k1xx_eeeprom.c +++ b/arch/arm/src/s32k1xx/s32k1xx_eeeprom.c @@ -140,7 +140,7 @@ static uint32_t execute_ftfc_command() if (retval & (FTTC_FSTAT_MGSTAT0 | FTTC_FSTAT_FPVIOL | FTTC_FSTAT_ACCERR | FTTC_FSTAT_RDCOLERR)) { - return retval; /* Error has occured */ + return retval; /* Error has occurred */ } return retval; diff --git a/arch/arm/src/s32k1xx/s32k1xx_lowputc.c b/arch/arm/src/s32k1xx/s32k1xx_lowputc.c index e0cfab6104..df4ded96f1 100644 --- a/arch/arm/src/s32k1xx/s32k1xx_lowputc.c +++ b/arch/arm/src/s32k1xx/s32k1xx_lowputc.c @@ -396,7 +396,7 @@ void s32k1xx_lowputc(int ch) } /* If the character to output is a newline, - * then pre-pend a carriage return + * then prepend a carriage return. */ if (ch == '\n') diff --git a/arch/arm/src/s32k1xx/s32k1xx_lpi2c.c b/arch/arm/src/s32k1xx/s32k1xx_lpi2c.c index 67781f5179..a86bd7172c 100644 --- a/arch/arm/src/s32k1xx/s32k1xx_lpi2c.c +++ b/arch/arm/src/s32k1xx/s32k1xx_lpi2c.c @@ -1835,7 +1835,7 @@ static int s32k1xx_lpi2c_dma_transfer(struct s32k1xx_lpi2c_priv_s *priv) LPI2C_MSR_ALF | LPI2C_MSR_FEF); - /* Enable the Iterrupts */ + /* Enable the Interrupts */ s32k1xx_lpi2c_putreg(priv, S32K1XX_LPI2C_MIER_OFFSET, LPI2C_MIER_NDIE | LPI2C_MIER_ALIE | @@ -2138,7 +2138,7 @@ static int s32k1xx_lpi2c_reset(struct i2c_master_s *dev) out: - /* Release the port for re-use by other clients */ + /* Release the port for reuse by other clients */ nxmutex_unlock(&priv->lock); return ret; diff --git a/arch/arm/src/s32k1xx/s32k1xx_progmem.c b/arch/arm/src/s32k1xx/s32k1xx_progmem.c index 8b3cdc779e..8cf1ccf691 100644 --- a/arch/arm/src/s32k1xx/s32k1xx_progmem.c +++ b/arch/arm/src/s32k1xx/s32k1xx_progmem.c @@ -101,7 +101,7 @@ static uint32_t execute_ftfc_command(void) if (retval & (FTTC_FSTAT_MGSTAT0 | FTTC_FSTAT_FPVIOL | FTTC_FSTAT_ACCERR | FTTC_FSTAT_RDCOLERR)) { - return retval; /* Error has occured */ + return retval; /* Error has occurred */ } else { @@ -261,7 +261,7 @@ ssize_t up_progmem_eraseblock(size_t block) if (execute_ftfc_command() & (FTTC_FSTAT_MGSTAT0 | FTTC_FSTAT_FPVIOL | FTTC_FSTAT_ACCERR | FTTC_FSTAT_RDCOLERR)) { - return -EIO; /* Error has occured */ + return -EIO; /* Error has occurred */ } return (ssize_t)S32K1XX_PROGMEM_BLOCK_SECTOR_SIZE; @@ -388,7 +388,7 @@ ssize_t up_progmem_write(size_t addr, const void *buf, size_t count) if (execute_ftfc_command() & (FTTC_FSTAT_MGSTAT0 | FTTC_FSTAT_FPVIOL | FTTC_FSTAT_ACCERR | FTTC_FSTAT_RDCOLERR)) { - return -EIO; /* Error has occured */ + return -EIO; /* Error has occurred */ } dest.addr = dest.addr + S32K1XX_PROGMEM_DFLASH_WRITE_UNIT_SIZE; diff --git a/arch/arm/src/s32k1xx/s32k1xx_serial.c b/arch/arm/src/s32k1xx/s32k1xx_serial.c index 31f98add2f..d46de3709e 100644 --- a/arch/arm/src/s32k1xx/s32k1xx_serial.c +++ b/arch/arm/src/s32k1xx/s32k1xx_serial.c @@ -210,7 +210,7 @@ struct s32k1xx_uart_s #ifdef SERIAL_HAVE_TXDMA const unsigned int dma_txreqsrc; /* DMAMUX source of TX DMA request */ - DMACH_HANDLE txdma; /* currently-open trasnmit DMA stream */ + DMACH_HANDLE txdma; /* currently-open transmit DMA stream */ sem_t txdmasem; /* Indicate TX DMA completion */ #endif @@ -813,7 +813,7 @@ static int s32k1xx_dma_setup(struct uart_dev_s *dev) modifyreg32(priv->uartbase + S32K1XX_LPUART_BAUD_OFFSET, 0, LPUART_BAUD_RDMAE); - /* Enable itnerrupt on Idel and errors */ + /* Enable interrupt on Idle and errors */ modifyreg32(priv->uartbase + S32K1XX_LPUART_CTRL_OFFSET, 0, LPUART_CTRL_PEIE | @@ -2472,7 +2472,7 @@ static int up_pm_prepare(struct pm_callback_s *cb, int domain, * * Description: * Performs the low level UART initialization early in debug so that the - * serial console will be available during bootup. This must be called + * serial console will be available during boot up. This must be called * before arm_serialinit. * ****************************************************************************/ diff --git a/arch/arm/src/s32k1xx/s32k1xx_serial.h b/arch/arm/src/s32k1xx/s32k1xx_serial.h index 8f8cf81373..d839d280b4 100644 --- a/arch/arm/src/s32k1xx/s32k1xx_serial.h +++ b/arch/arm/src/s32k1xx/s32k1xx_serial.h @@ -177,7 +177,7 @@ extern "C" * * Description: * Performs the low level UART initialization early in debug so that the - * serial console will be available during bootup. This must be called + * serial console will be available during boot up. This must be called * before arm_serialinit. * ****************************************************************************/ diff --git a/arch/arm/src/s32k3xx/Kconfig b/arch/arm/src/s32k3xx/Kconfig index a51948c17c..2c15d6b8ee 100644 --- a/arch/arm/src/s32k3xx/Kconfig +++ b/arch/arm/src/s32k3xx/Kconfig @@ -596,7 +596,7 @@ config S32K3XX_FS26 bool "FS26 SBC Disable watchdog" default n ---help--- - Disables the FS26 watchdog so that the S32K3XX MCU does not get resetted. + Disables the FS26 watchdog so that the S32K3XX MCU does not get reset. Engineering development purpose only, not for use in production. Please refer to the FS26 Datasheet. @@ -1235,7 +1235,7 @@ config S32K3XX_LPI2C_DMA_MAXMSG default 8 depends on S32K3XX_LPI2C_DMA ---help--- - This option set the mumber of mesg that can be in a transfer. + This option set the number of mesg that can be in a transfer. It is used to allocate space for the 16 bit LPI2C commands that will be DMA-ed to the LPI2C device. diff --git a/arch/arm/src/s32k3xx/hardware/s32k3xx_emac.h b/arch/arm/src/s32k3xx/hardware/s32k3xx_emac.h index 1ac45a4380..cd9f31b49e 100644 --- a/arch/arm/src/s32k3xx/hardware/s32k3xx_emac.h +++ b/arch/arm/src/s32k3xx/hardware/s32k3xx_emac.h @@ -2071,7 +2071,7 @@ #define EMAC_MAC_PPS1_WIDTH_PPSWIDTH1_MASK (0xffffffff << EMAC_MAC_PPS1_WIDTH_PPSWIDTH1_SHIFT) #define EMAC_MAC_PPS1_WIDTH_PPSWIDTH1(n) (((n) << EMAC_MAC_PPS1_WIDTH_PPSWIDTH1_SHIFT) & EMAC_MAC_PPS1_WIDTH_PPSWIDTH1_MASK) -/* MAC PPS2 Taget Time In Seconds (MAC_PPS2_TARGET_TIME_SECONDS) */ +/* MAC PPS2 Target Time In Seconds (MAC_PPS2_TARGET_TIME_SECONDS) */ #define EMAC_MAC_PPS2_TARGET_TIME_SECONDS_TSTRH2_SHIFT (0) /* Bits 0-32: PPS Target Time In Seconds 2 */ #define EMAC_MAC_PPS2_TARGET_TIME_SECONDS_TSTRH2_MASK (0xffffffff << EMAC_MAC_PPS2_TARGET_TIME_SECONDS_TSTRH2_SHIFT) #define EMAC_MAC_PPS2_TARGET_TIME_SECONDS_TSTRH2(n) (((n) << EMAC_MAC_PPS2_TARGET_TIME_SECONDS_TSTRH2_SHIFT) & EMAC_MAC_PPS2_TARGET_TIME_SECONDS_TSTRH2_MASK) @@ -2345,7 +2345,7 @@ #define EMAC_MTL_ECC_CONTROL_MRXPEE (1 << 3) /* Bit 3: MTL Rx Parser ECC Enable */ #define EMAC_MTL_ECC_CONTROL_MEEAO (1 << 8) /* Bit 8: MTL ECC Error Address Status Over-ride */ -/* MTL Safety Interript Status (MTL_SAFETY_INTERRUPT_STATUS) */ +/* MTL Safety Interrupt Status (MTL_SAFETY_INTERRUPT_STATUS) */ #define EMAC_MTL_SAFETY_INTERRUPT_STATUS_MECIS (1 << 0) /* Bit 0: MTL ECC Correctable Error Interrupt Status */ #define EMAC_MTL_SAFETY_INTERRUPT_STATUS_MEUIS (1 << 1) /* Bit 1: MTL ECC Uncorrectable Error Interrupt Status */ @@ -2377,7 +2377,7 @@ #define EMAC_MTL_ECC_ERR_STS_RCTL_CCES (1 << 4) /* Bit 4: Clear Correctable Error Status */ #define EMAC_MTL_ECC_ERR_STS_RCTL_CUES (1 << 5) /* Bit 5: Clear Uncorrectable Error Status */ -/* MTL ECC Error Adress Status (MTL_ECC_ERR_ADDR_STATUS) */ +/* MTL ECC Error Address Status (MTL_ECC_ERR_ADDR_STATUS) */ #define EMAC_MTL_ECC_ERR_ADDR_STATUS_ECEAS_SHIFT (0) /* Bits 0-16: MTL ECC Correctable Error Address Status */ #define EMAC_MTL_ECC_ERR_ADDR_STATUS_ECEAS_MASK (0xffff << EMAC_MTL_ECC_ERR_ADDR_STATUS_ECEAS_SHIFT) #define EMAC_MTL_ECC_ERR_ADDR_STATUS_ECEAS(n) (((n) << EMAC_MTL_ECC_ERR_ADDR_STATUS_ECEAS_SHIFT) & EMAC_MTL_ECC_ERR_ADDR_STATUS_ECEAS_MASK) @@ -2846,7 +2846,7 @@ #define EMAC_DMA_CH0_STATUS_REB(n) (((n) << EMAC_DMA_CH0_STATUS_REB_SHIFT) & EMAC_DMA_CH0_STATUS_REB_MASK) /* DMA Channel 0 Miss Frame Counter (DMA_CH0_MISS_FRAME_CNT) */ -#define EMAC_DMA_CH0_MISS_FRAME_CNT_MFC_SHIFT (0) /* Bits 0-11: Dropped Packet Counters Indicates the number of packet counters that DMA drops either because of bus error or because of programing RPF field in DMA_CH${i}_Rx_Control register */ +#define EMAC_DMA_CH0_MISS_FRAME_CNT_MFC_SHIFT (0) /* Bits 0-11: Dropped Packet Counters Indicates the number of packet counters that DMA drops either because of bus error or because of programming RPF field in DMA_CH${i}_Rx_Control register */ #define EMAC_DMA_CH0_MISS_FRAME_CNT_MFC_MASK (0x7ff << EMAC_DMA_CH0_MISS_FRAME_CNT_MFC_SHIFT) #define EMAC_DMA_CH0_MISS_FRAME_CNT_MFC(n) (((n) << EMAC_DMA_CH0_MISS_FRAME_CNT_MFC_SHIFT) & EMAC_DMA_CH0_MISS_FRAME_CNT_MFC_MASK) #define EMAC_DMA_CH0_MISS_FRAME_CNT_MFCO (1 << 15) /* Bit 15: Overflow status of the MFC Counter */ diff --git a/arch/arm/src/s32k3xx/hardware/s32k3xx_fxosc.h b/arch/arm/src/s32k3xx/hardware/s32k3xx_fxosc.h index ef189d6063..332a6d8b3e 100644 --- a/arch/arm/src/s32k3xx/hardware/s32k3xx_fxosc.h +++ b/arch/arm/src/s32k3xx/hardware/s32k3xx_fxosc.h @@ -81,7 +81,7 @@ /* Oscillator Status Register (STAT) */ /* Bits 0-30: Reserved */ -#define FXOSC_STAT_OSC_STAT (1 << 31) /* Bit 31: Crystal oscilator status (OSC_STAT) */ +#define FXOSC_STAT_OSC_STAT (1 << 31) /* Bit 31: Crystal oscillator status (OSC_STAT) */ # define FXOSC_STAT_OSC_STAT_OFF (0 << 31) /* Crystal oscillator is off or not stable */ # define FXOSC_STAT_OSC_STAT_ON (1 << 31) /* Crystal oscillator is on and providing a stable clock */ diff --git a/arch/arm/src/s32k3xx/hardware/s32k3xx_mscm.h b/arch/arm/src/s32k3xx/hardware/s32k3xx_mscm.h index d234f717d0..22c76b9dbe 100644 --- a/arch/arm/src/s32k3xx/hardware/s32k3xx_mscm.h +++ b/arch/arm/src/s32k3xx/hardware/s32k3xx_mscm.h @@ -179,7 +179,7 @@ #define MSCM_CPXCFG3_FPU (1 << 0) /* Bit 0: Floating Point Unit (FPU) */ #define MSCM_CPXCFG3_SIMD (1 << 1) /* Bit 1: SIMD/NEON Instruction Support (SIMD) */ -#define MSCM_CPXCFG3_MMU (1 << 2) /* Bit 2: Memory Mangement Unit (MMU) */ +#define MSCM_CPXCFG3_MMU (1 << 2) /* Bit 2: Memory Management Unit (MMU) */ #define MSCM_CPXCFG3_CMP (1 << 3) /* Bit 3: Core Memory Protection Unit (CMP) */ #define MSCM_CPXCFG3_CPY (1 << 4) /* Bit 4: Cryptography (CPY) */ /* Bits 5-31: Reserved */ diff --git a/arch/arm/src/s32k3xx/hardware/s32k3xx_qspi.h b/arch/arm/src/s32k3xx/hardware/s32k3xx_qspi.h index 86343e7338..34642e248c 100644 --- a/arch/arm/src/s32k3xx/hardware/s32k3xx_qspi.h +++ b/arch/arm/src/s32k3xx/hardware/s32k3xx_qspi.h @@ -153,7 +153,7 @@ /* Module Configuration Register (MCR) */ #define QSPI_MCR_SWRSTSD (1 << 0) /* Bit 0: Software reset for serial flash memory domain (SWRSTSD) */ -#define QSPI_MCR_SWRSTHD (1 << 1) /* Bit 1: Software reset fo AHB domain (SWRSTHD) */ +#define QSPI_MCR_SWRSTHD (1 << 1) /* Bit 1: Software reset for AHB domain (SWRSTHD) */ /* Bits 2-9: Reserved */ #define QSPI_MCR_CLR_RXF (1 << 10) /* Bit 10: Clear RX FIFO (CLR_RXF) */ #define QSPI_MCR_CLR_TXF (1 << 11) /* Bit 11: Clear TX FIFO/buffer (CLR_TXF) */ diff --git a/arch/arm/src/s32k3xx/hardware/s32k3xx_sxosc.h b/arch/arm/src/s32k3xx/hardware/s32k3xx_sxosc.h index 22485a9d8b..eb6f8f8b52 100644 --- a/arch/arm/src/s32k3xx/hardware/s32k3xx_sxosc.h +++ b/arch/arm/src/s32k3xx/hardware/s32k3xx_sxosc.h @@ -57,7 +57,7 @@ /* SXOSC Status Register (STAT) */ /* Bits 0-30: Reserved */ -#define SXOSC_STAT_OSC_STAT (1 << 31) /* Bit 31: Crystal oscilator status (OSC_STAT) */ +#define SXOSC_STAT_OSC_STAT (1 << 31) /* Bit 31: Crystal oscillator status (OSC_STAT) */ # define SXOSC_STAT_OSC_STAT_UNSTABLE (0 << 31) /* Crystal oscillator is unstable */ # define SXOSC_STAT_OSC_STAT_STABLE (1 << 31) /* Crystal oscillator is stable */ diff --git a/arch/arm/src/s32k3xx/s32k3xx_clockconfig.c b/arch/arm/src/s32k3xx/s32k3xx_clockconfig.c index 0bae42a560..aa014d1347 100644 --- a/arch/arm/src/s32k3xx/s32k3xx_clockconfig.c +++ b/arch/arm/src/s32k3xx/s32k3xx_clockconfig.c @@ -245,7 +245,7 @@ static uint32_t s32k3xx_get_phi0freq(void) * Name: s32k3xx_get_scsfreq * * Description: - * Gets SCS current system clock frequence + * Gets SCS current system clock frequency * * Input Parameters: * None diff --git a/arch/arm/src/s32k3xx/s32k3xx_edma.h b/arch/arm/src/s32k3xx/s32k3xx_edma.h index 00fff86f9c..b1d4f5d380 100644 --- a/arch/arm/src/s32k3xx/s32k3xx_edma.h +++ b/arch/arm/src/s32k3xx/s32k3xx_edma.h @@ -87,7 +87,7 @@ * i mxrt_dmach_stop(handle); * * 7. The callback will be received when the DMA completes (or an error - * occurs). After that, you may free the DMA channel, or re-use it on + * occurs). After that, you may free the DMA channel, or reuse it on * subsequent DMAs. * * s32k3xx_dmach_free(handle); diff --git a/arch/arm/src/s32k3xx/s32k3xx_emac.c b/arch/arm/src/s32k3xx/s32k3xx_emac.c index 128ef13647..65ee3bdb26 100644 --- a/arch/arm/src/s32k3xx/s32k3xx_emac.c +++ b/arch/arm/src/s32k3xx/s32k3xx_emac.c @@ -1229,7 +1229,7 @@ static int s32k3xx_recvframe(struct s32k3xx_driver_s *priv) * 3) All of the TX descriptors are in flight. * * This last case is obscure. It is due to that fact that each packet - * that we receive can generate an unstoppable transmisson. So we have + * that we receive can generate an unstoppable transmission. So we have * to stop receiving when we can not longer transmit. In this case, the * transmit logic should also have disabled further RX interrupts. */ @@ -1498,7 +1498,7 @@ static void s32k3xx_receive(struct s32k3xx_driver_s *priv) } /* We are finished with the RX buffer. NOTE: If the buffer is - * re-used for transmission, the dev->d_buf field will have been + * reused for transmission, the dev->d_buf field will have been * nullified. */ @@ -1750,7 +1750,7 @@ static void s32k3xx_interrupt_work(void *arg) putreg32(EMAC_DMA_CH0_STATUS_NIS, S32K3XX_EMAC_DMA_CH0_STATUS); } - /* Handle error interrupt only if CONFIG_DEBUG_NET is eanbled */ + /* Handle error interrupt only if CONFIG_DEBUG_NET is enabled */ #ifdef CONFIG_DEBUG_NET /* Check if there are pending "abnormal" interrupts */ diff --git a/arch/arm/src/s32k3xx/s32k3xx_lowputc.c b/arch/arm/src/s32k3xx/s32k3xx_lowputc.c index 8d75856244..3da18e9abc 100644 --- a/arch/arm/src/s32k3xx/s32k3xx_lowputc.c +++ b/arch/arm/src/s32k3xx/s32k3xx_lowputc.c @@ -682,7 +682,7 @@ void s32k3xx_lowputc(int ch) } /* If the character to output is a newline, - * then pre-pend a carriage return + * then prepend a carriage return. */ if (ch == '\n') diff --git a/arch/arm/src/s32k3xx/s32k3xx_lpi2c.c b/arch/arm/src/s32k3xx/s32k3xx_lpi2c.c index 4807b909be..a2b219e841 100644 --- a/arch/arm/src/s32k3xx/s32k3xx_lpi2c.c +++ b/arch/arm/src/s32k3xx/s32k3xx_lpi2c.c @@ -1810,7 +1810,7 @@ static int s32k3xx_lpi2c_dma_transfer(struct s32k3xx_lpi2c_priv_s *priv) LPI2C_MSR_ALF | LPI2C_MSR_FEF); - /* Enable the Iterrupts */ + /* Enable the Interrupts */ s32k3xx_lpi2c_putreg(priv, S32K3XX_LPI2C_MIER_OFFSET, LPI2C_MIER_NDIE | LPI2C_MIER_ALIE | @@ -2114,7 +2114,7 @@ static int s32k3xx_lpi2c_reset(struct i2c_master_s *dev) out: - /* Release the port for re-use by other clients */ + /* Release the port for reuse by other clients */ nxmutex_unlock(&priv->lock); return ret; diff --git a/arch/arm/src/s32k3xx/s32k3xx_pin.h b/arch/arm/src/s32k3xx/s32k3xx_pin.h index cb69e7cffc..38591a0316 100644 --- a/arch/arm/src/s32k3xx/s32k3xx_pin.h +++ b/arch/arm/src/s32k3xx/s32k3xx_pin.h @@ -228,7 +228,7 @@ #define _IMCR_MASK (0x01ff << _IMCR_SHIFT) # define IMCR(n) ((((n) - 512) << _IMCR_SHIFT) & _IMCR_MASK) -#define _WKPU_SHIFT _IMCR_SHIFT /* WKPU number re-uses the IMCR field, only applicable if Input SSS = 12 */ +#define _WKPU_SHIFT _IMCR_SHIFT /* WKPU number reuses the IMCR field, only applicable if Input SSS = 12 */ #define _WKPU_MASK (0x3f << _WKPU_SHIFT) # define WPKU(n) (((n) << _WKPU_SHIFT) & _WKPU_MASK) @@ -287,7 +287,7 @@ * --o- ---- ---- ---- ---- ---- ---- ---- */ -#define _PIN_OUTPUT_INVAL_SHIFT (29) /* Bit 29: GPIO Inititial Value */ +#define _PIN_OUTPUT_INVAL_SHIFT (29) /* Bit 29: GPIO Initial Value */ #define _PIN_OUTPUT_INVAL_MASK (1 << _PIN_OUTPUT_INVAL_SHIFT) # define GPIO_OUTPUT_ZERO (0 << _PIN_OUTPUT_INVAL_SHIFT) /* 0: Initial output value is 0 */ # define GPIO_OUTPUT_ONE (1 << _PIN_OUTPUT_INVAL_SHIFT) /* 1: Initial output value is 1 */ diff --git a/arch/arm/src/s32k3xx/s32k3xx_qspi.c b/arch/arm/src/s32k3xx/s32k3xx_qspi.c index f127067e49..701d4eb4a3 100644 --- a/arch/arm/src/s32k3xx/s32k3xx_qspi.c +++ b/arch/arm/src/s32k3xx/s32k3xx_qspi.c @@ -1129,7 +1129,7 @@ static uint32_t qspi_setfrequency(struct qspi_dev_s *dev, uint32_t frequency) (void)prescaler; (void)priv; - /* FIXME add suport for frequency switching, + /* FIXME add support for frequency switching, * typically reads can be higher the nwrites */ diff --git a/arch/arm/src/s32k3xx/s32k3xx_serial.c b/arch/arm/src/s32k3xx/s32k3xx_serial.c index cebaab68a6..90af8f20f8 100644 --- a/arch/arm/src/s32k3xx/s32k3xx_serial.c +++ b/arch/arm/src/s32k3xx/s32k3xx_serial.c @@ -2992,7 +2992,7 @@ static int s32k3xx_dma_setup(struct uart_dev_s *dev) modifyreg32(priv->uartbase + S32K3XX_LPUART_BAUD_OFFSET, 0, LPUART_BAUD_RDMAE); - /* Enable itnerrupt on Idel and erros */ + /* Enable interrupt on Idle and errors */ modifyreg32(priv->uartbase + S32K3XX_LPUART_CTRL_OFFSET, 0, LPUART_CTRL_PEIE | @@ -4363,7 +4363,7 @@ static int up_pm_prepare(struct pm_callback_s *cb, int domain, * * Description: * Performs the low level UART initialization early in debug so that the - * serial console will be available during bootup. This must be called + * serial console will be available during boot up. This must be called * before arm_serialinit. * ****************************************************************************/ diff --git a/arch/arm/src/s32k3xx/s32k3xx_serial.h b/arch/arm/src/s32k3xx/s32k3xx_serial.h index d1712bbaa8..5a4e1f7305 100644 --- a/arch/arm/src/s32k3xx/s32k3xx_serial.h +++ b/arch/arm/src/s32k3xx/s32k3xx_serial.h @@ -409,7 +409,7 @@ extern "C" * * Description: * Performs the low level UART initialization early in debug so that the - * serial console will be available during bootup. This must be called + * serial console will be available during boot up. This must be called * before arm_serialinit. * ****************************************************************************/ diff --git a/arch/arm/src/sam34/hardware/sam4cm_supc.h b/arch/arm/src/sam34/hardware/sam4cm_supc.h index 0b8b1aa3b2..de56a8726b 100644 --- a/arch/arm/src/sam34/hardware/sam4cm_supc.h +++ b/arch/arm/src/sam34/hardware/sam4cm_supc.h @@ -89,7 +89,7 @@ #define SUPC_SMMR_SMSMPL_MASK (7 << SUPC_SMMR_SMSMPL_SHIFT) # define SUPC_SMMR_SMSMPL_SMD (0 << SUPC_SMMR_SMSMPL_SHIFT) /* Supply Monitor disabled */ # define SUPC_SMMR_SMSMPL_CSM (1 << SUPC_SMMR_SMSMPL_SHIFT) /* Continuous Supply Monitor */ -# define SUPC_SMMR_SMSMPL_32SLCK (2 << SUPC_SMMR_SMSMPL_SHIFT) /* Eevery 32 SLCK periods */ +# define SUPC_SMMR_SMSMPL_32SLCK (2 << SUPC_SMMR_SMSMPL_SHIFT) /* Every 32 SLCK periods */ # define SUPC_SMMR_SMSMPL_256SLCK (3 << SUPC_SMMR_SMSMPL_SHIFT) /* Every 256 SLCK periods */ # define SUPC_SMMR_SMSMPL_2048SLCK (4 << SUPC_SMMR_SMSMPL_SHIFT) /* Every 2,048 SLCK periods */ diff --git a/arch/arm/src/sam34/hardware/sam_dmac.h b/arch/arm/src/sam34/hardware/sam_dmac.h index 8172b4b434..0f2f5440d6 100644 --- a/arch/arm/src/sam34/hardware/sam_dmac.h +++ b/arch/arm/src/sam34/hardware/sam_dmac.h @@ -311,7 +311,7 @@ # define DMAC_CHDR_DIS2 (1 << (DMAC_CHDR_DIS_SHIFT+2)) # define DMAC_CHDR_DIS3 (1 << (DMAC_CHDR_DIS_SHIFT+3)) # define DMAC_CHDR_DIS_ALL DMAC_CHDR_DIS_MASK -#define DMAC_CHDR_RES_SHIFT (8) /* Bits 8-11: Resume trasnfer, restoring context */ +#define DMAC_CHDR_RES_SHIFT (8) /* Bits 8-11: Resume transfer, restoring context */ #define DMAC_CHDR_RES_MASK (15 << DMAC_CHDR_RES_SHIFT) # define DMAC_CHDR_RES(n) (1 << (DMAC_CHDR_RES_SHIFT+(n))) # define DMAC_CHDR_RES0 (1 << (DMAC_CHDR_RES_SHIFT+0)) diff --git a/arch/arm/src/sam34/hardware/sam_supc.h b/arch/arm/src/sam34/hardware/sam_supc.h index 5c20aed927..48ae640dd5 100644 --- a/arch/arm/src/sam34/hardware/sam_supc.h +++ b/arch/arm/src/sam34/hardware/sam_supc.h @@ -112,7 +112,7 @@ #define SUPC_SMMR_SMSMPL_MASK (7 << SUPC_SMMR_SMSMPL_SHIFT) # define SUPC_SMMR_SMSMPL_SMD (0 << SUPC_SMMR_SMSMPL_SHIFT) /* Supply Monitor disabled */ # define SUPC_SMMR_SMSMPL_CSM (1 << SUPC_SMMR_SMSMPL_SHIFT) /* Continuous Supply Monitor */ -# define SUPC_SMMR_SMSMPL_32SLCK (2 << SUPC_SMMR_SMSMPL_SHIFT) /* Eevery 32 SLCK periods */ +# define SUPC_SMMR_SMSMPL_32SLCK (2 << SUPC_SMMR_SMSMPL_SHIFT) /* Every 32 SLCK periods */ # define SUPC_SMMR_SMSMPL_256SLCK (3 << SUPC_SMMR_SMSMPL_SHIFT) /* Every 256 SLCK periods */ # define SUPC_SMMR_SMSMPL_2048SLCK (4 << SUPC_SMMR_SMSMPL_SHIFT) /* Every 2,048 SLCK periods */ diff --git a/arch/arm/src/sam34/sam4cm_tc.c b/arch/arm/src/sam34/sam4cm_tc.c index a326f5fc07..d59304e3d6 100644 --- a/arch/arm/src/sam34/sam4cm_tc.c +++ b/arch/arm/src/sam34/sam4cm_tc.c @@ -402,7 +402,7 @@ static void sam_regdump(struct sam_chan_s *chan, const char *msg) * * Returned Value: * true: This is the first register access of this type. - * flase: This is the same as the preceding register access. + * false: This is the same as the preceding register access. * ****************************************************************************/ diff --git a/arch/arm/src/sam34/sam4l_clockconfig.c b/arch/arm/src/sam34/sam4l_clockconfig.c index d1422ad17c..f376e6170a 100644 --- a/arch/arm/src/sam34/sam4l_clockconfig.c +++ b/arch/arm/src/sam34/sam4l_clockconfig.c @@ -334,7 +334,7 @@ # error Missing PLL0 source # endif -/* PLL0 Multipler and Divider */ +/* PLL0 Multiplier and Divider */ # if !defined(BOARD_PLL0_MUL) # error BOARD_PLL0_MUL is not defined @@ -823,12 +823,12 @@ static inline void sam_enabledfll0(void) SAM_SCIF_DFLL0STEP, SAM_SCIF_DFLL0STEP_OFFSET); - /* Set the DFLL0 multipler register */ + /* Set the DFLL0 multiplier register */ sam_dfll0_putreg32(BOARD_DFLL0_MUL, SAM_SCIF_DFLL0MUL, SAM_SCIF_DFLL0MUL_OFFSET); - /* Set the multipler and spread spectrum generator control registers */ + /* Set the multiplier and spread spectrum generator control registers */ sam_dfll0_putreg32(0, SAM_SCIF_DFLL0SSG, SAM_SCIF_DFLL0SSG_OFFSET); @@ -1271,7 +1271,7 @@ void sam_clockconfig(void) fastwkup = false; #elif BOARD_CPU_FREQUENCY <= FLASH_MAXFREQ_PS1_HSDIS_FWS1 - /* Not high speed mode and frequency is below the thrshold. We can go to + /* Not high speed mode and frequency is below the threshold. We can go to * power scaling mode 1. */ diff --git a/arch/arm/src/sam34/sam_dmac.c b/arch/arm/src/sam34/sam_dmac.c index 5ce2e23f52..3afd20f6a3 100644 --- a/arch/arm/src/sam34/sam_dmac.c +++ b/arch/arm/src/sam34/sam_dmac.c @@ -979,7 +979,7 @@ static int sam_txbuffer(struct sam_dma_s *dmach, uint32_t paddr, uint32_t ctrla; uint32_t ctrlb; - /* If we are appending a buffer to a linklist, then re-use the CTRLA/B + /* If we are appending a buffer to a linklist, then reuse the CTRLA/B * values. Otherwise, create them from the properties of the transfer. */ @@ -1028,7 +1028,7 @@ static int sam_rxbuffer(struct sam_dma_s *dmach, uint32_t paddr, uint32_t ctrla; uint32_t ctrlb; - /* If we are appending a buffer to a linklist, then re-use the CTRLA/B + /* If we are appending a buffer to a linklist, then reuse the CTRLA/B * values. Otherwise, create them from the properties of the transfer. */ diff --git a/arch/arm/src/sam34/sam_emac.c b/arch/arm/src/sam34/sam_emac.c index 76c67b0160..0144794c7f 100644 --- a/arch/arm/src/sam34/sam_emac.c +++ b/arch/arm/src/sam34/sam_emac.c @@ -429,7 +429,7 @@ static int sam_emac_configure(struct sam_emac_s *priv); * * Returned Value: * true: This is the first register access of this type. - * flase: This is the same as the preceding register access. + * false: This is the same as the preceding register access. * ****************************************************************************/ @@ -1447,7 +1447,7 @@ static void sam_interrupt_work(void *arg) /* Check for the receipt of an RX packet. * * RXCOMP indicates that a packet has been received and stored in memory. - * The RXCOMP bit is cleared whent he interrupt status register was read. + * The RXCOMP bit is cleared when the interrupt status register was read. * RSR:REC indicates that one or more frames have been received and placed * in memory. This indication is cleared by writing a one to this bit. */ diff --git a/arch/arm/src/sam34/sam_serial.c b/arch/arm/src/sam34/sam_serial.c index 02123f42c9..97f625e275 100644 --- a/arch/arm/src/sam34/sam_serial.c +++ b/arch/arm/src/sam34/sam_serial.c @@ -1326,7 +1326,7 @@ static bool up_txempty(struct uart_dev_s *dev) * * Description: * Performs the low level USART initialization early in debug so that the - * serial console will be available during bootup. This must be called + * serial console will be available during boot up. This must be called * before arm_serialinit. * ****************************************************************************/ diff --git a/arch/arm/src/sam34/sam_spi.c b/arch/arm/src/sam34/sam_spi.c index 575794397c..98f8c19cf8 100644 --- a/arch/arm/src/sam34/sam_spi.c +++ b/arch/arm/src/sam34/sam_spi.c @@ -391,7 +391,7 @@ static struct sam_spidev_s g_spi1dev = * * Returned Value: * true: This is the first register access of this type. - * flase: This is the same as the preceding register access. + * false: This is the same as the preceding register access. * ****************************************************************************/ diff --git a/arch/arm/src/sam34/sam_udp.c b/arch/arm/src/sam34/sam_udp.c index 3af23f9ce3..ed468a37f7 100644 --- a/arch/arm/src/sam34/sam_udp.c +++ b/arch/arm/src/sam34/sam_udp.c @@ -2772,7 +2772,7 @@ sam_ep_reserve(struct sam_usbdev_s *priv, uint8_t epset) * * Description: * The endpoint is no long in-used. It will be unreserved and can be - * re-used if needed. + * reused if needed. * ****************************************************************************/ diff --git a/arch/arm/src/sama5/hardware/sam_dmac.h b/arch/arm/src/sama5/hardware/sam_dmac.h index b4a8cef170..54b2e2be51 100644 --- a/arch/arm/src/sama5/hardware/sam_dmac.h +++ b/arch/arm/src/sama5/hardware/sam_dmac.h @@ -557,7 +557,7 @@ # define DMAC_CHDR_DIS6 (1 << (DMAC_CHDR_DIS_SHIFT+6)) # define DMAC_CHDR_DIS7 (1 << (DMAC_CHDR_DIS_SHIFT+7)) # define DMAC_CHDR_DIS_ALL DMAC_CHDR_DIS_MASK -#define DMAC_CHDR_RES_SHIFT (8) /* Bits 8-15: Resume trasnfer, restoring context */ +#define DMAC_CHDR_RES_SHIFT (8) /* Bits 8-15: Resume transfer, restoring context */ #define DMAC_CHDR_RES_MASK (0xff << DMAC_CHDR_RES_SHIFT) # define DMAC_CHDR_RES(n) (1 << (DMAC_CHDR_RES_SHIFT+(n))) # define DMAC_CHDR_RES0 (1 << (DMAC_CHDR_RES_SHIFT+0)) diff --git a/arch/arm/src/sama5/sam_adc.c b/arch/arm/src/sama5/sam_adc.c index 329bff9f49..4a507259cd 100644 --- a/arch/arm/src/sama5/sam_adc.c +++ b/arch/arm/src/sama5/sam_adc.c @@ -539,7 +539,7 @@ static struct adc_dev_s g_adcdev = * * Returned Value: * true: This is the first register access of this type. - * flase: This is the same as the preceding register access. + * false: This is the same as the preceding register access. * ****************************************************************************/ @@ -865,7 +865,7 @@ static void sam_adc_trigperiod(struct sam_adc_s *priv, uint32_t period) uint32_t regval; uint32_t div; - /* Divide trigger period avoid overflows. Division by ten is awkard, but + /* Divide trigger period avoid overflows. Division by ten is awkward, but * appropriate here because times are specified in decimal with lots of * zeroes. */ @@ -1644,7 +1644,7 @@ static int sam_adc_trigger(struct sam_adc_s *priv) } /* Configure to trigger using Timer/counter 0, channel 1, 2, or 3. - * NOTE: This trigger option depends on having properly configuer + * NOTE: This trigger option depends on having properly configured * timer/counter 0 to provide this output. That is done independently * the timer/counter driver. */ diff --git a/arch/arm/src/sama5/sam_can.c b/arch/arm/src/sama5/sam_can.c index 44837a513b..4ba07231d2 100644 --- a/arch/arm/src/sama5/sam_can.c +++ b/arch/arm/src/sama5/sam_can.c @@ -105,7 +105,7 @@ * * CAN_INT_CERR YES Bit 24: Mailbox CRC Error * CAN_INT_SERR YES Bit 25: Mailbox Stuffing Error - * CAN_INT_AERR NO Bit 26: Acknowledgment Error (usally means no + * CAN_INT_AERR NO Bit 26: Acknowledgment Error (usually means no * CAN bus) * CAN_INT_FERR YES Bit 27: Form Error * @@ -141,7 +141,7 @@ struct sam_filter_s struct sam_config_s { uint8_t port; /* CAN port number (1 or 2) */ - uint8_t pid; /* CAN periperal ID/IRQ number */ + uint8_t pid; /* CAN peripheral ID/IRQ number */ uint8_t nrecvmb; /* Number of receive mailboxes */ uintptr_t base; /* Base address of the CAN control registers */ uint32_t baud; /* Configured baud */ @@ -1287,7 +1287,7 @@ static inline void can_rxinterrupt(struct can_dev_s *dev, int mbndx, md[0] = can_getreg(priv, SAM_CAN_MNDH_OFFSET(mbndx)); md[1] = can_getreg(priv, SAM_CAN_MNDL_OFFSET(mbndx)); - /* Get the ID associated with the newly received message: )nce a new + /* Get the ID associated with the newly received message: once a new * message is received, its ID is masked with the CAN_MAMx value and * compared with the CAN_MIDx value. If accepted, the message ID is * copied to the CAN_MIDx register. diff --git a/arch/arm/src/sama5/sam_classd.c b/arch/arm/src/sama5/sam_classd.c index 4b6e52dfc8..494a11dde8 100644 --- a/arch/arm/src/sama5/sam_classd.c +++ b/arch/arm/src/sama5/sam_classd.c @@ -1312,7 +1312,7 @@ static void classd_reset(struct classd_dev_s *priv) * Calculate the right and left attenuation values based on the * volume and balance settings. * - * The range is limited to 0..78 since any value <77 wil be treated as + * The range is limited to 0..78 since any value <77 will be treated as * mutes. * * Input Parameters: diff --git a/arch/arm/src/sama5/sam_dbgu.c b/arch/arm/src/sama5/sam_dbgu.c index 6b2df17652..e3e039998e 100644 --- a/arch/arm/src/sama5/sam_dbgu.c +++ b/arch/arm/src/sama5/sam_dbgu.c @@ -559,7 +559,7 @@ static bool dbgu_txempty(struct uart_dev_s *dev) * * Description: * Performs the low level DBGU initialization early in debug so that the - * DBGU console will be available during bootup. This must be called + * DBGU console will be available during boot up. This must be called * before getreg32it. * ****************************************************************************/ @@ -611,7 +611,7 @@ void sam_dbgu_register(void) * * Description: * Performs the low level DBGU initialization early in debug so that the - * DBGU console will be available during bootup. This must be called + * DBGU console will be available during boot up. This must be called * before getreg32it. * ****************************************************************************/ diff --git a/arch/arm/src/sama5/sam_dbgu.h b/arch/arm/src/sama5/sam_dbgu.h index a803ee5f83..286141f672 100644 --- a/arch/arm/src/sama5/sam_dbgu.h +++ b/arch/arm/src/sama5/sam_dbgu.h @@ -69,7 +69,7 @@ extern "C" * * Description: * Performs the low level DBGU initialization early in debug so that the - * DBGU console will be available during bootup. + * DBGU console will be available during boot up. * ****************************************************************************/ diff --git a/arch/arm/src/sama5/sam_dmac.c b/arch/arm/src/sama5/sam_dmac.c index 10ba0800c9..0e2f00759f 100644 --- a/arch/arm/src/sama5/sam_dmac.c +++ b/arch/arm/src/sama5/sam_dmac.c @@ -1486,7 +1486,7 @@ static int sam_txbuffer(struct sam_dmach_s *dmach, uint32_t paddr, uint32_t ctrla; uint32_t ctrlb; - /* If we are appending a buffer to a linklist, then re-use the CTRLA/B + /* If we are appending a buffer to a linklist, then reuse the CTRLA/B * values. Otherwise, create them from the properties of the transfer. */ @@ -1535,7 +1535,7 @@ static int sam_rxbuffer(struct sam_dmach_s *dmach, uint32_t paddr, uint32_t ctrla; uint32_t ctrlb; - /* If we are appending a buffer to a linklist, then re-use the CTRLA/B + /* If we are appending a buffer to a linklist, then reuse the CTRLA/B * values. Otherwise, create them from the properties of the transfer. */ @@ -2254,7 +2254,7 @@ int sam_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg) if (dmach->llhead) { - /* Save the callback info. This will be invoked whent the DMA + /* Save the callback info. This will be invoked when the DMA * completes */ diff --git a/arch/arm/src/sama5/sam_ehci.c b/arch/arm/src/sama5/sam_ehci.c index c0b7d39553..35e927c561 100644 --- a/arch/arm/src/sama5/sam_ehci.c +++ b/arch/arm/src/sama5/sam_ehci.c @@ -1501,7 +1501,7 @@ static struct sam_qh_s *sam_qh_create(struct sam_rhport_s *rhport, * FIELD DESCRIPTION VALUE/SOURCE * -------- ------------------------------- -------------------- * DEVADDR Device address Endpoint structure - * I Inactivate on Next Transaction 0 + * I Deactivate on Next Transaction 0 * ENDPT Endpoint number Endpoint structure * EPS Endpoint speed Endpoint structure * DTC Data toggle control 1 @@ -3808,7 +3808,7 @@ static int sam_epalloc(struct usbhost_driver_s *drvr, * Input Parameters: * drvr - The USB host driver instance obtained as a parameter from the * call to the class create() method. - * ep - The endpint to be freed. + * ep - The endpoint to be freed. * * Returned Value: * On success, zero (OK) is returned. On a failure, a negated errno value diff --git a/arch/arm/src/sama5/sam_emaca.c b/arch/arm/src/sama5/sam_emaca.c index e767c6022a..ef179ea85f 100644 --- a/arch/arm/src/sama5/sam_emaca.c +++ b/arch/arm/src/sama5/sam_emaca.c @@ -451,7 +451,7 @@ static int sam_emac_configure(struct sam_emac_s *priv); * * Returned Value: * true: This is the first register access of this type. - * flase: This is the same as the preceding register access. + * false: This is the same as the preceding register access. * ****************************************************************************/ @@ -1503,7 +1503,7 @@ static void sam_interrupt_work(void *arg) /* Check for the receipt of an RX packet. * * RXCOMP indicates that a packet has been received and stored in memory. - * The RXCOMP bit is cleared whent he interrupt status register was read. + * The RXCOMP bit is cleared when the interrupt status register was read. * RSR:REC indicates that one or more frames have been received and placed * in memory. This indication is cleared by writing a one to this bit. */ diff --git a/arch/arm/src/sama5/sam_emacb.c b/arch/arm/src/sama5/sam_emacb.c index e0893dd52a..be7137e66a 100644 --- a/arch/arm/src/sama5/sam_emacb.c +++ b/arch/arm/src/sama5/sam_emacb.c @@ -768,7 +768,7 @@ static struct sam_emac_s g_emac1; * * Returned Value: * true: This is the first register access of this type. - * flase: This is the same as the preceding register access. + * false: This is the same as the preceding register access. * ****************************************************************************/ diff --git a/arch/arm/src/sama5/sam_flexcom_serial.c b/arch/arm/src/sama5/sam_flexcom_serial.c index 63da053891..c1c752704d 100644 --- a/arch/arm/src/sama5/sam_flexcom_serial.c +++ b/arch/arm/src/sama5/sam_flexcom_serial.c @@ -1118,7 +1118,7 @@ static bool flexus_txempty(struct uart_dev_s *dev) * * Description: * Performs the low level Flexcom USART initialization early so that the - * Flexcom serial console will be available during bootup. This must be + * Flexcom serial console will be available during boot up. This must be * called before flexus_serialinit. * ****************************************************************************/ diff --git a/arch/arm/src/sama5/sam_flexcom_spi.c b/arch/arm/src/sama5/sam_flexcom_spi.c index e55e1062f3..08181fc527 100644 --- a/arch/arm/src/sama5/sam_flexcom_spi.c +++ b/arch/arm/src/sama5/sam_flexcom_spi.c @@ -523,7 +523,7 @@ static struct sam_flex_spidev_s g_flexcom4dev = * * Returned Value: * true: This is the first register access of this type. - * flase: This is the same as the preceding register access. + * false: This is the same as the preceding register access. * ****************************************************************************/ @@ -1815,7 +1815,7 @@ static void flex_spi_recvblock(struct spi_dev_s *dev, void *buffer, * Initialize the selected flexcom SPI port * * Input Parameters: - * port - the 5 flexcom ports only have 2 physial CS lines + * port - the 5 flexcom ports only have 2 physical CS lines * - so there are 10 "logical" ports. * * Returned Value: diff --git a/arch/arm/src/sama5/sam_gmac.c b/arch/arm/src/sama5/sam_gmac.c index 4f77784eda..8b4eb991a2 100644 --- a/arch/arm/src/sama5/sam_gmac.c +++ b/arch/arm/src/sama5/sam_gmac.c @@ -386,7 +386,7 @@ static int sam_gmac_configure(struct sam_gmac_s *priv); * * Returned Value: * true: This is the first register access of this type. - * flase: This is the same as the preceding register access. + * false: This is the same as the preceding register access. * ****************************************************************************/ @@ -1482,7 +1482,7 @@ static void sam_interrupt_work(void *arg) /* Check for the receipt of an RX packet. * * RXCOMP indicates that a packet has been received and stored in memory. - * The RXCOMP bit is cleared whent he interrupt status register was read. + * The RXCOMP bit is cleared when the interrupt status register was read. * RSR:REC indicates that one or more frames have been received and placed * in memory. This indication is cleared by writing a one to this bit. */ diff --git a/arch/arm/src/sama5/sam_hsmci.c b/arch/arm/src/sama5/sam_hsmci.c index eb09e0b5c6..3d8da21ddc 100644 --- a/arch/arm/src/sama5/sam_hsmci.c +++ b/arch/arm/src/sama5/sam_hsmci.c @@ -105,7 +105,7 @@ #elif defined(ATSAMA5D4) /* The SAMA5D3 has two HSMCI blocks: HSMCI0-1. They can be driven - * either by XDMAC0 (secure) or XDMAC1 (unsecure). + * either by XDMAC0 (secure) or XDMAC1 (insecure). */ # if !defined(CONFIG_SAMA5_XDMAC0) && !defined(CONFIG_SAMA5_XDMAC1) @@ -751,7 +751,7 @@ static struct sam_dev_s g_hsmci2 = * * Returned Value: * true: This is the first register access of this type. - * flase: This is the same as the preceding register access. + * false: This is the same as the preceding register access. * ****************************************************************************/ diff --git a/arch/arm/src/sama5/sam_lcd.c b/arch/arm/src/sama5/sam_lcd.c index eb252d4efb..a359d88d90 100644 --- a/arch/arm/src/sama5/sam_lcd.c +++ b/arch/arm/src/sama5/sam_lcd.c @@ -1023,7 +1023,7 @@ static const uintptr_t g_layerclut[LCDC_NLAYERS] = * * Returned Value: * true: This is the first register access of this type. - * flase: This is the same as the preceding register access. + * false: This is the same as the preceding register access. * ****************************************************************************/ diff --git a/arch/arm/src/sama5/sam_nand.c b/arch/arm/src/sama5/sam_nand.c index e43c4965ff..1016013e31 100644 --- a/arch/arm/src/sama5/sam_nand.c +++ b/arch/arm/src/sama5/sam_nand.c @@ -3112,7 +3112,7 @@ struct mtd_dev_s *sam_nand_initialize(int cs) * * Returned Value: * true: This is the first register access of this type. - * flase: This is the same as the preceding register access. + * false: This is the same as the preceding register access. * ****************************************************************************/ diff --git a/arch/arm/src/sama5/sam_nand.h b/arch/arm/src/sama5/sam_nand.h index 8b37bf09a4..52b16b89a7 100644 --- a/arch/arm/src/sama5/sam_nand.h +++ b/arch/arm/src/sama5/sam_nand.h @@ -485,7 +485,7 @@ void board_nand_ce(int cs, bool enable); * * Returned Value: * true: This is the first register access of this type. - * flase: This is the same as the preceding register access. + * false: This is the same as the preceding register access. * ****************************************************************************/ diff --git a/arch/arm/src/sama5/sam_pwm.c b/arch/arm/src/sama5/sam_pwm.c index a718b4133e..89f7ca9520 100644 --- a/arch/arm/src/sama5/sam_pwm.c +++ b/arch/arm/src/sama5/sam_pwm.c @@ -526,7 +526,7 @@ static struct sam_pwm_chan_s g_pwm_chan3 = * * Returned Value: * true: This is the first register access of this type. - * flase: This is the same as the preceding register access. + * false: This is the same as the preceding register access. * ****************************************************************************/ diff --git a/arch/arm/src/sama5/sam_qspi.c b/arch/arm/src/sama5/sam_qspi.c index 3087b51d4b..288e04f32b 100644 --- a/arch/arm/src/sama5/sam_qspi.c +++ b/arch/arm/src/sama5/sam_qspi.c @@ -380,7 +380,7 @@ static struct sam_qspidev_s g_qspi1dev = * * Returned Value: * true: This is the first register access of this type. - * flase: This is the same as the preceding register access. + * false: This is the same as the preceding register access. * ****************************************************************************/ diff --git a/arch/arm/src/sama5/sam_sdmmc.c b/arch/arm/src/sama5/sam_sdmmc.c index b01506c665..4ac441f8b3 100644 --- a/arch/arm/src/sama5/sam_sdmmc.c +++ b/arch/arm/src/sama5/sam_sdmmc.c @@ -519,7 +519,7 @@ static struct sam_sdmmcregs_s g_sampleregs[DEBUG_NSAMPLES]; * * Returned Value: * true: This is the first register access of this type. - * flase: This is the same as the preceding register access. + * false: This is the same as the preceding register access. * ****************************************************************************/ diff --git a/arch/arm/src/sama5/sam_serial.c b/arch/arm/src/sama5/sam_serial.c index a695fa8158..a6902e80e8 100644 --- a/arch/arm/src/sama5/sam_serial.c +++ b/arch/arm/src/sama5/sam_serial.c @@ -1581,7 +1581,7 @@ static bool up_txempty(struct uart_dev_s *dev) * * Description: * Performs the low level USART initialization early in debug so that the - * serial console will be available during bootup. This must be called + * serial console will be available during boot up. This must be called * before arm_serialinit. * ****************************************************************************/ diff --git a/arch/arm/src/sama5/sam_serial.h b/arch/arm/src/sama5/sam_serial.h index 6e0aa69afd..bef450dce9 100644 --- a/arch/arm/src/sama5/sam_serial.h +++ b/arch/arm/src/sama5/sam_serial.h @@ -68,7 +68,7 @@ extern "C" * * Description: * Performs the low level USART initialization early in debug so that the - * serial console will be available during bootup. This must be called + * serial console will be available during boot up. This must be called * before arm_serialinit. * ****************************************************************************/ @@ -82,7 +82,7 @@ void sam_earlyserialinit(void); * * Description: * Performs the low level USART initialization early in debug so that the - * serial console will be available during bootup. This must be called + * serial console will be available during boot up. This must be called * before arm_serialinit. * ****************************************************************************/ @@ -96,7 +96,7 @@ void uart_earlyserialinit(void); * * Description: * Performs the low level Flexcom USART initialization early so that the - * Flexcom serial console will be available during bootup. This must be + * Flexcom serial console will be available during boot up. This must be * called before flexus_serialinit. * ****************************************************************************/ diff --git a/arch/arm/src/sama5/sam_serialinit.c b/arch/arm/src/sama5/sam_serialinit.c index 94adcad729..2d8fe563ca 100644 --- a/arch/arm/src/sama5/sam_serialinit.c +++ b/arch/arm/src/sama5/sam_serialinit.c @@ -43,7 +43,7 @@ * * Description: * Performs the low level serial initialization early so that the serial - * console will be available during bootup. This must be called + * console will be available during boot up. This must be called * before arm_serialinit. * ****************************************************************************/ diff --git a/arch/arm/src/sama5/sam_spi.c b/arch/arm/src/sama5/sam_spi.c index 327f5eebe3..813f2cb9ba 100644 --- a/arch/arm/src/sama5/sam_spi.c +++ b/arch/arm/src/sama5/sam_spi.c @@ -397,7 +397,7 @@ static struct sam_spidev_s g_spi1dev = * * Returned Value: * true: This is the first register access of this type. - * flase: This is the same as the preceding register access. + * false: This is the same as the preceding register access. * ****************************************************************************/ diff --git a/arch/arm/src/sama5/sam_ssc.c b/arch/arm/src/sama5/sam_ssc.c index ea41ac8f94..f2f1e230e2 100644 --- a/arch/arm/src/sama5/sam_ssc.c +++ b/arch/arm/src/sama5/sam_ssc.c @@ -661,7 +661,7 @@ static const struct i2s_ops_s g_sscops = * * Returned Value: * true: This is the first register access of this type. - * flase: This is the same as the preceding register access. + * false: This is the same as the preceding register access. * ****************************************************************************/ diff --git a/arch/arm/src/sama5/sam_tc.c b/arch/arm/src/sama5/sam_tc.c index fba805fca0..5900d1745c 100644 --- a/arch/arm/src/sama5/sam_tc.c +++ b/arch/arm/src/sama5/sam_tc.c @@ -519,7 +519,7 @@ static void sam_regdump(struct sam_chan_s *chan, const char *msg) * * Returned Value: * true: This is the first register access of this type. - * flase: This is the same as the preceding register access. + * false: This is the same as the preceding register access. * ****************************************************************************/ diff --git a/arch/arm/src/sama5/sam_tsd.c b/arch/arm/src/sama5/sam_tsd.c index c03d4d40fa..d3b527d7e7 100644 --- a/arch/arm/src/sama5/sam_tsd.c +++ b/arch/arm/src/sama5/sam_tsd.c @@ -542,7 +542,7 @@ static void sam_tsd_bottomhalf(void *arg) /* Check the pen state. Down if: * - Pen status is down OR * - Pen down interrupt seen, but NOT if - * - Pen up interrrupt occurred as we need to deal with that + * - Pen up interrupt occurred as we need to deal with that */ pendown = ((((pending & ADC_SR_PENS) != 0) || @@ -1471,7 +1471,7 @@ static void sam_tsd_trigperiod(struct sam_tsd_s *priv, uint32_t period) uint32_t regval; uint32_t div; - /* Divide trigger period avoid overflows. Division by ten is awkard, but + /* Divide trigger period avoid overflows. Division by ten is awkward, but * appropriate here because times are specified in decimal with lots of * zeroes. */ @@ -1547,7 +1547,7 @@ static void sam_tsd_debounce(struct sam_tsd_s *priv, uint32_t time) DEBUGASSERT(time > 0); - /* Divide time and ADCCLK to avoid overflows. Division by ten is awkard, + /* Divide time and ADCCLK to avoid overflows. Division by ten is awkward, * but appropriate here because times are specified in decimal with lots of * zeroes. */ diff --git a/arch/arm/src/sama5/sam_udphs.c b/arch/arm/src/sama5/sam_udphs.c index c4332a594e..43e5604702 100644 --- a/arch/arm/src/sama5/sam_udphs.c +++ b/arch/arm/src/sama5/sam_udphs.c @@ -3219,7 +3219,7 @@ sam_ep_reserve(struct sam_usbdev_s *priv, uint8_t epset) * * Description: * The endpoint is no long in-used. It will be un-reserved and can be - * re-used if needed. + * reused if needed. * ****************************************************************************/ diff --git a/arch/arm/src/sama5/sam_wdt.c b/arch/arm/src/sama5/sam_wdt.c index 88590db608..f433cb5767 100644 --- a/arch/arm/src/sama5/sam_wdt.c +++ b/arch/arm/src/sama5/sam_wdt.c @@ -495,7 +495,7 @@ static int sam_settimeout(struct watchdog_lowerhalf_s *lower, regval = WDT_MR_WDV(reload) | WDT_MR_WDD(reload); #ifdef CONFIG_SAMA5_WDT_INTERRUPT - /* Generate an interrupt whent he watchdog timer expires */ + /* Generate an interrupt when the watchdog timer expires */ regval |= WDT_MR_WDFIEN; #else diff --git a/arch/arm/src/sama5/sam_xdmac.c b/arch/arm/src/sama5/sam_xdmac.c index 3a7ea31616..994033b725 100644 --- a/arch/arm/src/sama5/sam_xdmac.c +++ b/arch/arm/src/sama5/sam_xdmac.c @@ -1535,7 +1535,7 @@ static int sam_txbuffer(struct sam_xdmach_s *xdmach, uint32_t paddr, { uint32_t cubc; - /* If we are appending a buffer to a linklist, then re-use the previously + /* If we are appending a buffer to a linklist, then reuse the previously * calculated CC register value. Otherwise, create the CC register value * from the properties of the transfer. */ @@ -1575,7 +1575,7 @@ static int sam_rxbuffer(struct sam_xdmach_s *xdmach, uint32_t paddr, { uint32_t cubc; - /* If we are appending a buffer to a linklist, then re-use the previously + /* If we are appending a buffer to a linklist, then reuse the previously * calculated CC register value. Otherwise, create the CC register value * from the properties of the transfer. */ diff --git a/arch/arm/src/samd2l2/hardware/samd_dmac.h b/arch/arm/src/samd2l2/hardware/samd_dmac.h index 985b48de33..d4d010ebfb 100644 --- a/arch/arm/src/samd2l2/hardware/samd_dmac.h +++ b/arch/arm/src/samd2l2/hardware/samd_dmac.h @@ -179,19 +179,19 @@ #define DMAC_PRICTRL0_LVLPRI0_SHIFT (0) /* Bits 0-3: Level 0 channel priority number */ #define DMAC_PRICTRL0_LVLPRI0_MASK (15 << DMAC_PRICTRL0_LVLPRI0_SHIFT) # define DMAC_PRICTRL0_LVLPRI0(n) ((uint32_t)(n) << DMAC_PRICTRL0_LVLPRI0_SHIFT) -#define DMAC_PRICTRL0_RRLVLEN0 (1 << 7) /* Bit 7: Level 0 round-robin arbitrarion enable */ +#define DMAC_PRICTRL0_RRLVLEN0 (1 << 7) /* Bit 7: Level 0 round-robin arbitration enable */ #define DMAC_PRICTRL0_LVLPRI1_SHIFT (8) /* Bits 8-11: Level 1 channel priority number */ #define DMAC_PRICTRL0_LVLPRI1_MASK (15 << DMAC_PRICTRL0_LVLPRI1_SHIFT) # define DMAC_PRICTRL0_LVLPRI1(n) ((uint32_t)(n) << DMAC_PRICTRL0_LVLPRI1_SHIFT) -#define DMAC_PRICTRL0_RRLVLEN1 (1 << 15) /* Bit 15: Level 1 round-robin arbitrarion enable */ +#define DMAC_PRICTRL0_RRLVLEN1 (1 << 15) /* Bit 15: Level 1 round-robin arbitration enable */ #define DMAC_PRICTRL0_LVLPRI2_SHIFT (16) /* Bits 16-18: Level 2 channel priority number */ #define DMAC_PRICTRL0_LVLPRI2_MASK (7 << DMAC_PRICTRL0_LVLPRI2_SHIFT) # define DMAC_PRICTRL0_LVLPRI2(n) ((uint32_t)(n) << DMAC_PRICTRL0_LVLPRI2_SHIFT) -#define DMAC_PRICTRL0_RRLVLEN2 (1 << 23) /* Bit 23: Level 2 round-robin arbitrarion enable */ +#define DMAC_PRICTRL0_RRLVLEN2 (1 << 23) /* Bit 23: Level 2 round-robin arbitration enable */ #define DMAC_PRICTRL0_LVLPRI3_SHIFT (24) /* Bits 24-27: Level 3 channel priority number */ #define DMAC_PRICTRL0_LVLPRI3_MASK (7 << DMAC_PRICTRL0_LVLPRI3_SHIFT) # define DMAC_PRICTRL0_LVLPRI3(n) ((uint32_t)(n) << DMAC_PRICTRL0_LVLPRI3_SHIFT) -#define DMAC_PRICTRL0_RRLVLEN3 (1 << 31) /* Bit 23: Level 3 round-robin arbitrarion enable */ +#define DMAC_PRICTRL0_RRLVLEN3 (1 << 31) /* Bit 23: Level 3 round-robin arbitration enable */ /* Interrupt Pending Register */ diff --git a/arch/arm/src/samd2l2/hardware/saml_dmac.h b/arch/arm/src/samd2l2/hardware/saml_dmac.h index 270c90e3a1..c0b175462d 100644 --- a/arch/arm/src/samd2l2/hardware/saml_dmac.h +++ b/arch/arm/src/samd2l2/hardware/saml_dmac.h @@ -180,15 +180,15 @@ #define DMAC_PRICTRL0_LVLPRI0_SHIFT (0) /* Bits 0-3: Level 0 channel priority number */ #define DMAC_PRICTRL0_LVLPRI0_MASK (15 << DMAC_PRICTRL0_LVLPRI0_SHIFT) # define DMAC_PRICTRL0_LVLPRI0(n) ((uint32_t)(n) << DMAC_PRICTRL0_LVLPRI0_SHIFT) -#define DMAC_PRICTRL0_RRLVLEN0 (1 << 7) /* Bit 7: Level 0 round-robin arbitrarion enable */ +#define DMAC_PRICTRL0_RRLVLEN0 (1 << 7) /* Bit 7: Level 0 round-robin arbitration enable */ #define DMAC_PRICTRL0_LVLPRI1_SHIFT (8) /* Bits 8-11: Level 1 channel priority number */ #define DMAC_PRICTRL0_LVLPRI1_MASK (15 << DMAC_PRICTRL0_LVLPRI1_SHIFT) # define DMAC_PRICTRL0_LVLPRI1(n) ((uint32_t)(n) << DMAC_PRICTRL0_LVLPRI1_SHIFT) -#define DMAC_PRICTRL0_RRLVLEN1 (1 << 15) /* Bit 15: Level 1 round-robin arbitrarion enable */ +#define DMAC_PRICTRL0_RRLVLEN1 (1 << 15) /* Bit 15: Level 1 round-robin arbitration enable */ #define DMAC_PRICTRL0_LVLPRI2_SHIFT (16) /* Bits 16-18: Level 2 channel priority number */ #define DMAC_PRICTRL0_LVLPRI2_MASK (7 << DMAC_PRICTRL0_LVLPRI2_SHIFT) # define DMAC_PRICTRL0_LVLPRI2(n) ((uint32_t)(n) << DMAC_PRICTRL0_LVLPRI2_SHIFT) -#define DMAC_PRICTRL0_RRLVLEN2 (1 << 23) /* Bit 23: Level 2 round-robin arbitrarion enable */ +#define DMAC_PRICTRL0_RRLVLEN2 (1 << 23) /* Bit 23: Level 2 round-robin arbitration enable */ /* Interrupt Pending Register */ diff --git a/arch/arm/src/samd2l2/hardware/saml_eic.h b/arch/arm/src/samd2l2/hardware/saml_eic.h index 93ed610526..33b5787478 100644 --- a/arch/arm/src/samd2l2/hardware/saml_eic.h +++ b/arch/arm/src/samd2l2/hardware/saml_eic.h @@ -105,8 +105,8 @@ /* Synchronization busy register */ -#define EIC_SYNCBUSY_SWRST (1 << 0) /* Bit 0: Software reset syncrhonization busy */ -#define EIC_SYNCBUSY_ENABLE (1 << 1) /* Bit 1: Enable syncrhonization busy */ +#define EIC_SYNCBUSY_SWRST (1 << 0) /* Bit 0: Software reset synchronization busy */ +#define EIC_SYNCBUSY_ENABLE (1 << 1) /* Bit 1: Enable synchronization busy */ /* Event control, Interrupt enable clear, interrupt enable set register, * interrupt flag status and clear, and External interrupt asynchronous diff --git a/arch/arm/src/samd2l2/hardware/saml_evsys.h b/arch/arm/src/samd2l2/hardware/saml_evsys.h index 22f1138afa..e42ed6eb72 100644 --- a/arch/arm/src/samd2l2/hardware/saml_evsys.h +++ b/arch/arm/src/samd2l2/hardware/saml_evsys.h @@ -161,7 +161,7 @@ # define EVSYS_CHANNEL_EVGEN_TC1_MC0 (0x39 << EVSYS_CHANNEL_EVGEN_SHIFT) /* TC1 match/capture 0 */ # define EVSYS_CHANNEL_EVGEN_TC1_MC1 (0x3a << EVSYS_CHANNEL_EVGEN_SHIFT) /* TC1 match/capture 1 */ # define EVSYS_CHANNEL_EVGEN_TC2_OVF (0x3b << EVSYS_CHANNEL_EVGEN_SHIFT) /* TC2 Overflow */ -# define EVSYS_CHANNEL_EVGEN_TC2_MC0 (0x3c << EVSYS_CHANNEL_EVGEN_SHIFT) /* TC2 match/captue 0 */ +# define EVSYS_CHANNEL_EVGEN_TC2_MC0 (0x3c << EVSYS_CHANNEL_EVGEN_SHIFT) /* TC2 match/capture 0 */ # define EVSYS_CHANNEL_EVGEN_TC2_MC1 (0x3d << EVSYS_CHANNEL_EVGEN_SHIFT) /* TC2 match/capture 1 */ # define EVSYS_CHANNEL_EVGEN_TC3_OVF (0x3e << EVSYS_CHANNEL_EVGEN_SHIFT) /* TC3 Overflow */ # define EVSYS_CHANNEL_EVGEN_TC3_MC0 (0x3f << EVSYS_CHANNEL_EVGEN_SHIFT) /* TC3 match/capture 0 */ @@ -191,7 +191,7 @@ # define EVSYS_CHANNEL_PATH_RESYNCH (1 << EVSYS_CHANNEL_PATH_SHIFT) /* Resynchronized path */ # define EVSYS_CHANNEL_PATH_ASYNCH (2 << EVSYS_CHANNEL_PATH_SHIFT) /* Asynchronous path */ -#define EVSYS_CHANNEL_EDGESEL_SHIFT (10) /* Bits 10-11: Edge dection selection */ +#define EVSYS_CHANNEL_EDGESEL_SHIFT (10) /* Bits 10-11: Edge detection selection */ #define EVSYS_CHANNEL_EDGESEL_MASK (3 << EVSYS_CHANNEL_EDGESEL_SHIFT) # define EVSYS_CHANNEL_EDGESEL_NONE (0 << EVSYS_CHANNEL_EDGESEL_SHIFT) /* No event output */ # define EVSYS_CHANNEL_EDGESEL_RISING (1 << EVSYS_CHANNEL_EDGESEL_SHIFT) /* Detect on rising edge */ diff --git a/arch/arm/src/samd2l2/hardware/saml_i2c_slave.h b/arch/arm/src/samd2l2/hardware/saml_i2c_slave.h index 0cd399ef56..25607774a7 100644 --- a/arch/arm/src/samd2l2/hardware/saml_i2c_slave.h +++ b/arch/arm/src/samd2l2/hardware/saml_i2c_slave.h @@ -134,7 +134,7 @@ # define I2C_CTRLA_SDAHOLD_600NS (3 << I2C_CTRLA_SDAHOLD_SHIFT) /* 400-800ns hold time */ #define I2C_CTRLA_SEXTTOEN (1 << 23) /* Bit 23: Slave SCL low extend time-out */ -#define I2C_CTRLA_SPEED_SHIFT (24) /* Bits 24-25: Trnasfer speed */ +#define I2C_CTRLA_SPEED_SHIFT (24) /* Bits 24-25: Transfer speed */ #define I2C_CTRLA_SPEED_MASK (3 << I2C_CTRLA_SPEED_SHIFT) # define I2C_CTRLA_SPEED_STD (0 << I2C_CTRLA_SPEED_SHIFT) /* Standard (<=100KHz) fast <=400KHz */ # define I2C_CTRLA_SPEED_FAST (1 << I2C_CTRLA_SPEED_SHIFT) /* Fast-mode please (<=1MHz) */ diff --git a/arch/arm/src/samd2l2/hardware/saml_pm.h b/arch/arm/src/samd2l2/hardware/saml_pm.h index a4608dfea6..b636aa0a4f 100644 --- a/arch/arm/src/samd2l2/hardware/saml_pm.h +++ b/arch/arm/src/samd2l2/hardware/saml_pm.h @@ -90,7 +90,7 @@ * and Interrupt flag status and clear registers */ -#define PM_INT_PLRDY (1 << 0) /* Bit 0: Performanc level ready */ +#define PM_INT_PLRDY (1 << 0) /* Bit 0: Performance level ready */ /* Standby configuration */ diff --git a/arch/arm/src/samd2l2/hardware/saml_supc.h b/arch/arm/src/samd2l2/hardware/saml_supc.h index 98226393ff..dd11f6d5a8 100644 --- a/arch/arm/src/samd2l2/hardware/saml_supc.h +++ b/arch/arm/src/samd2l2/hardware/saml_supc.h @@ -50,7 +50,7 @@ #define SAM_SUPC_STATUS_OFFSET 0x000c /* Status */ #define SAM_SUPC_BOD33_OFFSET 0x0010 /* 3.3V brown-out detector control */ -#define SAM_SUPC_BOD12_OFFSET 0x0014 /* 1.2V brown-out detctor control */ +#define SAM_SUPC_BOD12_OFFSET 0x0014 /* 1.2V brown-out detector control */ #define SAM_SUPC_VREG_OFFSET 0x0018 /* Voltage regulator system control */ #define SAM_SUPC_VREF_OFFSET 0x001c /* Voltage references system control */ @@ -135,7 +135,7 @@ #define SUPC_BOD33_BKUPLEVEL_MASK (0x3f << SUPC_BOD33_BKUPLEVEL_SHIFT) # define SUPC_BOD33_BKUPLEVEL(n) ((uint32_t)(n) << SUPC_BOD33_BKUPLEVEL_SHIFT) -/* 1.2V brown-out detctor control */ +/* 1.2V brown-out detector control */ #define SUPC_BOD12_ENABLE (1 << 1) /* Bit 1: Enable */ #define SUPC_BOD12_HYST (1 << 2) /* Bit 2: Hysteresis */ diff --git a/arch/arm/src/samd2l2/hardware/saml_wdt.h b/arch/arm/src/samd2l2/hardware/saml_wdt.h index 336ce092a2..bfc5c924f5 100644 --- a/arch/arm/src/samd2l2/hardware/saml_wdt.h +++ b/arch/arm/src/samd2l2/hardware/saml_wdt.h @@ -130,10 +130,10 @@ /* Synchronization busy register */ -#define WDT_SYNCBUSY_ENABLE (1 << 1) /* Bit 1: Enable syncrhonization busy */ +#define WDT_SYNCBUSY_ENABLE (1 << 1) /* Bit 1: Enable synchronization busy */ #define WDT_SYNCBUSY_WEN (1 << 2) /* Bit 2: Window enable synchronization busy */ #define WDT_SYNCBUSY_ALWAYSON (1 << 3) /* Bit 3: Always-on synchronization busy */ -#define WDT_SYNCBUSY_CLEAR (1 << 4) /* Bit 4: Clear syncrhonization busy */ +#define WDT_SYNCBUSY_CLEAR (1 << 4) /* Bit 4: Clear synchronization busy */ /* Clear register */ diff --git a/arch/arm/src/samd2l2/sam_serial.c b/arch/arm/src/samd2l2/sam_serial.c index 60bd704faa..da606c56c5 100644 --- a/arch/arm/src/samd2l2/sam_serial.c +++ b/arch/arm/src/samd2l2/sam_serial.c @@ -960,7 +960,7 @@ static bool sam_txempty(struct uart_dev_s *dev) * * Description: * Performs the low level USART initialization early in debug so that the - * serial console will be available during bootup. This must be called + * serial console will be available during boot up. This must be called * before sam_serialinit. * * NOTE: On this platform arm_earlyserialinit() does not really do diff --git a/arch/arm/src/samd2l2/sam_spi.c b/arch/arm/src/samd2l2/sam_spi.c index 6666c5e6b1..6a6e6cacbf 100644 --- a/arch/arm/src/samd2l2/sam_spi.c +++ b/arch/arm/src/samd2l2/sam_spi.c @@ -520,7 +520,7 @@ static struct sam_spidev_s g_spi5dev = * * Returned Value: * true: This is the first register access of this type. - * flase: This is the same as the preceding register access. + * false: This is the same as the preceding register access. * ****************************************************************************/ diff --git a/arch/arm/src/samd2l2/sam_start.c b/arch/arm/src/samd2l2/sam_start.c index 10996555ac..d97cbab491 100644 --- a/arch/arm/src/samd2l2/sam_start.c +++ b/arch/arm/src/samd2l2/sam_start.c @@ -48,7 +48,7 @@ * 0x0000:0000 - Beginning of FLASH. Address of exception vectors. * 0x0003:ffff - End of flash (assuming 256KB of FLASH) * 0x2000:0000 - Start of SRAM and start of .data (_sdata) - * - End of .data (_edata) abd start of .bss (_sbss) + * - End of .data (_edata) and start of .bss (_sbss) * - End of .bss (_ebss) and bottom of idle stack * - _ebss + CONFIG_IDLETHREAD_STACKSIZE = end of idle stack, * start of heap diff --git a/arch/arm/src/samd2l2/sam_usb.c b/arch/arm/src/samd2l2/sam_usb.c index abc0d2d76f..6f36bd9b04 100644 --- a/arch/arm/src/samd2l2/sam_usb.c +++ b/arch/arm/src/samd2l2/sam_usb.c @@ -522,7 +522,7 @@ static const struct usb_epdesc_s g_ep0desc = .interval = 0 }; -/* Device error strings that may be enabled for more desciptive USB trace +/* Device error strings that may be enabled for more descriptive USB trace * output. */ @@ -562,7 +562,7 @@ const struct trace_msg_t g_usb_trace_strings_deverror[] = }; #endif -/* Interrupt event strings that may be enabled for more desciptive USB trace +/* Interrupt event strings that may be enabled for more descriptive USB trace * output. */ @@ -1524,7 +1524,7 @@ sam_ep_reserve(struct sam_usbdev_s *priv, uint8_t epset) * * Description: * The endpoint is no long in-used. It will be unreserved and can be - * re-used if needed. + * reused if needed. * ****************************************************************************/ diff --git a/arch/arm/src/samd5e5/hardware/sam_dmac.h b/arch/arm/src/samd5e5/hardware/sam_dmac.h index 9e75390d28..634459cf53 100644 --- a/arch/arm/src/samd5e5/hardware/sam_dmac.h +++ b/arch/arm/src/samd5e5/hardware/sam_dmac.h @@ -167,7 +167,7 @@ # define DMAC_PRICTRL0_QOS00_MEDIUM (2 << DMAC_PRICTRL0_QOS00_SHIFT) /* Sensitive to latency */ # define DMAC_PRICTRL0_QOS00_CRITICAL (3 << DMAC_PRICTRL0_QOS00_SHIFT) /* Latency critical */ -#define DMAC_PRICTRL0_RRLVLEN0 (1 << 7) /* Bit 7: Level 0 round-robin arbitrarion enable */ +#define DMAC_PRICTRL0_RRLVLEN0 (1 << 7) /* Bit 7: Level 0 round-robin arbitration enable */ #define DMAC_PRICTRL0_LVLPRI1_SHIFT (8) /* Bits 8-12: Level 1 channel priority number */ #define DMAC_PRICTRL0_LVLPRI1_MASK (31 << DMAC_PRICTRL0_LVLPRI1_SHIFT) # define DMAC_PRICTRL0_LVLPRI1(n) ((uint32_t)(n) << DMAC_PRICTRL0_LVLPRI1_SHIFT) @@ -178,7 +178,7 @@ # define DMAC_PRICTRL0_QOS01_MEDIUM (2 << DMAC_PRICTRL0_QOS01_SHIFT) /* Sensitive to latency */ # define DMAC_PRICTRL0_QOS01_CRITICAL (3 << DMAC_PRICTRL0_QOS01_SHIFT) /* Latency critical */ -#define DMAC_PRICTRL0_RRLVLEN1 (1 << 15) /* Bit 15: Level 1 round-robin arbitrarion enable */ +#define DMAC_PRICTRL0_RRLVLEN1 (1 << 15) /* Bit 15: Level 1 round-robin arbitration enable */ #define DMAC_PRICTRL0_LVLPRI2_SHIFT (16) /* Bits 16-20: Level 2 channel priority number */ #define DMAC_PRICTRL0_LVLPRI2_MASK (31 << DMAC_PRICTRL0_LVLPRI2_SHIFT) # define DMAC_PRICTRL0_LVLPRI2(n) ((uint32_t)(n) << DMAC_PRICTRL0_LVLPRI2_SHIFT) @@ -189,7 +189,7 @@ # define DMAC_PRICTRL0_QOS02_MEDIUM (2 << DMAC_PRICTRL0_QOS02_SHIFT) /* Sensitive to latency */ # define DMAC_PRICTRL0_QOS02_CRITICAL (3 << DMAC_PRICTRL0_QOS02_SHIFT) /* Latency critical */ -#define DMAC_PRICTRL0_RRLVLEN2 (1 << 23) /* Bit 23: Level 2 round-robin arbitrarion enable */ +#define DMAC_PRICTRL0_RRLVLEN2 (1 << 23) /* Bit 23: Level 2 round-robin arbitration enable */ #define DMAC_PRICTRL0_LVLPRI3_SHIFT (24) /* Bits 24-28: Level 2 channel priority number */ #define DMAC_PRICTRL0_LVLPRI3_MASK (31 << DMAC_PRICTRL0_LVLPRI3_SHIFT) # define DMAC_PRICTRL0_LVLPRI3(n) ((uint32_t)(n) << DMAC_PRICTRL0_LVLPRI3_SHIFT) @@ -200,7 +200,7 @@ # define DMAC_PRICTRL0_QOS03_MEDIUM (2 << DMAC_PRICTRL0_QOS03_SHIFT) /* Sensitive to latency */ # define DMAC_PRICTRL0_QOS03_CRITICAL (3 << DMAC_PRICTRL0_QOS03_SHIFT) /* Latency critical */ -#define DMAC_PRICTRL0_RRLVLEN3 (1 << 23) /* Bit 21: Level 3 round-robin arbitrarion enable */ +#define DMAC_PRICTRL0_RRLVLEN3 (1 << 23) /* Bit 21: Level 3 round-robin arbitration enable */ /* Interrupt Pending Register */ diff --git a/arch/arm/src/samd5e5/hardware/sam_eic.h b/arch/arm/src/samd5e5/hardware/sam_eic.h index 82bda39cbd..ba077cab67 100644 --- a/arch/arm/src/samd5e5/hardware/sam_eic.h +++ b/arch/arm/src/samd5e5/hardware/sam_eic.h @@ -98,7 +98,7 @@ /* Synchronization busy register */ -#define EIC_SYNCBUSY_SWRST (1 << 0) /* Bit 0: Software reset syncrhonization busy */ +#define EIC_SYNCBUSY_SWRST (1 << 0) /* Bit 0: Software reset synchronization busy */ #define EIC_SYNCBUSY_ENABLE (1 << 1) /* Bit 1: Enable synchronization busy */ /* Event control, Interrupt enable clear, interrupt enable set register, diff --git a/arch/arm/src/samd5e5/hardware/sam_i2c_slave.h b/arch/arm/src/samd5e5/hardware/sam_i2c_slave.h index 63b095aaa0..921659e131 100644 --- a/arch/arm/src/samd5e5/hardware/sam_i2c_slave.h +++ b/arch/arm/src/samd5e5/hardware/sam_i2c_slave.h @@ -171,7 +171,7 @@ # define I2C_CTRLA_SDAHOLD_600NS (3 << I2C_CTRLA_SDAHOLD_SHIFT) /* 400-800ns hold time */ #define I2C_CTRLA_SEXTTOEN (1 << 23) /* Bit 23: Slave SCL low extend time-out */ -#define I2C_CTRLA_SPEED_SHIFT (24) /* Bits 24-25: Trnasfer speed */ +#define I2C_CTRLA_SPEED_SHIFT (24) /* Bits 24-25: Transfer speed */ #define I2C_CTRLA_SPEED_MASK (3 << I2C_CTRLA_SPEED_SHIFT) # define I2C_CTRLA_SPEED_STD (0 << I2C_CTRLA_SPEED_SHIFT) /* Standard (<=100KHz) fast <=400KHz */ # define I2C_CTRLA_SPEED_FAST (1 << I2C_CTRLA_SPEED_SHIFT) /* Fast-mode please (<=1MHz) */ diff --git a/arch/arm/src/samd5e5/hardware/sam_supc.h b/arch/arm/src/samd5e5/hardware/sam_supc.h index eaa2c32093..0c976e97c4 100644 --- a/arch/arm/src/samd5e5/hardware/sam_supc.h +++ b/arch/arm/src/samd5e5/hardware/sam_supc.h @@ -42,7 +42,7 @@ #define SAM_SUPC_INTFLAG_OFFSET 0x0008 /* Interrupt flag status and clear */ #define SAM_SUPC_STATUS_OFFSET 0x000c /* Status */ #define SAM_SUPC_BOD33_OFFSET 0x0010 /* 3.3V brown-out detector control */ -#define SAM_SUPC_BOD12_OFFSET 0x0014 /* 1.2V brown-out detctor control */ +#define SAM_SUPC_BOD12_OFFSET 0x0014 /* 1.2V brown-out detector control */ #define SAM_SUPC_VREG_OFFSET 0x0018 /* Voltage regulator system control */ #define SAM_SUPC_VREF_OFFSET 0x001c /* Voltage references system control */ #define SAM_SUPC_BBPS_OFFSET 0x0020 /* Battery backup power switch control */ diff --git a/arch/arm/src/samd5e5/hardware/sam_wdt.h b/arch/arm/src/samd5e5/hardware/sam_wdt.h index b40733e5cd..fbf21f1f09 100644 --- a/arch/arm/src/samd5e5/hardware/sam_wdt.h +++ b/arch/arm/src/samd5e5/hardware/sam_wdt.h @@ -122,10 +122,10 @@ /* Synchronization busy register */ -#define WDT_SYNCBUSY_ENABLE (1 << 1) /* Bit 1: Enable syncrhonization busy */ +#define WDT_SYNCBUSY_ENABLE (1 << 1) /* Bit 1: Enable synchronization busy */ #define WDT_SYNCBUSY_WEN (1 << 2) /* Bit 2: Window enable synchronization busy */ #define WDT_SYNCBUSY_ALWAYSON (1 << 3) /* Bit 3: Always-on synchronization busy */ -#define WDT_SYNCBUSY_CLEAR (1 << 4) /* Bit 4: Clear syncrhonization busy */ +#define WDT_SYNCBUSY_CLEAR (1 << 4) /* Bit 4: Clear synchronization busy */ /* Clear register */ diff --git a/arch/arm/src/samd5e5/sam_gmac.c b/arch/arm/src/samd5e5/sam_gmac.c index fa25aa8920..167abe4e24 100644 --- a/arch/arm/src/samd5e5/sam_gmac.c +++ b/arch/arm/src/samd5e5/sam_gmac.c @@ -383,7 +383,7 @@ static int sam_gmac_configure(struct sam_gmac_s *priv); * * Returned Value: * true: This is the first register access of this type. - * flase: This is the same as the preceding register access. + * false: This is the same as the preceding register access. * ****************************************************************************/ @@ -1447,7 +1447,7 @@ static void sam_interrupt_work(void *arg) /* Check for the receipt of an RX packet. * * RXCOMP indicates that a packet has been received and stored in memory. - * The RXCOMP bit is cleared whent he interrupt status register was read. + * The RXCOMP bit is cleared when the interrupt status register was read. * RSR:REC indicates that one or more frames have been received and placed * in memory. This indication is cleared by writing a one to this bit. */ diff --git a/arch/arm/src/samd5e5/sam_oneshot.h b/arch/arm/src/samd5e5/sam_oneshot.h index 306416204e..357ad4df2d 100644 --- a/arch/arm/src/samd5e5/sam_oneshot.h +++ b/arch/arm/src/samd5e5/sam_oneshot.h @@ -71,7 +71,7 @@ struct sam_oneshot_s * the callback */ #ifdef CONFIG_SAMD5E5_FREERUN volatile uint32_t start_count; /* Stores the value of the freerun counter, - * at each start of the onshot timer. Is neccesary + * at each start of the onshot timer. Is necessary * to find out if the onshot counter was updated * correctly at the time of the call to * sam_oneshot_cancel or not. */ diff --git a/arch/arm/src/samd5e5/sam_oneshot_lowerhalf.c b/arch/arm/src/samd5e5/sam_oneshot_lowerhalf.c index 15ec64f52c..c41675769b 100644 --- a/arch/arm/src/samd5e5/sam_oneshot_lowerhalf.c +++ b/arch/arm/src/samd5e5/sam_oneshot_lowerhalf.c @@ -148,7 +148,7 @@ static void sam_oneshot_handler(void *arg) * lower An instance of the lower-half oneshot state structure. This * structure must have been previously initialized via a call to * oneshot_initialize(); - * ts The location in which to return the maxumum delay. + * ts The location in which to return the maximum delay. * * Returned Value: * Zero (OK) is returned on success; a negated errno value is returned diff --git a/arch/arm/src/samd5e5/sam_serial.c b/arch/arm/src/samd5e5/sam_serial.c index e3f0e0f3a8..1557f82f4f 100644 --- a/arch/arm/src/samd5e5/sam_serial.c +++ b/arch/arm/src/samd5e5/sam_serial.c @@ -1007,7 +1007,7 @@ static bool sam_txempty(struct uart_dev_s *dev) * * Description: * Performs the low level USART initialization early in debug so that the - * serial console will be available during bootup. This must be called + * serial console will be available during boot up. This must be called * before sam_serialinit. * * NOTE: On this platform arm_earlyserialinit() does not really do diff --git a/arch/arm/src/samd5e5/sam_spi.c b/arch/arm/src/samd5e5/sam_spi.c index 0e8b239e76..fef77de1c6 100644 --- a/arch/arm/src/samd5e5/sam_spi.c +++ b/arch/arm/src/samd5e5/sam_spi.c @@ -616,7 +616,7 @@ static struct sam_spidev_s g_spi7dev = * * Returned Value: * true: This is the first register access of this type. - * flase: This is the same as the preceding register access. + * false: This is the same as the preceding register access. * ****************************************************************************/ diff --git a/arch/arm/src/samd5e5/sam_usb.c b/arch/arm/src/samd5e5/sam_usb.c index c8bd638800..87328b597d 100644 --- a/arch/arm/src/samd5e5/sam_usb.c +++ b/arch/arm/src/samd5e5/sam_usb.c @@ -1050,7 +1050,7 @@ static const struct usb_epdesc_s g_ep0desc = }; #endif -/* Device error strings that may be enabled for more desciptive USB trace +/* Device error strings that may be enabled for more descriptive USB trace * output. */ @@ -1090,7 +1090,7 @@ const struct trace_msg_t g_usb_trace_strings_deverror[] = }; #endif -/* Interrupt event strings that may be enabled for more desciptive USB trace +/* Interrupt event strings that may be enabled for more descriptive USB trace * output. */ @@ -1776,7 +1776,7 @@ static int sam_req_write(struct sam_usbdev_s *priv, struct sam_ep_s *privep) * (2) called with a request packet that has len == 0 * * len == 0 means that it is requested to send a zero length packet - * required by protocoll + * required by protocol. */ else if ((privreq->req.len == 0) && !privep->zlpsent) @@ -2190,7 +2190,7 @@ sam_ep_reserve(struct sam_usbdev_s *priv, uint8_t epset) * * Description: * The endpoint is no long in-used. It will be unreserved and can be - * re-used if needed. + * reused if needed. * ****************************************************************************/ @@ -3927,7 +3927,7 @@ static int sam_usb_interrupt(int irq, void *context, void *arg) regval = sam_getreg16(SAM_USBDEV_INTENSET); pending = isr & regval; - /* Get the set of pending enpoint interrupts */ + /* Get the set of pending endpoint interrupts */ pendingep = sam_getreg16(SAM_USBDEV_EPINTSMRY); @@ -3998,7 +3998,7 @@ static int sam_usb_interrupt(int irq, void *context, void *arg) sam_putreg16(USBDEV_INT_WAKEUP | USBDEV_INT_EORSM | USBDEV_INT_SUSPEND, SAM_USBDEV_INTFLAG); - /* Disable wakup and endofresume Enable suspend interrupt */ + /* Disable wakeup and endofresume. Enable suspend interrupt */ sam_putreg16(USBDEV_INT_WAKEUP | USBDEV_INT_EORSM, SAM_USBDEV_INTENCLR); @@ -8392,7 +8392,7 @@ static void sam_hostreset(struct sam_usbhost_s *priv) * Description: * Initialize/re-initialize hardware for host mode operation. At present, * this function is called only from sam_hw_initialize(). But if OTG mode - * were supported, this function would also be called to swtich between + * were supported, this function would also be called to switch between * host and device modes on a connector ID change interrupt. * * Input Parameters: @@ -8503,7 +8503,7 @@ static inline void sam_sw_initialize(struct sam_usbhost_s *priv) * Name: sam_hw_initialize * * Description: - * One-time setup of the host controller harware for normal operations. + * One-time setup of the host controller hardware for normal operations. * * Input Parameters: * priv -- USB host driver private data structure. diff --git a/arch/arm/src/samv7/hardware/sam_supc.h b/arch/arm/src/samv7/hardware/sam_supc.h index 27b9f87245..d671e12cb2 100644 --- a/arch/arm/src/samv7/hardware/sam_supc.h +++ b/arch/arm/src/samv7/hardware/sam_supc.h @@ -90,7 +90,7 @@ #define SUPC_SMMR_SMSMPL_MASK (7 << SUPC_SMMR_SMSMPL_SHIFT) # define SUPC_SMMR_SMSMPL_SMD (0 << SUPC_SMMR_SMSMPL_SHIFT) /* Supply Monitor disabled */ # define SUPC_SMMR_SMSMPL_CSM (1 << SUPC_SMMR_SMSMPL_SHIFT) /* Continuous Supply Monitor */ -# define SUPC_SMMR_SMSMPL_32SLCK (2 << SUPC_SMMR_SMSMPL_SHIFT) /* Eevery 32 SLCK periods */ +# define SUPC_SMMR_SMSMPL_32SLCK (2 << SUPC_SMMR_SMSMPL_SHIFT) /* Every 32 SLCK periods */ # define SUPC_SMMR_SMSMPL_256SLCK (3 << SUPC_SMMR_SMSMPL_SHIFT) /* Every 256 SLCK periods */ # define SUPC_SMMR_SMSMPL_2048SLCK (4 << SUPC_SMMR_SMSMPL_SHIFT) /* Every 2,048 SLCK periods */ diff --git a/arch/arm/src/samv7/sam_1wire.c b/arch/arm/src/samv7/sam_1wire.c index 271cdfb94c..329037dec0 100644 --- a/arch/arm/src/samv7/sam_1wire.c +++ b/arch/arm/src/samv7/sam_1wire.c @@ -690,7 +690,7 @@ static int sam_process(struct sam_1wire_s *priv, ret = priv->result; leave_critical_section(irqs); - /* Release the port for re-use by other clients */ + /* Release the port for reuse by other clients */ nxmutex_unlock(&priv->lock); return ret; diff --git a/arch/arm/src/samv7/sam_emac.c b/arch/arm/src/samv7/sam_emac.c index 9190c8ec6b..e44f296865 100644 --- a/arch/arm/src/samv7/sam_emac.c +++ b/arch/arm/src/samv7/sam_emac.c @@ -912,7 +912,7 @@ static uint8_t g_emac_nqueues = EMAC_NQUEUES_REVA; /* Assume Rev A */ * * Returned Value: * true: This is the first register access of this type. - * flase: This is the same as the preceding register access. + * false: This is the same as the preceding register access. * ****************************************************************************/ diff --git a/arch/arm/src/samv7/sam_ethernet.h b/arch/arm/src/samv7/sam_ethernet.h index b826ecc8cc..05c4349036 100644 --- a/arch/arm/src/samv7/sam_ethernet.h +++ b/arch/arm/src/samv7/sam_ethernet.h @@ -200,7 +200,7 @@ int sam_emac_initialize(int intf); * netdev ioctl. The application level code have gotten the MAC * address from some configuration parameter or by accessing some * non-volatile storage containing the address. This is the - * "cannonically correct" way to set the MAC address. + * "canonically correct" way to set the MAC address. * 2) Alterntively, the board logic may support some other less obvious * non-volatile storage and the board-level boot-up code may access * this and use this interface to set the Ethernet MAC address more diff --git a/arch/arm/src/samv7/sam_hsmci.c b/arch/arm/src/samv7/sam_hsmci.c index 8fdef26abf..3755470284 100644 --- a/arch/arm/src/samv7/sam_hsmci.c +++ b/arch/arm/src/samv7/sam_hsmci.c @@ -678,7 +678,7 @@ static int sam_carddetect_handler(int irq, void *context, * * Returned Value: * true: This is the first register access of this type. - * flase: This is the same as the preceding register access. + * false: This is the same as the preceding register access. * ****************************************************************************/ diff --git a/arch/arm/src/samv7/sam_lin_sock.c b/arch/arm/src/samv7/sam_lin_sock.c index 9f9745f851..4da4ab5bf6 100644 --- a/arch/arm/src/samv7/sam_lin_sock.c +++ b/arch/arm/src/samv7/sam_lin_sock.c @@ -1164,7 +1164,7 @@ static void sam_lin_errinterrupt_work(void *arg) if ((priv->sr & UART_INT_LINBE) != 0) { - /* Buss error */ + /* Bus error */ errbits |= CAN_ERR_BUSERROR; } diff --git a/arch/arm/src/samv7/sam_mcan.c b/arch/arm/src/samv7/sam_mcan.c index bbf63022a7..74fa14331c 100644 --- a/arch/arm/src/samv7/sam_mcan.c +++ b/arch/arm/src/samv7/sam_mcan.c @@ -991,18 +991,18 @@ static const struct can_ops_s g_mcanops = #ifdef CONFIG_SAMV7_MCAN0 -/* MCAN0 message RAM allocation. The RAM is initalized to zeroes to ensure +/* MCAN0 message RAM allocation. The RAM is initialized to zeroes to ensure * valid parity/ECC checksums. This should avoid possible BEC or BEU * interrupts according to MCAN manual. * * The message RAM is also located in .mcan section that should be placed - * at the begining of .data section in linker script. The CAN controller + * at the beginning of .data section in linker script. The CAN controller * seems to incorrectly handle lower 16 bits address overflow. For example * message RAM starting at 0x2040fc20 would not work for buffers that * go beyond 0x20410000. The same issue would occur even if TX buffers * would start directly at 0x20410000. The upper 16 bits would still have * 0x2040 value because of RX buffers located in 0x2040ffff range. The - * section ensures the RAM starts at the begining of the data section and + * section ensures the RAM starts at the beginning of the data section and * thus overflow should not occur. */ @@ -1106,18 +1106,18 @@ static struct can_dev_s g_mcan0dev = #ifdef CONFIG_SAMV7_MCAN1 -/* MCAN1 message RAM allocation. The RAM is initalized to zeroes to ensure +/* MCAN1 message RAM allocation. The RAM is initialized to zeroes to ensure * valid parity/ECC checksums. This should avoid possible BEC or BEU * interrupts according to MCAN manual. * * The message RAM is also located in .mcan section that should be placed - * at the begining of .data section in linker script. The CAN controller + * at the beginning of .data section in linker script. The CAN controller * seems to incorrectly handle lower 16 bits address overflow. For example * message RAM starting at 0x2040fc20 would not work for buffers that * go beyond 0x20410000. The same issue would occur even if TX buffers * would start directly at 0x20410000. The upper 16 bits would still have * 0x2040 value because of RX buffers located in 0x2040ffff range. The - * section ensures the RAM starts at the begining of the data section and + * section ensures the RAM starts at the beginning of the data section and * thus overflow should not occur. */ diff --git a/arch/arm/src/samv7/sam_pwm.c b/arch/arm/src/samv7/sam_pwm.c index f503706b9b..7d11e32c42 100644 --- a/arch/arm/src/samv7/sam_pwm.c +++ b/arch/arm/src/samv7/sam_pwm.c @@ -631,7 +631,7 @@ static void pwm_set_comparison(struct pwm_lowerhalf_s *dev) if (pwm_getreg(priv, SAMV7_PWM_CMPMX + COMP_OFFSET * i) & CMPM_CEN) { - /* Use update register if comparision unit is used */ + /* Use update register if comparison unit is used */ pwm_putreg(priv, SAMV7_PWM_CMPVUPDX + COMP_OFFSET * i, width); pwm_putreg(priv, SAMV7_PWM_CMPMUPDX + COMP_OFFSET * i, CMPM_CEN); @@ -697,9 +697,9 @@ static void pwm_set_deadtime(struct pwm_lowerhalf_s *dev, uint8_t channel, * and not 16 as duty cycle or period counter. Therefore a 12 bits recount * is necessary to set the dead time value corresponding to selected * frequency. This expects the dead time value selected in the application - * is moved left by 12 and devided by 100. For example: + * is moved left by 12 and divided by 100. For example: * dead_time_a = (selected_dead_time_duty << 12) / 100 - * This aproach is the same as with duty cycle setup in the application + * This approach is the same as with duty cycle setup in the application * but with 12 bits. * * Also note that it might not be possible to get correct delay on lower diff --git a/arch/arm/src/samv7/sam_qencoder.c b/arch/arm/src/samv7/sam_qencoder.c index 3290bf3553..6863ffc107 100644 --- a/arch/arm/src/samv7/sam_qencoder.c +++ b/arch/arm/src/samv7/sam_qencoder.c @@ -75,7 +75,7 @@ struct sam_lowerhalf_s * All variables are of an unsigned type, while the variables in the * struct qe_index_s are of a signed type. The reason for using unsigned * types is that the operations on unsigned types when extending is - * defined (overflow arithmetics). + * defined (overflow arithmetic). */ uint32_t last_pos; /* The actual position */ @@ -383,7 +383,7 @@ static int sam_qeindex(struct qe_lowerhalf_s *lower, struct qe_index_s *dest) bool captured = false; struct sam_lowerhalf_s *priv = (struct sam_lowerhalf_s *)lower; - /* Perform the current position retrieval everytime */ + /* Perform the current position retrieval every time */ sam_position(lower, ¤t_pos); dest->qenc_pos = current_pos; diff --git a/arch/arm/src/samv7/sam_qspi.c b/arch/arm/src/samv7/sam_qspi.c index 749b79e31a..c84ef50cf3 100644 --- a/arch/arm/src/samv7/sam_qspi.c +++ b/arch/arm/src/samv7/sam_qspi.c @@ -337,7 +337,7 @@ static struct sam_qspidev_s g_qspi0dev = * * Returned Value: * true: This is the first register access of this type. - * flase: This is the same as the preceding register access. + * false: This is the same as the preceding register access. * ****************************************************************************/ diff --git a/arch/arm/src/samv7/sam_rswdt.c b/arch/arm/src/samv7/sam_rswdt.c index aafb03ade6..ab8e9fcacb 100644 --- a/arch/arm/src/samv7/sam_rswdt.c +++ b/arch/arm/src/samv7/sam_rswdt.c @@ -496,7 +496,7 @@ static int sam_settimeout(struct watchdog_lowerhalf_s *lower, regval = WDT_MR_WDV(reload) | RSWDT_MR_WDD_ALLONES; #ifdef CONFIG_SAMV7_RSWDT_INTERRUPT - /* Generate an interrupt whent he watchdog timer expires */ + /* Generate an interrupt when the watchdog timer expires */ regval |= WDT_MR_WDFIEN; #else diff --git a/arch/arm/src/samv7/sam_serial.c b/arch/arm/src/samv7/sam_serial.c index 1a97cc0412..35e3365912 100644 --- a/arch/arm/src/samv7/sam_serial.c +++ b/arch/arm/src/samv7/sam_serial.c @@ -2400,7 +2400,7 @@ static void sam_dma_txcallback(DMA_HANDLE handle, void *arg, int status) if (status != OK) { - /* This means some error occured during DMA transfer. This is most + /* This means some error occurred during DMA transfer. This is most * likely just rare error so schedule work again. Note that this is not * ideal and we could end in an infinite loop. Better approach would be * to use some error counter and report error to serial driver if @@ -2476,7 +2476,7 @@ static void sam_dma_txcallback(DMA_HANDLE handle, void *arg, int status) * * This function should be called from a timer or other periodic context. * - * This polling also in not neccessary if CONFIG_SAMV7_SERIAL_DMA_TIMEOUT + * This polling also in not necessary if CONFIG_SAMV7_SERIAL_DMA_TIMEOUT * is defined as sam_dma_rxcallback() is called each time idle bus is * detected. This however only applies to USART peripherals, UART has to * be polled in any case. @@ -2555,7 +2555,7 @@ void sam_serial_dma_poll(void) * * Description: * Performs the low level USART initialization early in debug so that the - * serial console will be available during bootup. This must be called + * serial console will be available during boot up. This must be called * before arm_serialinit. * ****************************************************************************/ diff --git a/arch/arm/src/samv7/sam_spi.c b/arch/arm/src/samv7/sam_spi.c index f9da85e4f7..94222fba99 100644 --- a/arch/arm/src/samv7/sam_spi.c +++ b/arch/arm/src/samv7/sam_spi.c @@ -406,7 +406,7 @@ static struct sam_spidev_s g_spi1dev = * * Returned Value: * true: This is the first register access of this type. - * flase: This is the same as the preceding register access. + * false: This is the same as the preceding register access. * ****************************************************************************/ diff --git a/arch/arm/src/samv7/sam_spi_slave.c b/arch/arm/src/samv7/sam_spi_slave.c index b6c9cf1d5c..06cf1e5792 100644 --- a/arch/arm/src/samv7/sam_spi_slave.c +++ b/arch/arm/src/samv7/sam_spi_slave.c @@ -235,7 +235,7 @@ static struct sam_spidev_s g_spi1_ctrlr = * * Returned Value: * true: This is the first register access of this type. - * flase: This is the same as the preceding register access. + * false: This is the same as the preceding register access. * ****************************************************************************/ @@ -1007,7 +1007,7 @@ static bool spi_qfull(struct spi_slave_ctrlr_s *ctrlr) if (ret < 0) { /* REVISIT: No mechanism to report error. This error should only - * occurr if the calling task was canceled. + * occur if the calling task was canceled. */ spierr("RROR: nxmutex_lock failed: %d\n", ret); diff --git a/arch/arm/src/samv7/sam_ssc.c b/arch/arm/src/samv7/sam_ssc.c index 192d1abab6..0f2530e073 100644 --- a/arch/arm/src/samv7/sam_ssc.c +++ b/arch/arm/src/samv7/sam_ssc.c @@ -635,7 +635,7 @@ static const struct i2s_ops_s g_sscops = * * Returned Value: * true: This is the first register access of this type. - * flase: This is the same as the preceding register access. + * false: This is the same as the preceding register access. * ****************************************************************************/ diff --git a/arch/arm/src/samv7/sam_tc.c b/arch/arm/src/samv7/sam_tc.c index 4b3a994b80..32a1908b39 100644 --- a/arch/arm/src/samv7/sam_tc.c +++ b/arch/arm/src/samv7/sam_tc.c @@ -633,7 +633,7 @@ static void sam_regdump(struct sam_chan_s *chan, const char *msg) * * Returned Value: * true: This is the first register access of this type. - * flase: This is the same as the preceding register access. + * false: This is the same as the preceding register access. * ****************************************************************************/ diff --git a/arch/arm/src/samv7/sam_usbdevhs.c b/arch/arm/src/samv7/sam_usbdevhs.c index cfee6b82ac..a268aa046c 100644 --- a/arch/arm/src/samv7/sam_usbdevhs.c +++ b/arch/arm/src/samv7/sam_usbdevhs.c @@ -3562,7 +3562,7 @@ sam_ep_reserve(struct sam_usbdev_s *priv, uint16_t epset) * * Description: * The endpoint is no long in-used. It will be un-reserved and can be - * re-used if needed. + * reused if needed. * ****************************************************************************/ diff --git a/arch/arm/src/samv7/sam_wdt.c b/arch/arm/src/samv7/sam_wdt.c index 1fcddd22a0..e612163aad 100644 --- a/arch/arm/src/samv7/sam_wdt.c +++ b/arch/arm/src/samv7/sam_wdt.c @@ -506,7 +506,7 @@ static int sam_settimeout(struct watchdog_lowerhalf_s *lower, regval = WDT_MR_WDV(reload) | WDT_MR_WDD(WDT_MR_WDD_MAX); #ifdef CONFIG_SAMV7_WDT_INTERRUPT - /* Generate an interrupt whent he watchdog timer expires */ + /* Generate an interrupt when the watchdog timer expires */ regval |= WDT_MR_WDFIEN; #else diff --git a/arch/arm/src/samv7/sam_xdmac.c b/arch/arm/src/samv7/sam_xdmac.c index 7237a6172c..79e93b38ee 100644 --- a/arch/arm/src/samv7/sam_xdmac.c +++ b/arch/arm/src/samv7/sam_xdmac.c @@ -1116,7 +1116,7 @@ static int sam_txbuffer(struct sam_xdmach_s *xdmach, uint32_t paddr, { uint32_t cubc; - /* If we are appending a buffer to a linklist, then re-use the previously + /* If we are appending a buffer to a linklist, then reuse the previously * calculated CC register value. Otherwise, create the CC register value * from the properties of the transfer. */ @@ -1156,7 +1156,7 @@ static int sam_rxbuffer(struct sam_xdmach_s *xdmach, uint32_t paddr, { uint32_t cubc; - /* If we are appending a buffer to a linklist, then re-use the previously + /* If we are appending a buffer to a linklist, then reuse the previously * calculated CC register value. Otherwise, create the CC register value * from the properties of the transfer. */ @@ -1961,7 +1961,7 @@ int sam_dmarxsetup_circular(DMA_HANDLE handle, nextdescr = i; } - /* Settup of llhead and lltail does not really matter in this case */ + /* Setup of llhead and lltail does not really matter in this case */ xdmach->llhead = descr[0]; xdmach->lltail = descr[0]; diff --git a/arch/arm/src/stm32/Kconfig b/arch/arm/src/stm32/Kconfig index 1d3211a178..13a3fbc47f 100644 --- a/arch/arm/src/stm32/Kconfig +++ b/arch/arm/src/stm32/Kconfig @@ -6811,10 +6811,10 @@ config STM32_TIM1_CHANNEL channel {1,..,4} config STM32_TIM1_CLOCK - int "TIM1 work frequence for capture" + int "TIM1 work frequency for capture" default 1000000 ---help--- - This clock frequence limiting the count rate at the expense of resolution. + This clock frequency limiting the count rate at the expense of resolution. endif # STM32_TIM1_CAP @@ -6840,10 +6840,10 @@ config STM32_TIM2_CHANNEL channel {1,..,4} config STM32_TIM2_CLOCK - int "TIM2 work frequence for capture" + int "TIM2 work frequency for capture" default 1000000 ---help--- - This clock frequence limiting the count rate at the expense of resolution. + This clock frequency limiting the count rate at the expense of resolution. endif # STM32_TIM2_CAP @@ -6869,10 +6869,10 @@ config STM32_TIM3_CHANNEL channel {1,..,4} config STM32_TIM3_CLOCK - int "TIM3 work frequence for capture" + int "TIM3 work frequency for capture" default 1000000 ---help--- - This clock frequence limiting the count rate at the expense of resolution. + This clock frequency limiting the count rate at the expense of resolution. endif # STM32_TIM3_CAP @@ -6898,10 +6898,10 @@ config STM32_TIM4_CHANNEL channel {1,..,4} config STM32_TIM4_CLOCK - int "TIM4 work frequence for capture" + int "TIM4 work frequency for capture" default 1000000 ---help--- - This clock frequence limiting the count rate at the expense of resolution. + This clock frequency limiting the count rate at the expense of resolution. endif # STM32_TIM4_CAP @@ -6927,10 +6927,10 @@ config STM32_TIM5_CHANNEL channel {1,..,4} config STM32_TIM5_CLOCK - int "TIM5 work frequence for capture" + int "TIM5 work frequency for capture" default 1000000 ---help--- - This clock frequence limiting the count rate at the expense of resolution. + This clock frequency limiting the count rate at the expense of resolution. endif # STM32_TIM5_CAP @@ -6956,10 +6956,10 @@ config STM32_TIM8_CHANNEL channel {1,..,4} config STM32_TIM8_CLOCK - int "TIM8 work frequence for capture" + int "TIM8 work frequency for capture" default 1000000 ---help--- - This clock frequence limiting the count rate at the expense of resolution. + This clock frequency limiting the count rate at the expense of resolution. endif # STM32_TIM8_CAP @@ -6985,10 +6985,10 @@ config STM32_TIM9_CHANNEL channel {1,..,4} config STM32_TIM9_CLOCK - int "TIM9 work frequence for capture" + int "TIM9 work frequency for capture" default 1000000 ---help--- - This clock frequence limiting the count rate at the expense of resolution. + This clock frequency limiting the count rate at the expense of resolution. endif # STM32_TIM9_CAP @@ -7014,10 +7014,10 @@ config STM32_TIM10_CHANNEL channel {1,..,4} config STM32_TIM10_CLOCK - int "TIM10 work frequence for capture" + int "TIM10 work frequency for capture" default 1000000 ---help--- - This clock frequence limiting the count rate at the expense of resolution. + This clock frequency limiting the count rate at the expense of resolution. endif # STM32_TIM10_CAP @@ -7043,10 +7043,10 @@ config STM32_TIM11_CHANNEL channel {1,..,4} config STM32_TIM11_CLOCK - int "TIM11 work frequence for capture" + int "TIM11 work frequency for capture" default 1000000 ---help--- - This clock frequence limiting the count rate at the expense of resolution. + This clock frequency limiting the count rate at the expense of resolution. endif # STM32_TIM11_CAP @@ -7072,10 +7072,10 @@ config STM32_TIM12_CHANNEL channel {1,..,4} config STM32_TIM12_CLOCK - int "TIM12 work frequence for capture" + int "TIM12 work frequency for capture" default 1000000 ---help--- - This clock frequence limiting the count rate at the expense of resolution. + This clock frequency limiting the count rate at the expense of resolution. endif # STM32_TIM12_CAP @@ -7101,10 +7101,10 @@ config STM32_TIM13_CHANNEL channel {1,..,4} config STM32_TIM13_CLOCK - int "TIM13 work frequence for capture" + int "TIM13 work frequency for capture" default 1000000 ---help--- - This clock frequence limiting the count rate at the expense of resolution. + This clock frequency limiting the count rate at the expense of resolution. endif # STM32_TIM13_CAP @@ -7130,10 +7130,10 @@ config STM32_TIM14_CHANNEL channel {1,..,4} config STM32_TIM14_CLOCK - int "TIM14 work frequence for capture" + int "TIM14 work frequency for capture" default 1000000 ---help--- - This clock frequence limiting the count rate at the expense of resolution. + This clock frequency limiting the count rate at the expense of resolution. endif # STM32_TIM14_CAP @@ -11299,7 +11299,7 @@ choice config STM32_FDCAN1_CLASSIC bool "Classic CAN" ---help--- - Enable Clasic CAN mode + Enable Classic CAN mode config STM32_FDCAN1_FD bool "CAN FD" @@ -11413,7 +11413,7 @@ choice config STM32_FDCAN2_CLASSIC bool "Classic CAN" ---help--- - Enable Clasic CAN mode + Enable Classic CAN mode config STM32_FDCAN2_FD bool "CAN FD" @@ -11527,7 +11527,7 @@ choice config STM32_FDCAN3_CLASSIC bool "Classic CAN" ---help--- - Enable Clasic CAN mode + Enable Classic CAN mode config STM32_FDCAN3_FD bool "CAN FD" diff --git a/arch/arm/src/stm32/hardware/stm32_adc_v2g4.h b/arch/arm/src/stm32/hardware/stm32_adc_v2g4.h index de66ec0ecd..211bff7fe4 100644 --- a/arch/arm/src/stm32/hardware/stm32_adc_v2g4.h +++ b/arch/arm/src/stm32/hardware/stm32_adc_v2g4.h @@ -319,7 +319,7 @@ #define ADC_CR_ADCALDIF (1 << 30) /* Bit 30: Differential mode for calibration */ #define ADC_CR_ADCAL (1 << 31) /* Bit 31: ADC calibration */ -/* For complaince with the ADC driver we also define ADVREGEN like +/* For compliance with the ADC driver we also define ADVREGEN like * for previous chips. For new chips ST decided to better describe * the mechanism behind ADVREGEN bits. */ diff --git a/arch/arm/src/stm32/hardware/stm32_otghs.h b/arch/arm/src/stm32/hardware/stm32_otghs.h index 384451f661..59583ad969 100644 --- a/arch/arm/src/stm32/hardware/stm32_otghs.h +++ b/arch/arm/src/stm32/hardware/stm32_otghs.h @@ -100,7 +100,7 @@ #define STM32_OTGHS_HCCHAR7_OFFSET 0x05e0 /* Host channel-7 characteristics register */ #define STM32_OTGHS_HCCHAR8_OFFSET 0x0600 /* Host channel-8 characteristics register */ #define STM32_OTGHS_HCCHAR9_OFFSET 0x0620 /* Host channel-9 characteristics register */ -#define STM32_OTGHS_HCCHAR10_OFFSET 0x0640 /* Host channel-10 caracteristics register */ +#define STM32_OTGHS_HCCHAR10_OFFSET 0x0640 /* Host channel-10 characteristics register */ #define STM32_OTGHS_HCCHAR11_OFFSET 0x0660 /* Host channel-11 characteristics register */ #define STM32_OTGHS_HCINT_OFFSET(n) (0x508 + ((n) << 5)) diff --git a/arch/arm/src/stm32/hardware/stm32_tim_v1v2.h b/arch/arm/src/stm32/hardware/stm32_tim_v1v2.h index 249bb8716d..bc1408b484 100644 --- a/arch/arm/src/stm32/hardware/stm32_tim_v1v2.h +++ b/arch/arm/src/stm32/hardware/stm32_tim_v1v2.h @@ -513,7 +513,7 @@ #define ATIM_CR2_OIS3N (1 << 13) /* Bit 13: Output Idle state 3 (OC3N output) */ #define ATIM_CR2_OIS4 (1 << 14) /* Bit 14: Output Idle state 4 (OC4 output) */ #ifdef HAVE_IP_TIMERS_V2 -# define ATIM_CR2_OIS5 (1 << 16) /* Bit 16: OOutput Idle state 5 (OC5 output) */ +# define ATIM_CR2_OIS5 (1 << 16) /* Bit 16: Output Idle state 5 (OC5 output) */ # define ATIM_CR2_OIS6 (1 << 18) /* Bit 18: Output Idle state 6 (OC6 output) */ # define ATIM_CR2_MMS2_SHIFT (20) /* Bits 20-23: Master Mode Selection 2 */ # define ATIM_CR2_MMS2_MASK (15 << ATIM_CR2_MMS2_SHIFT) diff --git a/arch/arm/src/stm32/hardware/stm32_tim_v3.h b/arch/arm/src/stm32/hardware/stm32_tim_v3.h index c43dac153b..eb6e542139 100644 --- a/arch/arm/src/stm32/hardware/stm32_tim_v3.h +++ b/arch/arm/src/stm32/hardware/stm32_tim_v3.h @@ -472,7 +472,7 @@ #define ATIM_CR2_OIS3N (1 << 13) /* Bit 13: Output Idle state 3 (OC3N output) */ #define ATIM_CR2_OIS4 (1 << 14) /* Bit 14: Output Idle state 4 (OC4 output) */ #define ATIM_CR2_OIS4N (1 << 15) /* Bit 15: Output Idle state 4 (OC4N output) */ -#define ATIM_CR2_OIS5 (1 << 16) /* Bit 16: OOutput Idle state 5 (OC5 output) */ +#define ATIM_CR2_OIS5 (1 << 16) /* Bit 16: Output Idle state 5 (OC5 output) */ #define ATIM_CR2_OIS6 (1 << 18) /* Bit 18: Output Idle state 6 (OC6 output) */ #define ATIM_CR2_MMS2_SHIFT (20) /* Bits 20-23: Master Mode Selection 2 */ #define ATIM_CR2_MMS2_MASK (0xf << ATIM_CR2_MMS2_SHIFT) diff --git a/arch/arm/src/stm32/stm32_1wire.c b/arch/arm/src/stm32/stm32_1wire.c index d48b3e1e8d..88215338e3 100644 --- a/arch/arm/src/stm32/stm32_1wire.c +++ b/arch/arm/src/stm32/stm32_1wire.c @@ -828,7 +828,7 @@ static int stm32_1wire_process(struct stm32_1wire_priv_s *priv, ret = priv->result; leave_critical_section(irqs); - /* Release the port for re-use by other clients */ + /* Release the port for reuse by other clients */ nxmutex_unlock(&priv->lock); return ret; diff --git a/arch/arm/src/stm32/stm32_capture.h b/arch/arm/src/stm32/stm32_capture.h index f953cf4b2b..fde7ceb9b7 100644 --- a/arch/arm/src/stm32/stm32_capture.h +++ b/arch/arm/src/stm32/stm32_capture.h @@ -153,7 +153,7 @@ typedef enum STM32_CAP_TS_TI2FP2 = (6 << GTIM_SMCR_TS_SHIFT), STM32_CAP_TS_ETRF = (7 << GTIM_SMCR_TS_SHIFT), - /* Master/Slave mode seting */ + /* Master/Slave mode setting */ STM32_CAP_MSM_MASK = (1 << 7) } stm32_cap_smc_cfg_t; diff --git a/arch/arm/src/stm32/stm32_capture_lowerhalf.c b/arch/arm/src/stm32/stm32_capture_lowerhalf.c index bfe99635d8..0246f5e28f 100644 --- a/arch/arm/src/stm32/stm32_capture_lowerhalf.c +++ b/arch/arm/src/stm32/stm32_capture_lowerhalf.c @@ -82,9 +82,9 @@ struct stm32_lowerhalf_s bool started; /* True: Timer has been started */ const uint8_t resolution; /* Number of bits in the timer */ uint8_t channel; /* pwm input channel */ - uint32_t clock; /* Timer clock frequence */ - uint8_t duty; /* Result pwm frequence */ - uint32_t freq; /* Result pwm frequence */ + uint32_t clock; /* Timer clock frequency */ + uint8_t duty; /* Result pwm frequency */ + uint32_t freq; /* Result pwm frequency */ }; /**************************************************************************** @@ -446,7 +446,7 @@ static int stm32_getduty(struct cap_lowerhalf_s *lower, uint8_t *duty) * Input Parameters: * lower - A pointer the publicly visible representation of the * "lower-half" driver state structure. - * freq - Frequence in Hz . + * freq - Frequency in Hz. * * Returned Value: * Zero on success; a negated errno value on failure. diff --git a/arch/arm/src/stm32/stm32_cordic.c b/arch/arm/src/stm32/stm32_cordic.c index 52d501d978..2a6f4c1333 100644 --- a/arch/arm/src/stm32/stm32_cordic.c +++ b/arch/arm/src/stm32/stm32_cordic.c @@ -272,7 +272,7 @@ int cordic_calc(struct cordic_lowerhalf_s *lower, } /* Read results - blocking. - * NOTE: We don't need to wait for RRDY flag as wait sates are + * NOTE: We don't need to wait for RRDY flag as wait states are * inserted automatically on RDATA read. */ diff --git a/arch/arm/src/stm32/stm32_dma2d.c b/arch/arm/src/stm32/stm32_dma2d.c index 94faf5ab49..c88dd900d2 100644 --- a/arch/arm/src/stm32/stm32_dma2d.c +++ b/arch/arm/src/stm32/stm32_dma2d.c @@ -69,7 +69,7 @@ STM32_DMA2D_CR_MODE_BLEND | \ STM32_DMA2D_CR_MODE_COLOR -/* Only 8 bit per pixel overal supported */ +/* Only 8 bit per pixel overall supported */ #define DMA2D_PF_BYPP(n) ((n) / 8) diff --git a/arch/arm/src/stm32/stm32_dma_v1.c b/arch/arm/src/stm32/stm32_dma_v1.c index c0b3ca4766..ca3fef9bbd 100644 --- a/arch/arm/src/stm32/stm32_dma_v1.c +++ b/arch/arm/src/stm32/stm32_dma_v1.c @@ -629,7 +629,7 @@ void stm32_dmastart(DMA_HANDLE handle, dma_callback_t callback, DEBUGASSERT(handle != NULL); - /* Save the callback info. This will be invoked whent the DMA completes */ + /* Save the callback info. This will be invoked when the DMA completes. */ dmach->callback = callback; dmach->arg = arg; diff --git a/arch/arm/src/stm32/stm32_dma_v2.c b/arch/arm/src/stm32/stm32_dma_v2.c index cd73ce1c71..3098a33e0d 100644 --- a/arch/arm/src/stm32/stm32_dma_v2.c +++ b/arch/arm/src/stm32/stm32_dma_v2.c @@ -775,7 +775,7 @@ void stm32_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg, DEBUGASSERT(handle != NULL); - /* Save the callback info. This will be invoked whent the DMA completes */ + /* Save the callback info. This will be invoked when the DMA completes. */ dmast->callback = callback; dmast->arg = arg; diff --git a/arch/arm/src/stm32/stm32_fdcan.c b/arch/arm/src/stm32/stm32_fdcan.c index 2802995d0e..d63cfaa76d 100644 --- a/arch/arm/src/stm32/stm32_fdcan.c +++ b/arch/arm/src/stm32/stm32_fdcan.c @@ -2394,7 +2394,7 @@ static int fdcan_send(struct can_dev_s *dev, struct can_msg_s *msg) * Format word T1: * Data Length Code (DLC) - Value from message structure * Bit Rate Switch (BRS) - Bit rate switching for CAN FD - * FD format (FDF) - Frame transmited in CAN FD format + * FD format (FDF) - Frame transmitted in CAN FD format * Event FIFO Control (EFC) - Do not store events. * Message Marker (MM) - Always zero */ @@ -2965,10 +2965,10 @@ static int fdcan_interrupt(int irq, void *context, void *arg) canerr("ERROR: Common %08" PRIx32 "\n", pending & FDCAN_CMNERR_INTS); - /* When a protocol error ocurrs, the problem is recorded in + /* When a protocol error occurs, the problem is recorded in * the LEC/DLEC fields of the PSR register. In lieu of - * seprate interrupt flags for each error, the hardware - * groups procotol errors under a single interrupt each for + * separate interrupt flags for each error, the hardware + * groups protocol errors under a single interrupt each for * arbitration and data phases. * * These errors have a tendency to flood the system with @@ -2983,7 +2983,7 @@ static int fdcan_interrupt(int irq, void *context, void *arg) canerr("ERROR: PSR %08" PRIx32 "\n", psr); ie &= ~(FDCAN_INT_PEA | FDCAN_INT_PED); fdcan_putreg(priv, STM32_FDCAN_IE_OFFSET, ie); - caninfo("disabled protocol error intterupts\n"); + caninfo("disabled protocol error interrupts\n"); } /* Clear the error indications */ @@ -3058,7 +3058,7 @@ static int fdcan_interrupt(int irq, void *context, void *arg) { ie |= (FDCAN_INT_PEA | FDCAN_INT_PED); fdcan_putreg(priv, STM32_FDCAN_IE_OFFSET, ie); - caninfo("Renabled protocol error intterupts\n"); + caninfo("Re-enabled protocol error interrupts\n"); } /* Clear the pending TX completion interrupt (and all @@ -3227,7 +3227,7 @@ static int fdcan_hw_initialize(struct stm32_fdcan_s *priv) stm32_configgpio(config->rxpinset); stm32_configgpio(config->txpinset); - /* Renable device if previosuly disabled in fdcan_shutdown() */ + /* Re-enable device if previously disabled in fdcan_shutdown() */ if (priv->state == FDCAN_STATE_DISABLED) { diff --git a/arch/arm/src/stm32/stm32_fdcan_sock.c b/arch/arm/src/stm32/stm32_fdcan_sock.c index 273f3122a9..4c3c5df332 100644 --- a/arch/arm/src/stm32/stm32_fdcan_sock.c +++ b/arch/arm/src/stm32/stm32_fdcan_sock.c @@ -1660,7 +1660,7 @@ static int fdcan_send(struct stm32_fdcan_s *priv) * Format word T1: * Data Length Code (DLC) - Value from message structure * Bit Rate Switch (BRS) - Bit rate switching for CAN FD - * FD format (FDF) - Frame transmited in CAN FD format + * FD format (FDF) - Frame transmitted in CAN FD format * Event FIFO Control (EFC) - Do not store events. * Message Marker (MM) - Always zero */ @@ -2055,10 +2055,10 @@ static void fdcan_error_work(void *arg) if ((pending & FDCAN_CMNERR_INTS) != 0) { - /* When a protocol error ocurrs, the problem is recorded in + /* When a protocol error occurs, the problem is recorded in * the LEC/DLEC fields of the PSR register. In lieu of - * seprate interrupt flags for each error, the hardware - * groups procotol errors under a single interrupt each for + * separate interrupt flags for each error, the hardware + * groups protocol errors under a single interrupt each for * arbitration and data phases. * * These errors have a tendency to flood the system with @@ -2699,7 +2699,7 @@ static int fdcan_hw_initialize(struct stm32_fdcan_s *priv) stm32_configgpio(config->rxpinset); stm32_configgpio(config->txpinset); - /* Renable device if previosuly disabled in fdcan_shutdown() */ + /* Re-enable device if previously disabled in fdcan_shutdown() */ if (priv->state == FDCAN_STATE_DISABLED) { diff --git a/arch/arm/src/stm32/stm32_i2c.c b/arch/arm/src/stm32/stm32_i2c.c index a8fd44c269..d7be286f7c 100644 --- a/arch/arm/src/stm32/stm32_i2c.c +++ b/arch/arm/src/stm32/stm32_i2c.c @@ -1844,7 +1844,7 @@ static int stm32_i2c_reset(struct i2c_master_s *dev) out: - /* Release the port for re-use by other clients */ + /* Release the port for reuse by other clients */ nxmutex_unlock(&priv->lock); return ret; diff --git a/arch/arm/src/stm32/stm32_i2c_alt.c b/arch/arm/src/stm32/stm32_i2c_alt.c index a23a66ec62..73f738b0aa 100644 --- a/arch/arm/src/stm32/stm32_i2c_alt.c +++ b/arch/arm/src/stm32/stm32_i2c_alt.c @@ -2351,7 +2351,7 @@ static int stm32_i2c_reset(struct i2c_master_s *dev) out: - /* Release the port for re-use by other clients */ + /* Release the port for reuse by other clients */ nxmutex_unlock(&priv->lock); return ret; diff --git a/arch/arm/src/stm32/stm32_i2c_v2.c b/arch/arm/src/stm32/stm32_i2c_v2.c index 3ddf200be7..b847aafd4b 100644 --- a/arch/arm/src/stm32/stm32_i2c_v2.c +++ b/arch/arm/src/stm32/stm32_i2c_v2.c @@ -2622,7 +2622,7 @@ static int stm32_i2c_reset(struct i2c_master_s *dev) out: - /* Release the port for re-use by other clients */ + /* Release the port for reuse by other clients */ nxmutex_unlock(&priv->lock); return ret; diff --git a/arch/arm/src/stm32/stm32_i2s.c b/arch/arm/src/stm32/stm32_i2s.c index f14b1a083f..04beb31f60 100644 --- a/arch/arm/src/stm32/stm32_i2s.c +++ b/arch/arm/src/stm32/stm32_i2s.c @@ -469,7 +469,7 @@ static const struct i2s_ops_s g_i2sops = * * Returned Value: * true: This is the first register access of this type. - * flase: This is the same as the preceding register access. + * false: This is the same as the preceding register access. * ****************************************************************************/ diff --git a/arch/arm/src/stm32/stm32_ltdc.c b/arch/arm/src/stm32/stm32_ltdc.c index f2692a5cad..da2e4ac58b 100644 --- a/arch/arm/src/stm32/stm32_ltdc.c +++ b/arch/arm/src/stm32/stm32_ltdc.c @@ -206,7 +206,7 @@ # error Undefined or unrecognized base resolution #endif -/* LTDC only supports 8 bit per pixel overal */ +/* LTDC only supports 8 bit per pixel overall */ #define STM32_LTDC_LX_BYPP(n) ((n) / 8) @@ -664,7 +664,7 @@ struct stm32_interrupt_s * Private Function Prototypes ****************************************************************************/ -/* Overal LTDC helper */ +/* Overall LTDC helper */ static void stm32_ltdc_enable(bool enable); static void stm32_ltdc_gpioconfig(void); diff --git a/arch/arm/src/stm32/stm32_otgfsdev.c b/arch/arm/src/stm32/stm32_otgfsdev.c index fccf3778a4..82b58d472e 100644 --- a/arch/arm/src/stm32/stm32_otgfsdev.c +++ b/arch/arm/src/stm32/stm32_otgfsdev.c @@ -2189,8 +2189,8 @@ static inline void stm32_ep0out_testmode(struct stm32_usbdev_s *priv, * Name: stm32_ep0out_stdrequest * * Description: - * Handle a stanard request on EP0. Pick off the things of interest to the - * USB device controller driver; pass what is left to the class driver. + * Handle a standard request on EP0. Pick off the things of interest to + * the USB device controller driver; pass what is left to the class driver. * ****************************************************************************/ @@ -5640,7 +5640,7 @@ void arm_usbinitialize(void) arm_usbuninitialize(); - /* Initialie the driver data structure */ + /* Initialize the driver data structure */ stm32_swinitialize(priv); diff --git a/arch/arm/src/stm32/stm32_otgfshost.c b/arch/arm/src/stm32/stm32_otgfshost.c index 036ae63cef..6f88e17aaf 100644 --- a/arch/arm/src/stm32/stm32_otgfshost.c +++ b/arch/arm/src/stm32/stm32_otgfshost.c @@ -2774,7 +2774,7 @@ static inline void stm32_gint_hcoutisr(struct stm32_usbhost_s *priv, else if ((pending & OTGFS_HCINT_STALL) != 0) { - /* Clear the pending the STALL response receiv (STALL) interrupt */ + /* Clear the pending the STALL response receive (STALL) interrupt */ stm32_putreg(STM32_OTGFS_HCINT(chidx), OTGFS_HCINT_STALL); diff --git a/arch/arm/src/stm32/stm32_otghsdev.c b/arch/arm/src/stm32/stm32_otghsdev.c index 3bee990bc0..94ebf034e8 100644 --- a/arch/arm/src/stm32/stm32_otghsdev.c +++ b/arch/arm/src/stm32/stm32_otghsdev.c @@ -2110,8 +2110,8 @@ static inline void stm32_ep0out_testmode(struct stm32_usbdev_s *priv, * Name: stm32_ep0out_stdrequest * * Description: - * Handle a stanard request on EP0. Pick off the things of interest to the - * USB device controller driver; pass what is left to the class driver. + * Handle a standard request on EP0. Pick off the things of interest to + * the USB device controller driver; pass what is left to the class driver. * ****************************************************************************/ @@ -5529,7 +5529,7 @@ void arm_usbinitialize(void) arm_usbuninitialize(); - /* Initialie the driver data structure */ + /* Initialize the driver data structure */ stm32_swinitialize(priv); diff --git a/arch/arm/src/stm32/stm32_otghshost.c b/arch/arm/src/stm32/stm32_otghshost.c index b2753ded09..32d59765f6 100644 --- a/arch/arm/src/stm32/stm32_otghshost.c +++ b/arch/arm/src/stm32/stm32_otghshost.c @@ -2775,7 +2775,7 @@ static inline void stm32_gint_hcoutisr(struct stm32_usbhost_s *priv, else if ((pending & OTGHS_HCINT_STALL) != 0) { - /* Clear the pending the STALL response receiv (STALL) interrupt */ + /* Clear the pending the STALL response receive (STALL) interrupt */ stm32_putreg(STM32_OTGHS_HCINT(chidx), OTGHS_HCINT_STALL); diff --git a/arch/arm/src/stm32/stm32_pwm.c b/arch/arm/src/stm32/stm32_pwm.c index 684f6a753d..fe2f05cc99 100644 --- a/arch/arm/src/stm32/stm32_pwm.c +++ b/arch/arm/src/stm32/stm32_pwm.c @@ -2953,7 +2953,7 @@ static int pwm_outputs_enable(struct pwm_lowerhalf_s *dev, uint32_t ccer = 0; uint32_t regval = 0; - /* Get curren register state */ + /* Get current register state */ ccer = pwm_getreg(priv, STM32_GTIM_CCER_OFFSET); @@ -2976,7 +2976,7 @@ static int pwm_outputs_enable(struct pwm_lowerhalf_s *dev, if (state == true) { - /* Enable outpus - set bits */ + /* Enable outputs - set bits */ ccer |= regval; } @@ -3039,7 +3039,7 @@ errout: * Name: pwm_trgo_configure * * Description: - * Confiugre an output synchronisation event for PWM timer (TRGO/TRGO2) + * Configure an output synchronisation event for PWM timer (TRGO/TRGO2) * ****************************************************************************/ @@ -3142,7 +3142,7 @@ static uint16_t pwm_outputs_from_channels(struct stm32_pwmtimer_s *priv) if (channel != 0) { - /* Enable output if confiugred */ + /* Enable output if configured */ if (priv->channels[i].out1.in_use == 1) { diff --git a/arch/arm/src/stm32/stm32_qencoder.c b/arch/arm/src/stm32/stm32_qencoder.c index 0fe7312039..cd26ed9e26 100644 --- a/arch/arm/src/stm32/stm32_qencoder.c +++ b/arch/arm/src/stm32/stm32_qencoder.c @@ -1312,7 +1312,7 @@ static int stm32_setindex(struct qe_lowerhalf_s *lower, uint32_t pos) struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; int ret = OK; - sninfo("Set QE TIM%d the index pin positon %" PRIx32 "\n", + sninfo("Set QE TIM%d the index pin position %" PRIx32 "\n", priv->config->timid, pos); DEBUGASSERT(lower && priv->inuse); diff --git a/arch/arm/src/stm32/stm32_sdio.c b/arch/arm/src/stm32/stm32_sdio.c index 2a3df2d720..f1fcbc56b8 100644 --- a/arch/arm/src/stm32/stm32_sdio.c +++ b/arch/arm/src/stm32/stm32_sdio.c @@ -2198,7 +2198,7 @@ static int stm32_waitresponse(struct sdio_dev_s *dev, uint32_t cmd) * * Returned Value: * Number of bytes sent on success; a negated errno on failure. Here a - * failure means only a faiure to obtain the requested response (due to + * failure means only a failure to obtain the requested response (due to * transport problem -- timeout, CRC, etc.). The implementation only * assures that the response is returned intacta and does not check errors * within the response itself. diff --git a/arch/arm/src/stm32/stm32_serial.c b/arch/arm/src/stm32/stm32_serial.c index 8d1df6a613..0d2cc519ac 100644 --- a/arch/arm/src/stm32/stm32_serial.c +++ b/arch/arm/src/stm32/stm32_serial.c @@ -473,7 +473,7 @@ struct up_dev_s #ifdef SERIAL_HAVE_TXDMA const unsigned int txdma_channel; /* DMA channel assigned */ - DMA_HANDLE txdma; /* currently-open trasnmit DMA stream */ + DMA_HANDLE txdma; /* currently-open transmit DMA stream */ #endif #ifdef SERIAL_HAVE_RXDMA @@ -3446,7 +3446,7 @@ uart_dev_t *stm32_serial_get_uart(int uart_num) * * Description: * Performs the low level USART initialization early in debug so that the - * serial console will be available during bootup. This must be called + * serial console will be available during boot up. This must be called * before arm_serialinit. * ****************************************************************************/ diff --git a/arch/arm/src/stm32/stm32f30xxx_rcc.c b/arch/arm/src/stm32/stm32f30xxx_rcc.c index 36171bfcc4..1e2796b085 100644 --- a/arch/arm/src/stm32/stm32f30xxx_rcc.c +++ b/arch/arm/src/stm32/stm32f30xxx_rcc.c @@ -550,7 +550,7 @@ static void stm32_stdclockconfig(void) #endif #if defined(CONFIG_STM32_RTC_LSECLOCK) - /* Normally peripheral clocks are enabled later in bootup, but we need + /* Normally peripheral clocks are enabled later in boot up, but we need * clock on PWR *now* as without this setting registers that enable LSE * won't work. * diff --git a/arch/arm/src/stm32/stm32f40xxx_i2c.c b/arch/arm/src/stm32/stm32f40xxx_i2c.c index fac079150c..5b9f733892 100644 --- a/arch/arm/src/stm32/stm32f40xxx_i2c.c +++ b/arch/arm/src/stm32/stm32f40xxx_i2c.c @@ -2572,7 +2572,7 @@ static int stm32_i2c_reset(struct i2c_master_s *dev) out: - /* Release the port for re-use by other clients */ + /* Release the port for reuse by other clients */ nxmutex_unlock(&priv->lock); return ret; diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_crc.h b/arch/arm/src/stm32f0l0g0/hardware/stm32_crc.h index 49b9a97d4a..8aa180ded0 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32_crc.h +++ b/arch/arm/src/stm32f0l0g0/hardware/stm32_crc.h @@ -66,7 +66,7 @@ # define CRC_CR_POLYSIZE_8 (2 << CRC_CR_POLYSIZE_SHIFT) /* 10: 8 bit polynomial */ # define CRC_CR_POLYSIZE_7 (3 << CRC_CR_POLYSIZE_SHIFT) /* 10: 8 bit polynomial */ -#define CRC_CR_REVIN_SHIFT 5 /* Bits 5-6: These bits ontrol the reversal of the bit order of the input data */ +#define CRC_CR_REVIN_SHIFT 5 /* Bits 5-6: These bits control the reversal of the bit order of the input data */ #define CRC_CR_REVIN_MASK (3 << CRC_CR_REVIN_SHIFT) # define CRC_CR_REVIN_NONE (0 << CRC_CR_REVIN_SHIFT) /* 00: bit order is not affected */ # define CRC_CR_REVIN_BYTE (1 << CRC_CR_REVIN_SHIFT) /* 01: reversal done by byte */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_crs.h b/arch/arm/src/stm32f0l0g0/hardware/stm32_crs.h index 58a106bd8b..00e007a49c 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32_crs.h +++ b/arch/arm/src/stm32f0l0g0/hardware/stm32_crs.h @@ -84,7 +84,7 @@ #define CRS_ISR_SYNCOKF (1 << 0) /* Bit 0: SYNC event OK flag */ #define CRS_ISR_SYNCWARNF (1 << 1) /* Bit 1: SYNC warning flag */ -#define CRS_ISR_ERRF (1 << 2) /* Bit 2: Errot flag */ +#define CRS_ISR_ERRF (1 << 2) /* Bit 2: Error flag */ #define CRS_ISR_ESYNCF (1 << 3) /* Bit 3: Expected SYNC flag */ #define CRS_ISR_SYNCERR (1 << 8) /* Bit 8: SYNC error */ #define CRS_ISR_SYNCMISS (1 << 9) /* Bit 9: SYNC missed */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_tim.h b/arch/arm/src/stm32f0l0g0/hardware/stm32_tim.h index d505239eb4..41952b81ba 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32_tim.h +++ b/arch/arm/src/stm32f0l0g0/hardware/stm32_tim.h @@ -293,7 +293,7 @@ #define ATIM_CR2_OIS3 (1 << 12) /* Bit 12: Output Idle state 3 (OC3 output) */ #define ATIM_CR2_OIS3N (1 << 13) /* Bit 13: Output Idle state 3 (OC3N output) */ #define ATIM_CR2_OIS4 (1 << 14) /* Bit 14: Output Idle state 4 (OC4 output) */ -#define ATIM_CR2_OIS5 (1 << 16) /* Bit 16: OOutput Idle state 5 (OC5 output) */ +#define ATIM_CR2_OIS5 (1 << 16) /* Bit 16: Output Idle state 5 (OC5 output) */ #define ATIM_CR2_OIS6 (1 << 18) /* Bit 18: Output Idle state 6 (OC6 output) */ #define ATIM_CR2_MMS2_SHIFT (20) /* Bits 20-23: Master Mode Selection 2 */ #define ATIM_CR2_MMS2_MASK (15 << ATIM_CR2_MMS2_SHIFT) diff --git a/arch/arm/src/stm32f0l0g0/stm32_adc.c b/arch/arm/src/stm32f0l0g0/stm32_adc.c index 249cfdc629..c84a623dd8 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_adc.c +++ b/arch/arm/src/stm32f0l0g0/stm32_adc.c @@ -1038,7 +1038,7 @@ static void adc_calibrate(struct stm32_dev_s *priv) { /* Calibrate the ADC. * 1. ADC must be disabled - * 2. the voltage regulater must be enabled + * 2. the voltage regulator must be enabled */ adc_modifyreg(priv, STM32_ADC_CR_OFFSET, 0, ADC_CR_ADCAL); diff --git a/arch/arm/src/stm32f0l0g0/stm32_dma_v1.c b/arch/arm/src/stm32f0l0g0/stm32_dma_v1.c index 6197ffb676..24c7542f81 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_dma_v1.c +++ b/arch/arm/src/stm32f0l0g0/stm32_dma_v1.c @@ -532,7 +532,7 @@ void stm32_dmastart(DMA_HANDLE handle, dma_callback_t callback, DEBUGASSERT(handle != NULL); - /* Save the callback info. This will be invoked whent the DMA completes */ + /* Save the callback info. This will be invoked when the DMA completes. */ dmach->callback = callback; dmach->arg = arg; diff --git a/arch/arm/src/stm32f0l0g0/stm32_hsi48.c b/arch/arm/src/stm32f0l0g0/stm32_hsi48.c index 38513476eb..17bddd7eb0 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_hsi48.c +++ b/arch/arm/src/stm32f0l0g0/stm32_hsi48.c @@ -72,7 +72,7 @@ * frequency which is subject to manufacturing process variations. * * Input Parameters: - * Identifies the syncrhonization source for the HSI48. When used as the + * Identifies the synchronization source for the HSI48. When used as the * USB source clock, this must be set to SYNCSRC_USB. * * Returned Value: diff --git a/arch/arm/src/stm32f0l0g0/stm32_hsi48.h b/arch/arm/src/stm32f0l0g0/stm32_hsi48.h index cc1bc064ce..37a6981ff5 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_hsi48.h +++ b/arch/arm/src/stm32f0l0g0/stm32_hsi48.h @@ -66,7 +66,7 @@ enum syncsrc_e * frequency which is subject to manufacturing process variations. * * Input Parameters: - * Identifies the syncrhonization source for the HSI48. When used as the + * Identifies the synchronization source for the HSI48. When used as the * USB source clock, this must be set to SYNCSRC_USB. * * Returned Value: diff --git a/arch/arm/src/stm32f0l0g0/stm32_i2c.c b/arch/arm/src/stm32f0l0g0/stm32_i2c.c index 93ba0f2f4c..dc477f4dab 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_i2c.c +++ b/arch/arm/src/stm32f0l0g0/stm32_i2c.c @@ -2606,7 +2606,7 @@ static int stm32_i2c_reset(struct i2c_master_s *dev) out: - /* Release the port for re-use by other clients */ + /* Release the port for reuse by other clients */ nxmutex_unlock(&priv->lock); return ret; diff --git a/arch/arm/src/stm32f0l0g0/stm32_pwm.c b/arch/arm/src/stm32f0l0g0/stm32_pwm.c index 207e0472db..c22229a3da 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_pwm.c +++ b/arch/arm/src/stm32f0l0g0/stm32_pwm.c @@ -4,7 +4,7 @@ * SPDX-License-Identifier: BSD-3-Clause * SPDX-FileCopyrightText: 2019 Fundação CERTI. All rights reserved. * SPDX-FileContributor: Daniel Pereira Volpato - * SPDX-FileContributor: Guillherme da Silva amaral + * SPDX-FileContributor: Guillherme da Silva Amaral * SPDX-FileContributor: Gregory Nutt * SPDX-FileContributor: Paul Alexander Patience * SPDX-FileContributor: Mateusz Szafoni diff --git a/arch/arm/src/stm32f0l0g0/stm32_serial_v1.c b/arch/arm/src/stm32f0l0g0/stm32_serial_v1.c index 209881cf00..36febad423 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_serial_v1.c +++ b/arch/arm/src/stm32f0l0g0/stm32_serial_v1.c @@ -2409,7 +2409,7 @@ static int stm32serial_pmprepare(struct pm_callback_s *cb, int domain, * * Description: * Performs the low level USART initialization early in debug so that the - * serial console will be available during bootup. This must be called + * serial console will be available during boot up. This must be called * before stm32serial_getregit. * ****************************************************************************/ diff --git a/arch/arm/src/stm32f0l0g0/stm32_serial_v2.c b/arch/arm/src/stm32f0l0g0/stm32_serial_v2.c index 6f439dffbc..668ab919dd 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_serial_v2.c +++ b/arch/arm/src/stm32f0l0g0/stm32_serial_v2.c @@ -1903,7 +1903,7 @@ uart_dev_t *stm32_serial_get_uart(int uart_num) * * Description: * Performs the low level USART initialization early in debug so that the - * serial console will be available during bootup. This must be called + * serial console will be available during boot up. This must be called * before arm_serialinit. * ****************************************************************************/ diff --git a/arch/arm/src/stm32f7/hardware/stm32_sai.h b/arch/arm/src/stm32f7/hardware/stm32_sai.h index 1256f90385..c71d7adc87 100644 --- a/arch/arm/src/stm32f7/hardware/stm32_sai.h +++ b/arch/arm/src/stm32f7/hardware/stm32_sai.h @@ -142,7 +142,7 @@ #define SAI_CR1_SYNCEN_MASK (3 << SAI_CR1_SYNCEN_SHIFT) # define SAI_CR1_SYNCEN_ASYNCH (0 << SAI_CR1_SYNCEN_SHIFT) /* Asynchronous mode */ # define SAI_CR1_SYNCEN_INTERNAL (1 << SAI_CR1_SYNCEN_SHIFT) /* Synchronous with other internal sub-block */ -# define SAI_CR1_SYNCEN_EXTERNAL (2 << SAI_CR1_SYNCEN_SHIFT) /* Aynchronous with external SAI peripheral */ +# define SAI_CR1_SYNCEN_EXTERNAL (2 << SAI_CR1_SYNCEN_SHIFT) /* Asynchronous with external SAI peripheral */ #define SAI_CR1_MONO (1 << 12) /* Bit 12: Mono mode */ #define SAI_CR1_OUTDRIV (1 << 13) /* Bit 13: Output drive */ diff --git a/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_tim.h b/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_tim.h index ef7f48b9b2..d9d897fe1e 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_tim.h +++ b/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_tim.h @@ -400,7 +400,7 @@ #define ATIM_CR2_OIS3 (1 << 12) /* Bit 12: Output Idle state 3 (OC3 output) */ #define ATIM_CR2_OIS3N (1 << 13) /* Bit 13: Output Idle state 3 (OC3N output) */ #define ATIM_CR2_OIS4 (1 << 14) /* Bit 14: Output Idle state 4 (OC4 output) */ -#define ATIM_CR2_OIS5 (1 << 16) /* Bit 16: OOutput Idle state 5 (OC5 output) */ +#define ATIM_CR2_OIS5 (1 << 16) /* Bit 16: Output Idle state 5 (OC5 output) */ #define ATIM_CR2_OIS6 (1 << 18) /* Bit 18: Output Idle state 6 (OC6 output) */ #define ATIM_CR2_MMS2_SHIFT (20) /* Bits 20-23: Master Mode Selection 2 */ #define ATIM_CR2_MMS2_MASK (15 << ATIM_CR2_MMS2_SHIFT) diff --git a/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_tim.h b/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_tim.h index 7499edcbef..44bea32690 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_tim.h +++ b/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_tim.h @@ -400,7 +400,7 @@ #define ATIM_CR2_OIS3 (1 << 12) /* Bit 12: Output Idle state 3 (OC3 output) */ #define ATIM_CR2_OIS3N (1 << 13) /* Bit 13: Output Idle state 3 (OC3N output) */ #define ATIM_CR2_OIS4 (1 << 14) /* Bit 14: Output Idle state 4 (OC4 output) */ -#define ATIM_CR2_OIS5 (1 << 16) /* Bit 16: OOutput Idle state 5 (OC5 output) */ +#define ATIM_CR2_OIS5 (1 << 16) /* Bit 16: Output Idle state 5 (OC5 output) */ #define ATIM_CR2_OIS6 (1 << 18) /* Bit 18: Output Idle state 6 (OC6 output) */ #define ATIM_CR2_MMS2_SHIFT (20) /* Bits 20-23: Master Mode Selection 2 */ #define ATIM_CR2_MMS2_MASK (15 << ATIM_CR2_MMS2_SHIFT) diff --git a/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_tim.h b/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_tim.h index f46bec4920..fc2fa7bec8 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_tim.h +++ b/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_tim.h @@ -406,7 +406,7 @@ #define ATIM_CR2_OIS3 (1 << 12) /* Bit 12: Output Idle state 3 (OC3 output) */ #define ATIM_CR2_OIS3N (1 << 13) /* Bit 13: Output Idle state 3 (OC3N output) */ #define ATIM_CR2_OIS4 (1 << 14) /* Bit 14: Output Idle state 4 (OC4 output) */ -#define ATIM_CR2_OIS5 (1 << 16) /* Bit 16: OOutput Idle state 5 (OC5 output) */ +#define ATIM_CR2_OIS5 (1 << 16) /* Bit 16: Output Idle state 5 (OC5 output) */ #define ATIM_CR2_OIS6 (1 << 18) /* Bit 18: Output Idle state 6 (OC6 output) */ #define ATIM_CR2_MMS2_SHIFT (20) /* Bits 20-23: Master Mode Selection 2 */ #define ATIM_CR2_MMS2_MASK (15 << ATIM_CR2_MMS2_SHIFT) diff --git a/arch/arm/src/stm32f7/stm32_dma2d.c b/arch/arm/src/stm32f7/stm32_dma2d.c index eacfe7460c..0c65135b8f 100644 --- a/arch/arm/src/stm32f7/stm32_dma2d.c +++ b/arch/arm/src/stm32f7/stm32_dma2d.c @@ -69,7 +69,7 @@ STM32_DMA2D_CR_MODE_BLEND | \ STM32_DMA2D_CR_MODE_COLOR -/* Only 8 bit per pixel overal supported */ +/* Only 8 bit per pixel overall supported */ #define DMA2D_PF_BYPP(n) ((n) / 8) diff --git a/arch/arm/src/stm32f7/stm32_ethernet.c b/arch/arm/src/stm32f7/stm32_ethernet.c index ade5283d1b..90ba62ab81 100644 --- a/arch/arm/src/stm32f7/stm32_ethernet.c +++ b/arch/arm/src/stm32f7/stm32_ethernet.c @@ -1572,7 +1572,7 @@ static int stm32_recvframe(struct stm32_ethmac_s *priv) * 3) All of the TX descriptors are in flight. * * This last case is obscure. It is due to that fact that each packet - * that we receive can generate an unstoppable transmisson. So we have + * that we receive can generate an unstoppable transmission. So we have * to stop receiving when we can not longer transmit. In this case, the * transmit logic should also have disabled further RX interrupts. */ @@ -1858,7 +1858,7 @@ static void stm32_receive(struct stm32_ethmac_s *priv) } /* We are finished with the RX buffer. NOTE: If the buffer is - * re-used for transmission, the dev->d_buf field will have been + * reused for transmission, the dev->d_buf field will have been * nullified. */ @@ -3934,7 +3934,7 @@ int stm32_ethinitialize(int intf) stm32_get_uniqueid(uid); crc = crc64(uid, 12); - /* Specify as localy administrated address */ + /* Specify as locally administrated address */ priv->dev.d_mac.ether.ether_addr_octet[0] = (crc >> 0) | 0x02; priv->dev.d_mac.ether.ether_addr_octet[0] &= ~0x1; diff --git a/arch/arm/src/stm32f7/stm32_i2c.c b/arch/arm/src/stm32f7/stm32_i2c.c index ca4b3b2e9d..51e31253eb 100644 --- a/arch/arm/src/stm32f7/stm32_i2c.c +++ b/arch/arm/src/stm32f7/stm32_i2c.c @@ -2640,7 +2640,7 @@ static int stm32_i2c_reset(struct i2c_master_s *dev) out: - /* Release the port for re-use by other clients */ + /* Release the port for reuse by other clients */ nxmutex_unlock(&priv->lock); return ret; diff --git a/arch/arm/src/stm32f7/stm32_i2s.c b/arch/arm/src/stm32f7/stm32_i2s.c index 928e8466fa..5ce102916b 100644 --- a/arch/arm/src/stm32f7/stm32_i2s.c +++ b/arch/arm/src/stm32f7/stm32_i2s.c @@ -516,7 +516,7 @@ static const struct i2s_ops_s g_i2sops = * * Returned Value: * true: This is the first register access of this type. - * flase: This is the same as the preceding register access. + * false: This is the same as the preceding register access. * ****************************************************************************/ diff --git a/arch/arm/src/stm32f7/stm32_ltdc.c b/arch/arm/src/stm32f7/stm32_ltdc.c index ed0c7dd2f3..24d0f52eba 100644 --- a/arch/arm/src/stm32f7/stm32_ltdc.c +++ b/arch/arm/src/stm32f7/stm32_ltdc.c @@ -206,7 +206,7 @@ # error Undefined or unrecognized base resolution #endif -/* LTDC only supports 8 bit per pixel overal */ +/* LTDC only supports 8 bit per pixel overall */ #define STM32_LTDC_LX_BYPP(n) ((n) / 8) @@ -665,7 +665,7 @@ struct stm32_interrupt_s * Private Function Prototypes ****************************************************************************/ -/* Overal LTDC helper */ +/* Overall LTDC helper */ static void stm32_ltdc_enable(bool enable); static void stm32_ltdc_gpioconfig(void); diff --git a/arch/arm/src/stm32f7/stm32_otgdev.c b/arch/arm/src/stm32f7/stm32_otgdev.c index fd094c8fbe..e29e88005c 100644 --- a/arch/arm/src/stm32f7/stm32_otgdev.c +++ b/arch/arm/src/stm32f7/stm32_otgdev.c @@ -2229,8 +2229,8 @@ static inline void stm32_ep0out_testmode(struct stm32_usbdev_s *priv, * Name: stm32_ep0out_stdrequest * * Description: - * Handle a stanard request on EP0. Pick off the things of interest to the - * USB device controller driver; pass what is left to the class driver. + * Handle a standard request on EP0. Pick off the things of interest to + * the USB device controller driver; pass what is left to the class driver. * ****************************************************************************/ @@ -5757,7 +5757,7 @@ void arm_usbinitialize(void) arm_usbuninitialize(); - /* Initialie the driver data structure */ + /* Initialize the driver data structure */ stm32_swinitialize(priv); diff --git a/arch/arm/src/stm32f7/stm32_otghost.c b/arch/arm/src/stm32f7/stm32_otghost.c index 5c7c67783d..58d6139219 100644 --- a/arch/arm/src/stm32f7/stm32_otghost.c +++ b/arch/arm/src/stm32f7/stm32_otghost.c @@ -2759,7 +2759,7 @@ static inline void stm32_gint_hcoutisr(struct stm32_usbhost_s *priv, else if ((pending & OTG_HCINT_STALL) != 0) { - /* Clear the pending the STALL response receiv (STALL) interrupt */ + /* Clear the pending STALL response receive (STALL) interrupt */ stm32_putreg(STM32_OTG_HCINT(chidx), OTG_HCINT_STALL); diff --git a/arch/arm/src/stm32f7/stm32_pwm.c b/arch/arm/src/stm32f7/stm32_pwm.c index b8e131702e..9bcfd510af 100644 --- a/arch/arm/src/stm32f7/stm32_pwm.c +++ b/arch/arm/src/stm32f7/stm32_pwm.c @@ -2535,7 +2535,7 @@ static int pwm_outputs_enable(struct pwm_lowerhalf_s *dev, uint32_t ccer = 0; uint32_t regval = 0; - /* Get curren register state */ + /* Get current register state */ ccer = pwm_getreg(priv, STM32_GTIM_CCER_OFFSET); @@ -2556,7 +2556,7 @@ static int pwm_outputs_enable(struct pwm_lowerhalf_s *dev, if (state == true) { - /* Enable outpus - set bits */ + /* Enable outputs - set bits */ ccer |= regval; } @@ -2619,7 +2619,7 @@ errout: * Name: pwm_trgo_configure * * Description: - * Confiugre an output synchronisation event for PWM timer (TRGO/TRGO2) + * Configure an output synchronisation event for PWM timer (TRGO/TRGO2) * ****************************************************************************/ @@ -2720,7 +2720,7 @@ static uint16_t pwm_outputs_from_channels(struct stm32_pwmtimer_s *priv) if (channel != 0) { - /* Enable output if confiugred */ + /* Enable output if configured */ if (priv->channels[i].out1.in_use == 1) { diff --git a/arch/arm/src/stm32f7/stm32_sai.c b/arch/arm/src/stm32f7/stm32_sai.c index ca7126347f..fbf25984db 100644 --- a/arch/arm/src/stm32f7/stm32_sai.c +++ b/arch/arm/src/stm32f7/stm32_sai.c @@ -622,8 +622,8 @@ static void sai_dump_regs(struct stm32f7_sai_s *priv, const char *msg) uint32_t cpl = cr2 & SAI_CR2_CPL; i2sinfo("\t\tCR2: CPL[13] = %s\n", - cpl ? "1's complement represention" - : "2's complement represention"); + cpl ? "1's complement representation" + : "2's complement representation"); uint32_t comp = (cr2 & SAI_CR2_COMP_MASK) >> SAI_CR2_COMP_SHIFT; const char *comp_string[] = { "No companding algorithm", diff --git a/arch/arm/src/stm32f7/stm32_sdmmc.c b/arch/arm/src/stm32f7/stm32_sdmmc.c index cc45433146..0a6e07163e 100644 --- a/arch/arm/src/stm32f7/stm32_sdmmc.c +++ b/arch/arm/src/stm32f7/stm32_sdmmc.c @@ -2447,7 +2447,7 @@ static int stm32_waitresponse(struct sdio_dev_s *dev, uint32_t cmd) * * Returned Value: * Number of bytes sent on success; a negated errno on failure. Here a - * failure means only a faiure to obtain the requested response (due to + * failure means only a failure to obtain the requested response (due to * transport problem -- timeout, CRC, etc.). The implementation only * assures that the response is returned intact and does not check errors * within the response itself. diff --git a/arch/arm/src/stm32f7/stm32_serial.c b/arch/arm/src/stm32f7/stm32_serial.c index aebcd705fb..153e6bc776 100644 --- a/arch/arm/src/stm32f7/stm32_serial.c +++ b/arch/arm/src/stm32f7/stm32_serial.c @@ -481,7 +481,7 @@ struct up_dev_s #ifdef SERIAL_HAVE_TXDMA const unsigned int txdma_channel; /* DMA channel assigned */ - DMA_HANDLE txdma; /* currently-open trasnmit DMA stream */ + DMA_HANDLE txdma; /* currently-open transmit DMA stream */ #endif /* RX DMA state */ @@ -3600,7 +3600,7 @@ static int up_pm_prepare(struct pm_callback_s *cb, int domain, * * Description: * Performs the low level USART initialization early in debug so that the - * serial console will be available during bootup. This must be called + * serial console will be available during boot up. This must be called * before arm_serialinit. * ****************************************************************************/ diff --git a/arch/arm/src/stm32f7/stm32f72xx73xx_rcc.c b/arch/arm/src/stm32f7/stm32f72xx73xx_rcc.c index 7137aadc42..7fc53e1e4d 100644 --- a/arch/arm/src/stm32f7/stm32f72xx73xx_rcc.c +++ b/arch/arm/src/stm32f7/stm32f72xx73xx_rcc.c @@ -794,7 +794,7 @@ static void stm32_stdclockconfig(void) /* Over-drive is needed if * - Voltage output scale 1 mode is selected and SYSCLK frequency is * over 180 MHz. - * - Voltage output scale 2 mode is selected and SYSCLK frequence is + * - Voltage output scale 2 mode is selected and SYSCLK frequency is * over 168 MHz. */ diff --git a/arch/arm/src/stm32f7/stm32f74xx75xx_rcc.c b/arch/arm/src/stm32f7/stm32f74xx75xx_rcc.c index f4a42c53b7..2720ae3867 100644 --- a/arch/arm/src/stm32f7/stm32f74xx75xx_rcc.c +++ b/arch/arm/src/stm32f7/stm32f74xx75xx_rcc.c @@ -791,7 +791,7 @@ static void stm32_stdclockconfig(void) /* Over-drive is needed if * - Voltage output scale 1 mode is selected and SYSCLK frequency is * over 180 MHz. - * - Voltage output scale 2 mode is selected and SYSCLK frequence is + * - Voltage output scale 2 mode is selected and SYSCLK frequency is * over 168 MHz. */ diff --git a/arch/arm/src/stm32f7/stm32f76xx77xx_rcc.c b/arch/arm/src/stm32f7/stm32f76xx77xx_rcc.c index 4771020fd4..ad7c70c816 100644 --- a/arch/arm/src/stm32f7/stm32f76xx77xx_rcc.c +++ b/arch/arm/src/stm32f7/stm32f76xx77xx_rcc.c @@ -809,7 +809,7 @@ static void stm32_stdclockconfig(void) /* Over-drive is needed if * - Voltage output scale 1 mode is selected and SYSCLK frequency is * over 180 MHz. - * - Voltage output scale 2 mode is selected and SYSCLK frequence is + * - Voltage output scale 2 mode is selected and SYSCLK frequency is * over 168 MHz. */ diff --git a/arch/arm/src/stm32h5/Kconfig b/arch/arm/src/stm32h5/Kconfig index 34f79872c1..b348a77668 100644 --- a/arch/arm/src/stm32h5/Kconfig +++ b/arch/arm/src/stm32h5/Kconfig @@ -4827,7 +4827,7 @@ choice config STM32H5_FDCAN1_CLASSIC bool "Classic CAN" ---help--- - Enable Clasic CAN mode + Enable Classic CAN mode config STM32H5_FDCAN1_FD bool "CAN FD" @@ -4954,7 +4954,7 @@ choice config STM32H5_FDCAN2_CLASSIC bool "Classic CAN" ---help--- - Enable Clasic CAN mode + Enable Classic CAN mode config STM32H5_FDCAN2_FD bool "CAN FD" diff --git a/arch/arm/src/stm32h5/hardware/stm32_crs.h b/arch/arm/src/stm32h5/hardware/stm32_crs.h index 8c63e1cb87..2831acabe3 100644 --- a/arch/arm/src/stm32h5/hardware/stm32_crs.h +++ b/arch/arm/src/stm32h5/hardware/stm32_crs.h @@ -84,7 +84,7 @@ #define CRS_ISR_SYNCOKF (1 << 0) /* Bit 0: SYNC event OK flag */ #define CRS_ISR_SYNCWARNF (1 << 1) /* Bit 1: SYNC warning flag */ -#define CRS_ISR_ERRF (1 << 2) /* Bit 2: Errot flag */ +#define CRS_ISR_ERRF (1 << 2) /* Bit 2: Error flag */ #define CRS_ISR_ESYNCF (1 << 3) /* Bit 3: Expected SYNC flag */ #define CRS_ISR_SYNCERR (1 << 8) /* Bit 8: SYNC error */ #define CRS_ISR_SYNCMISS (1 << 9) /* Bit 9: SYNC missed */ diff --git a/arch/arm/src/stm32h5/hardware/stm32_tim.h b/arch/arm/src/stm32h5/hardware/stm32_tim.h index 2adf9d4770..0c169a1295 100644 --- a/arch/arm/src/stm32h5/hardware/stm32_tim.h +++ b/arch/arm/src/stm32h5/hardware/stm32_tim.h @@ -476,7 +476,7 @@ #define ATIM_CR2_OIS3N (1 << 13) /* Bit 13: Output Idle state 3 (OC3N output) */ #define ATIM_CR2_OIS4 (1 << 14) /* Bit 14: Output idle state 4 (OC4 output) */ #define ATIM_CR2_OIS4N (1 << 15) /* Bit 15: Output idle state 4 (OC4N output) */ -#define ATIM_CR2_OIS5 (1 << 16) /* Bit 16: OOutput Idle state 5 (OC5 output) */ +#define ATIM_CR2_OIS5 (1 << 16) /* Bit 16: Output Idle state 5 (OC5 output) */ #define ATIM_CR2_OIS6 (1 << 18) /* Bit 18: Output Idle state 6 (OC6 output) */ #define ATIM_CR2_MMS2_SHIFT (20) /* Bits 20-23: Master Mode Selection 2 */ #define ATIM_CR2_MMS2_MASK (15 << ATIM_CR2_MMS2_SHIFT) diff --git a/arch/arm/src/stm32h5/hardware/stm32h5xxx_rcc.h b/arch/arm/src/stm32h5/hardware/stm32h5xxx_rcc.h index 21615302b8..4f312333fd 100644 --- a/arch/arm/src/stm32h5/hardware/stm32h5xxx_rcc.h +++ b/arch/arm/src/stm32h5/hardware/stm32h5xxx_rcc.h @@ -598,7 +598,7 @@ #define RCC_AHB1ENR_GPDMA1EN (1 << 0) /* Bit 0: GPDMA1 clock enable */ #define RCC_AHB1ENR_GPDMA2EN (1 << 1) /* Bit 1: GPDMA2 clock enable */ -#define RCC_AHB1ENR_FLASHEN (1 << 8) /* Bit 8: Flash Interace clock enable */ +#define RCC_AHB1ENR_FLASHEN (1 << 8) /* Bit 8: Flash Interface clock enable */ #define RCC_AHB1ENR_CRCEN (1 << 12) /* Bit 12: CRC clock enable */ #define RCC_AHB1ENR_CORDICEN (1 << 14) /* Bit 14: CORDIC clock enable */ #define RCC_AHB1ENR_FMACEN (1 << 15) /* Bit 15: FMAC clock enable */ @@ -714,7 +714,7 @@ #define RCC_AHB1LPENR_GPDMA1LPEN (1 << 0) /* Bit 0: GPDMA1 clock enable during sleep mode */ #define RCC_AHB1LPENR_GPDMA2LPEN (1 << 1) /* Bit 1: GPDMA2 clock enable during sleep mode */ -#define RCC_AHB1LPENR_FLITFLPEN (1 << 8) /* Bit 8: Flash Interace clock enable during sleep mode */ +#define RCC_AHB1LPENR_FLITFLPEN (1 << 8) /* Bit 8: Flash Interface clock enable during sleep mode */ #define RCC_AHB1LPENR_CRCLPEN (1 << 12) /* Bit 12: CRC clock enable during sleep mode */ #define RCC_AHB1LPENR_CORDICLPEN (1 << 14) /* Bit 14: CORDIC clock enable during sleep mode */ #define RCC_AHB1LPENR_FMACLPEN (1 << 15) /* Bit 15: FMAC clock enable during sleep mode */ diff --git a/arch/arm/src/stm32h5/stm32_adc.c b/arch/arm/src/stm32h5/stm32_adc.c index 748723f352..0a8ab1f38c 100644 --- a/arch/arm/src/stm32h5/stm32_adc.c +++ b/arch/arm/src/stm32h5/stm32_adc.c @@ -1306,7 +1306,7 @@ static int adc_interrupt(struct adc_dev_s *dev, uint32_t adcisr) } while ((adc_getreg(priv, STM32_ADC_ISR_OFFSET) & ADC_INT_EOC) != 0); - /* We dont't add EOC to the bits to clear. It will cause a race + /* We don't add EOC to the bits to clear. It will cause a race * condition. EOC should only be cleared by reading the ADC_DR */ } diff --git a/arch/arm/src/stm32h5/stm32_ethernet.c b/arch/arm/src/stm32h5/stm32_ethernet.c index 41a88fb221..fbfdc2c3fb 100644 --- a/arch/arm/src/stm32h5/stm32_ethernet.c +++ b/arch/arm/src/stm32h5/stm32_ethernet.c @@ -1663,7 +1663,7 @@ static int stm32_recvframe(struct stm32_ethmac_s *priv) * 3) All of the TX descriptors are in flight. * * This last case is obscure. It is due to that fact that each packet - * that we receive can generate an unstoppable transmisson. So we have + * that we receive can generate an unstoppable transmission. So we have * to stop receiving when we can not longer transmit. In this case, the * transmit logic should also have disabled further RX interrupts. */ @@ -1969,7 +1969,7 @@ static void stm32_receive(struct stm32_ethmac_s *priv) } /* We are finished with the RX buffer. NOTE: If the buffer is - * re-used for transmission, the dev->d_buf field will have been + * reused for transmission, the dev->d_buf field will have been * nullified. */ @@ -4196,7 +4196,7 @@ static inline int stm32_ethinitialize(int intf) stm32_get_uniqueid(uid); crc = crc64(uid, 12); - /* Specify as localy administrated address */ + /* Specify as locally administrated address */ priv->dev.d_mac.ether.ether_addr_octet[0] = (crc >> 0) | 0x02; priv->dev.d_mac.ether.ether_addr_octet[0] &= ~0x1; diff --git a/arch/arm/src/stm32h5/stm32_fdcan.c b/arch/arm/src/stm32h5/stm32_fdcan.c index 2816d9b29c..48b78f343f 100644 --- a/arch/arm/src/stm32h5/stm32_fdcan.c +++ b/arch/arm/src/stm32h5/stm32_fdcan.c @@ -2265,7 +2265,7 @@ static int fdcan_send(struct can_dev_s *dev, struct can_msg_s *msg) * Format word T1: * Data Length Code (DLC) - Value from message structure * Bit Rate Switch (BRS) - Bit rate switching for CAN FD - * FD format (FDF) - Frame transmited in CAN FD format + * FD format (FDF) - Frame transmitted in CAN FD format * Event FIFO Control (EFC) - Do not store events. * Message Marker (MM) - Always zero */ @@ -2840,10 +2840,10 @@ static int fdcan_interrupt(int irq, void *context, void *arg) canerr("ERROR: Common %08" PRIx32 "\n", pending & FDCAN_CMNERR_INTS); - /* When a protocol error ocurrs, the problem is recorded in + /* When a protocol error occurs, the problem is recorded in * the LEC/DLEC fields of the PSR register. In lieu of - * seprate interrupt flags for each error, the hardware - * groups procotol errors under a single interrupt each for + * separate interrupt flags for each error, the hardware + * groups protocol errors under a single interrupt each for * arbitration and data phases. * * These errors have a tendency to flood the system with @@ -2858,7 +2858,7 @@ static int fdcan_interrupt(int irq, void *context, void *arg) canerr("ERROR: PSR %08" PRIx32 "\n", psr); ie &= ~(FDCAN_INT_PEA | FDCAN_INT_PED); fdcan_putreg(priv, STM32_FDCAN_IE_OFFSET, ie); - caninfo("disabled protocol error intterupts\n"); + caninfo("disabled protocol error interrupts\n"); } /* Clear the error indications */ @@ -2933,7 +2933,7 @@ static int fdcan_interrupt(int irq, void *context, void *arg) { ie |= (FDCAN_INT_PEA | FDCAN_INT_PED); fdcan_putreg(priv, STM32_FDCAN_IE_OFFSET, ie); - caninfo("Renabled protocol error intterupts\n"); + caninfo("Re-enabled protocol error interrupts\n"); } /* Clear the pending TX completion interrupt (and all @@ -3102,7 +3102,7 @@ static int fdcan_hw_initialize(struct stm32_fdcan_s *priv) stm32_configgpio(config->rxpinset); stm32_configgpio(config->txpinset); - /* Renable device if previosuly disabled in fdcan_shutdown() */ + /* Re-enable device if previously disabled in fdcan_shutdown() */ if (priv->state == FDCAN_STATE_DISABLED) { diff --git a/arch/arm/src/stm32h5/stm32_hsi48.c b/arch/arm/src/stm32h5/stm32_hsi48.c index 7aa4a08fda..7ad06b8491 100644 --- a/arch/arm/src/stm32h5/stm32_hsi48.c +++ b/arch/arm/src/stm32h5/stm32_hsi48.c @@ -57,7 +57,7 @@ * frequency which is subject to manufacturing process variations. * * Input Parameters: - * Identifies the syncrhonization source for the HSI48. When used as the + * Identifies the synchronization source for the HSI48. When used as the * USB source clock, this must be set to SYNCSRC_USB. * * Returned Value: diff --git a/arch/arm/src/stm32h5/stm32_hsi48.h b/arch/arm/src/stm32h5/stm32_hsi48.h index 6d931f539e..458a27f6aa 100644 --- a/arch/arm/src/stm32h5/stm32_hsi48.h +++ b/arch/arm/src/stm32h5/stm32_hsi48.h @@ -66,7 +66,7 @@ enum syncsrc_e * frequency which is subject to manufacturing process variations. * * Input Parameters: - * Identifies the syncrhonization source for the HSI48. When used as the + * Identifies the synchronization source for the HSI48. When used as the * USB source clock, this must be set to SYNCSRC_USB. * * Returned Value: diff --git a/arch/arm/src/stm32h5/stm32_i2c.c b/arch/arm/src/stm32h5/stm32_i2c.c index 94573e3e66..55975c646f 100644 --- a/arch/arm/src/stm32h5/stm32_i2c.c +++ b/arch/arm/src/stm32h5/stm32_i2c.c @@ -1234,7 +1234,7 @@ static void stm32_i2c_setclock(struct stm32_i2c_priv_s *priv, if (frequency != priv->frequency) { /* Set timing specs based on i2c frequency - * Specifications pulled from secion 6.1 in + * Specifications pulled from section 6.1 in * UM10204 (NXP I2C Spec). Time in nanoseconds. */ @@ -1448,7 +1448,7 @@ static void stm32_i2c_setclock(struct stm32_i2c_priv_s *priv, /* Note: It is possible to exit this loop with invalid settings when * using an improper i2c_ker_ck. Choose i2c_ker_ck wisely. - * Addtionally, take care setting the digital and analog filters. + * Additionally, take care setting the digital and analog filters. */ /* I2C peripheral must be disabled to update clocking configuration. @@ -2915,7 +2915,7 @@ static int stm32_i2c_reset(struct i2c_master_s *dev) out: - /* Release the port for re-use by other clients */ + /* Release the port for reuse by other clients */ nxmutex_unlock(&priv->lock); return ret; diff --git a/arch/arm/src/stm32h5/stm32_serial.c b/arch/arm/src/stm32h5/stm32_serial.c index 88e8d98352..c27d9b7567 100644 --- a/arch/arm/src/stm32h5/stm32_serial.c +++ b/arch/arm/src/stm32h5/stm32_serial.c @@ -3692,7 +3692,7 @@ static int stm32serial_pmprepare(struct pm_callback_s *cb, int domain, * * Description: * Performs the low level USART initialization early in debug so that the - * serial console will be available during bootup. This must be called + * serial console will be available during boot up. This must be called * before arm_serialinit. * ****************************************************************************/ diff --git a/arch/arm/src/stm32h7/Kconfig b/arch/arm/src/stm32h7/Kconfig index 5e92defbd4..a0b9f60c26 100644 --- a/arch/arm/src/stm32h7/Kconfig +++ b/arch/arm/src/stm32h7/Kconfig @@ -314,11 +314,11 @@ choice default STM32H7_PWR_DEFAULT_SUPPLY depends on STM32H7_HAVE_SMPS && !STM32H7_HAVE_PWR_DIRECT_SMPS_SUPPLY ---help--- - The STM32H7x5 and STM32H7x7 support power supply configrations for the VCORE core domain and an external supply, + The STM32H7x5 and STM32H7x7 support power supply configurations for the VCORE core domain and an external supply, by configuring the SMPS step-down converter and voltage regulator. Note:The SMPS step-down converter is not available on all packages. - Currenlty the only supported modes are Direct SMPS supply and LDO supply. + Currently the only supported modes are Direct SMPS supply and LDO supply. config STM32H7_PWR_DEFAULT_SUPPLY bool "Default" diff --git a/arch/arm/src/stm32h7/hardware/stm32_dac.h b/arch/arm/src/stm32h7/hardware/stm32_dac.h index 563a0557af..ba4a7dc199 100644 --- a/arch/arm/src/stm32h7/hardware/stm32_dac.h +++ b/arch/arm/src/stm32h7/hardware/stm32_dac.h @@ -39,15 +39,15 @@ #define STM32_DAC1_CR_OFFSET 0x0000 /* control register */ #define STM32_DAC1_SWTRGR_OFFSET 0x0004 /* software trigger register */ -#define STM32_DAC1_DHR12R1_OFFSET 0x0008 /* ch1 12-bit right alinged data hold register */ -#define STM32_DAC1_DHR12L1_OFFSET 0x000C /* ch1 12-bit left alinged data hold register */ -#define STM32_DAC1_DHR8R1_OFFSET 0x0010 /* ch1 8-bit right alinged data hold register */ -#define STM32_DAC1_DHR12R2_OFFSET 0x0014 /* ch2 12-bit right alinged data hold register */ -#define STM32_DAC1_DHR12L2_OFFSET 0x0018 /* ch2 12-bit left alinged data hold register */ -#define STM32_DAC1_DHR8R2_OFFSET 0x001C /* ch2 8-bit right alinged data hold register */ -#define STM32_DAC1_DHR12RD_OFFSET 0x0020 /* dual 12-bit right alinged data hold register */ -#define STM32_DAC1_DHR12LD_OFFSET 0x0024 /* dual 2 12-bit left alinged data hold register */ -#define STM32_DAC1_DHR8RD_OFFSET 0x0028 /* dual 2 8-bit right alinged data hold register */ +#define STM32_DAC1_DHR12R1_OFFSET 0x0008 /* ch1 12-bit right aligned data hold register */ +#define STM32_DAC1_DHR12L1_OFFSET 0x000C /* ch1 12-bit left aligned data hold register */ +#define STM32_DAC1_DHR8R1_OFFSET 0x0010 /* ch1 8-bit right aligned data hold register */ +#define STM32_DAC1_DHR12R2_OFFSET 0x0014 /* ch2 12-bit right aligned data hold register */ +#define STM32_DAC1_DHR12L2_OFFSET 0x0018 /* ch2 12-bit left aligned data hold register */ +#define STM32_DAC1_DHR8R2_OFFSET 0x001C /* ch2 8-bit right aligned data hold register */ +#define STM32_DAC1_DHR12RD_OFFSET 0x0020 /* dual 12-bit right aligned data hold register */ +#define STM32_DAC1_DHR12LD_OFFSET 0x0024 /* dual 2 12-bit left aligned data hold register */ +#define STM32_DAC1_DHR8RD_OFFSET 0x0028 /* dual 2 8-bit right aligned data hold register */ #define STM32_DAC1_DOR1_OFFSET 0x002C /* ch1 data output register */ #define STM32_DAC1_DOR2_OFFSET 0x0030 /* ch2 data output register */ #define STM32_DAC1_SR_OFFSET 0x0034 /* status register */ @@ -87,7 +87,7 @@ #define DAC_CR_EN1 (1 << 0) /* Bit 0: ch1 enable */ #define DAC_CR_TEN1 (1 << 1) /* Bit 1: ch1 trigger enable */ -#define DAC_CR_TSEL1_SHIFT (1 << 2) /* Bits 5-2: ch1 triger sel */ +#define DAC_CR_TSEL1_SHIFT (1 << 2) /* Bits 5-2: ch1 trigger sel */ #define DAC_CR_TSEL1_MASK (15 << DAC_CR_TSEL1_SHIFT) #define DAC_CR_WAVE1_SHIFT (1 << 6) /* Bits 7-6: ch1 wave enable */ #define DAC_CR_WAVE1_MASK (3 << DAC_CR_WAVE1_SHIFT) @@ -98,7 +98,7 @@ #define DAC_CR_CEN1 (1 << 14) /* Bit 14: ch1 calibration enable */ #define DAC_CR_EN2 (1 << 16) /* Bit 16: ch2 enable */ #define DAC_CR_TEN2 (1 << 17) /* Bit 17: ch2 trigger enable */ -#define DAC_CR_TSEL2_SHIFT (1 << 18) /* Bits 28-21: ch2 triger sel */ +#define DAC_CR_TSEL2_SHIFT (1 << 18) /* Bits 28-21: ch2 trigger sel */ #define DAC_CR_TSEL2_MASK (15 << DAC_CR_TSEL2_SHIFT) #define DAC_CR_WAVE2_SHIFT (1 << 22) /* Bits 23-22: ch2 wave enable */ #define DAC_CR_WAVE2_MASK (3 << DAC_CR_WAVE2_SHIFT) diff --git a/arch/arm/src/stm32h7/hardware/stm32_fdcan.h b/arch/arm/src/stm32h7/hardware/stm32_fdcan.h index da076a81a8..0af9a42fcc 100644 --- a/arch/arm/src/stm32h7/hardware/stm32_fdcan.h +++ b/arch/arm/src/stm32h7/hardware/stm32_fdcan.h @@ -204,7 +204,7 @@ /* *************** Bit definition for FDCAN_ENDN register *****************/ #define FDCAN_ENDN_ETV_SHIFT (0U) #define FDCAN_ENDN_ETV_MASK (0xFFFFFFFFU << FDCAN_ENDN_ETV_SHIFT) /* 0xFFFFFFFF */ -#define FDCAN_ENDN_ETV FDCAN_ENDN_ETV_MASK /* Endiannes Test Value */ +#define FDCAN_ENDN_ETV FDCAN_ENDN_ETV_MASK /* Endianness Test Value */ /* *************** Bit definition for FDCAN_DBTP register *****************/ #define FDCAN_DBTP_DSJW_SHIFT (0U) diff --git a/arch/arm/src/stm32h7/hardware/stm32_tim.h b/arch/arm/src/stm32h7/hardware/stm32_tim.h index b360f7cf9c..d50bedadd0 100644 --- a/arch/arm/src/stm32h7/hardware/stm32_tim.h +++ b/arch/arm/src/stm32h7/hardware/stm32_tim.h @@ -423,7 +423,7 @@ #define ATIM_CR2_OIS3 (1 << 12) /* Bit 12: Output Idle state 3 (OC3 output) */ #define ATIM_CR2_OIS3N (1 << 13) /* Bit 13: Output Idle state 3 (OC3N output) */ #define ATIM_CR2_OIS4 (1 << 14) /* Bit 14: Output Idle state 4 (OC4 output) */ -#define ATIM_CR2_OIS5 (1 << 16) /* Bit 16: OOutput Idle state 5 (OC5 output) */ +#define ATIM_CR2_OIS5 (1 << 16) /* Bit 16: Output Idle state 5 (OC5 output) */ #define ATIM_CR2_OIS6 (1 << 18) /* Bit 18: Output Idle state 6 (OC6 output) */ #define ATIM_CR2_MMS2_SHIFT (20) /* Bits 20-23: Master Mode Selection 2 */ #define ATIM_CR2_MMS2_MASK (15 << ATIM_CR2_MMS2_SHIFT) diff --git a/arch/arm/src/stm32h7/stm32_adc.c b/arch/arm/src/stm32h7/stm32_adc.c index 0e9f664bba..61cba49fa9 100644 --- a/arch/arm/src/stm32h7/stm32_adc.c +++ b/arch/arm/src/stm32h7/stm32_adc.c @@ -2107,7 +2107,7 @@ static int adc_interrupt(struct adc_dev_s *dev, uint32_t adcisr) } while ((adc_getreg(priv, STM32_ADC_ISR_OFFSET) & ADC_INT_EOC) != 0); - /* We dont't add EOC to the bits to clear. It will cause a race + /* We don't add EOC to the bits to clear. It will cause a race * condition. EOC should only be cleared by reading the ADC_DR */ } diff --git a/arch/arm/src/stm32h7/stm32_ethernet.c b/arch/arm/src/stm32h7/stm32_ethernet.c index 476a5fb3ea..088a88638d 100644 --- a/arch/arm/src/stm32h7/stm32_ethernet.c +++ b/arch/arm/src/stm32h7/stm32_ethernet.c @@ -1722,7 +1722,7 @@ static int stm32_recvframe(struct stm32_ethmac_s *priv) * 3) All of the TX descriptors are in flight. * * This last case is obscure. It is due to that fact that each packet - * that we receive can generate an unstoppable transmisson. So we have + * that we receive can generate an unstoppable transmission. So we have * to stop receiving when we can not longer transmit. In this case, the * transmit logic should also have disabled further RX interrupts. */ @@ -2028,7 +2028,7 @@ static void stm32_receive(struct stm32_ethmac_s *priv) } /* We are finished with the RX buffer. NOTE: If the buffer is - * re-used for transmission, the dev->d_buf field will have been + * reused for transmission, the dev->d_buf field will have been * nullified. */ @@ -4291,7 +4291,7 @@ static inline int stm32_ethinitialize(int intf) stm32_get_uniqueid(uid); crc = crc64(uid, 12); - /* Specify as localy administrated address */ + /* Specify as locally administrated address */ priv->dev.d_mac.ether.ether_addr_octet[0] = (crc >> 0) | 0x02; priv->dev.d_mac.ether.ether_addr_octet[0] &= ~0x1; diff --git a/arch/arm/src/stm32h7/stm32_fdcan_sock.c b/arch/arm/src/stm32h7/stm32_fdcan_sock.c index f5455829da..5d3561dd0e 100644 --- a/arch/arm/src/stm32h7/stm32_fdcan_sock.c +++ b/arch/arm/src/stm32h7/stm32_fdcan_sock.c @@ -2616,10 +2616,10 @@ static void fdcan_error_work(void *arg) if ((pending & FDCAN_CMNERR_INTS) != 0) { - /* When a protocol error ocurrs, the problem is recorded in + /* When a protocol error occurs, the problem is recorded in * the LEC/DLEC fields of the PSR register. In lieu of - * seprate interrupt flags for each error, the hardware - * groups procotol errors under a single interrupt each for + * separate interrupt flags for each error, the hardware + * groups protocol errors under a single interrupt each for * arbitration and data phases. * * These errors have a tendency to flood the system with diff --git a/arch/arm/src/stm32h7/stm32_i2c.c b/arch/arm/src/stm32h7/stm32_i2c.c index 9f96a33e53..7f1ecdae4d 100644 --- a/arch/arm/src/stm32h7/stm32_i2c.c +++ b/arch/arm/src/stm32h7/stm32_i2c.c @@ -2614,7 +2614,7 @@ static int stm32_i2c_reset(struct i2c_master_s *dev) out: - /* Release the port for re-use by other clients */ + /* Release the port for reuse by other clients */ nxmutex_unlock(&priv->lock); return ret; diff --git a/arch/arm/src/stm32h7/stm32_ltdc.c b/arch/arm/src/stm32h7/stm32_ltdc.c index 7654d0d014..5209f28f9c 100644 --- a/arch/arm/src/stm32h7/stm32_ltdc.c +++ b/arch/arm/src/stm32h7/stm32_ltdc.c @@ -204,7 +204,7 @@ # error Undefined or unrecognized base resolution #endif -/* LTDC only supports 8 bit per pixel overal */ +/* LTDC only supports 8 bit per pixel overall */ #define STM32_LTDC_LX_BYPP(n) ((n) / 8) @@ -671,7 +671,7 @@ struct stm32_interrupt_s * Private Function Prototypes ****************************************************************************/ -/* Overal LTDC helper */ +/* Overall LTDC helper */ static void stm32_ltdc_enable(bool enable); static void stm32_ltdc_gpioconfig(void); diff --git a/arch/arm/src/stm32h7/stm32_otgdev.c b/arch/arm/src/stm32h7/stm32_otgdev.c index 90b57cd979..fad27fdc5f 100644 --- a/arch/arm/src/stm32h7/stm32_otgdev.c +++ b/arch/arm/src/stm32h7/stm32_otgdev.c @@ -2205,8 +2205,8 @@ static inline void stm32_ep0out_testmode(struct stm32_usbdev_s *priv, * Name: stm32_ep0out_stdrequest * * Description: - * Handle a stanard request on EP0. Pick off the things of interest to the - * USB device controller driver; pass what is left to the class driver. + * Handle a standard request on EP0. Pick off the things of interest to + * the USB device controller driver; pass what is left to the class driver. * ****************************************************************************/ @@ -5705,7 +5705,7 @@ void arm_usbinitialize(void) arm_usbuninitialize(); - /* Initialie the driver data structure */ + /* Initialize the driver data structure */ stm32_swinitialize(priv); diff --git a/arch/arm/src/stm32h7/stm32_otghost.c b/arch/arm/src/stm32h7/stm32_otghost.c index 35492f1598..033de86567 100644 --- a/arch/arm/src/stm32h7/stm32_otghost.c +++ b/arch/arm/src/stm32h7/stm32_otghost.c @@ -2785,7 +2785,7 @@ static inline void stm32_gint_hcoutisr(struct stm32_usbhost_s *priv, else if ((pending & OTG_HCINT_STALL) != 0) { - /* Clear the pending the STALL response receiv (STALL) interrupt */ + /* Clear the pending STALL response receive (STALL) interrupt */ stm32_putreg(STM32_OTG_HCINT(chidx), OTG_HCINT_STALL); diff --git a/arch/arm/src/stm32h7/stm32_pwm.c b/arch/arm/src/stm32h7/stm32_pwm.c index 5cfd41f536..a35c64fbf0 100644 --- a/arch/arm/src/stm32h7/stm32_pwm.c +++ b/arch/arm/src/stm32h7/stm32_pwm.c @@ -2627,7 +2627,7 @@ static int pwm_outputs_enable(struct pwm_lowerhalf_s *dev, uint32_t ccer = 0; uint32_t regval = 0; - /* Get curren register state */ + /* Get current register state */ ccer = pwm_getreg(priv, STM32_GTIM_CCER_OFFSET); @@ -2650,7 +2650,7 @@ static int pwm_outputs_enable(struct pwm_lowerhalf_s *dev, if (state == true) { - /* Enable outpus - set bits */ + /* Enable outputs - set bits */ ccer |= regval; } @@ -2713,7 +2713,7 @@ errout: * Name: pwm_sync_configure * * Description: - * Confiugre an output synchronisation event for PWM timer (TRGO/TRGO2) + * Configure an output synchronisation event for PWM timer (TRGO/TRGO2) * ****************************************************************************/ @@ -2815,7 +2815,7 @@ static uint16_t pwm_outputs_from_channels(struct stm32_pwmtimer_s *priv) if (channel != 0) { - /* Enable output if confiugred */ + /* Enable output if configured */ if (priv->channels[i].out1.in_use == 1) { diff --git a/arch/arm/src/stm32h7/stm32_sdmmc.c b/arch/arm/src/stm32h7/stm32_sdmmc.c index 8ccd767f4e..6a2dc98d6b 100644 --- a/arch/arm/src/stm32h7/stm32_sdmmc.c +++ b/arch/arm/src/stm32h7/stm32_sdmmc.c @@ -2549,7 +2549,7 @@ static int stm32_waitresponse(struct sdio_dev_s *dev, uint32_t cmd) * * Returned Value: * Number of bytes sent on success; a negated errno on failure. Here a - * failure means only a faiure to obtain the requested response (due to + * failure means only a failure to obtain the requested response (due to * transport problem -- timeout, CRC, etc.). The implementation only * assures that the response is returned intact and does not check errors * within the response itself. diff --git a/arch/arm/src/stm32h7/stm32_serial.c b/arch/arm/src/stm32h7/stm32_serial.c index ee4d1efc37..2758273fcc 100644 --- a/arch/arm/src/stm32h7/stm32_serial.c +++ b/arch/arm/src/stm32h7/stm32_serial.c @@ -630,7 +630,7 @@ struct up_dev_s #ifdef SERIAL_HAVE_TXDMA const unsigned int txdma_channel; /* DMA channel assigned */ - DMA_HANDLE txdma; /* currently-open trasnmit DMA stream */ + DMA_HANDLE txdma; /* currently-open transmit DMA stream */ #endif /* RX DMA state */ @@ -3350,7 +3350,7 @@ static void up_dma_txcallback(DMA_HANDLE handle, uint8_t status, void *arg) uart_xmitchars_done(&priv->dev); - /* Send more if availaible */ + /* Send more if available */ up_dma_txavailable(&priv->dev); } @@ -3818,7 +3818,7 @@ uart_dev_t *stm32_serial_get_uart(int uart_num) * * Description: * Performs the low level USART initialization early in debug so that the - * serial console will be available during bootup. This must be called + * serial console will be available during boot up. This must be called * before arm_serialinit. * ****************************************************************************/ diff --git a/arch/arm/src/stm32h7/stm32_start.c b/arch/arm/src/stm32h7/stm32_start.c index 3d026b0015..a91a9f66bf 100644 --- a/arch/arm/src/stm32h7/stm32_start.c +++ b/arch/arm/src/stm32h7/stm32_start.c @@ -307,7 +307,7 @@ void __start(void) defined(CONFIG_ARCH_CHIP_STM32H7_CORTEXM7) && \ defined(CONFIG_STM32H7_CORTEXM4_ENABLED) - /* Start CM4 core after clock configration is done */ + /* Start CM4 core after clock configuration is done */ stm32h7_start_cm4(); #endif diff --git a/arch/arm/src/stm32h7/stm32h7x3xx_rcc.c b/arch/arm/src/stm32h7/stm32h7x3xx_rcc.c index 3fba9aeb19..1c9293b05c 100644 --- a/arch/arm/src/stm32h7/stm32h7x3xx_rcc.c +++ b/arch/arm/src/stm32h7/stm32h7x3xx_rcc.c @@ -806,7 +806,7 @@ void stm32_stdclockconfig(void) putreg32(regval, STM32_RCC_CFGR); #endif - /* Configure PLL123 clock source and multipiers */ + /* Configure PLL123 clock source and multipliers */ #ifdef STM32_BOARD_USEHSI regval = (RCC_PLLCKSELR_PLLSRC_HSI | diff --git a/arch/arm/src/stm32h7/stm32h7x7xx_rcc.c b/arch/arm/src/stm32h7/stm32h7x7xx_rcc.c index a6c80b93c6..95944ad711 100644 --- a/arch/arm/src/stm32h7/stm32h7x7xx_rcc.c +++ b/arch/arm/src/stm32h7/stm32h7x7xx_rcc.c @@ -770,7 +770,7 @@ void stm32_stdclockconfig(void) putreg32(regval, STM32_RCC_CFGR); #endif - /* Configure PLL123 clock source and multipiers */ + /* Configure PLL123 clock source and multipliers */ #ifdef STM32_BOARD_USEHSI regval = (RCC_PLLCKSELR_PLLSRC_HSI | diff --git a/arch/arm/src/stm32l4/Kconfig b/arch/arm/src/stm32l4/Kconfig index 1056605ff1..29433a89d8 100644 --- a/arch/arm/src/stm32l4/Kconfig +++ b/arch/arm/src/stm32l4/Kconfig @@ -5374,7 +5374,7 @@ config STM32L4_ADC1_EXTSEL depends on STM32L4_ADC1 ---help--- Select the external event used to trigger the start of conversion of - a regular group. See Reference Manual for mor information. + a regular group. See Reference Manual for more information. endif @@ -5398,7 +5398,7 @@ config STM32L4_ADC2_EXTSEL depends on STM32L4_ADC2 ---help--- Select the external event used to trigger the start of conversion of - a regular group. See Reference Manual for mor information. + a regular group. See Reference Manual for more information. endif @@ -5422,7 +5422,7 @@ config STM32L4_ADC3_EXTSEL depends on STM32L4_ADC3 ---help--- Select the external event used to trigger the start of conversion of - a regular group. See Reference Manual for mor information. + a regular group. See Reference Manual for more information. endif diff --git a/arch/arm/src/stm32l4/hardware/stm32l4_crs.h b/arch/arm/src/stm32l4/hardware/stm32l4_crs.h index 50bbad5d0a..5ff70d77ea 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4_crs.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4_crs.h @@ -84,7 +84,7 @@ #define CRS_ISR_SYNCOKF (1 << 0) /* Bit 0: SYNC event OK flag */ #define CRS_ISR_SYNCWARNF (1 << 1) /* Bit 1: SYNC warning flag */ -#define CRS_ISR_ERRF (1 << 2) /* Bit 2: Errot flag */ +#define CRS_ISR_ERRF (1 << 2) /* Bit 2: Error flag */ #define CRS_ISR_ESYNCF (1 << 3) /* Bit 3: Expected SYNC flag */ #define CRS_ISR_SYNCERR (1 << 8) /* Bit 8: SYNC error */ #define CRS_ISR_SYNCMISS (1 << 9) /* Bit 9: SYNC missed */ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4_sai.h b/arch/arm/src/stm32l4/hardware/stm32l4_sai.h index a87eac7fac..ea33be29c5 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4_sai.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4_sai.h @@ -142,7 +142,7 @@ #define SAI_CR1_SYNCEN_MASK (3 << SAI_CR1_SYNCEN_SHIFT) # define SAI_CR1_SYNCEN_ASYNCH (0 << SAI_CR1_SYNCEN_SHIFT) /* Asynchronous mode */ # define SAI_CR1_SYNCEN_INTERNAL (1 << SAI_CR1_SYNCEN_SHIFT) /* Synchronous with other internal sub-block */ -# define SAI_CR1_SYNCEN_EXTERNAL (2 << SAI_CR1_SYNCEN_SHIFT) /* Aynchronous with external SAI peripheral */ +# define SAI_CR1_SYNCEN_EXTERNAL (2 << SAI_CR1_SYNCEN_SHIFT) /* Asynchronous with external SAI peripheral */ #define SAI_CR1_MONO (1 << 12) /* Bit 12: Mono mode */ #define SAI_CR1_OUTDRIV (1 << 13) /* Bit 13: Output drive */ diff --git a/arch/arm/src/stm32l4/stm32l4_1wire.c b/arch/arm/src/stm32l4/stm32l4_1wire.c index 0aae900071..73683cbddc 100644 --- a/arch/arm/src/stm32l4/stm32l4_1wire.c +++ b/arch/arm/src/stm32l4/stm32l4_1wire.c @@ -742,7 +742,7 @@ static int stm32_1wire_process(struct stm32_1wire_priv_s *priv, ret = priv->result; leave_critical_section(irqs); - /* Release the port for re-use by other clients */ + /* Release the port for reuse by other clients */ nxmutex_unlock(&priv->lock); return ret; diff --git a/arch/arm/src/stm32l4/stm32l4_can.c b/arch/arm/src/stm32l4/stm32l4_can.c index 64dbd10461..b88af51150 100644 --- a/arch/arm/src/stm32l4/stm32l4_can.c +++ b/arch/arm/src/stm32l4/stm32l4_can.c @@ -1569,7 +1569,7 @@ static int stm32l4can_txinterrupt(int irq, void *context, void *arg) if ((regval & CAN_TSR_TXOK0) != 0) { - /* Tell the upper half that the tansfer is finished. */ + /* Tell the upper half that the transfer is finished. */ can_txdone(dev); } @@ -1589,7 +1589,7 @@ static int stm32l4can_txinterrupt(int irq, void *context, void *arg) if ((regval & CAN_TSR_TXOK1) != 0) { - /* Tell the upper half that the tansfer is finished. */ + /* Tell the upper half that the transfer is finished. */ can_txdone(dev); } @@ -1609,7 +1609,7 @@ static int stm32l4can_txinterrupt(int irq, void *context, void *arg) if ((regval & CAN_TSR_TXOK2) != 0) { - /* Tell the upper half that the tansfer is finished. */ + /* Tell the upper half that the transfer is finished. */ can_txdone(dev); } diff --git a/arch/arm/src/stm32l4/stm32l4_hsi48.c b/arch/arm/src/stm32l4/stm32l4_hsi48.c index e96b3cf369..75ab0311ff 100644 --- a/arch/arm/src/stm32l4/stm32l4_hsi48.c +++ b/arch/arm/src/stm32l4/stm32l4_hsi48.c @@ -56,7 +56,7 @@ * frequency which is subject to manufacturing process variations. * * Input Parameters: - * Identifies the syncrhonization source for the HSI48. When used as the + * Identifies the synchronization source for the HSI48. When used as the * USB source clock, this must be set to SYNCSRC_USB. * * Returned Value: diff --git a/arch/arm/src/stm32l4/stm32l4_hsi48.h b/arch/arm/src/stm32l4/stm32l4_hsi48.h index d038664727..4028f5a2bb 100644 --- a/arch/arm/src/stm32l4/stm32l4_hsi48.h +++ b/arch/arm/src/stm32l4/stm32l4_hsi48.h @@ -66,7 +66,7 @@ enum syncsrc_e * frequency which is subject to manufacturing process variations. * * Input Parameters: - * Identifies the syncrhonization source for the HSI48. When used as the + * Identifies the synchronization source for the HSI48. When used as the * USB source clock, this must be set to SYNCSRC_USB. * * Returned Value: diff --git a/arch/arm/src/stm32l4/stm32l4_i2c.c b/arch/arm/src/stm32l4/stm32l4_i2c.c index a886a2edec..6eb13835d1 100644 --- a/arch/arm/src/stm32l4/stm32l4_i2c.c +++ b/arch/arm/src/stm32l4/stm32l4_i2c.c @@ -150,7 +150,7 @@ * Interrupt mode relies on the following interrupt events: * * TXIS - Transmit interrupt - * (data transmitted to bus and acknowedged) + * (data transmitted to bus and acknowledged) * NACKF - Not Acknowledge Received * (data transmitted to bus and NOT acknowledged) * RXNE - Receive interrupt @@ -2807,7 +2807,7 @@ static int stm32l4_i2c_reset(struct i2c_master_s *dev) out: - /* Release the port for re-use by other clients */ + /* Release the port for reuse by other clients */ nxmutex_unlock(&priv->lock); return ret; diff --git a/arch/arm/src/stm32l4/stm32l4_otgfshost.c b/arch/arm/src/stm32l4/stm32l4_otgfshost.c index 57b67c5a1f..3442697642 100644 --- a/arch/arm/src/stm32l4/stm32l4_otgfshost.c +++ b/arch/arm/src/stm32l4/stm32l4_otgfshost.c @@ -2777,7 +2777,7 @@ static inline void stm32l4_gint_hcoutisr(struct stm32l4_usbhost_s *priv, else if ((pending & OTGFS_HCINT_STALL) != 0) { - /* Clear the pending the STALL response receiv (STALL) interrupt */ + /* Clear the pending STALL response receive (STALL) interrupt */ stm32l4_putreg(STM32L4_OTGFS_HCINT(chidx), OTGFS_HCINT_STALL); diff --git a/arch/arm/src/stm32l4/stm32l4_pwm.c b/arch/arm/src/stm32l4/stm32l4_pwm.c index efd5dc8055..3f677073a1 100644 --- a/arch/arm/src/stm32l4/stm32l4_pwm.c +++ b/arch/arm/src/stm32l4/stm32l4_pwm.c @@ -2527,7 +2527,7 @@ static int pwm_outputs_enable(struct pwm_lowerhalf_s *dev, uint32_t ccer = 0; uint32_t regval = 0; - /* Get curren register state */ + /* Get current register state */ ccer = pwm_getreg(priv, STM32L4_GTIM_CCER_OFFSET); @@ -2549,7 +2549,7 @@ static int pwm_outputs_enable(struct pwm_lowerhalf_s *dev, if (state == true) { - /* Enable outpus - set bits */ + /* Enable outputs - set bits */ ccer |= regval; } @@ -2683,7 +2683,7 @@ pwm_outputs_from_channels(struct stm32l4_pwmtimer_s *priv) if (channel != 0) { - /* Enable output if confiugred */ + /* Enable output if configured */ if (priv->channels[i].out1.in_use == 1) { diff --git a/arch/arm/src/stm32l4/stm32l4_sdmmc.c b/arch/arm/src/stm32l4/stm32l4_sdmmc.c index 2b2ed6aef2..9c2195db6f 100644 --- a/arch/arm/src/stm32l4/stm32l4_sdmmc.c +++ b/arch/arm/src/stm32l4/stm32l4_sdmmc.c @@ -2212,7 +2212,7 @@ static int stm32_waitresponse(struct sdio_dev_s *dev, uint32_t cmd) * * Returned Value: * Number of bytes sent on success; a negated errno on failure. Here a - * failure means only a faiure to obtain the requested response (due to + * failure means only a failure to obtain the requested response (due to * transport problem -- timeout, CRC, etc.). The implementation only * assures that the response is returned intact and does not check errors * within the response itself. diff --git a/arch/arm/src/stm32l4/stm32l4_serial.c b/arch/arm/src/stm32l4/stm32l4_serial.c index 94694d96de..e2114f940e 100644 --- a/arch/arm/src/stm32l4/stm32l4_serial.c +++ b/arch/arm/src/stm32l4/stm32l4_serial.c @@ -3090,7 +3090,7 @@ static int stm32l4serial_pmprepare(struct pm_callback_s *cb, int domain, * * Description: * Performs the low level USART initialization early in debug so that the - * serial console will be available during bootup. This must be called + * serial console will be available during boot up. This must be called * before arm_serialinit. * ****************************************************************************/ diff --git a/arch/arm/src/stm32l5/hardware/stm32l562xx_pinmap.h b/arch/arm/src/stm32l5/hardware/stm32l562xx_pinmap.h index 3965384ff1..c85dbb7c8d 100644 --- a/arch/arm/src/stm32l5/hardware/stm32l562xx_pinmap.h +++ b/arch/arm/src/stm32l5/hardware/stm32l562xx_pinmap.h @@ -42,7 +42,7 @@ * etc. Drivers, however, will use the pin selection without the numeric * suffix. Additional definitions are required in the board.h file. For * example, if FDCAN1_RX connects via PA11 on some board, then the following - * definitions should appear inthe board.h header file for that board: + * definitions should appear in the board.h header file for that board: * * #define GPIO_FDCAN1_RX GPIO_FDCAN1_RX_1 * diff --git a/arch/arm/src/stm32l5/hardware/stm32l562xx_pinmap_legacy.h b/arch/arm/src/stm32l5/hardware/stm32l562xx_pinmap_legacy.h index c6fb33cec0..500e73abd6 100644 --- a/arch/arm/src/stm32l5/hardware/stm32l562xx_pinmap_legacy.h +++ b/arch/arm/src/stm32l5/hardware/stm32l562xx_pinmap_legacy.h @@ -42,7 +42,7 @@ * etc. Drivers, however, will use the pin selection without the numeric * suffix. Additional definitions are required in the board.h file. For * example, if FDCAN1_RX connects via PA11 on some board, then the following - * definitions should appear inthe board.h header file for that board: + * definitions should appear in the board.h header file for that board: * * #define GPIO_FDCAN1_RX GPIO_FDCAN1_RX_1 * diff --git a/arch/arm/src/stm32l5/hardware/stm32l5_tim.h b/arch/arm/src/stm32l5/hardware/stm32l5_tim.h index d5877904ad..1e99dba009 100644 --- a/arch/arm/src/stm32l5/hardware/stm32l5_tim.h +++ b/arch/arm/src/stm32l5/hardware/stm32l5_tim.h @@ -361,7 +361,7 @@ #define ATIM_CR2_OIS3 (1 << 12) /* Bit 12: Output Idle state 3 (OC3 output) */ #define ATIM_CR2_OIS3N (1 << 13) /* Bit 13: Output Idle state 3 (OC3N output) */ #define ATIM_CR2_OIS4 (1 << 14) /* Bit 14: Output Idle state 4 (OC4 output) */ -#define ATIM_CR2_OIS5 (1 << 16) /* Bit 16: OOutput Idle state 5 (OC5 output) */ +#define ATIM_CR2_OIS5 (1 << 16) /* Bit 16: Output Idle state 5 (OC5 output) */ #define ATIM_CR2_OIS6 (1 << 18) /* Bit 18: Output Idle state 6 (OC6 output) */ #define ATIM_CR2_MMS2_SHIFT (20) /* Bits 20-23: Master Mode Selection 2 */ #define ATIM_CR2_MMS2_MASK (15 << ATIM_CR2_MMS2_SHIFT) diff --git a/arch/arm/src/stm32l5/stm32l5_serial.c b/arch/arm/src/stm32l5/stm32l5_serial.c index 1e7a5e21e6..a020496714 100644 --- a/arch/arm/src/stm32l5/stm32l5_serial.c +++ b/arch/arm/src/stm32l5/stm32l5_serial.c @@ -3023,7 +3023,7 @@ static int stm32l5serial_pmprepare(struct pm_callback_s *cb, int domain, * * Description: * Performs the low level USART initialization early in debug so that the - * serial console will be available during bootup. This must be called + * serial console will be available during boot up. This must be called * before arm_serialinit. * ****************************************************************************/ diff --git a/arch/arm/src/stm32l5/stm32l5_spi.c b/arch/arm/src/stm32l5/stm32l5_spi.c index fbadb39b98..94bc1e3ba7 100644 --- a/arch/arm/src/stm32l5/stm32l5_spi.c +++ b/arch/arm/src/stm32l5/stm32l5_spi.c @@ -924,12 +924,12 @@ static void spi_modifycr(uint32_t addr, struct stm32l5_spidev_s *priv, * Name: spi_lock * * Description: - * On SPI busses where there are multiple devices, it will be necessary to - * lock SPI to have exclusive access to the busses for a sequence of + * On SPI buses where there are multiple devices, it will be necessary to + * lock SPI to have exclusive access to the buses for a sequence of * transfers. The bus should be locked before the chip is selected. After * locking the SPI bus, the caller should then also call the setfrequency, * setbits, and setmode methods to make sure that the SPI is properly - * configured for the device. If the SPI buss is being shared, then it + * configured for the device. If the SPI bus is being shared, then it * may have been left in an incompatible state. * * Input Parameters: diff --git a/arch/arm/src/stm32u5/hardware/stm32_pwr.h b/arch/arm/src/stm32u5/hardware/stm32_pwr.h index 2792c34e9d..27626af188 100644 --- a/arch/arm/src/stm32u5/hardware/stm32_pwr.h +++ b/arch/arm/src/stm32u5/hardware/stm32_pwr.h @@ -190,7 +190,7 @@ #define PWR_SVMSR_REGS_LDO 0 /* 0: LDO selected */ #define PWR_SVMSR_REGS_SMPS PWR_SVMSR_REGS /* 1: SMPS selected */ #define PWR_SVMSR_PVDO (1 << 4) /* Bit 4: Programmable voltage detector output */ -#define PWR_SVMSR_ACTVOSRDY (1 << 15) /* Bit 15: Voltage level ready for currenty used VOS */ +#define PWR_SVMSR_ACTVOSRDY (1 << 15) /* Bit 15: Voltage level ready for currently used VOS */ #define PWR_SVMSR_ACTVOS_SHIFT 16 #define PWR_SVMSR_ACTVOS_MASK (3 << PWR_SVMSR_ACTVOS_SHIFT) /* Bits 16-17: VOS currently applied to V_CORE */ #define PWR_SVMSR_ACTVOS_RANGE4 (0 << PWR_SVMSR_ACTVOS_SHIFT) /* 00: Range 4 (lowest power) */ diff --git a/arch/arm/src/stm32u5/hardware/stm32_tim.h b/arch/arm/src/stm32u5/hardware/stm32_tim.h index e721b05314..d9adc74810 100644 --- a/arch/arm/src/stm32u5/hardware/stm32_tim.h +++ b/arch/arm/src/stm32u5/hardware/stm32_tim.h @@ -361,7 +361,7 @@ #define ATIM_CR2_OIS3 (1 << 12) /* Bit 12: Output Idle state 3 (OC3 output) */ #define ATIM_CR2_OIS3N (1 << 13) /* Bit 13: Output Idle state 3 (OC3N output) */ #define ATIM_CR2_OIS4 (1 << 14) /* Bit 14: Output Idle state 4 (OC4 output) */ -#define ATIM_CR2_OIS5 (1 << 16) /* Bit 16: OOutput Idle state 5 (OC5 output) */ +#define ATIM_CR2_OIS5 (1 << 16) /* Bit 16: Output Idle state 5 (OC5 output) */ #define ATIM_CR2_OIS6 (1 << 18) /* Bit 18: Output Idle state 6 (OC6 output) */ #define ATIM_CR2_MMS2_SHIFT (20) /* Bits 20-23: Master Mode Selection 2 */ #define ATIM_CR2_MMS2_MASK (15 << ATIM_CR2_MMS2_SHIFT) diff --git a/arch/arm/src/stm32u5/hardware/stm32u5xx_pinmap.h b/arch/arm/src/stm32u5/hardware/stm32u5xx_pinmap.h index c2a69c312d..db8c471bda 100644 --- a/arch/arm/src/stm32u5/hardware/stm32u5xx_pinmap.h +++ b/arch/arm/src/stm32u5/hardware/stm32u5xx_pinmap.h @@ -42,7 +42,7 @@ * etc. Drivers, however, will use the pin selection without the numeric * suffix. Additional definitions are required in the board.h file. For * example, if FDCAN1_RX connects via PA11 on some board, then the following - * definitions should appear inthe board.h header file for that board: + * definitions should appear in the board.h header file for that board: * * #define GPIO_FDCAN1_RX GPIO_FDCAN1_RX_1 * diff --git a/arch/arm/src/stm32u5/hardware/stm32u5xx_rcc.h b/arch/arm/src/stm32u5/hardware/stm32u5xx_rcc.h index 5608b178e0..a106a9e574 100644 --- a/arch/arm/src/stm32u5/hardware/stm32u5xx_rcc.h +++ b/arch/arm/src/stm32u5/hardware/stm32u5xx_rcc.h @@ -343,7 +343,7 @@ #define RCC_PLL1CFGR_PLL1RGE_SHIFT (2) /* Bits 2-3: PLL1 input frequency range */ #define RCC_PLL1CFGR_PLL1RGE_MASK (3 << RCC_PLL1CFGR_PLL1RGE_SHIFT) #define RCC_PLL1CFGR_PLL1RGE_4_TO_8MHZ (0 << RCC_PLL1CFGR_PLL1RGE_SHIFT) /* 00-01-10: PLL1 input (ref1_ck) clock range frequency between 4 and 8 MHz */ -#define RCC_PLL1CFGR_PLL1RGE_8_TO_16MHZ (3 << RCC_PLL1CFGR_PLL1RGE_SHIFT) /* 11: PLL1 input (ref1_ck) clock range frequeny between 8 and 16 MHz */ +#define RCC_PLL1CFGR_PLL1RGE_8_TO_16MHZ (3 << RCC_PLL1CFGR_PLL1RGE_SHIFT) /* 11: PLL1 input (ref1_ck) clock range frequency between 8 and 16 MHz */ #define RCC_PLL1CFGR_PLL1FRACEN (1 << 4) /* Bit 4: PLL1 fractional latch enable */ #define RCC_PLL1CFGR_PLL1M_SHIFT (8) /* Bits 8-11: Prescaler for PLL1 */ #define RCC_PLL1CFGR_PLL1M_MASK (0xf << RCC_PLL1CFGR_PLL1M_SHIFT) diff --git a/arch/arm/src/stm32u5/stm32_i2c.c b/arch/arm/src/stm32u5/stm32_i2c.c index b34c86a8f1..2f12e93f27 100644 --- a/arch/arm/src/stm32u5/stm32_i2c.c +++ b/arch/arm/src/stm32u5/stm32_i2c.c @@ -151,7 +151,7 @@ * Interrupt mode relies on the following interrupt events: * * TXIS - Transmit interrupt - * (data transmitted to bus and acknowedged) + * (data transmitted to bus and acknowledged) * NACKF - Not Acknowledge Received * (data transmitted to bus and NOT acknowledged) * RXNE - Receive interrupt @@ -2857,7 +2857,7 @@ static int stm32_i2c_reset(struct i2c_master_s *dev) out: - /* Release the port for re-use by other clients */ + /* Release the port for reuse by other clients */ nxmutex_unlock(&priv->lock); return ret; diff --git a/arch/arm/src/stm32u5/stm32_pwr.c b/arch/arm/src/stm32u5/stm32_pwr.c index 3f137423a8..86d1436e7c 100644 --- a/arch/arm/src/stm32u5/stm32_pwr.c +++ b/arch/arm/src/stm32u5/stm32_pwr.c @@ -254,7 +254,7 @@ void stm32_pwr_adjustvcore(unsigned sysclock) * Name stm32_pwr_enable_smps * * Description: - * Select between the Low-Drop Out (LDO) or Switched Mode Power Suppy + * Select between the Low-Drop Out (LDO) or Switched Mode Power Supply * (SMPS) regulator. Compare [RM0456], section 10.5.1 SMPS and LDO * embedded regulators. * diff --git a/arch/arm/src/stm32u5/stm32_pwr.h b/arch/arm/src/stm32u5/stm32_pwr.h index 6d27f6cc6f..97da688453 100644 --- a/arch/arm/src/stm32u5/stm32_pwr.h +++ b/arch/arm/src/stm32u5/stm32_pwr.h @@ -109,7 +109,7 @@ void stm32_pwr_adjustvcore(unsigned sysclock); * Name stm32_pwr_enable_smps * * Description: - * Select between the Low-Drop Out (LDO) or Switched Mode Power Suppy + * Select between the Low-Drop Out (LDO) or Switched Mode Power Supply * (SMPS) regulator. Compare [RM0456], section 10.5.1 SMPS and LDO * embedded regulators. * diff --git a/arch/arm/src/stm32u5/stm32_serial.c b/arch/arm/src/stm32u5/stm32_serial.c index 8740919d96..b8ff14b211 100644 --- a/arch/arm/src/stm32u5/stm32_serial.c +++ b/arch/arm/src/stm32u5/stm32_serial.c @@ -3023,7 +3023,7 @@ static int stm32serial_pmprepare(struct pm_callback_s *cb, int domain, * * Description: * Performs the low level USART initialization early in debug so that the - * serial console will be available during bootup. This must be called + * serial console will be available during boot up. This must be called * before arm_serialinit. * ****************************************************************************/ diff --git a/arch/arm/src/stm32wb/stm32wb_blehci.c b/arch/arm/src/stm32wb/stm32wb_blehci.c index d43d93aa8a..9f88c4af3a 100644 --- a/arch/arm/src/stm32wb/stm32wb_blehci.c +++ b/arch/arm/src/stm32wb/stm32wb_blehci.c @@ -375,7 +375,7 @@ void stm32wb_blehci_initialize(void) stm32wb_mboxinitialize(stm32wb_blehci_rxevt); - /* Enable communication hardware and bootup CPU2 */ + /* Enable communication hardware and boot up CPU2 */ stm32wb_mboxenable(); } diff --git a/arch/arm/src/stm32wb/stm32wb_gpio.c b/arch/arm/src/stm32wb/stm32wb_gpio.c index 4f3eca1daf..c8a2444e3c 100644 --- a/arch/arm/src/stm32wb/stm32wb_gpio.c +++ b/arch/arm/src/stm32wb/stm32wb_gpio.c @@ -314,7 +314,7 @@ int stm32wb_configgpio(uint32_t cfgset) * Description: * Unconfigure a GPIO pin based on bit-encoded description of the pin, set * it into default HiZ state (and possibly mark it's unused) and unlock it - * whether it was previsouly selected as alternative function + * whether it was previously selected as alternative function * (GPIO_ALT|GPIO_CNF_AFPP|...). * * This is a safety function and prevents hardware from schocks, as diff --git a/arch/arm/src/stm32wb/stm32wb_i2c.c b/arch/arm/src/stm32wb/stm32wb_i2c.c index c92bda3c3c..49d56a4114 100644 --- a/arch/arm/src/stm32wb/stm32wb_i2c.c +++ b/arch/arm/src/stm32wb/stm32wb_i2c.c @@ -2461,7 +2461,7 @@ static int stm32wb_i2c_reset(struct i2c_master_s * dev) out: - /* Release the port for re-use by other clients */ + /* Release the port for reuse by other clients */ nxmutex_unlock(&priv->lock); return ret; diff --git a/arch/arm/src/stm32wb/stm32wb_mbox.c b/arch/arm/src/stm32wb/stm32wb_mbox.c index 28f4683ebb..5df5eeaa62 100644 --- a/arch/arm/src/stm32wb/stm32wb_mbox.c +++ b/arch/arm/src/stm32wb/stm32wb_mbox.c @@ -731,7 +731,7 @@ void stm32wb_mboxenable(void) stm32wb_ipcc_unmaskrxo(STM32WB_MBOX_SYSEVT_CHANNEL); - /* Enable IPCC hardware and bootup CPU2 */ + /* Enable IPCC hardware and boot up CPU2 */ stm32wb_ipccenable(); } diff --git a/arch/arm/src/stm32wb/stm32wb_rcc.h b/arch/arm/src/stm32wb/stm32wb_rcc.h index 5a3eb33784..c770e462bd 100644 --- a/arch/arm/src/stm32wb/stm32wb_rcc.h +++ b/arch/arm/src/stm32wb/stm32wb_rcc.h @@ -227,7 +227,7 @@ void stm32wb_rcc_disable_lsi(void); * frequency which is subject to manufacturing process variations. * * Input Parameters: - * Identifies the syncrhonization source for the HSI48. When used as the + * Identifies the synchronization source for the HSI48. When used as the * USB source clock, this must be set to SYNCSRC_USB. * * Returned Value: diff --git a/arch/arm/src/stm32wb/stm32wb_rcc_hsi48.c b/arch/arm/src/stm32wb/stm32wb_rcc_hsi48.c index 2bd8eb5e8a..e8d12b2d35 100644 --- a/arch/arm/src/stm32wb/stm32wb_rcc_hsi48.c +++ b/arch/arm/src/stm32wb/stm32wb_rcc_hsi48.c @@ -53,7 +53,7 @@ * frequency which is subject to manufacturing process variations. * * Input Parameters: - * Identifies the syncrhonization source for the HSI48. When used as the + * Identifies the synchronization source for the HSI48. When used as the * USB source clock, this must be set to SYNCSRC_USB. * * Returned Value: diff --git a/arch/arm/src/stm32wb/stm32wb_serial.c b/arch/arm/src/stm32wb/stm32wb_serial.c index 60f1700724..be811020d2 100644 --- a/arch/arm/src/stm32wb/stm32wb_serial.c +++ b/arch/arm/src/stm32wb/stm32wb_serial.c @@ -2685,7 +2685,7 @@ static int stm32wb_serial_pmprepare(struct pm_callback_s *cb, int domain, * * Description: * Performs the low level USART initialization early in debug so that the - * serial console will be available during bootup. This must be called + * serial console will be available during boot up. This must be called * before arm_serialinit. * ****************************************************************************/ diff --git a/arch/arm/src/stm32wl5/hardware/stm32wl5_exti.h b/arch/arm/src/stm32wl5/hardware/stm32wl5_exti.h index 1c0b4b51f9..3a3b11d974 100644 --- a/arch/arm/src/stm32wl5/hardware/stm32wl5_exti.h +++ b/arch/arm/src/stm32wl5/hardware/stm32wl5_exti.h @@ -108,7 +108,7 @@ #define EXTI2_HSE32CSS (1 << 12) /* EXTI line 43: RCC HSE32 CSS interrupt */ #define EXTI2_RADIOIRQ (1 << 13) /* EXTI line 44: Radio interrupt */ #define EXTI2_RADIOBSY (1 << 14) /* EXTI line 45: Radio busy wakeup */ -#define EXTI2_CDBGPWRUPREQ (1 << 15) /* EXTI line 46: Debug power-up request wakup */ +#define EXTI2_CDBGPWRUPREQ (1 << 15) /* EXTI line 46: Debug power-up request wakeup */ /* Rising Trigger selection register */ diff --git a/arch/arm/src/stm32wl5/hardware/stm32wl5_flash.h b/arch/arm/src/stm32wl5/hardware/stm32wl5_flash.h index 83ac471444..0f14d1b02a 100644 --- a/arch/arm/src/stm32wl5/hardware/stm32wl5_flash.h +++ b/arch/arm/src/stm32wl5/hardware/stm32wl5_flash.h @@ -173,7 +173,7 @@ /* Flash Access Control Register 2 (ACR2) */ -#define FLASH_ACR2_PRIVMODE (1 << 0) /* Bit 0: Enable flash priviliged access mode */ +#define FLASH_ACR2_PRIVMODE (1 << 0) /* Bit 0: Enable flash privileged access mode */ #define FLASH_ACR2_HDPADIS (1 << 1) /* Bit 1: Disable user flash hide protection area access */ #define FLASH_ACR2_C2SWDBGEN (1 << 2) /* Bit 2: Enable cpu2 debug access */ diff --git a/arch/arm/src/stm32wl5/hardware/stm32wl5_pwr.h b/arch/arm/src/stm32wl5/hardware/stm32wl5_pwr.h index d86d8b2c69..978e931a4d 100644 --- a/arch/arm/src/stm32wl5/hardware/stm32wl5_pwr.h +++ b/arch/arm/src/stm32wl5/hardware/stm32wl5_pwr.h @@ -147,7 +147,7 @@ #define PWR_CR4_WP3 (1 << 2) /* Bit 2: Wakeup pin WKUP3 polarity */ #define PWR_CR4_VBE (1 << 8) /* Bit 8: Vbat battery charging enable */ #define PWR_CR4_VBRS (1 << 9) /* Bit 9: Vbat battery charging resistor selection */ -#define PWR_CR4_WRFBUSYP (1 << 11) /* Bit 11: Radio event detection on failling edge */ +#define PWR_CR4_WRFBUSYP (1 << 11) /* Bit 11: Radio event detection on failing edge */ #define PWR_CR4_C2BOOT (1 << 15) /* Bit 15: Boot cpu2 after reset if event is available */ # define PWR_CR4_VBRS_5k 0 /* 0: 5k resistor */ @@ -163,8 +163,8 @@ #define PWR_SR1_WUF1 (1 << 0) /* Bit 0: Wakeup flag 1 */ #define PWR_SR1_WUF2 (1 << 1) /* Bit 1: Wakeup flag 2 */ #define PWR_SR1_WUF3 (1 << 2) /* Bit 2: Wakeup flag 3 */ -#define PWR_SR1_WPVDF (1 << 8) /* Bit 8: Wakup PVD flag */ -#define PWR_SR1_WRFBUSYF (1 << 11) /* Bit 11: Radio busy wakup flag */ +#define PWR_SR1_WPVDF (1 << 8) /* Bit 8: Wakeup PVD flag */ +#define PWR_SR1_WRFBUSYF (1 << 11) /* Bit 11: Radio busy wakeup flag */ #define PWR_SR1_C2HF (1 << 14) /* Bit 14: Cpu2 hold interrupt flag */ #define PWR_SR1_WUFI (1 << 15) /* Bit 15: Wakeup internal flag */ diff --git a/arch/arm/src/stm32wl5/hardware/stm32wl5_tim.h b/arch/arm/src/stm32wl5/hardware/stm32wl5_tim.h index fb6120fe9a..1ffe5b7803 100644 --- a/arch/arm/src/stm32wl5/hardware/stm32wl5_tim.h +++ b/arch/arm/src/stm32wl5/hardware/stm32wl5_tim.h @@ -241,7 +241,7 @@ #define ATIM_CR2_OIS3 (1 << 12) /* Bit 12: Output Idle state 3 (OC3 output) */ #define ATIM_CR2_OIS3N (1 << 13) /* Bit 13: Output Idle state 3 (OC3N output) */ #define ATIM_CR2_OIS4 (1 << 14) /* Bit 14: Output Idle state 4 (OC4 output) */ -#define ATIM_CR2_OIS5 (1 << 16) /* Bit 16: OOutput Idle state 5 (OC5 output) */ +#define ATIM_CR2_OIS5 (1 << 16) /* Bit 16: Output Idle state 5 (OC5 output) */ #define ATIM_CR2_OIS6 (1 << 18) /* Bit 18: Output Idle state 6 (OC6 output) */ #define ATIM_CR2_MMS2_SHIFT (20) /* Bits 20-23: Master Mode Selection 2 */ #define ATIM_CR2_MMS2_MASK (15 << ATIM_CR2_MMS2_SHIFT) diff --git a/arch/arm/src/stm32wl5/stm32wl5_ipcc.c b/arch/arm/src/stm32wl5/stm32wl5_ipcc.c index ecf768d14c..9336c32b1d 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_ipcc.c +++ b/arch/arm/src/stm32wl5/stm32wl5_ipcc.c @@ -355,7 +355,7 @@ static ssize_t stm32wl5_ipcc_write(struct ipcc_lower_s *ipcc, modifyreg32(STM32WL5_IPCC_C1SCR, 0, STM32WL5_IPCC_SCR_CHNS(ipcc->chan)); - /* Reenable interrupts */ + /* Re-enable interrupts */ modifyreg32(STM32WL5_IPCC_C1MR, STM32WL5_IPCC_MR_CHNFM(ipcc->chan), 0); up_enable_irq(STM32WL5_IRQ_IPCC_C1_TX_IT); @@ -460,7 +460,7 @@ static int stm32wl5_ipcc_rx_isr(int irq, void *context, void *arg) * Function will copy requests number of bytes to buffer. If there is not * enough data in IPCC memory, less bytes than requests will be copied. * Buflen does not have to be bigger than IPCC memory - function can be - * called multiple times and only new data will be transfered. If we don't + * called multiple times and only new data will be transferred. If we don't * have control over IPCC memory (CHnF is 0 - second CPU is writing data * to memory) then it's assumed no data is there to read and 0 is returned. * @@ -533,7 +533,7 @@ static ssize_t stm32wl5_ipcc_read(struct ipcc_lower_s *ipcc, modifyreg32(STM32WL5_IPCC_C1MR, STM32WL5_IPCC_MR_CHNOM(ipcc->chan), 0); } - /* Reenable interrupt */ + /* Re-enable interrupt */ up_enable_irq(STM32WL5_IRQ_IPCC_C1_RX_IT); @@ -671,7 +671,7 @@ static ssize_t stm32wl5_ipcc_buffer_data(struct ipcc_lower_s *ipcc, ret = stm32wl5_ipcc_copy_to_buffer(ipcc->chan, rxbuf); - /* Reenable interrupt */ + /* Re-enable interrupt */ up_enable_irq(STM32WL5_IRQ_IPCC_C1_RX_IT); @@ -755,7 +755,7 @@ static int stm32wl5_ipcc_cleanup(struct ipcc_lower_s *ipcc) * chan - channel to initialize * * Returned Value: - * Structure to link lower and upper halfs of the driver, or NULL on + * Structure to link lower and upper halves of the driver, or NULL on * initialization failure. * * Assumptions/Limitations: diff --git a/arch/arm/src/stm32wl5/stm32wl5_ipcc.h b/arch/arm/src/stm32wl5/stm32wl5_ipcc.h index e37da7b0f7..14b68fdb15 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_ipcc.h +++ b/arch/arm/src/stm32wl5/stm32wl5_ipcc.h @@ -130,7 +130,7 @@ * +----------+ */ -/* IPCC needs continous memory of known address that is shared +/* IPCC needs continuous memory of known address that is shared * between CPUs. Because of that we reserve memory at beginning * of SRAM2. SRAM2 region will be right after IPCC reserved memory */ diff --git a/arch/arm/src/stm32wl5/stm32wl5_rcc.c b/arch/arm/src/stm32wl5/stm32wl5_rcc.c index e9e3b7d863..05a8120683 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_rcc.c +++ b/arch/arm/src/stm32wl5/stm32wl5_rcc.c @@ -676,7 +676,7 @@ void stm32wl5_stdclockconfig(void) #if defined(STM32WL5_BOARD_USETCXO) /* nucleo-wl55jc uses TCXO crystal, which needs to be first - * powered up with PB0 pin - or more convinently by setting + * powered up with PB0 pin - or more conveniently by setting * HSEBYPPWR register. This has to be done before HSE is enabled */ diff --git a/arch/arm/src/stm32wl5/stm32wl5_serial.c b/arch/arm/src/stm32wl5/stm32wl5_serial.c index 826aa39ff8..9702a13823 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_serial.c +++ b/arch/arm/src/stm32wl5/stm32wl5_serial.c @@ -2774,7 +2774,7 @@ static int stm32wl5serial_pmprepare(struct pm_callback_s *cb, int domain, * * Description: * Performs the low level USART initialization early in debug so that the - * serial console will be available during bootup. This must be called + * serial console will be available during boot up. This must be called * before arm_serialinit. * ****************************************************************************/ diff --git a/arch/arm/src/str71x/str71x_emi.h b/arch/arm/src/str71x/str71x_emi.h index d61b30d985..23aef4124d 100644 --- a/arch/arm/src/str71x/str71x_emi.h +++ b/arch/arm/src/str71x/str71x_emi.h @@ -35,14 +35,14 @@ * Pre-processor Definitions ****************************************************************************/ -/* External Memory Interfac (EMI) register offset ***************************/ +/* External Memory Interface (EMI) register offset **************************/ #define STR71X_EMI_BCON0_OFFSET (0x0000) /* 16-bits wide */ #define STR71X_EMI_BCON1_OFFSET (0x0004) /* 16-bits wide */ #define STR71X_EMI_BCON2_OFFSET (0x0008) /* 16-bits wide */ #define STR71X_EMI_BCON3_OFFSET (0x000c) /* 16-bits wide */ -/* External Memory Interfac (EMI) register addresses ************************/ +/* External Memory Interface (EMI) register addresses ***********************/ #define STR71X_EMI_BCON0 (STR71X_EMI_BASE + STR71X_EMI_BCON0_OFFSET) #define STR71X_EMI_BCON1 (STR71X_EMI_BASE + STR71X_EMI_BCON1_OFFSET) diff --git a/arch/arm/src/str71x/str71x_head.S b/arch/arm/src/str71x/str71x_head.S index b74c821dd3..630fab1d8a 100644 --- a/arch/arm/src/str71x/str71x_head.S +++ b/arch/arm/src/str71x/str71x_head.S @@ -312,7 +312,7 @@ eicloop: mov \value, \irqno, lsl #16 str \value, [\eicbase, \offset] - /* Increment the offset to the next SIR register and inrement + /* Increment the offset to the next SIR register and increment * the IRQ number. */ diff --git a/arch/arm/src/str71x/str71x_pcu.h b/arch/arm/src/str71x/str71x_pcu.h index f438731c0c..cd19d0d5be 100644 --- a/arch/arm/src/str71x/str71x_pcu.h +++ b/arch/arm/src/str71x/str71x_pcu.h @@ -100,7 +100,7 @@ #define STR71X_PCUPPL2CR_PLLEN (0x0080) /* Bit 7: PLL2 enable */ #define STR71X_PCUPPL2CR_USBEN (0x0100) /* Bit 8: Enable PLL clock to USB */ #define STR71X_PCUPPL2CR_IRQMASK (0x0200) /* Bit 9: Enable interrupt request CPU on lock transition */ -#define STR71X_PCUPPL2CR_IRQPEND (0x0400) /* Bit 10: Interrtup request to CPU on lock transition pending */ +#define STR71X_PCUPPL2CR_IRQPEND (0x0400) /* Bit 10: Interrupt request to CPU on lock transition pending */ #define STR71X_PCUPPL2CR_LOCK (0x8000) /* Bit 15: PLL2 locked */ /* PCU BOOTCR register bit definitions */ diff --git a/arch/arm/src/str71x/str71x_serial.c b/arch/arm/src/str71x/str71x_serial.c index c37ecbfa5c..37b17f9dd5 100644 --- a/arch/arm/src/str71x/str71x_serial.c +++ b/arch/arm/src/str71x/str71x_serial.c @@ -881,7 +881,7 @@ static bool up_txempty(struct uart_dev_s *dev) * Description: * Performs the low level UART initialization early in * debug so that the serial console will be available - * during bootup. This must be called before arm_serialinit. + * during boot up. This must be called before arm_serialinit. * ****************************************************************************/ diff --git a/arch/arm/src/tiva/common/tiva_i2c.c b/arch/arm/src/tiva/common/tiva_i2c.c index 93c901f725..54aeb4279d 100644 --- a/arch/arm/src/tiva/common/tiva_i2c.c +++ b/arch/arm/src/tiva/common/tiva_i2c.c @@ -588,7 +588,7 @@ static struct tiva_i2c_priv_s tiva_i2c9_priv = * * Returned Value: * true: This is the first register access of this type. - * flase: This is the same as the preceding register access. + * false: This is the same as the preceding register access. * ****************************************************************************/ @@ -1853,7 +1853,7 @@ static int tiva_i2c_reset(struct i2c_master_s *dev) out: - /* Release the port for re-use by other clients */ + /* Release the port for reuse by other clients */ nxmutex_unlock(&priv->lock); return ret; diff --git a/arch/arm/src/tiva/common/tiva_serial.c b/arch/arm/src/tiva/common/tiva_serial.c index eb9e733b1f..a3a2842f68 100644 --- a/arch/arm/src/tiva/common/tiva_serial.c +++ b/arch/arm/src/tiva/common/tiva_serial.c @@ -1478,7 +1478,7 @@ static bool up_txempty(struct uart_dev_s *dev) * Description: * Performs the low level UART initialization early in * debug so that the serial console will be available - * during bootup. This must be called before arm_serialinit. + * during boot up. This must be called before arm_serialinit. * ****************************************************************************/ diff --git a/arch/arm/src/tiva/common/tiva_sock_can.c b/arch/arm/src/tiva/common/tiva_sock_can.c index 33ddd0b70e..72219e1d2a 100644 --- a/arch/arm/src/tiva/common/tiva_sock_can.c +++ b/arch/arm/src/tiva/common/tiva_sock_can.c @@ -1636,7 +1636,7 @@ static void tivacan_reset(struct net_driver_s *dev) #endif /* CONFIG_TIVA_CAN1 */ if (modnum > 1) { - canerr("ERROR: tried to reset nonexistant module CAN%d\n", + canerr("ERROR: tried to reset nonexistent module CAN%d\n", canmod->modnum); } diff --git a/arch/arm/src/tiva/common/tiva_timerlib.c b/arch/arm/src/tiva/common/tiva_timerlib.c index 656dc48107..923824fe40 100644 --- a/arch/arm/src/tiva/common/tiva_timerlib.c +++ b/arch/arm/src/tiva/common/tiva_timerlib.c @@ -432,7 +432,7 @@ static struct tiva_gptmstate_s g_gptm7_state; * * Returned Value: * true: This is the first register access of this type. - * flase: This is the same as the preceding register access. + * false: This is the same as the preceding register access. * ****************************************************************************/ diff --git a/arch/arm/src/tiva/hardware/cc13x0/cc13x0_ddi0_osc.h b/arch/arm/src/tiva/hardware/cc13x0/cc13x0_ddi0_osc.h index f184202a87..cd66028f66 100644 --- a/arch/arm/src/tiva/hardware/cc13x0/cc13x0_ddi0_osc.h +++ b/arch/arm/src/tiva/hardware/cc13x0/cc13x0_ddi0_osc.h @@ -131,7 +131,7 @@ # define DDI0_OSC_CTL0_ACLK_REF_SRC_RCOSCLF (2 << DDI0_OSC_CTL0_ACLK_REF_SRC_SEL_SHIFT) /* RCOSC_LF (32kHz) */ # define DDI0_OSC_CTL0_ACLK_REF_SRC_XOSCLF (3 << DDI0_OSC_CTL0_ACLK_REF_SRC_SEL_SHIFT) /* XOSC_LF (32.768kHz) */ -#define DDI0_OSC_CTL0_ACLK_TDC_SRC_SEL_SHIFT (7) /* Bits 7-8: ource select for aclk_tdc */ +#define DDI0_OSC_CTL0_ACLK_TDC_SRC_SEL_SHIFT (7) /* Bits 7-8: Source select for aclk_tdc */ #define DDI0_OSC_CTL0_ACLK_TDC_SRC_SEL_MASK (3 << DDI0_OSC_CTL0_ACLK_TDC_SRC_SEL_SHIFT) # define DDI0_OSC_CTL0_ACLK_TDC_SRC_RCOSCHF48 (0 << DDI0_OSC_CTL0_ACLK_TDC_SRC_SEL_SHIFT) /* RCOSC_HF (48MHz) */ # define DDI0_OSC_CTL0_ACLK_TDC_SRC_RCOSCHF24 (1 << DDI0_OSC_CTL0_ACLK_TDC_SRC_SEL_SHIFT) /* RCOSC_HF (24MHz) */ diff --git a/arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_ddi0_osc.h b/arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_ddi0_osc.h index 81b0f29767..f7b662642b 100644 --- a/arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_ddi0_osc.h +++ b/arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_ddi0_osc.h @@ -129,7 +129,7 @@ # define DDI0_OSC_CTL0_ACLK_REF_SRC_XOSCLF (3 << DDI0_OSC_CTL0_ACLK_REF_SRC_SEL_SHIFT) /* XOSC_LF (32.768kHz) */ # define DDI0_OSC_CTL0_ACLK_REF_SRC_RCOSCMF (4 << DDI0_OSC_CTL0_ACLK_REF_SRC_SEL_SHIFT) /* RCOSC_MF (2MHz) */ -#define DDI0_OSC_CTL0_ACLK_TDC_SRC_SEL_SHIFT (7) /* Bits 7-8: ource select for aclk_tdc */ +#define DDI0_OSC_CTL0_ACLK_TDC_SRC_SEL_SHIFT (7) /* Bits 7-8: Source select for aclk_tdc */ #define DDI0_OSC_CTL0_ACLK_TDC_SRC_SEL_MASK (3 << DDI0_OSC_CTL0_ACLK_TDC_SRC_SEL_SHIFT) # define DDI0_OSC_CTL0_ACLK_TDC_SRC_RCOSCHF48 (0 << DDI0_OSC_CTL0_ACLK_TDC_SRC_SEL_SHIFT) /* RCOSC_HF (48MHz) */ # define DDI0_OSC_CTL0_ACLK_TDC_SRC_RCOSCHF24 (1 << DDI0_OSC_CTL0_ACLK_TDC_SRC_SEL_SHIFT) /* RCOSC_HF (24MHz) */ diff --git a/arch/arm/src/tiva/hardware/tiva_ssi.h b/arch/arm/src/tiva/hardware/tiva_ssi.h index 5d3289d2c4..8e91359b70 100644 --- a/arch/arm/src/tiva/hardware/tiva_ssi.h +++ b/arch/arm/src/tiva/hardware/tiva_ssi.h @@ -159,7 +159,7 @@ #define SSI_CR0_FRF_SHIFT 4 /* Bits 5-4: SSI Frame Format Select */ #define SSI_CR0_FRF_MASK (3 << SSI_CR0_FRF_SHIFT) #define SSI_CR0_FRF_SPI (0 << SSI_CR0_FRF_SHIFT) /* Freescale SPI format */ -#define SSI_CR0_FRF_SSFF (1 << SSI_CR0_FRF_SHIFT) /* TI synchronous serial fram format */ +#define SSI_CR0_FRF_SSFF (1 << SSI_CR0_FRF_SHIFT) /* TI synchronous serial frame format */ #define SSI_CR0_FRF_UWIRE (2 << SSI_CR0_FRF_SHIFT) /* MICROWIRE frame format */ #define SSI_CR0_SPO (1 << 6) /* Bit 6: SSI Serial Clock Polarity */ #define SSI_CR0_SPH (1 << 7) /* Bit 7: SSI Serial Clock Phase */ diff --git a/arch/arm/src/tiva/tm4c/tm4c_ethernet.c b/arch/arm/src/tiva/tm4c/tm4c_ethernet.c index afc5c540ba..12a67a4251 100644 --- a/arch/arm/src/tiva/tm4c/tm4c_ethernet.c +++ b/arch/arm/src/tiva/tm4c/tm4c_ethernet.c @@ -1529,7 +1529,7 @@ static int tiva_recvframe(struct tiva_ethmac_s *priv) * 3) All of the TX descriptors are in flight. * * This last case is obscure. It is due to that fact that each packet - * that we receive can generate an unstoppable transmisson. So we have + * that we receive can generate an unstoppable transmission. So we have * to stop receiving when we can not longer transmit. In this case, the * transmit logic should also have disabled further RX interrupts. */ @@ -1764,7 +1764,7 @@ static void tiva_receive(struct tiva_ethmac_s *priv) } /* We are finished with the RX buffer. NOTE: If the buffer is - * re-used for transmission, the dev->d_buf field will have been + * reused for transmission, the dev->d_buf field will have been * nullified. */ @@ -2002,7 +2002,7 @@ static void tiva_interrupt_work(void *arg) tiva_putreg(EMAC_DMAINT_NIS, TIVA_EMAC_DMARIS); } - /* Handle error interrupt only if CONFIG_DEBUG_NET is eanbled */ + /* Handle error interrupt only if CONFIG_DEBUG_NET is enabled */ #ifdef CONFIG_DEBUG_NET diff --git a/arch/arm/src/tlsr82/Kconfig b/arch/arm/src/tlsr82/Kconfig index 61d5762273..dfb8d9ddf8 100644 --- a/arch/arm/src/tlsr82/Kconfig +++ b/arch/arm/src/tlsr82/Kconfig @@ -125,7 +125,7 @@ config TLSR82_WATCHDOG default n config TLSR82_WDOG_DEFTIMOUT - int "Tlsr82 Watchdog deafult timeout time (ms)" + int "Tlsr82 Watchdog default timeout time (ms)" default 5000 depends on TLSR82_WATCHDOG ---help--- @@ -236,7 +236,7 @@ config TLSR82_SPI_CONSOLE ---help--- This configuration will enable the spi as the console output (printf), input function is not implemented in current code. - This is a useful debug option, beacause some tc32 archtecture chips + This is a useful debug option, because some tc32 architecture chips only have one uart, another debug log output channel is needed when the only uart is used for doing other things. @@ -245,8 +245,8 @@ config TLSR82_SPI_SYSLOG default n ---help--- This configuration will enable the spi as the syslog output - channel (syslog). This is a useful debug option, beacause some tc32 - archtecture chips only have one uart, another debug log output + channel (syslog). This is a useful debug option, because some tc32 + architecture chips only have one uart, another debug log output channel is needed when the only uart is used for doing other things. endif @@ -329,7 +329,7 @@ config TLSR82_ADC_CALI default n ---help--- When enable the adc calibration, adc driver will read the calibration - parameters stored in the falsh during initialization and use these + parameters stored in the flash during initialization and use these parameters to calibrate the sample value. config TLSR82_ADC_CALI_PARA_ADDR @@ -416,7 +416,7 @@ config TLSR82_FLASH_WRITE_BUFFER default n depends on MTD_BYTE_WRITE ---help--- - When enable this config, the flash byte write opreation will write the + When enable this config, the flash byte write operation will write the data to a middle buffer and then write the flash using this buffer to avoid the data buffer passed by apps is at flash. The flash not support read during writing. @@ -440,11 +440,11 @@ config TLSR82_FLASH_PROTECT if the application has performance requirements. config TLSR82_FLASH_CALI - bool "Flash volatge calibration enable" + bool "Flash voltage calibration enable" default n ---help--- When enable the flash calibration, flash driver will read the calibration - parameters stored in the falsh during initialization and use these + parameters stored in the flash during initialization and use these parameters to calibrate the flash voltage. config TLSR82_FLASH_CALI_PARA_ADDR @@ -456,7 +456,7 @@ config TLSR82_FLASH_CALI_PARA_ADDR equal to the address defined in production tools. config TLSR82_FLASH_TEST - bool "Enable the falsh test when initializing" + bool "Enable the flash test when initializing" default n ---help--- When enable this config, the flash test function will execute when diff --git a/arch/arm/src/tlsr82/chip/b87/boot/cstartup_flash.S b/arch/arm/src/tlsr82/chip/b87/boot/cstartup_flash.S index 24e13ee3cd..735ccc413a 100644 --- a/arch/arm/src/tlsr82/chip/b87/boot/cstartup_flash.S +++ b/arch/arm/src/tlsr82/chip/b87/boot/cstartup_flash.S @@ -23,7 +23,7 @@ #include #include -#define SRAM_SIZE_32K_EN 0 /* defaut sram size=64k */ +#define SRAM_SIZE_32K_EN 0 /* default sram size=64k */ #define FLL_STK_EN 1 #define ZERO_IC_TAG_EN 1 diff --git a/arch/arm/src/tlsr82/hardware/tlsr82_adc.h b/arch/arm/src/tlsr82/hardware/tlsr82_adc.h index 5cc0186c9a..e60162671b 100644 --- a/arch/arm/src/tlsr82/hardware/tlsr82_adc.h +++ b/arch/arm/src/tlsr82/hardware/tlsr82_adc.h @@ -118,7 +118,7 @@ #define ADC_MODE_INPUT_RSVD (0x0 << ADC_MODE_INPUT_SHIFT) #define ADC_MODE_INPUT_DIFF (0x1 << ADC_MODE_INPUT_SHIFT) -/* ADC Sample 0 defnition +/* ADC Sample 0 definition * - Sample cycle */ @@ -136,7 +136,7 @@ * - Sample length */ -/* ADC Channel enabel definition */ +/* ADC Channel enable definition */ #define ADC_CTRL0_CHANEN_SHIFT 2 #define ADC_CTRL0_CHANEN_MASK (0x1 << ADC_CTRL0_CHANEN_SHIFT) diff --git a/arch/arm/src/tlsr82/hardware/tlsr82_dma.h b/arch/arm/src/tlsr82/hardware/tlsr82_dma.h index 963d3d4a01..b5a2bd596e 100644 --- a/arch/arm/src/tlsr82/hardware/tlsr82_dma.h +++ b/arch/arm/src/tlsr82/hardware/tlsr82_dma.h @@ -92,7 +92,7 @@ /* DMA irq register definitions * DMA_IRQ_MASK_REG: enable or disable the dma interrupt * DMA_IRQ_EN_REG : enable or disable the dma channel - * DMA_IRQ_STA_REG : get the dma interupt status and write 1 to clear + * DMA_IRQ_STA_REG : get the dma interrupt status and write 1 to clear */ #define DMA_IRQ_MASK_REG REG_ADDR8(0xc21) diff --git a/arch/arm/src/tlsr82/hardware/tlsr82_register.h b/arch/arm/src/tlsr82/hardware/tlsr82_register.h index 67925d0902..d7ba18e68d 100644 --- a/arch/arm/src/tlsr82/hardware/tlsr82_register.h +++ b/arch/arm/src/tlsr82/hardware/tlsr82_register.h @@ -64,7 +64,7 @@ #define RESET_RST2_REG REG_ADDR8(0x62) #define RESET_PWDNEN_REG REG_ADDR8(0x6f) -/* Reset reson definition */ +/* Reset reason definition */ #define RESET_RST0_SPI BIT(0) #define RESET_RST0_I2C BIT(1) diff --git a/arch/arm/src/tlsr82/hardware/tlsr82_uart.h b/arch/arm/src/tlsr82/hardware/tlsr82_uart.h index cee0e6d6e5..f242180448 100644 --- a/arch/arm/src/tlsr82/hardware/tlsr82_uart.h +++ b/arch/arm/src/tlsr82/hardware/tlsr82_uart.h @@ -140,7 +140,7 @@ #define UART_GET_TX_BUF_CNT() ((UART_BUF_CNT0_REG & UART_BUF_CNT0_TX_CNT) >>\ UART_BUF_CNT0_TX_CNT_SHIFT) -/* Uart interupt register definitions */ +/* Uart interrupt register definitions */ #define UART_IRQ_REG REG_ADDR8(0x9e) diff --git a/arch/arm/src/tlsr82/tc32/tc32_backtrace.c b/arch/arm/src/tlsr82/tc32/tc32_backtrace.c index 76c64aca77..c81d894c5b 100644 --- a/arch/arm/src/tlsr82/tc32/tc32_backtrace.c +++ b/arch/arm/src/tlsr82/tc32/tc32_backtrace.c @@ -37,7 +37,7 @@ * Pre-processor Definitions ****************************************************************************/ -/* Macro and definitions for simple decoding of instuctions. +/* Macro and definitions for simple decoding of instructions. * To check an instruction, it is ANDed with the IMASK_ and * the result is compared with the IOP_. The macro INSTR_IS * does this and returns !0 to indicate a match. @@ -89,7 +89,7 @@ static inline uint32_t tc32_getsp(void) * Name: getlroffset * * Description: - * getlroffset() returns the currect link address offset. + * getlroffset() returns the current link address offset. * * Input Parameters: * lr - Link register address @@ -164,13 +164,13 @@ static bool in_code_region(void *pc) * Name: backtrace_push_internal * * Description: - * backtrace_push_internal() returns the currect link address from + * backtrace_push_internal() returns the current link address from * program counter and stack pointer * * Input Parameters: - * psp - Double poninter to the SP, this parameter will be changed if + * psp - Double pointer to the SP, this parameter will be changed if * the corresponding LR address is successfully found. - * ppc - Double poninter to the PC, this parameter will be changed if + * ppc - Double pointer to the PC, this parameter will be changed if * the corresponding LR address is successfully found. * * Returned Value: @@ -402,7 +402,7 @@ static int backtrace_branch(void *limit, void *sp, * The up call up_backtrace_init_code_regions() will set the start * and end addresses of the customized program sections, this method * will help the different boards to configure the current text - * sections for some complicate platfroms + * sections for some complicate platforms. * * Input Parameters: * regions The start and end address of the text segment diff --git a/arch/arm/src/tlsr82/tc32/tc32_exception.S b/arch/arm/src/tlsr82/tc32/tc32_exception.S index 978ba6caff..a3780ff81d 100644 --- a/arch/arm/src/tlsr82/tc32/tc32_exception.S +++ b/arch/arm/src/tlsr82/tc32/tc32_exception.S @@ -156,14 +156,14 @@ tc32_exception: * Restore all the register according to R0 */ - /* Dsiable interrupt to protect the SVC mode */ + /* Disable interrupt to protect the SVC mode */ tloadr r2, _REG_IRQ_EN /* disable irq */ tmov r3, #0 /* disable irq */ tstorerb r3, [r2] /* disable irq */ /* Restore SVC mode SP (R13), SVC mode LR (R14, based saved PC) - * PC is not need to retore */ + * PC is not need to restore */ tloadr r2, [r0, #(4 * REG_SP)] tloadr r3, [r0, #(4 * REG_PC)] diff --git a/arch/arm/src/tlsr82/tlsr82_adc.c b/arch/arm/src/tlsr82/tlsr82_adc.c index 1514d0193e..a0e644511f 100644 --- a/arch/arm/src/tlsr82/tlsr82_adc.c +++ b/arch/arm/src/tlsr82/tlsr82_adc.c @@ -271,7 +271,7 @@ static inline void tlsr82_adc_dfifo_disable(void) static inline void tlsr82_adc_dfifo_config(uint8_t *buffer, size_t size) { /* Config the data buffer, so DFIFO2 can copy sample value to buffer - * DFIFO buffer address : only need low 16 bit, beacause the high 16 bit + * DFIFO buffer address : only need low 16 bit, because the high 16 bit * must be 0x0084 * DFIFO buffer size : DFIFO_ADC_SIZE_REG = n ==> 4 * (n + 1) size * DFIFO_ADC_SIZE_REG = size / 4 - 1 @@ -369,7 +369,7 @@ static void tlsr82_adc_clk_ctrl(bool enable) * * Description: * Config the adc to different mode, after this, the adc can start sample - * the voltage in the gpio pin (Base mode) or the chip volatge (Vbat + * the voltage in the gpio pin (Base mode) or the chip voltage (Vbat * channel mode). * Five configuration conditions: * 1. Same channel, do not need do not need re-configuration; @@ -429,7 +429,7 @@ static void tlsr82_adc_config(struct adc_chan_s *priv) * BASE mode, 1/8 */ - /* Enable misc chanel and set totaol length for sampling state be 2 */ + /* Enable misc channel and set totaol length for sampling state be 2 */ tlsr82_analog_write(ADC_CTRL0_REG, ADC_CTRL0_CHANEN_ENABLE | (2 << ADC_CTRL0_SAMPLEN_SHIFT)); @@ -537,7 +537,7 @@ static void tlsr82_adc_pin_config(uint32_t pinset) GPIO_SET_AS_GPIO(GPIO_GET(GROUP, cfg), GPIO_GET(PIN, cfg)); - /* Base mode pin config, diable input, disable output, output set low */ + /* Base mode pin config, disable input, disable output, output set low */ tlsr82_gpio_input_ctrl(cfg, false); @@ -828,7 +828,7 @@ static void tlsr82_adc_calibrate(struct adc_chan_s *priv) } } - ainfo("Calibration paramters:\n"); + ainfo("Calibration parameters:\n"); ainfo(" base two-point: gain=%d, offset=%d\n", priv->info->base_vref, priv->info->base_off); ainfo(" base one-point: vref=%lu\n", priv->info->base_vref); @@ -975,7 +975,7 @@ static void adc_reset(struct adc_dev_s *dev) tlsr82_adc_clk_ctrl(false); /* adc_reset() will be called in adc_register(), the same one adc - * device should be resetted only once. + * device should be reset only once. */ priv->info->registered = true; diff --git a/arch/arm/src/tlsr82/tlsr82_aes.c b/arch/arm/src/tlsr82/tlsr82_aes.c index 41cbcb3572..22c64db042 100644 --- a/arch/arm/src/tlsr82/tlsr82_aes.c +++ b/arch/arm/src/tlsr82/tlsr82_aes.c @@ -109,7 +109,7 @@ int tlsr82_aes_encrypt(const uint8_t *key, const uint8_t *data, while ((AES_CTRL_REG & AES_CTRL_CODEC_FINISHED) == 0); - /* Asign the result */ + /* Assign the result */ for (i = 0; i < 4; i++) { diff --git a/arch/arm/src/tlsr82/tlsr82_analog.c b/arch/arm/src/tlsr82/tlsr82_analog.c index 5d521f1ae7..858236f5ce 100644 --- a/arch/arm/src/tlsr82/tlsr82_analog.c +++ b/arch/arm/src/tlsr82/tlsr82_analog.c @@ -111,7 +111,7 @@ uint8_t locate_code(".ram_code") tlsr82_analog_read(uint8_t addr) tlsr82_analog_wait(); - /* Get the data and clear the analog contrl register */ + /* Get the data and clear the analog control register */ data = ANALOG_DATA_REG; ANALOG_CTRL_REG = 0; @@ -151,7 +151,7 @@ void locate_code(".ram_code") tlsr82_analog_write(uint8_t addr, uint8_t val) tlsr82_analog_wait(); - /* Clear the analog contrl register */ + /* Clear the analog control register */ ANALOG_CTRL_REG = 0; diff --git a/arch/arm/src/tlsr82/tlsr82_cpu.h b/arch/arm/src/tlsr82/tlsr82_cpu.h index e32f0e7c9e..fb60c23b0b 100644 --- a/arch/arm/src/tlsr82/tlsr82_cpu.h +++ b/arch/arm/src/tlsr82/tlsr82_cpu.h @@ -37,7 +37,7 @@ typedef enum { LDO_MODE = 0x40, /* LDO mode */ DCDC_LDO_MODE = 0x41, /* DCDC_LDO mode */ - DCDC_MODE = 0x43, /* DCDC mode (16pin chip not suported) */ + DCDC_MODE = 0x43, /* DCDC mode (16pin chip not supported) */ } power_mode_t; typedef enum diff --git a/arch/arm/src/tlsr82/tlsr82_flash.c b/arch/arm/src/tlsr82/tlsr82_flash.c index 26944bf789..08a121dea7 100644 --- a/arch/arm/src/tlsr82/tlsr82_flash.c +++ b/arch/arm/src/tlsr82/tlsr82_flash.c @@ -112,7 +112,7 @@ #define FLASH_CMD_ERASE_SECTOR 0x20 #define FLASH_CMD_ERASE_SECURITY_REG 0x44 -/* Read the flash uniqe id command +/* Read the flash unique id command * FLASH_CMD_READ_UID1: GD_PUYA_ZB_TH * FLASH_CMD_READ_UID2: XTX */ @@ -151,7 +151,7 @@ /* When enable the ble sdk, we can not disable the system timer * and rf(ble) interrupt to avoid loss of ble packets. We also * need to call sched_lock()/sched_unlock() to avoid task switch - * beacause sem_post() will be called in ble interrupt (Task + * because sem_post() will be called in ble interrupt (Task * switch may leads that the chip execute code in flash during * the operation of flash). */ @@ -245,7 +245,7 @@ static const uint32_t g_support_mid_num = * Name: flash_send_cmd * * Description: - * Configurate the gpio drive strength be high/low. + * Configure the gpio drive strength be high/low. * * Input Parameters: * cmd - GPIO config information @@ -740,7 +740,7 @@ void tlsr82_flash_calibrate(uint32_t mid) if ((0xffff == cali_data) || (0 != (cali_data & 0xf8f8))) { - /* No flash calibration paramters */ + /* No flash calibration parameters */ finfo("No flash calibration parameters\n"); @@ -783,7 +783,7 @@ void tlsr82_flash_calibrate(uint32_t mid) if (0xff == cali_data) { - /* No flash calibration paramters */ + /* No flash calibration parameters */ finfo("No flash calibration parameters\n"); diff --git a/arch/arm/src/tlsr82/tlsr82_flash_mtd.c b/arch/arm/src/tlsr82/tlsr82_flash_mtd.c index 923de2f89b..10f0f4ea38 100644 --- a/arch/arm/src/tlsr82/tlsr82_flash_mtd.c +++ b/arch/arm/src/tlsr82/tlsr82_flash_mtd.c @@ -134,7 +134,7 @@ struct tlsr82_flash_dev_s { struct mtd_dev_s mtd; /* MTD interface */ uint32_t baseaddr; /* mtd flash start address */ - uint32_t size; /* avaliable size for MTD */ + uint32_t size; /* available size for MTD */ uint16_t nsectors; /* Number of erase sectors */ uint16_t sectorsize; /* Size of one sector */ uint16_t pagesize; /* Size of one page */ @@ -433,7 +433,7 @@ static int tlsr82_flash_test(struct tlsr82_flash_dev_s *priv) if (memcmp(flash_read_buffer, flash_buffer, TLSR82_PAGE_SIZE) != 0) { - ferr(" Flash write compre is not equal, page_i=%d\n", i); + ferr(" Flash write compare is not equal, page_i=%d\n", i); tlsr82_flash_print("Write buffer data:", flash_buffer, TLSR82_PAGE_SIZE); tlsr82_flash_print("Read buffer data:", flash_read_buffer, @@ -603,7 +603,7 @@ static int tlsr82_flash_test(struct tlsr82_flash_dev_s *priv) if (memcmp(flash_read_buffer, flash_buffer, TLSR82_PAGE_SIZE) != 0) { - ferr(" Flash write compre is not equal, page_i=%d\n", i); + ferr(" Flash write compare is not equal, page_i=%d\n", i); tlsr82_flash_print("Write buffer data:", flash_buffer, TLSR82_PAGE_SIZE); tlsr82_flash_print("Read buffer data:", flash_read_buffer, @@ -736,7 +736,7 @@ static ssize_t tlsr82_flash_write (struct mtd_dev_s *dev, off_t offset, do { - /* The allow length is the max allow write lentgh that not cross page */ + /* The allow length is the max allow write length that not cross page */ allow_len = TLSR82_PAGE_SIZE - (addr & (TLSR82_PAGE_SIZE - 1)); write_len = MIN(nbytes, allow_len); @@ -864,7 +864,7 @@ static int tlsr82_flash_ioctl(struct mtd_dev_s *dev, int cmd, * * Parameter: * offset - offset from 0 of internal flash - * size - avaiable size for NVM + * size - available size for NVM * ****************************************************************************/ diff --git a/arch/arm/src/tlsr82/tlsr82_gpio.c b/arch/arm/src/tlsr82/tlsr82_gpio.c index 4e0fea4499..75e8bdf51c 100644 --- a/arch/arm/src/tlsr82/tlsr82_gpio.c +++ b/arch/arm/src/tlsr82/tlsr82_gpio.c @@ -144,7 +144,7 @@ static void tlsr82_gpio_dumpregs(const char *msg) * Name: tlsr82_gpio_ds_ctrl * * Description: - * Configurate the gpio drive strength be high/low. + * Configure the gpio drive strength be high/low. * * Input Parameters: * gpio_cfg_t - GPIO config information @@ -200,7 +200,7 @@ static void tlsr82_gpio_ds_ctrl(gpio_cfg_t cfg, uint8_t ds) * Name: tlsr82_gpio_pol_ctrl * * Description: - * Configurate the gpio interrupt polarity (interruot trigger edge). + * Configure the gpio interrupt polarity (interrupt trigger edge). * * Input Parameters: * gpio_cfg_t - GPIO config information @@ -481,7 +481,7 @@ void tlsr82_gpio_output_ctrl(gpio_cfg_t cfg, bool enable) * Name: tlsr82_gpio_pupd_ctrl * * Description: - * Configurate the gpio pull-up/pull-down. + * Configure the gpio pull-up/pull-down. * * Input Parameters: * gpio_cfg_t - GPIO config information @@ -779,7 +779,7 @@ int tlsr82_gpioirqconfig(gpio_cfg_t cfg, xcpt_t func, void *arg) } else { - /* Find an approprite callback object */ + /* Find an appropriate callback object */ for (i = 0; i < CONFIG_GPIO_IRQ_MAX_NUM; ++i) { @@ -787,7 +787,7 @@ int tlsr82_gpioirqconfig(gpio_cfg_t cfg, xcpt_t func, void *arg) gpio_irq_cbs[i].callback == NULL) { /* 1. Re-config the same pin before unconfig it, just direct - * use pervious callback object. + * use previous callback object. * 2. New pinset, use a new callback object. */ @@ -875,19 +875,19 @@ void tlsr82_gpioirqenable(gpio_cfg_t cfg) } else if (irqmode == GPIO_IRQ_M0_VAL) { - /* Set M0, the timer interrupt is controled by timer */ + /* Set M0, the timer interrupt is controlled by timer */ BM_SET(GPIO_IRQ_M0_REG(group), BIT(pin)); } else if (irqmode == GPIO_IRQ_M1_VAL) { - /* Set M1, the timer interrupt is controled by timer */ + /* Set M1, the timer interrupt is controlled by timer */ BM_SET(GPIO_IRQ_M1_REG(group), BIT(pin)); } else if (irqmode == GPIO_IRQ_M2_VAL) { - /* Set M2, the timer interrupt is controled by timer */ + /* Set M2, the timer interrupt is controlled by timer */ BM_SET(GPIO_IRQ_M2_REG(group), BIT(pin)); } diff --git a/arch/arm/src/tlsr82/tlsr82_gpio_cfg.c b/arch/arm/src/tlsr82/tlsr82_gpio_cfg.c index f062043677..13b556499c 100644 --- a/arch/arm/src/tlsr82/tlsr82_gpio_cfg.c +++ b/arch/arm/src/tlsr82/tlsr82_gpio_cfg.c @@ -143,7 +143,7 @@ int tlsr82_gpio_cfg_check(uint32_t cfg, uint32_t mux) pinnum = GPIO_PIN2NUM(cfg); cfg_af = GPIO_GET(AF, cfg); - /* ADC and LPC is not configed by gpio mux register */ + /* ADC and LPC is not configured by gpio mux register */ if ((mux == MUX_ADC) || (mux == MUX_LPC)) { diff --git a/arch/arm/src/tlsr82/tlsr82_pwm.c b/arch/arm/src/tlsr82/tlsr82_pwm.c index f0e742470e..3c4db69f29 100644 --- a/arch/arm/src/tlsr82/tlsr82_pwm.c +++ b/arch/arm/src/tlsr82/tlsr82_pwm.c @@ -460,7 +460,7 @@ static void pwm_enable(struct tlsr82_pwmtimer_s *priv, bool en) * Name: pwm_cfg_check * * Description: - * This method is called when the driver intialize. This function will + * This method is called when the driver initialize. This function will * check the pincfg, if pincfg is not valid or current pin can not be used * as PWM, this function will call * PANIC() to assert here. @@ -699,7 +699,7 @@ static int pwm_stop(struct pwm_lowerhalf_s *dev) PWM_INT_CLEAR(priv->id); #ifdef CONFIG_TLSR82_PWM0_PULSECOUNT - /* Diable and clear PWM0 count interrupt flag */ + /* Disable and clear PWM0 count interrupt flag */ if (priv->count > 0) { diff --git a/arch/arm/src/tlsr82/tlsr82_serial.c b/arch/arm/src/tlsr82/tlsr82_serial.c index 597c3f491d..8ce9393b86 100644 --- a/arch/arm/src/tlsr82/tlsr82_serial.c +++ b/arch/arm/src/tlsr82/tlsr82_serial.c @@ -399,7 +399,7 @@ static inline void uart_reset(int uart_num) * Name: uart_get_rxfifo_num * * Description: - * Get the recieved data numbers in the rx fifo. + * Get the received data numbers in the rx fifo. * * Parameters: * uart_num - the uart hardware index @@ -447,8 +447,8 @@ static inline uint8_t uart_get_txfifo_num(int uart_num) * UART_IRQ_RXBUF * * Returned Values: - * interrupt status: 0, interrupt not occured - * 1, interrupt occured + * interrupt status: 0, interrupt not occurred + * 1, interrupt occurred * ****************************************************************************/ @@ -806,7 +806,7 @@ static void uart_baudrate_config(uint32_t baudrate) int tmp; int min; - /* Caculate the uart clkdiv and bit width + /* Calculate the uart clkdiv and bit width * baudrate = CPU_CLK / ((clkdiv + 1) * (bwpc + 1)), 3 <= bwpc <= 15 */ @@ -827,10 +827,10 @@ static void uart_baudrate_config(uint32_t baudrate) tmp = CPU_CLK / clkdivp1_arr[j]; tmp = abs(tmp / (i + 1) - baudrate); - /* Get the clkdiv and bwpc that make the smallest difference - * between expected baudrate and real baudrate, mealwhile the - * clkdiv should be smaller as soon as possible to get a larger - * uart clock, whick leads more precise baudrate. + /* Get the clkdiv and bwpc that causes the smallest difference + * between expected baudrate and real baudrate, meanwhile the + * clkdiv should be as small as possible to get a larger + * UART clock, which leads to a more precise baudrate. */ if ((tmp == min && i > bwpc) || (tmp < min)) @@ -906,7 +906,7 @@ static void uart_parity_config(int parity) * * Parameters: * stopbits - 0, one stop bit - * - 1, one and a halp stop bit + * - 1, one and a half stop bit * - 2, two stop bits * * Returned Values: @@ -1033,7 +1033,7 @@ static int tlsr82_uart_setup(struct uart_dev_s *dev) uart_parity_config(priv->parity); uart_stopbits_config(priv->stopbits); - /* Diable uart rx_buff and tx_buff irq */ + /* Disable uart rx_buff and tx_buff irq */ uart_irq_rx_enable(false); uart_irq_tx_enable(false); @@ -1630,7 +1630,7 @@ void arm_serialinit(void) * Description: * Performs the low level UART initialization early in * debug so that the serial console will be available - * during bootup. This must be called before arm_serialinit. + * during boot up. This must be called before arm_serialinit. * ****************************************************************************/ diff --git a/arch/arm/src/tlsr82/tlsr82_spi_console.c b/arch/arm/src/tlsr82/tlsr82_spi_console.c index 6de71dc6b5..712293fbfe 100644 --- a/arch/arm/src/tlsr82/tlsr82_spi_console.c +++ b/arch/arm/src/tlsr82/tlsr82_spi_console.c @@ -318,7 +318,7 @@ void spi_console_init(void) * * Description: * Provide priority, low-level access to support OS debug - * writes. When the SPI is used for syslog ouput, the up_putc() should be + * writes. When the SPI is used for syslog output, the up_putc() should be * implemented by spi. * ****************************************************************************/ diff --git a/arch/arm/src/tms570/hardware/tms570_sci.h b/arch/arm/src/tms570/hardware/tms570_sci.h index 0782fe57b9..f2b6b26766 100644 --- a/arch/arm/src/tms570/hardware/tms570_sci.h +++ b/arch/arm/src/tms570/hardware/tms570_sci.h @@ -225,7 +225,7 @@ #define SCI_INT_TIMEOUT (1 << 4) /* Bit 4: Timeout interrupt */ #define SCI_INT_TOAWUS (1 << 6) /* Bit 6: Timeout after wakeup signal interrupt */ #define SCI_INT_TOA3WUS (1 << 7) /* Bit 7: Timeout after 2 Wakeup signls interrupt */ -#define SCI_INT_TX (1 << 8) /* Bit 8: Tranmitter interrupt */ +#define SCI_INT_TX (1 << 8) /* Bit 8: Transmitter interrupt */ #define SCI_INT_RX (1 << 9) /* Bit 9: Receiver interrupt */ #define SCI_INT_ID (1 << 13) /* Bit 13: Identification interrupt */ #define SCI_INT_PE (1 << 24) /* Bit 24: Parity error interrupt */ @@ -282,7 +282,7 @@ # define SCI_INTVECT_OE (9) /* Overrun error interrupt */ # define SCI_INTVECT_BE (10) /* Bit error interrupt */ # define SCI_INTVECT_RX (11) /* Receive interrupt */ -# define SCI_INTVECT_TX (12) /* Tranmit interrupt */ +# define SCI_INTVECT_TX (12) /* Transmit interrupt */ # define SCI_INTVECT_NRE (13) /* No response error interrupt */ # define SCI_INTVECT_TOAWUS (14) /* Timeout after wakeup signal interrupt */ # define SCI_INTVECT_TOA3WUS (15) /* Timeout after 2 Wakeup signls interrupt */ diff --git a/arch/arm/src/tms570/tms570_clockconfig.c b/arch/arm/src/tms570/tms570_clockconfig.c index 0badf2fea6..961493176d 100644 --- a/arch/arm/src/tms570/tms570_clockconfig.c +++ b/arch/arm/src/tms570/tms570_clockconfig.c @@ -339,7 +339,7 @@ static void tms570_pll_setup(void) * NR = REFCLKDIV+1 * Fintclk = Fclkin / NR * - * PLLMUL controls multipler on divided input clock (Fintclk): + * PLLMUL controls multiplier on divided input clock (Fintclk): * * Non-modulated: * NF = (PLLMUL + 256) / 256 diff --git a/arch/arm/src/tms570/tms570_lowputc.c b/arch/arm/src/tms570/tms570_lowputc.c index 059e1aee08..1762ac7cbe 100644 --- a/arch/arm/src/tms570/tms570_lowputc.c +++ b/arch/arm/src/tms570/tms570_lowputc.c @@ -299,7 +299,7 @@ int tms570_sci_configure(uint32_t base, * STOP=? Depends on configuration settings * CLOCK=1 The internal SCICLK is the clock source * LIN=0 LIN mode is disabled - * SWRST=0 SCI is initiailized and held in reset state + * SWRST=0 SCI is initialized and held in reset state * SLEEP=0 Sleep mode is disabled * ADAPT=0 Automatic baud rate adjustment is disabled * MBUF=0 The multi-buffer mode is disabled. diff --git a/arch/arm/src/tms570/tms570_serial.c b/arch/arm/src/tms570/tms570_serial.c index f39ad502ff..979905b0b0 100644 --- a/arch/arm/src/tms570/tms570_serial.c +++ b/arch/arm/src/tms570/tms570_serial.c @@ -469,7 +469,7 @@ static int tms570_interrupt(int irq, void *context, void *arg) } break; - case SCI_INTVECT_TX: /* Tranmit interrupt */ + case SCI_INTVECT_TX: /* Transmit interrupt */ { /* Transmit data register available ... * process outgoing bytes diff --git a/arch/arm/src/xmc4/hardware/xmc4_ethernet.h b/arch/arm/src/xmc4/hardware/xmc4_ethernet.h index 1eed60a653..5269db12a0 100644 --- a/arch/arm/src/xmc4/hardware/xmc4_ethernet.h +++ b/arch/arm/src/xmc4/hardware/xmc4_ethernet.h @@ -191,7 +191,7 @@ #define XMC4_ETH_TRANSMIT_POLL_DEMAND_OFFSET 0x1004 /* Transmit Poll Demand Register */ #define XMC4_ETH_RECEIVE_POLL_DEMAND_OFFSET 0x1008 /* Receive Poll Demand Register */ #define XMC4_ETH_RECEIVE_DESCRIPTOR_LIST_ADDRESS_OFFSET 0x100c /* Receive Descriptor Address Register */ -#define XMC4_ETH_TRANSMIT_DESCRIPTOR_LIST_ADDRESS_OFFSET 0x1010 /* Transmit descripter Address Register */ +#define XMC4_ETH_TRANSMIT_DESCRIPTOR_LIST_ADDRESS_OFFSET 0x1010 /* Transmit descriptor Address Register */ #define XMC4_ETH_STATUS_OFFSET 0x1014 /* Status Register */ #define XMC4_ETH_OPERATION_MODE_OFFSET 0x1018 /* Operation Mode Register */ #define XMC4_ETH_INTERRUPT_ENABLE_OFFSET 0x101c /* Interrupt Enable Register */ @@ -732,7 +732,7 @@ /* Receive Descriptor Address Register */ #define ETH_RECEIVE_DESCRIPTOR_LIST_ADDRESS_ -/* Transmit descripter Address Register */ +/* Transmit descriptor Address Register */ #define ETH_TRANSMIT_DESCRIPTOR_LIST_ADDRESS_ /* Status Register */ diff --git a/arch/arm/src/xmc4/hardware/xmc4_posif.h b/arch/arm/src/xmc4/hardware/xmc4_posif.h index da4e40515b..04334a486b 100644 --- a/arch/arm/src/xmc4/hardware/xmc4_posif.h +++ b/arch/arm/src/xmc4/hardware/xmc4_posif.h @@ -68,12 +68,12 @@ /* Hall Sensor Mode Registers */ #define XMC4_POSIF_HALP_OFFSET 0x0030 /* Hall Current and Expected patterns */ -#define XMC4_POSIF_HALPS_OFFSET 0x0034 /* Hall Current and Expected Shadow paterns */ +#define XMC4_POSIF_HALPS_OFFSET 0x0034 /* Hall Current and Expected Shadow patterns */ /* Multi-Channel Mode Registers */ -#define XMC4_POSIF_MCM_OFFSET 0x0040 /* Multi-Channel Mode Patern */ -#define XMC4_POSIF_MCSM_OFFSET 0x0044 /* Multi-Channel Mode Shadow Patern */ +#define XMC4_POSIF_MCM_OFFSET 0x0040 /* Multi-Channel Mode Pattern */ +#define XMC4_POSIF_MCSM_OFFSET 0x0044 /* Multi-Channel Mode Shadow Pattern */ #define XMC4_POSIF_MCMS_OFFSET 0x0048 /* Multi-Channel Mode Control Set */ #define XMC4_POSIF_MCMC_OFFSET 0x004C /* Multi-Channel Mode Control Clear */ #define XMC4_POSIF_MCMF_OFFSET 0x0050 /* Multi-Channel Mode Flag Status */ @@ -100,10 +100,10 @@ #define XMC4_POSIF0_MIDR (XMC4_POSIF0_BASE + XMC4_POSIF_MIDR_OFFSET) /* Module identification register */ #define XMC4_POSIF0_HALP (XMC4_POSIF0_BASE + XMC4_POSIF_HALP_OFFSET) /* Hall Current and Expected patterns */ -#define XMC4_POSIF0_HALPS (XMC4_POSIF0_BASE + XMC4_POSIF_HALPS_OFFSET) /* Hall Current and Expected Shadow paterns */ +#define XMC4_POSIF0_HALPS (XMC4_POSIF0_BASE + XMC4_POSIF_HALPS_OFFSET) /* Hall Current and Expected Shadow patterns */ -#define XMC4_POSIF0_MCM (XMC4_POSIF0_BASE + XMC4_POSIF_MCM_OFFSET) /* Multi-Channel Mode Patern */ -#define XMC4_POSIF0_MCSM (XMC4_POSIF0_BASE + XMC4_POSIF_MCSM_OFFSET) /* Multi-Channel Mode Shadow Patern */ +#define XMC4_POSIF0_MCM (XMC4_POSIF0_BASE + XMC4_POSIF_MCM_OFFSET) /* Multi-Channel Mode Pattern */ +#define XMC4_POSIF0_MCSM (XMC4_POSIF0_BASE + XMC4_POSIF_MCSM_OFFSET) /* Multi-Channel Mode Shadow Pattern */ #define XMC4_POSIF0_MCMS (XMC4_POSIF0_BASE + XMC4_POSIF_MCMS_OFFSET) /* Multi-Channel Mode Control Set */ #define XMC4_POSIF0_MCMC (XMC4_POSIF0_BASE + XMC4_POSIF_MCMC_OFFSET) /* Multi-Channel Mode Control Clear */ #define XMC4_POSIF0_MCMF (XMC4_POSIF0_BASE + XMC4_POSIF_MCMF_OFFSET) /* Multi-Channel Mode Flag Status */ @@ -126,10 +126,10 @@ #define XMC4_POSIF1_MIDR (XMC4_POSIF1_BASE + XMC4_POSIF_MIDR_OFFSET) /* Module identification register */ #define XMC4_POSIF1_HALP (XMC4_POSIF1_BASE + XMC4_POSIF_HALP_OFFSET) /* Hall Current and Expected patterns */ -#define XMC4_POSIF1_HALPS (XMC4_POSIF1_BASE + XMC4_POSIF_HALPS_OFFSET) /* Hall Current and Expected Shadow paterns */ +#define XMC4_POSIF1_HALPS (XMC4_POSIF1_BASE + XMC4_POSIF_HALPS_OFFSET) /* Hall Current and Expected Shadow patterns */ -#define XMC4_POSIF1_MCM (XMC4_POSIF1_BASE + XMC4_POSIF_MCM_OFFSET) /* Multi-Channel Mode Patern */ -#define XMC4_POSIF1_MCSM (XMC4_POSIF1_BASE + XMC4_POSIF_MCSM_OFFSET) /* Multi-Channel Mode Shadow Patern */ +#define XMC4_POSIF1_MCM (XMC4_POSIF1_BASE + XMC4_POSIF_MCM_OFFSET) /* Multi-Channel Mode Pattern */ +#define XMC4_POSIF1_MCSM (XMC4_POSIF1_BASE + XMC4_POSIF_MCSM_OFFSET) /* Multi-Channel Mode Shadow Pattern */ #define XMC4_POSIF1_MCMS (XMC4_POSIF1_BASE + XMC4_POSIF_MCMS_OFFSET) /* Multi-Channel Mode Control Set */ #define XMC4_POSIF1_MCMC (XMC4_POSIF1_BASE + XMC4_POSIF_MCMC_OFFSET) /* Multi-Channel Mode Control Clear */ #define XMC4_POSIF1_MCMF (XMC4_POSIF1_BASE + XMC4_POSIF_MCMF_OFFSET) /* Multi-Channel Mode Flag Status */ diff --git a/arch/arm/src/xmc4/hardware/xmc4_vadc.h b/arch/arm/src/xmc4/hardware/xmc4_vadc.h index 9aaea47af8..5eb04f69ab 100644 --- a/arch/arm/src/xmc4/hardware/xmc4_vadc.h +++ b/arch/arm/src/xmc4/hardware/xmc4_vadc.h @@ -190,7 +190,7 @@ typedef struct /* (@ 0x40004400) */ volatile uint32_t RESD[16]; /* (@ 0x40004780) Result Register, Debug */ } vadc_group_t; -/* Define pointers for VADC global and group stuctures */ +/* Define pointers for VADC global and group structures */ #define VADC ((vadc_global_t *) XMC4_VADC_BASE) #define VADC_G0 ((vadc_group_t *) XMC4_VADC_G0_BASE) #define VADC_G1 ((vadc_group_t *) XMC4_VADC_G1_BASE) diff --git a/arch/arm/src/xmc4/xmc4_ccu4.c b/arch/arm/src/xmc4/xmc4_ccu4.c index 9e0a783281..1a58e2f7d7 100644 --- a/arch/arm/src/xmc4/xmc4_ccu4.c +++ b/arch/arm/src/xmc4/xmc4_ccu4.c @@ -24,7 +24,7 @@ * XMC CCU Driver * * For now, this file contains only helper methods mandatory for xmc tickless - * feature. Contibutions are welcomed. + * feature. Contributions are welcome. * ****************************************************************************/ diff --git a/arch/arm/src/xmc4/xmc4_i2c.c b/arch/arm/src/xmc4/xmc4_i2c.c index 6ae40a73d4..4a01fb7202 100644 --- a/arch/arm/src/xmc4/xmc4_i2c.c +++ b/arch/arm/src/xmc4/xmc4_i2c.c @@ -76,7 +76,7 @@ #define XMC_I2C_CMD_READ (1U) #define I2C_WORDLENGTH (7U) /* 8 bits word length */ -#define I2C_TRM_MODE (3U) /* Shift and transfert config */ +#define I2C_TRM_MODE (3U) /* Shift and transfer config */ #define I2C_TDV_SET (1U) /* A transmission of data in TBUF \ * can be started if TDV = 1 */ @@ -546,7 +546,7 @@ static bool i2c_get_status_flag(struct xmc4_i2cdev_s *priv, * Name: i2c_clear_status_flag * * Description: - * Clear the flags from PSR register by writting in PSCR register. + * Clear the flags from PSR register by writing in PSCR register. * * Returned Value: * Zero on success; a negated errno value on failure @@ -633,7 +633,7 @@ static void i2c_fill_transmit_buffer(struct xmc4_i2cdev_s *priv, * Get the data word from receive buffer. * * Returned Value: - * Recived data word in uint8_t. + * Received data word in uint8_t. * *****************************************************************************/ @@ -660,7 +660,7 @@ static uint8_t i2c_get_receive_buffer(struct xmc4_i2cdev_s *priv) * Name: i2c_start * * Description: - * Start and send an I2C frame with the given slave adress. + * Start and send an I2C frame with the given slave address. * Send the following on bus : [START/RESTART A6 A5 A4 A3 A2 A1 A0 R/W] * *****************************************************************************/ @@ -815,7 +815,7 @@ static int i2c_transfer(struct i2c_master_s *dev, nxmutex_lock(&priv->lock); - /* Enter critical section to avoid interrupts during i2c transfert */ + /* Enter critical section to avoid interrupts during i2c transfer */ irqstate_t state = enter_critical_section(); @@ -914,7 +914,7 @@ static int i2c_transfer(struct i2c_master_s *dev, bool should_stop = !(message_has_no_stop || next_message_has_no_start); - /* TODO : Should you stop when last msg and overide flags ? */ + /* TODO : Should you stop when last msg and override flags ? */ if (should_stop) { diff --git a/arch/arm/src/xmc4/xmc4_lowputc.h b/arch/arm/src/xmc4/xmc4_lowputc.h index f70a0f0401..1febe1cad5 100644 --- a/arch/arm/src/xmc4/xmc4_lowputc.h +++ b/arch/arm/src/xmc4/xmc4_lowputc.h @@ -74,7 +74,7 @@ void xmc4_lowsetup(void); * * Description: * Performs the low level UART initialization early in debug so that the - * serial console will be available during bootup. This must be called + * serial console will be available during boot up. This must be called * before xmc4_serialinit. NOTE: This function depends on GPIO pin * configuration performed in xmc4_lowsetup() and main clock initialization * performed in xmc4_clock_configure(). diff --git a/arch/arm/src/xmc4/xmc4_pwm.c b/arch/arm/src/xmc4/xmc4_pwm.c index 8302f386b0..4376d7e490 100644 --- a/arch/arm/src/xmc4/xmc4_pwm.c +++ b/arch/arm/src/xmc4/xmc4_pwm.c @@ -395,7 +395,7 @@ static int pwm_set_period_match(struct xmc4_pwm_s *priv, uint16_t period_val) * Name: pwm_set_compare_match * * Description: - * Set the comapre match register (CC4yCRS.CRS). + * Set the compare match register (CC4yCRS.CRS). * Must call pwm_shadow_transfert() after. * * Returned Value: @@ -452,7 +452,7 @@ static int pwm_set_passive_level(struct xmc4_pwm_s *priv, uint8_t level) * Name: pwm_shadow_transfert * * Description: - * Enable the transfert of the CRS, PRS and PSL registers for the next + * Enable the transfer of the CRS, PRS and PSL registers for the next * period. Must be called if one of these register is changed. * Must call pwm_shadow_transfert() after. * @@ -915,7 +915,7 @@ static int pwm_timer(struct xmc4_pwm_s *priv, const struct pwm_info_s *info) if (new_prescaler == priv->prescaler) { - /* Prescaller doesn't change, update shadow transfert */ + /* Prescaller doesn't change, update shadow transfer */ pwm_set_period_match(priv, prs); pwm_set_compare_match(priv, crs); @@ -960,7 +960,7 @@ static int pwm_timer(struct xmc4_pwm_s *priv, const struct pwm_info_s *info) } else { - /* Frequency doesn't change, update shadow transfert */ + /* Frequency doesn't change, update shadow transfer */ pwm_set_compare_match(priv, crs); pwm_set_passive_level(priv, info->cpol); diff --git a/arch/arm/src/xmc4/xmc4_serial.c b/arch/arm/src/xmc4/xmc4_serial.c index 9b1d161601..10e7388fab 100644 --- a/arch/arm/src/xmc4/xmc4_serial.c +++ b/arch/arm/src/xmc4/xmc4_serial.c @@ -1039,7 +1039,7 @@ static bool xmc4_txempty(struct uart_dev_s *dev) * * Description: * Performs the low level UART initialization early in debug so that the - * serial console will be available during bootup. This must be called + * serial console will be available during boot up. This must be called * before xmc4_serialinit. NOTE: This function depends on GPIO pin * configuration performed in xmc4_lowsetup() and main clock initialization * performed in xmc4_clock_configure(). diff --git a/arch/arm/src/xmc4/xmc4_spi.c b/arch/arm/src/xmc4/xmc4_spi.c index 4290860173..b2383ff94b 100644 --- a/arch/arm/src/xmc4/xmc4_spi.c +++ b/arch/arm/src/xmc4/xmc4_spi.c @@ -574,7 +574,7 @@ static struct xmc4_spidev_s g_spi5dev = * * Returned Value: * true: This is the first register access of this type. - * flase: This is the same as the preceding register access. + * false: This is the same as the preceding register access. * ****************************************************************************/ diff --git a/arch/arm/src/xmc4/xmc4_tickless.c b/arch/arm/src/xmc4/xmc4_tickless.c index de98114c45..c05a9c3a2a 100644 --- a/arch/arm/src/xmc4/xmc4_tickless.c +++ b/arch/arm/src/xmc4/xmc4_tickless.c @@ -240,7 +240,7 @@ void up_timer_initialize(void) /* Initialize Interval Timer * - * Ths timer is configured to be a oneshot timer, that has + * The timer is configured to be a oneshot timer, that has * a resolution that matches the USEC_PER_TICK, and * will be started in up_timer_start and uses its period * (not compare value) to trigger an interrupt. diff --git a/arch/arm/src/xmc4/xmc4_vadc.c b/arch/arm/src/xmc4/xmc4_vadc.c index 8cc6572b54..fcdd58dec1 100644 --- a/arch/arm/src/xmc4/xmc4_vadc.c +++ b/arch/arm/src/xmc4/xmc4_vadc.c @@ -486,7 +486,7 @@ int xmc4_vadc_group_channel_initialize(vadc_group_t *const group_ptr, const uint * * Description: * Adds a channel to the background scan sequence. The pending - * register are updated only after a new load event occured. + * register are updated only after a new load event occurred. * Configures the register bit fields of BRSSEL. * * Returned Value: diff --git a/arch/arm/src/xmc4/xmc4_vadc.h b/arch/arm/src/xmc4/xmc4_vadc.h index 1b2b9d9ed9..bf74a353da 100644 --- a/arch/arm/src/xmc4/xmc4_vadc.h +++ b/arch/arm/src/xmc4/xmc4_vadc.h @@ -587,7 +587,7 @@ int xmc4_vadc_group_channel_initialize(vadc_group_t *const group_ptr, * * Description: * Adds a channel to the background scan sequence. The pending - * register are updated only after a new load event occured. + * register are updated only after a new load event occurred. * Configures the register bit fields of BRSSEL. * * Returned Value: diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index f1cecab469..913e446937 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -220,7 +220,7 @@ config ARCH_HAVE_EL3 ---help--- Some ARM aarch64 Cortex-family processors only supports EL0~El2(eg. Cortex-R82). For these Processors, the code - runing at EL3 is not necessary and system register for EL3 + running at EL3 is not necessary and system register for EL3 is not accessible config ARCH_HAVE_CLUSTER_PMU @@ -267,7 +267,7 @@ config ARCH_EARLY_PRINT The aarch64 have EL0~El3 execute level and NS/S (security state), the NuttX should be execute at EL1 in NS(ARmv8-A) or S(ARmv8-R) state. but booting NuttX have different ELs and state while with - different platform, if NuttX runing at wrong ELs or state it will + different platform, if NuttX running at wrong ELs or state it will not normal anymore. So we need to print something in arm64_head.S to debug this situation. Enabling this option will need to implement arm64_earlyprintinit and @@ -466,7 +466,7 @@ config ARM64_SEMIHOSTING_HOSTFS_CACHE_COHERENCE bool "Cache coherence in semihosting hostfs" depends on ARCH_DCACHE ---help--- - Flush & Invalidte cache before & after bkpt instruction. + Flush & Invalidate cache before & after bkpt instruction. endif # ARM64_SEMIHOSTING_HOSTFS diff --git a/arch/arm64/include/imx9/imx93_irq.h b/arch/arm64/include/imx9/imx93_irq.h index 90b7c17835..b703622e2c 100644 --- a/arch/arm64/include/imx9/imx93_irq.h +++ b/arch/arm64/include/imx9/imx93_irq.h @@ -202,8 +202,8 @@ #define IMX9_IRQ_RESERVED208 (IMX9_IRQ_EXT + 176) /* LCDIF Sync Interrupt */ #define IMX9_IRQ_DSI (IMX9_IRQ_EXT + 177) /* MIPI DSI Interrupt Request */ #define IMX9_IRQ_RESERVED210 (IMX9_IRQ_EXT + 178) /* Machine learning processor interrupt */ -#define IMX9_IRQ_ENET_MAC0_RX_TX_D ONE1 (IMX9_IRQ_EXT + 179) /* MAC 0 Receive/ Trasmit Frame/ Buffer Done */ -#define IMX9_IRQ_ENET_MAC0_RX_TX_D ONE2 (IMX9_IRQ_EXT + 180) /* MAC 0 Receive/ Trasmit Frame/ Buffer Done */ +#define IMX9_IRQ_ENET_MAC0_RX_TX_D ONE1 (IMX9_IRQ_EXT + 179) /* MAC 0 Receive/ Transmit Frame/ Buffer Done */ +#define IMX9_IRQ_ENET_MAC0_RX_TX_D ONE2 (IMX9_IRQ_EXT + 180) /* MAC 0 Receive/ Transmit Frame/ Buffer Done */ #define IMX9_IRQ_ENET (IMX9_IRQ_EXT + 181) /* MAC 0 IRQ */ #define IMX9_IRQ_ENET_1588 (IMX9_IRQ_EXT + 182) /* MAC 0 1588 Timer Interrupt - synchronous */ #define IMX9_IRQ_ENET_QOS_PMT (IMX9_IRQ_EXT + 183) /* ENET QOS PMT interrupt */ diff --git a/arch/arm64/include/zynq-mpsoc/irq.h b/arch/arm64/include/zynq-mpsoc/irq.h index a04243f55f..89a4522eed 100644 --- a/arch/arm64/include/zynq-mpsoc/irq.h +++ b/arch/arm64/include/zynq-mpsoc/irq.h @@ -54,7 +54,7 @@ #define ZYNQ_MPSOC_IRQ_CAN1 56 /* CAN1 controller IRQ */ #define ZYNQ_MPSOC_IRQ_LPD_APM 57 /* LPD and OCM APM IRQ */ #define ZYNQ_MPSOC_IRQ_RTC_ALARM 58 /* RTC alarm IRQ */ -#define ZYNQ_MPSOC_IRQ_RTC_SECONDS 59 /* RTC sceond IRQ */ +#define ZYNQ_MPSOC_IRQ_RTC_SECONDS 59 /* RTC second IRQ */ #define ZYNQ_MPSOC_IRQ_CLKMON 60 /* LPD clock test IRQ */ #define ZYNQ_MPSOC_IRQ_IPI_CH7 61 /* IPI channel 7 IRQ */ #define ZYNQ_MPSOC_IRQ_IPI_CH8 62 /* IPI channel 8 IRQ */ diff --git a/arch/arm64/src/a64/a64_mipi_dsi.c b/arch/arm64/src/a64/a64_mipi_dsi.c index 6322ec0560..41c8779bb3 100644 --- a/arch/arm64/src/a64/a64_mipi_dsi.c +++ b/arch/arm64/src/a64/a64_mipi_dsi.c @@ -723,9 +723,9 @@ int a64_mipi_dsi_enable(void) /* DSI Pixel Package Register 3 (A31 Page 849) * Set CRC_Init_LineN (Bits 16 to 31) to 0xffff - * (CRC initial to this value in transmitions except 1st one) + * (CRC initial to this value in transmissions except 1st one) * Set CRC_Init_Line0 (Bits 0 to 15) to 0xffff - * (CRC initial to this value in 1st transmition every frame) + * (CRC initial to this value in 1st transmission every frame) */ dsi_pixel_pf1 = CRC_INIT_LINEN(0XFFFF) | CRC_INIT_LINE0(0XFFFF); diff --git a/arch/arm64/src/a64/a64_serial.c b/arch/arm64/src/a64/a64_serial.c index d2ed531855..b795faf629 100644 --- a/arch/arm64/src/a64/a64_serial.c +++ b/arch/arm64/src/a64/a64_serial.c @@ -1334,7 +1334,7 @@ static struct uart_dev_s g_uart4port = * Description: * Performs the low level UART initialization early in * debug so that the serial console will be available - * during bootup. This must be called before arm64_serialinit. + * during boot up. This must be called before arm64_serialinit. * * Returned Value: * None diff --git a/arch/arm64/src/a64/a64_twi.c b/arch/arm64/src/a64/a64_twi.c index 5264084ee1..79d913a72f 100644 --- a/arch/arm64/src/a64/a64_twi.c +++ b/arch/arm64/src/a64/a64_twi.c @@ -1295,7 +1295,7 @@ static int a64_twi_isr_process(struct a64_twi_priv_s *priv) if (priv->dcnt > 0) { - /* get data then clear flag,then next data comming */ + /* get data then clear flag, then next data coming */ *priv->ptr++ = twi_get_byte(priv); priv->dcnt--; @@ -1414,7 +1414,7 @@ static int twi_interrupt(int irq, void *context, void *arg) ret = a64_twi_isr_process(priv); - /* enable irq only when twi is transfering, otherwise disable irq */ + /* enable irq only when twi is transferring, otherwise disable irq */ if (priv->intstate != INTSTATE_IDLE) { @@ -1566,7 +1566,7 @@ static int twi_transfer(struct i2c_master_s *dev, */ twi_enable_irq(priv); /* enable irq */ - twi_disable_ack(priv); /* disabe ACK */ + twi_disable_ack(priv); /* disable ACK */ /* No Data Byte to be written after read command */ @@ -1610,7 +1610,7 @@ out: priv->intstate = INTSTATE_IDLE; - /* Release the port for re-use by other clients */ + /* Release the port for reuse by other clients */ leave_critical_section(flags); nxmutex_unlock(&priv->lock); diff --git a/arch/arm64/src/a64/hardware/a64_twi.h b/arch/arm64/src/a64/hardware/a64_twi.h index 0fca742c42..70755a752c 100644 --- a/arch/arm64/src/a64/hardware/a64_twi.h +++ b/arch/arm64/src/a64/hardware/a64_twi.h @@ -45,7 +45,7 @@ #define A64_TWI_STAT_OFFSET (0x10) /* 28 interrupt types + 0xF8 normal type = 29 */ #define A64_TWI_CCR_OFFSET (0x14) /* 31:7 bit reserved,6-3bit,CLK_M,2-0bit CLK_N */ #define A64_TWI_SRST_OFFSET (0x18) /* 31:1 bit reserved;0bit,write 1 to clear 0. */ -#define A64_TWI_EFR_OFFSET (0x1c) /* 31:2 bit reserved,1:0 bit data byte follow read comand */ +#define A64_TWI_EFR_OFFSET (0x1c) /* 31:2 bit reserved,1:0 bit data byte follow read command */ #define A64_TWI_LCR_OFFSET (0x20) /* 31:6 bits reserved 5:0 bit for sda&scl control*/ #define A64_TWI_DVFS_OFFSET (0x24) /* 31:3 bits reserved 2:0 bit for dvfs control. only A10 support */ diff --git a/arch/arm64/src/bcm2711/bcm2711_serial.c b/arch/arm64/src/bcm2711/bcm2711_serial.c index 9d353877c2..dc4d0c0415 100644 --- a/arch/arm64/src/bcm2711/bcm2711_serial.c +++ b/arch/arm64/src/bcm2711/bcm2711_serial.c @@ -706,7 +706,7 @@ static int bcm2711_miniuart_irq_handler(int irq, void *context, void *arg) * Description: * Performs the low level UART initialization early in * debug so that the serial console will be available - * during bootup. This must be called before arm64_serialinit. + * during boot up. This must be called before arm64_serialinit. * * Returned Value: * None diff --git a/arch/arm64/src/bcm2711/hardware/bcm2711_memmap.h b/arch/arm64/src/bcm2711/hardware/bcm2711_memmap.h index 72f249e4ac..0ee903a609 100644 --- a/arch/arm64/src/bcm2711/hardware/bcm2711_memmap.h +++ b/arch/arm64/src/bcm2711/hardware/bcm2711_memmap.h @@ -60,7 +60,7 @@ #define BCM_ARMT_BASEADDR \ (BCM_PERIPHERAL_BASEADDR + 0x0000b000) /* ARM timer */ #define BCM_AUX_BASEADDR \ - (BCM_PERIPHERAL_BASEADDR + 0x000215000) /* Auxilliary */ + (BCM_PERIPHERAL_BASEADDR + 0x000215000) /* Auxiliary */ #define BCM_GPCLK_BASEADDR \ (BCM_PERIPHERAL_BASEADDR + 0x000101000) /* General purpose clock */ #define BCM_GPIO_BASEADDR \ diff --git a/arch/arm64/src/common/arm64_gic.h b/arch/arm64/src/common/arm64_gic.h index 05926b4f62..4467eaaee2 100644 --- a/arch/arm64/src/common/arm64_gic.h +++ b/arch/arm64/src/common/arm64_gic.h @@ -336,7 +336,7 @@ int arm64_gic_v2m_initialize(void); * * 1. It saves the current task state at the head of the current assigned * task list. - * 2. It porcess g_delivertasks + * 2. It processes g_delivertasks * 3. Returns from interrupt, restoring the state of the new task at the * head of the ready to run list. * diff --git a/arch/arm64/src/common/arm64_head.S b/arch/arm64/src/common/arm64_head.S index 7d210d1233..46fe4bf01e 100644 --- a/arch/arm64/src/common/arm64_head.S +++ b/arch/arm64/src/common/arm64_head.S @@ -124,8 +124,8 @@ real_start: /* The global variable cpu_boot_params is not safety to * access in some case. eg. Some debugger will reboot * the NuttX but not reload the whole image, so it will - * be not predicable for the initial value of the global - * value in that case + * be not predictable for the initial value of the global + * value in that case. * * get_cpu_id is safety because the CPU identification is * not change in any case, so the code will judge in a diff --git a/arch/arm64/src/common/arm64_internal.h b/arch/arm64/src/common/arm64_internal.h index 3045d36702..7ac7fb09ab 100644 --- a/arch/arm64/src/common/arm64_internal.h +++ b/arch/arm64/src/common/arm64_internal.h @@ -330,7 +330,7 @@ void arm64_serialinit(void); * * Description: * Performs the low level UART initialization early in debug so that the - * serial console will be available during bootup. This must be called + * serial console will be available during boot up. This must be called * before arm64_serialinit. * * Note: diff --git a/arch/arm64/src/common/arm64_mmu.h b/arch/arm64/src/common/arm64_mmu.h index a0677568c5..916b4c9de9 100644 --- a/arch/arm64/src/common/arm64_mmu.h +++ b/arch/arm64/src/common/arm64_mmu.h @@ -63,7 +63,7 @@ (0x44 << (MT_NORMAL_NC * 8)) | \ (MT_NORMAL_VAL << (MT_NORMAL * 8))) -/* More flags from user's perpective are supported using remaining bits +/* More flags from user's perspective are supported using remaining bits * of "attrs" field, i.e. attrs[31:3], underlying code will take care * of setting PTE fields correctly. * diff --git a/arch/arm64/src/common/arm64_mpu.c b/arch/arm64/src/common/arm64_mpu.c index 52c885c4da..098c9a2b15 100644 --- a/arch/arm64/src/common/arm64_mpu.c +++ b/arch/arm64/src/common/arm64_mpu.c @@ -180,7 +180,7 @@ void mpu_freeregion(unsigned int region) { unsigned int num_regions = get_num_regions(); - /* Check region vaild */ + /* Check region valid */ DEBUGASSERT(region < num_regions); diff --git a/arch/arm64/src/common/arm64_smpcall.c b/arch/arm64/src/common/arm64_smpcall.c index c5a764f2b4..1c54dfa424 100644 --- a/arch/arm64/src/common/arm64_smpcall.c +++ b/arch/arm64/src/common/arm64_smpcall.c @@ -55,7 +55,7 @@ * * 1. It saves the current task state at the head of the current assigned * task list. - * 2. It porcess g_delivertasks + * 2. It processes g_delivertasks * 3. Returns from interrupt, restoring the state of the new task at the * head of the ready to run list. * diff --git a/arch/arm64/src/common/arm64_syscall.c b/arch/arm64/src/common/arm64_syscall.c index 3bd6e12bcb..4e44f5df69 100644 --- a/arch/arm64/src/common/arm64_syscall.c +++ b/arch/arm64/src/common/arm64_syscall.c @@ -173,7 +173,7 @@ uint64_t *arm64_syscall(uint64_t *regs) cmd = regs[REG_X0]; /* if cmd == SYS_restore_context (*running_task)->xcp.regs is valid - * should not be overwriten + * should not be overwritten */ if (cmd != SYS_restore_context) diff --git a/arch/arm64/src/imx8/imx8_serial.h b/arch/arm64/src/imx8/imx8_serial.h index e8ae517fba..7f2f428686 100644 --- a/arch/arm64/src/imx8/imx8_serial.h +++ b/arch/arm64/src/imx8/imx8_serial.h @@ -64,7 +64,7 @@ * * Description: * Performs the low level UART initialization early in debug so that the - * serial console will be available during bootup. This must be called + * serial console will be available during boot up. This must be called * before arm_serialinit. * ****************************************************************************/ @@ -79,7 +79,7 @@ void imx8_earlyserialinit(void); * * Description: * Performs the low level UART initialization early in debug so that the - * serial console will be available during bootup. This must be called + * serial console will be available during boot up. This must be called * before arm_serialinit. * ****************************************************************************/ diff --git a/arch/arm64/src/imx8/imx8qm_serial.c b/arch/arm64/src/imx8/imx8qm_serial.c index 3d5dd8b90b..f8f3b90e12 100644 --- a/arch/arm64/src/imx8/imx8qm_serial.c +++ b/arch/arm64/src/imx8/imx8qm_serial.c @@ -1018,7 +1018,7 @@ static struct uart_dev_s g_uart1port = * Description: * Performs the low level UART initialization early in * debug so that the serial console will be available - * during bootup. This must be called before arm64_serialinit. + * during boot up. This must be called before arm64_serialinit. * ****************************************************************************/ diff --git a/arch/arm64/src/imx9/Kconfig b/arch/arm64/src/imx9/Kconfig index c09b75b7ed..1a663b96cf 100644 --- a/arch/arm64/src/imx9/Kconfig +++ b/arch/arm64/src/imx9/Kconfig @@ -64,8 +64,8 @@ config IMX9_HAVE_ATF_FIRMWARE select ARM64_HAVE_PSCI ---help--- Configure this n if using Nuttx bootloader that does not - implement EL3 services, by default this is y when using uboot as - a bootloader + implement EL3 services. By default this is y when using uboot as + a bootloader. config IMX9_BOOTLOADER bool "Bootloader" @@ -839,7 +839,7 @@ config IMX9_LPI2C_DMA_MAXMSG default 8 depends on IMX9_LPI2C_DMA ---help--- - This option set the number of mesg that can be in a transfer. + This option sets the number of mesg that can be in a transfer. It is used to allocate space for the 16 bit LPI2C commands that will be DMA-ed to the LPI2C device. diff --git a/arch/arm64/src/imx9/hardware/imx9_blk_ctrl.h b/arch/arm64/src/imx9/hardware/imx9_blk_ctrl.h index 745c6922a4..49cf35b105 100644 --- a/arch/arm64/src/imx9/hardware/imx9_blk_ctrl.h +++ b/arch/arm64/src/imx9/hardware/imx9_blk_ctrl.h @@ -46,7 +46,7 @@ #define IMX9_WAKUPMIX_I3C2_WAKEUP_OFFSET 0x38 /* I3C2 WAKEUPX CLR */ #define IMX9_WAKUPMIX_IPG_DEBUG_CA55C0_OFFSET 0x3c /* IPG DEBUG mask bit for CA55 core0 */ #define IMX9_WAKUPMIX_IPG_DEBUG_CA55C1_OFFSET 0x40 /* IPG DEBUG mask bit for CA55 core1 */ -#define IMX9_WAKUPMIX_AXI_ATTR_CFG_OFFSET 0x44 /* AXI CACHE OVERRITE BIT */ +#define IMX9_WAKUPMIX_AXI_ATTR_CFG_OFFSET 0x44 /* AXI CACHE OVERRIDE BIT */ #define IMX9_WAKUPMIX_I3C2_SDA_IRQ_OFFSET 0x48 /* I3C SDA IRQ Control */ /* Wakeupmix block control registers ****************************************/ diff --git a/arch/arm64/src/imx9/hardware/imx9_enet.h b/arch/arm64/src/imx9/hardware/imx9_enet.h index 4f7050527a..3f6520bc31 100644 --- a/arch/arm64/src/imx9/hardware/imx9_enet.h +++ b/arch/arm64/src/imx9/hardware/imx9_enet.h @@ -326,7 +326,7 @@ #define ENET_TXIC_ICFT_SHIFT (20) /* Bits 0-15: Interrupt coalescing timer threshold */ #define ENET_TXIC_ICFT_SHIFT_MASK (0xff << ENET_TXIC_ICFT_SHIFT) #define ENET_TXIC_ICTT_ICCS (1 << 30) /* Bit 30: Interrupt Coalescing Timer Clock Source Select */ -#define ENET_TXIC_ICTT_ICEN (1 << 31) /* Bit 31: Eable/disabel Interrupt Coalescing */ +#define ENET_TXIC_ICTT_ICEN (1 << 31) /* Bit 31: Enable/disable Interrupt Coalescing */ /* Receive Interrupt Coalescing Register */ @@ -336,7 +336,7 @@ #define ENET_RXIC_ICFT_SHIFT (20) /* Bits 0-15: Interrupt coalescing timer threshold */ #define ENET_RXIC_ICFT_SHIFT_MASK (0xff << ENET_TXIC_ICFT_SHIFT) #define ENET_RXIC_ICTT_ICCS (1 << 30) /* Bit 30: Interrupt Coalescing Timer Clock Source Select */ -#define ENET_RXIC_ICTT_ICEN (1 << 31) /* Bit 31: Eable/disabel Interrupt Coalescing */ +#define ENET_RXIC_ICTT_ICEN (1 << 31) /* Bit 31: Enable/disable Interrupt Coalescing */ /* Transmit FIFO Watermark Register */ diff --git a/arch/arm64/src/imx9/hardware/imx9_flexcan.h b/arch/arm64/src/imx9/hardware/imx9_flexcan.h index 89bd18f79b..439891d573 100644 --- a/arch/arm64/src/imx9/hardware/imx9_flexcan.h +++ b/arch/arm64/src/imx9/hardware/imx9_flexcan.h @@ -221,7 +221,7 @@ #define CAN_ESR1_TWRNINT (1 << 17) /* Bit 17: Tx Warning Interrupt Flag */ #define CAN_ESR1_SYNCH (1 << 18) /* Bit 18: CAN Synchronization Status */ #define CAN_ESR1_BOFFDONEINT (1 << 19) /* Bit 19: Bus Off Done Interrupt */ -#define CAN_ESR1_ERRINTFAST (1 << 20) /* Bit 20: Error Iterrupt for Errors Detected in Data Phase of CAN FD frames */ +#define CAN_ESR1_ERRINTFAST (1 << 20) /* Bit 20: Error Interrupt for Errors Detected in Data Phase of CAN FD frames */ #define CAN_ESR1_ERROVR (1 << 21) /* Bit 21: Error Overrun */ #define CAN_ESR1_ATP (1 << 22) /* Bit 22: Active to Passive State */ #define CAN_ESR1_PTA (1 << 23) /* Bit 23: Passive to Active State */ @@ -355,7 +355,7 @@ #define CAN_CBT_ERJW_SHIFT (16) /* Bits 16-20: Extended Resync Jump Width */ #define CAN_CBT_ERJW_MASK (0x1f << CAN_CBT_ERJW_SHIFT) #define CAN_CBT_ERJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_ERJW_SHIFT)) & CAN_CBT_ERJW_MASK) -#define CAN_CBT_EPRESDIV_SHIFT (21) /* Bits 21-30: Extendet Prescaler Division Factor */ +#define CAN_CBT_EPRESDIV_SHIFT (21) /* Bits 21-30: Extended Prescaler Division Factor */ #define CAN_CBT_EPRESDIV_MASK (0x3ff << CAN_CBT_EPRESDIV_SHIFT) #define CAN_CBT_EPRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPRESDIV_SHIFT)) & CAN_CBT_EPRESDIV_MASK) #define CAN_CBT_BTF (1 << 31) /* Bit 31: Bit Timing Format Enable */ diff --git a/arch/arm64/src/imx9/hardware/imx9_lpit.h b/arch/arm64/src/imx9/hardware/imx9_lpit.h index 629cdc6edc..cbccdd9a6c 100644 --- a/arch/arm64/src/imx9/hardware/imx9_lpit.h +++ b/arch/arm64/src/imx9/hardware/imx9_lpit.h @@ -37,7 +37,7 @@ #define IMX9_LPIT_PARAM_OFFSET 0x0004 /* Parameter */ #define IMX9_LPIT_MCR_OFFSET 0x0008 /* Module Control */ #define IMX9_LPIT_MSR_OFFSET 0x000c /* Module Status Register */ -#define IMX9_LPIT_MIER_OFFSET 0x0010 /* Moduel Interrupt Enable */ +#define IMX9_LPIT_MIER_OFFSET 0x0010 /* Module Interrupt Enable */ #define IMX9_LPIT_SETTEN_OFFSET 0x0014 /* Set Timer Enable */ #define IMX9_LPIT_CLRTEN_OFFSET 0x0018 /* Clear Timer Enable */ #define IMX9_LPIT_TVAL0_OFFSET 0x0020 /* Timer Channel 0 Value */ diff --git a/arch/arm64/src/imx9/imx9_ccm.c b/arch/arm64/src/imx9/imx9_ccm.c index c3019e83cc..7cb1fef962 100644 --- a/arch/arm64/src/imx9/imx9_ccm.c +++ b/arch/arm64/src/imx9/imx9_ccm.c @@ -51,7 +51,7 @@ * Name: ccm_clk_src_tz_access * * Description: - * Clock source access contol enable. + * Clock source access control enable. * * Input Parameters: * pscll - Clock source diff --git a/arch/arm64/src/imx9/imx9_edma.h b/arch/arm64/src/imx9/imx9_edma.h index dc3489dd22..a0bf7a539a 100644 --- a/arch/arm64/src/imx9/imx9_edma.h +++ b/arch/arm64/src/imx9/imx9_edma.h @@ -82,7 +82,7 @@ * i mxrt_dmach_stop(handle); * * 7. The callback will be received when the DMA completes (or an error - * occurs). After that, you may free the DMA channel, or re-use it on + * occurs). After that, you may free the DMA channel, or reuse it on * subsequent DMAs. * * imx9_dmach_free(handle); diff --git a/arch/arm64/src/imx9/imx9_enet.c b/arch/arm64/src/imx9/imx9_enet.c index 1513bf4a46..ca39be1984 100644 --- a/arch/arm64/src/imx9/imx9_enet.c +++ b/arch/arm64/src/imx9/imx9_enet.c @@ -94,7 +94,7 @@ /* We need an even number of RX buffers, since RX descriptors are * freed for the DMA in pairs due to two descriptors always fitting - * in one cache line (cahce line size is 64, descriptor size is 32) + * in one cache line (cache line size is 64, descriptor size is 32) */ #if CONFIG_IMX9_ENET_NRXBUFFERS < 2 @@ -2062,16 +2062,16 @@ int imx9_read_phy_status(struct imx9_driver_s *priv) if (priv->cur_phy == NULL) { - /* We don't support guessing the link speed based ou our and link + /* We don't support guessing the link speed based on our and link * partner's capabilities. For now, user must manually set the - * speed and duplex if the phy is unknown + * speed and duplex if the phy is unknown. */ nerr("Unknown PHY, can't read link speed\n"); return ERROR; } - /* Special handling for rtl8211f, which needs to chage page */ + /* Special handling for rtl8211f, which needs to change page. */ if (imx9_phy_is(priv, GMII_RTL8211F_NAME)) { @@ -2216,7 +2216,7 @@ static int imx9_determine_phy(struct imx9_driver_s *priv) * * Input Parameters: * priv - Reference to the private ENET driver state structure - * name - a pointer to comapre to. + * name - a pointer to compare to. * * Returned Value: * 1 on match, a 0 on no match. diff --git a/arch/arm64/src/imx9/imx9_flexcan.c b/arch/arm64/src/imx9/imx9_flexcan.c index 4d603a005a..a25e3d3501 100644 --- a/arch/arm64/src/imx9/imx9_flexcan.c +++ b/arch/arm64/src/imx9/imx9_flexcan.c @@ -1070,7 +1070,7 @@ static void imx9_txdone(struct imx9_driver_s *priv, uint32_t flags) { /* Received something in this buffer? * This should only happen if we sent RTR and then did - * run out of RX MBs (which are at lower indecies). + * run out of RX MBs (which are at lower indices). * Or perhaps this shouldn't happen at all when AEN=1. This * is unclear in the RM. */ @@ -1081,7 +1081,7 @@ static void imx9_txdone(struct imx9_driver_s *priv, uint32_t flags) /* Only possible TX codes after transmission are ABORT or * INACTIVE. If it transitioned to RX MB after RTR sent, - * inactivate it. + * deactivate it. */ if (code != CAN_TXMB_ABORT && code != CAN_TXMB_INACTIVE) diff --git a/arch/arm64/src/imx9/imx9_flexspi.c b/arch/arm64/src/imx9/imx9_flexspi.c index 45be422ad4..2e05dd3ef6 100644 --- a/arch/arm64/src/imx9/imx9_flexspi.c +++ b/arch/arm64/src/imx9/imx9_flexspi.c @@ -272,7 +272,7 @@ struct flexspi_config_s bool enable_ahb_bufferable; /* Enable/disable AHB bufferable write access support, when enabled, * FLEXSPI return before waiting for command execution finished */ - bool enable_ahb_cachable; /* Enable AHB bus cachable read access support */ + bool enable_ahb_cachable; /* Enable AHB bus cacheable read access support */ } ahb_config; }; @@ -973,7 +973,7 @@ static int imx9_flexspi_read_blocking(struct flexspi_type_s *base, size = 0; } - /* Pop out a watermark level datas from IP RX FIFO */ + /* Pop out a watermark level data from IP RX FIFO */ base->INTR |= (uint32_t)FLEXSPI_IP_RX_FIFO_WATERMARK_AVAILABLE_FLAG; } diff --git a/arch/arm64/src/imx9/imx9_flexspi_nor.c b/arch/arm64/src/imx9/imx9_flexspi_nor.c index 5e22cfd8bf..8a205fc04f 100644 --- a/arch/arm64/src/imx9/imx9_flexspi_nor.c +++ b/arch/arm64/src/imx9/imx9_flexspi_nor.c @@ -914,7 +914,7 @@ static int imx9_flexspi_nor_ioctl(struct mtd_dev_s *dev, * necessary to make it appear so. */ - /* We report 4k blocksize, that is more convient for upper + /* We report 4k blocksize, that is more convenient for upper * layers */ diff --git a/arch/arm64/src/imx9/imx9_lowputc.c b/arch/arm64/src/imx9/imx9_lowputc.c index 82b94880d5..075d9f1cb9 100644 --- a/arch/arm64/src/imx9/imx9_lowputc.c +++ b/arch/arm64/src/imx9/imx9_lowputc.c @@ -502,7 +502,7 @@ void arm64_lowputc(char ch) } /* If the character to output is a newline, - * then pre-pend a carriage return + * then prepend a carriage return. */ if (ch == '\n') diff --git a/arch/arm64/src/imx9/imx9_lpi2c.c b/arch/arm64/src/imx9/imx9_lpi2c.c index a51f996e73..dde4bdfd71 100644 --- a/arch/arm64/src/imx9/imx9_lpi2c.c +++ b/arch/arm64/src/imx9/imx9_lpi2c.c @@ -1983,7 +1983,7 @@ static int imx9_lpi2c_dma_transfer(struct imx9_lpi2c_priv_s *priv) LPI2C_MSR_ALF | LPI2C_MSR_FEF); - /* Enable the Iterrupts */ + /* Enable the Interrupts */ imx9_lpi2c_putreg(priv, IMX9_LPI2C_MIER_OFFSET, LPI2C_MIER_NDIE | LPI2C_MIER_ALIE | @@ -2300,7 +2300,7 @@ static int imx9_lpi2c_reset(struct i2c_master_s *dev) out: - /* Release the port for re-use by other clients */ + /* Release the port for reuse by other clients */ nxmutex_unlock(&priv->lock); return ret; diff --git a/arch/arm64/src/imx9/imx9_lpspi.c b/arch/arm64/src/imx9/imx9_lpspi.c index 0dd6af7fc2..b6caa7d4d1 100644 --- a/arch/arm64/src/imx9/imx9_lpspi.c +++ b/arch/arm64/src/imx9/imx9_lpspi.c @@ -2069,7 +2069,7 @@ struct spi_dev_s *imx9_lpspibus_initialize(int bus) * Name: imx9_lpspibus_uninitialize * * Description: - * Unitialize the selected SPI bus + * Uninitialize the selected SPI bus * * Input Parameters: * dev - Device-specific state data diff --git a/arch/arm64/src/imx9/imx9_lpspi.h b/arch/arm64/src/imx9/imx9_lpspi.h index b621ab10d8..0e39c31f69 100644 --- a/arch/arm64/src/imx9/imx9_lpspi.h +++ b/arch/arm64/src/imx9/imx9_lpspi.h @@ -73,7 +73,7 @@ struct spi_dev_s *imx9_lpspibus_initialize(int bus); * Name: imx9_lpspibus_uninitialize * * Description: - * Unitialize the selected SPI bus if refcount is 1 + * Uninitialize the selected SPI bus if refcount is 1 * * Input Parameters: * dev - Device-specific state data diff --git a/arch/arm64/src/imx9/imx9_lpuart.c b/arch/arm64/src/imx9/imx9_lpuart.c index 7384993aa8..de1ed636fb 100644 --- a/arch/arm64/src/imx9/imx9_lpuart.c +++ b/arch/arm64/src/imx9/imx9_lpuart.c @@ -1296,7 +1296,7 @@ static int imx9_dma_setup(struct uart_dev_s *dev) modifyreg32(priv->uartbase + IMX9_LPUART_BAUD_OFFSET, 0, LPUART_BAUD_RDMAE); - /* Enable interrupt on idle and erros */ + /* Enable interrupt on idle and errors */ modifyreg32(priv->uartbase + IMX9_LPUART_CTRL_OFFSET, 0, LPUART_CTRL_PEIE | @@ -2572,7 +2572,7 @@ static int up_pm_prepare(struct pm_callback_s *cb, int domain, * * Description: * Performs the low level UART initialization early in debug so that the - * serial console will be available during bootup. This must be called + * serial console will be available during boot up. This must be called * before arm64_serialinit. * ****************************************************************************/ diff --git a/arch/arm64/src/imx9/imx9_system_ctl.c b/arch/arm64/src/imx9/imx9_system_ctl.c index 0a67c47bd5..d88a245793 100644 --- a/arch/arm64/src/imx9/imx9_system_ctl.c +++ b/arch/arm64/src/imx9/imx9_system_ctl.c @@ -53,7 +53,7 @@ void imx9_mix_powerup(void) modifyreg32(IMX9_SRC_ML_SLICE_BASE + SRC_SLICE_AUTHEN_CTRL_OFFSET, 0, BIT(9)); - /* Enable s400 handsake */ + /* Enable s400 handshake */ modifyreg32(IMX9_BLK_CTRL_S_AONMIX2_BASE + AON_MIX_LP_HANDSAKE, 0, BIT(13)); diff --git a/arch/arm64/src/imx9/imx9_usbdev.c b/arch/arm64/src/imx9/imx9_usbdev.c index d9de18fd3e..e641c6e253 100644 --- a/arch/arm64/src/imx9/imx9_usbdev.c +++ b/arch/arm64/src/imx9/imx9_usbdev.c @@ -235,7 +235,7 @@ const struct trace_msg_t g_usb_trace_strings_intdecode[] = /* This represents a Endpoint Transfer Descriptor dQH overlay (32 bytes) */ #define IMX9_DTD_S \ - volatile uint32_t nextdesc; /* Address of the next DMA descripto in RAM */ \ + volatile uint32_t nextdesc; /* Address of the next DMA descriptor in RAM */ \ volatile uint32_t config; /* Misc. bit encoded configuration information */ \ uint32_t buffer0; /* Buffer start address */ \ uint32_t buffer1; /* Buffer start address */ \ @@ -324,7 +324,7 @@ struct imx9_dqh_s #define IMX9_EP0MAXPACKET (64) /* EP0 max packet size (1-64) */ #define IMX9_BULKMAXPACKET (512) /* Bulk endpoint max packet (8/16/32/64/512) */ #define IMX9_INTRMAXPACKET (1024) /* Interrupt endpoint max packet (1 to 1024) */ -#define IMX9_ISOCMAXPACKET (512) /* Acutally 1..1023 */ +#define IMX9_ISOCMAXPACKET (512) /* Actually 1..1023 */ /* Endpoint bit position in SETUPSTAT, PRIME, FLUSH, STAT, COMPLETE * registers @@ -1276,7 +1276,7 @@ static void imx9_usbreset(struct imx9_usb_s *priv) imx9_set_address(priv, 0); - /* Initialise the Enpoint List Address */ + /* Initialise the Endpoint List Address */ imx9_putreg(priv, IMX9_USBDEV_ENDPOINTLIST_OFFSET, (uint32_t)(uintptr_t)priv->qh); diff --git a/arch/arm64/src/imx9/imx9_usdhc.c b/arch/arm64/src/imx9/imx9_usdhc.c index 732d56c1d8..dc7c8ed8c3 100644 --- a/arch/arm64/src/imx9/imx9_usdhc.c +++ b/arch/arm64/src/imx9/imx9_usdhc.c @@ -2850,7 +2850,7 @@ static sdio_eventset_t imx9_eventwait(struct sdio_dev_s *dev) } /* In case of timeout or task cancellation, we need to reset the semaphore; - * it might have been double-posted if interrupt occured at the same time + * it might have been double-posted if interrupt occurred at the same time. */ if (ret < 0 || diff --git a/arch/arm64/src/qemu/Kconfig b/arch/arm64/src/qemu/Kconfig index df2f26be49..668b9c564d 100644 --- a/arch/arm64/src/qemu/Kconfig +++ b/arch/arm64/src/qemu/Kconfig @@ -42,7 +42,7 @@ config ARCH_CHIP_QEMU_UNKNOWN endchoice # Qemu Chip Selection config ARCH_CHIP_QEMU_WITH_HV - bool "Qemu with hypvervisor (e.g. kvm, hvf)" + bool "Qemu with hypervisor (e.g. kvm, hvf)" default n endmenu # "Qemu Chip Selection" diff --git a/arch/arm64/src/rk3399/rk3399_serial.c b/arch/arm64/src/rk3399/rk3399_serial.c index 4bd504932f..cb7c396867 100644 --- a/arch/arm64/src/rk3399/rk3399_serial.c +++ b/arch/arm64/src/rk3399/rk3399_serial.c @@ -1272,7 +1272,7 @@ static struct uart_dev_s g_uart4port = * Description: * Performs the low level UART initialization early in * debug so that the serial console will be available - * during bootup. This must be called before arm64_serialinit. + * during boot up. This must be called before arm64_serialinit. * * Returned Value: * None diff --git a/arch/arm64/src/zynq-mpsoc/hardware/zynq_pll.h b/arch/arm64/src/zynq-mpsoc/hardware/zynq_pll.h index 398f5b3476..06487bfcd6 100644 --- a/arch/arm64/src/zynq-mpsoc/hardware/zynq_pll.h +++ b/arch/arm64/src/zynq-mpsoc/hardware/zynq_pll.h @@ -70,13 +70,13 @@ enum mpsoc_clk * Function: mpsoc_clk_rate_get * * Description: - * Get controller running frequence + * Get controller running frequency * * Input Parameters: * clk - peripheral clock ID * * Returned Value: - * Running frequence. + * Running frequency. * ****************************************************************************/ @@ -86,14 +86,14 @@ uintptr_t mpsoc_clk_rate_get(enum mpsoc_clk clk); * Function: mpsoc_clk_rate_set * * Description: - * Set running frequence + * Set running frequency * * Input Parameters: * clk - peripheral clock ID * rate - clock freq * * Returned Value: - * peripheral running frequence. + * peripheral running frequency. * ****************************************************************************/ diff --git a/arch/arm64/src/zynq-mpsoc/zynq_boot.c b/arch/arm64/src/zynq-mpsoc/zynq_boot.c index c2d3ff753d..2668892bcd 100644 --- a/arch/arm64/src/zynq-mpsoc/zynq_boot.c +++ b/arch/arm64/src/zynq-mpsoc/zynq_boot.c @@ -177,7 +177,7 @@ void arm64_chip_boot(void) /* Default exception level is EL1 for the NuttX OS. However, if we debug * NuttX by JTAG, The XSCT of Vivado SDK will set the Zynq MPSoC * to EL3. Other levels are not supported at the moment. And in this - * operating conditon, we can't use SMC for there's no ATF support. + * operating condition, we can't use SMC for there's no ATF support. */ #if CONFIG_ARCH_ARM64_EXCEPTION_LEVEL < 3 diff --git a/arch/arm64/src/zynq-mpsoc/zynq_enet.c b/arch/arm64/src/zynq-mpsoc/zynq_enet.c index e74e8a5d6e..d45980a200 100644 --- a/arch/arm64/src/zynq-mpsoc/zynq_enet.c +++ b/arch/arm64/src/zynq-mpsoc/zynq_enet.c @@ -498,7 +498,7 @@ static struct zynq_gmac_s g_gmac[] = * * Returned Value: * true: This is the first register access of this type. - * flase: This is the zynqe as the preceding register access. + * false: This is the zynqe as the preceding register access. * ****************************************************************************/ @@ -1588,7 +1588,7 @@ static void zynq_interrupt_work(void *arg) /* Check for the receipt of an RX packet. * * RXCOMP indicates that a packet has been received and stored in memory. - * The RXCOMP bit is cleared whent he interrupt status register was read. + * The RXCOMP bit is cleared when the interrupt status register was read. * RSR:REC indicates that one or more frames have been received and placed * in memory. This indication is cleared by writing a one to this bit. */ diff --git a/arch/arm64/src/zynq-mpsoc/zynq_pll.c b/arch/arm64/src/zynq-mpsoc/zynq_pll.c index 2ce894cde0..ae934a3528 100644 --- a/arch/arm64/src/zynq-mpsoc/zynq_pll.c +++ b/arch/arm64/src/zynq-mpsoc/zynq_pll.c @@ -250,13 +250,13 @@ static uint32_t mpsoc_clk_register_get(enum mpsoc_clk clk_pll) * Function: mpsoc_clk_pll_get * * Description: - * Get clock source post frequence + * Get clock source post frequency * * Input Parameters: * clk_ctrl - Ctrl register value of clock source. * * Returned Value: - * Clock source post frequence. + * Clock source post frequency. * ****************************************************************************/ @@ -265,7 +265,7 @@ static uintptr_t mpsoc_clk_pll_get(uintptr_t clk_ctrl) uint32_t src_sel; src_sel = (clk_ctrl & PLLCTRL_POST_SRC_MASK) >> - PLLCTRL_POST_SRC_SHFT; /* get pass-thru clock source */ + PLLCTRL_POST_SRC_SHFT; /* get pass-through clock source */ switch (src_sel) { @@ -290,13 +290,13 @@ static uintptr_t mpsoc_clk_pll_get(uintptr_t clk_ctrl) * Function: mpsoc_clk_pll_rate_get * * Description: - * Get clock source pll output frequence + * Get clock source pll output frequency * * Input Parameters: * clk_pll - clock source pll. * * Returned Value: - * Pll output frequence. + * Pll output frequency. * ****************************************************************************/ @@ -433,13 +433,13 @@ static enum mpsoc_clk mpsoc_peripheral_clk_pll_set(uint32_t clkctrl) * Function: mpsoc_cpu_clk_get * * Description: - * Get ARM CPU running frequence + * Get ARM CPU running frequency * * Input Parameters: * none. * * Returned Value: - * ARM CPU running frequence. + * ARM CPU running frequency. * ****************************************************************************/ @@ -466,13 +466,13 @@ static uint32_t mpsoc_cpu_clk_get(void) * Function: mpsoc_ddr_clk_get * * Description: - * Get DDR running frequence + * Get DDR running frequency * * Input Parameters: * none. * * Returned Value: - * DDR running frequence. + * DDR running frequency. * ****************************************************************************/ @@ -499,13 +499,13 @@ static uint32_t mpsoc_ddr_clk_get(void) * Function: mpsoc_peripheral_clk_get * * Description: - * Get peripheral running frequence + * Get peripheral running frequency * * Input Parameters: * peripheral clock ID. * * Returned Value: - * peripheral running frequence. + * peripheral running frequency. * ****************************************************************************/ @@ -541,7 +541,7 @@ static uint32_t mpsoc_peripheral_clk_get(enum mpsoc_clk clk) * Function: mpsoc_peripheral_clk_two_divs_calc * * Description: - * Get peripheral running frequence + * Get peripheral running frequency * * Input Parameters: * rate - clock freq @@ -550,7 +550,7 @@ static uint32_t mpsoc_peripheral_clk_get(enum mpsoc_clk clk) * div1 - divisor1 * * Returned Value: - * best running frequence. + * best running frequency. * ****************************************************************************/ @@ -591,14 +591,14 @@ static uintptr_t mpsoc_peripheral_clk_two_divs_calc(uintptr_t rate, * Function: mpsoc_peripheral_clk_set * * Description: - * Set peripheral running frequence + * Set peripheral running frequency * * Input Parameters: * clk - peripheral clock ID * rate - clock freq * * Returned Value: - * New peripheral running frequence. + * New peripheral running frequency. * ****************************************************************************/ @@ -644,13 +644,13 @@ static uint32_t mpsoc_peripheral_clk_set(enum mpsoc_clk clk, uintptr_t rate) * Function: mpsoc_ttc_clk_get * * Description: - * Get ttc controller running frequence + * Get ttc controller running frequency * * Input Parameters: * clk - peripheral clock ID * * Returned Value: - * PLL frequence. + * PLL frequency. * ****************************************************************************/ @@ -714,13 +714,13 @@ static uint32_t mpsoc_ttc_clk_get(enum mpsoc_clk clk) * Function: mpsoc_clk_rate_get * * Description: - * Get controller running frequence + * Get controller running frequency * * Input Parameters: * clk - peripheral clock ID * * Returned Value: - * Running frequence. + * Running frequency. * ****************************************************************************/ @@ -753,14 +753,14 @@ uintptr_t mpsoc_clk_rate_get(enum mpsoc_clk clk) * Function: mpsoc_clk_rate_set * * Description: - * Set running frequence + * Set running frequency * * Input Parameters: * clk - peripheral clock ID * rate - clock freq * * Returned Value: - * peripheral running frequence. + * peripheral running frequency. * ****************************************************************************/ diff --git a/arch/arm64/src/zynq-mpsoc/zynq_serial.c b/arch/arm64/src/zynq-mpsoc/zynq_serial.c index 8b58718cfc..446419f621 100644 --- a/arch/arm64/src/zynq-mpsoc/zynq_serial.c +++ b/arch/arm64/src/zynq-mpsoc/zynq_serial.c @@ -1261,7 +1261,7 @@ static struct uart_dev_s g_uart1port = * Description: * Performs the low level UART initialization early in * debug so that the serial console will be available - * during bootup. This must be called before arm64_serialinit. + * during boot up. This must be called before arm64_serialinit. * * Returned Value: * None diff --git a/arch/avr/src/at32uc3/at32uc3_irq.c b/arch/avr/src/at32uc3/at32uc3_irq.c index 3a574f8862..dde918347e 100644 --- a/arch/avr/src/at32uc3/at32uc3_irq.c +++ b/arch/avr/src/at32uc3/at32uc3_irq.c @@ -260,7 +260,7 @@ int up_prioritize_irq(int irq, int priority) * Return the highest priority pending INTn interrupt (hwere n=level). * This is called directly from interrupt handling logic. This should be * save since the UC3B will save all C scratch/volatile registers (and - * this function should not alter the perserved/static registers). + * this function should not alter the preserved/static registers). * ****************************************************************************/ diff --git a/arch/avr/src/at32uc3/at32uc3_serial.c b/arch/avr/src/at32uc3/at32uc3_serial.c index 707ffa09b8..ffe182c3b5 100644 --- a/arch/avr/src/at32uc3/at32uc3_serial.c +++ b/arch/avr/src/at32uc3/at32uc3_serial.c @@ -692,7 +692,7 @@ static bool up_txready(struct uart_dev_s *dev) * * Description: * Performs the low level USART initialization early in debug so that the - * serial console will be available during bootup. This must be called + * serial console will be available during boot up. This must be called * before avr_serialinit. NOTE: This function depends on GPIO pin * configuration performed in up_consoleinit() and main clock * initialization performed in up_clkinitialize(). diff --git a/arch/avr/src/at90usb/at90usb_serial.c b/arch/avr/src/at90usb/at90usb_serial.c index 14136d2d69..fca902c84e 100644 --- a/arch/avr/src/at90usb/at90usb_serial.c +++ b/arch/avr/src/at90usb/at90usb_serial.c @@ -513,7 +513,7 @@ static bool usart1_txempty(struct uart_dev_s *dev) * * Description: * Performs the low level USART initialization early in debug so that the - * serial console will be available during bootup. This must be called + * serial console will be available during boot up. This must be called * before avr_serialinit. * ****************************************************************************/ diff --git a/arch/avr/src/atmega/atmega_serial.c b/arch/avr/src/atmega/atmega_serial.c index e4aa06b9d8..88af216ead 100644 --- a/arch/avr/src/atmega/atmega_serial.c +++ b/arch/avr/src/atmega/atmega_serial.c @@ -799,7 +799,7 @@ static bool usart1_txready(struct uart_dev_s *dev) * Name: usart0/1_txempty * * Description: - * Return true if the tranmsit data register and shift reqister are both + * Return true if the tranmsit data register and shift register are both * empty * ****************************************************************************/ @@ -829,7 +829,7 @@ static bool usart1_txempty(struct uart_dev_s *dev) * * Description: * Performs the low level USART initialization early in debug so that the - * serial console will be available during bootup. This must be called + * serial console will be available during boot up. This must be called * before avr_serialinit. * ****************************************************************************/ diff --git a/arch/ceva/include/spinlock.h b/arch/ceva/include/spinlock.h index b0d59172a4..dbdb6e1dd6 100644 --- a/arch/ceva/include/spinlock.h +++ b/arch/ceva/include/spinlock.h @@ -83,7 +83,7 @@ typedef uint32_t spinlock_t; * Description: * Perform an atomic test and set operation on the provided spinlock. * - * This function must be provided via the architecture-specific logoic. + * This function must be provided via the architecture-specific logic. * * Input Parameters: * lock - The address of spinlock object. diff --git a/arch/ceva/include/xm6/barriers.h b/arch/ceva/include/xm6/barriers.h index f3bcb85c62..c5b6d183c7 100644 --- a/arch/ceva/include/xm6/barriers.h +++ b/arch/ceva/include/xm6/barriers.h @@ -52,7 +52,7 @@ static inline void up_dsb(void) : "r"(MSS_BARRIER) ); - /* Wait unitl the barrier operation complete */ + /* Wait until the barrier operation complete */ } while ((barrier & 0x80) != 0); #undef MSS_BARRIER diff --git a/arch/ceva/include/xm6/spinlock.h b/arch/ceva/include/xm6/spinlock.h index 7b3eb96dec..4fbfb70c3e 100644 --- a/arch/ceva/include/xm6/spinlock.h +++ b/arch/ceva/include/xm6/spinlock.h @@ -48,7 +48,7 @@ * Description: * Perform an atomic test and set operation on the provided spinlock. * - * This function must be provided via the architecture-specific logoic. + * This function must be provided via the architecture-specific logic. * * Input Parameters: * lock - The address of spinlock object. diff --git a/arch/ceva/src/common/ceva_board.c b/arch/ceva/src/common/ceva_board.c index 24bf765c40..f587a3ba7d 100644 --- a/arch/ceva/src/common/ceva_board.c +++ b/arch/ceva/src/common/ceva_board.c @@ -86,7 +86,7 @@ void board_late_initialize(void) * arg - The boardctl() argument is passed to the board_app_initialize() * implementation without modification. The argument has no * meaning to NuttX; the meaning of the argument is a contract - * between the board-specific initalization logic and the + * between the board-specific initialization logic and the * matching application logic. The value cold be such things as a * mode enumeration value, a set of DIP switch switch settings, a * pointer to configuration data read from a file or serial FLASH, diff --git a/arch/ceva/src/common/ceva_svcall.c b/arch/ceva/src/common/ceva_svcall.c index bc231a49d9..439cb6781a 100644 --- a/arch/ceva/src/common/ceva_svcall.c +++ b/arch/ceva/src/common/ceva_svcall.c @@ -94,7 +94,7 @@ int ceva_svcall(int irq, void *context, void *arg) * A0 = SYS_save_context * A1 = saveregs * - * In this case, we simply need to copy the current regsters to the + * In this case, we simply need to copy the current registers to the * save register space references in the saved A1 and return. */ @@ -116,7 +116,7 @@ int ceva_svcall(int irq, void *context, void *arg) * * In this case, we simply need to set current_regs to restore register * area referenced in the saved A1. context == current_regs is the - * noraml exception return. By setting current_regs = context[A1], + * normal exception return. By setting current_regs = context[A1], * we force the return to the saved context referenced in A1. */ diff --git a/arch/ceva/src/xc5/Kconfig b/arch/ceva/src/xc5/Kconfig index b6ae32ad7c..cc79710114 100644 --- a/arch/ceva/src/xc5/Kconfig +++ b/arch/ceva/src/xc5/Kconfig @@ -8,4 +8,4 @@ comment "XC5 Configuration Options" config XC5_PSU_ENABLE bool "Enable power management of XC5" ---help--- - Doze or idle mode of xc5 power managerment. + Doze or idle mode of xc5 power management. diff --git a/arch/ceva/src/xc5/fork.S b/arch/ceva/src/xc5/fork.S index ba71c2b4d5..ff6dc14d22 100644 --- a/arch/ceva/src/xc5/fork.S +++ b/arch/ceva/src/xc5/fork.S @@ -63,7 +63,7 @@ * - Allocation of the child task's TCB. * - Initialization of file descriptors and streams * - Configuration of environment variables - * - Setup the intput parameters for the task. + * - Setup the input parameters for the task. * - Initialization of the TCB (including call to up_initial_state() * 4) ceva_fork() provides any additional operating context. ceva_fork must: * - Allocate and initialize the stack @@ -72,7 +72,7 @@ * 5) ceva_fork() then calls nxtask_forkstart() * 6) nxtask_forkstart() then executes the child thread. * - * Input Paremeters: + * Input Parameters: * None * * Return: diff --git a/arch/ceva/src/xm6/fork.S b/arch/ceva/src/xm6/fork.S index d5b16fb714..947be2cec5 100644 --- a/arch/ceva/src/xm6/fork.S +++ b/arch/ceva/src/xm6/fork.S @@ -73,7 +73,7 @@ * - Allocation of the child task's TCB. * - Initialization of file descriptors and streams * - Configuration of environment variables - * - Setup the intput parameters for the task. + * - Setup the input parameters for the task. * - Initialization of the TCB (including call to up_initial_state() * 4) ceva_fork() provides any additional operating context. ceva_fork must: * - Allocate and initialize the stack @@ -82,7 +82,7 @@ * 5) ceva_fork() then calls nxtask_forkstart() * 6) nxtask_forkstart() then executes the child thread. * - * Input Paremeters: + * Input Parameters: * None * * Return: diff --git a/arch/hc/include/hcs12/irq.h b/arch/hc/include/hcs12/irq.h index 2113a76d94..99a07e0895 100644 --- a/arch/hc/include/hcs12/irq.h +++ b/arch/hc/include/hcs12/irq.h @@ -50,10 +50,10 @@ #define HCS12_CCR_S (1 << 7) /* Bit 7: STOP instruction control bit */ /**************************************************************************** - * Register state save strucure + * Register state save structure * Low Address <-- SP after state save * [PPAGE] - * [soft regisers] + * [soft registers] * XYH * XYL * ZH diff --git a/arch/hc/src/m9s12/m9s12_saveusercontext.S b/arch/hc/src/m9s12/m9s12_saveusercontext.S index 6455d51d00..7c31287eca 100644 --- a/arch/hc/src/m9s12/m9s12_saveusercontext.S +++ b/arch/hc/src/m9s12/m9s12_saveusercontext.S @@ -71,9 +71,9 @@ * Name: up_saveusercontext * * Description: - * Create this state save strucure: + * Create this state save structure: * Low Address [PPAGE] - * [soft regisers] + * [soft registers] * XYH * XYL * ZH diff --git a/arch/hc/src/m9s12/m9s12_serial.c b/arch/hc/src/m9s12/m9s12_serial.c index bac472ef04..70629322fd 100644 --- a/arch/hc/src/m9s12/m9s12_serial.c +++ b/arch/hc/src/m9s12/m9s12_serial.c @@ -712,7 +712,7 @@ static bool up_txempty(struct uart_dev_s *dev) * * Description: * Performs the low level SCI initialization early in debug so that the - * serial console will be available during bootup. This must be called + * serial console will be available during boot up. This must be called * before hc_serialinit. * ****************************************************************************/ diff --git a/arch/hc/src/m9s12/m9s12_start.S b/arch/hc/src/m9s12/m9s12_start.S index 52c8450cb2..e1dd793e31 100644 --- a/arch/hc/src/m9s12/m9s12_start.S +++ b/arch/hc/src/m9s12/m9s12_start.S @@ -118,7 +118,7 @@ clr HCS12_CRG_CLKSEL - /* Set the multipler and divider and enable the PLL */ + /* Set the multiplier and divider and enable the PLL */ bclr *HCS12_CRG_PLLCTL #CRG_PLLCTL_PLLON ldab #HCS12_SYNR_VALUE diff --git a/arch/hc/src/m9s12/m9s12_vectors.S b/arch/hc/src/m9s12/m9s12_vectors.S index 68d38f2e80..a6ab5c583e 100644 --- a/arch/hc/src/m9s12/m9s12_vectors.S +++ b/arch/hc/src/m9s12/m9s12_vectors.S @@ -204,7 +204,7 @@ handlers: * Description: * Common IRQ handling logic * - * On entry in to vcommon: (1) The interrupt stack fram is in place, and (2) the + * On entry in to vcommon: (1) The interrupt stack frame is in place, and (2) the * IRQ number is in B. * * On entry into an I- or X-interrupt, into an SWI, or into an undefined @@ -225,7 +225,7 @@ handlers: * * Low Address <-- SP after state save * [PPAGE] - * [soft regisers] + * [soft registers] * XYH * XYL * ZH @@ -341,7 +341,7 @@ vcommon: * thread, thereby completing a context switch. * * Low Address [PPAGE] - * [soft regisers] + * [soft registers] * XYH * XYL * ZH diff --git a/arch/mips/include/mips32/cp0.h b/arch/mips/include/mips32/cp0.h index 73d1de9bc8..4e06d00466 100644 --- a/arch/mips/include/mips32/cp0.h +++ b/arch/mips/include/mips32/cp0.h @@ -283,7 +283,7 @@ #define CP0_CAUSE_WP (1 << 22) /* Watch exception was deferred */ #define CP0_CAUSE_IV (1 << 23) /* Bit 23: Interrupt exception uses special interrupt vector */ -#define CP0_CAUSE_CE_SHIFT (28) /* Bits 28-29: Coprocessor unit number fo Coprocessor Unusable exception */ +#define CP0_CAUSE_CE_SHIFT (28) /* Bits 28-29: Coprocessor unit number for Coprocessor Unusable exception */ #define CP0_CAUSE_CE_MASK (3 << CP0_CAUSE_CE_SHIFT) #define CP0_CAUSE_BD (1 << 31) /* Bit 31: Last exception occurred in a branch delay slot */ diff --git a/arch/mips/include/mips32/irq.h b/arch/mips/include/mips32/irq.h index 8f293f6297..9cbe1b5c7c 100644 --- a/arch/mips/include/mips32/irq.h +++ b/arch/mips/include/mips32/irq.h @@ -67,7 +67,7 @@ #define REG_EPC_NDX 2 #define REG_STATUS_NDX 3 -/* General pupose registers */ +/* General purpose registers */ /* $0: Zero register does not need to be saved */ diff --git a/arch/mips/src/mips32/mips_fork.c b/arch/mips/src/mips32/mips_fork.c index 6ebdf5204d..831757447f 100644 --- a/arch/mips/src/mips32/mips_fork.c +++ b/arch/mips/src/mips32/mips_fork.c @@ -152,7 +152,7 @@ pid_t mips_fork(const struct fork_s *context) sinfo("Parent: stackutil:%" PRIu32 "\n", stackutil); - /* Make some feeble effort to perserve the stack contents. This is + /* Make some feeble effort to preserve the stack contents. This is * feeble because the stack surely contains invalid pointers and other * content that will not work in the child context. However, if the * user follows all of the caveats of fork() usage, even this feeble diff --git a/arch/mips/src/pic32mx/Kconfig b/arch/mips/src/pic32mx/Kconfig index 4442f7ed34..10aff0700f 100644 --- a/arch/mips/src/pic32mx/Kconfig +++ b/arch/mips/src/pic32mx/Kconfig @@ -1063,7 +1063,7 @@ config PIC32MX_PHY_AUTONEG Enable auto-negotiation config PIC32MX_PHY_SPEED100 - bool "100Mbps spped" + bool "100Mbps speed" default n depends on PIC32MX_ETHERNET && !PIC32MX_PHY_AUTONEG ---help--- diff --git a/arch/mips/src/pic32mx/pic32mx_ethernet.c b/arch/mips/src/pic32mx/pic32mx_ethernet.c index dc4e3ffeff..90dc2f5410 100644 --- a/arch/mips/src/pic32mx/pic32mx_ethernet.c +++ b/arch/mips/src/pic32mx/pic32mx_ethernet.c @@ -117,7 +117,7 @@ # define CONFIG_PIC32MX_MULTICAST 1 #endif -/* Use defaults if the number of discriptors is not provided */ +/* Use defaults if the number of descriptors is not provided */ #ifndef CONFIG_PIC32MX_ETH_NTXDESC # define CONFIG_PIC32MX_ETH_NTXDESC 2 @@ -711,7 +711,7 @@ static inline void pic32mx_txdescinit(struct pic32mx_driver_s *priv) int i; /* Assign a buffer to each TX descriptor. For now, just mark each TX - * descriptor as owned by softare andnot linked. + * descriptor as owned by software and not linked. */ for (i = 0; i < CONFIG_PIC32MX_ETH_NTXDESC; i++) @@ -835,7 +835,7 @@ static inline void pic32mx_rxdescinit(struct pic32mx_driver_s *priv) * * Returned Value: * A pointer to the next available Tx descriptor on success; NULL if the - * next Tx dscriptor is not available. + * next Tx descriptor is not available. * ****************************************************************************/ @@ -2120,7 +2120,7 @@ static int pic32mx_ifup(struct net_driver_s *dev) pic32mx_putreg(ETH_CON2_RXBUFSZ(CONFIG_NET_ETH_PKTSIZE), PIC32MX_ETH_CON2); - /* Reset state varialbes */ + /* Reset state variables */ priv->pd_polling = false; priv->pd_txpending = false; diff --git a/arch/mips/src/pic32mx/pic32mx_oc.h b/arch/mips/src/pic32mx/pic32mx_oc.h index 9408f7ab44..5fbd63e3db 100644 --- a/arch/mips/src/pic32mx/pic32mx_oc.h +++ b/arch/mips/src/pic32mx/pic32mx_oc.h @@ -163,7 +163,7 @@ #define OC_CON_OC32 (1 << 5) /* Bit 5: 32-bit compare more */ #define OC_CON_SIDL (1 << 13) /* Bit 13: Stop in idle mode */ #define OC_CON_FRZ (1 << 14) /* Bit 14: Freeze in debug exception mode */ -#define OC_CON_ON (1 << 15) /* Bit 15: Output compare periperal on */ +#define OC_CON_ON (1 << 15) /* Bit 15: Output compare peripheral on */ /* Output compare data register -- 32-bit data register */ diff --git a/arch/mips/src/pic32mx/pic32mx_serial.c b/arch/mips/src/pic32mx/pic32mx_serial.c index e2a2a143b3..f7bf6fabaa 100644 --- a/arch/mips/src/pic32mx/pic32mx_serial.c +++ b/arch/mips/src/pic32mx/pic32mx_serial.c @@ -831,7 +831,7 @@ static bool up_txempty(struct uart_dev_s *dev) * * Description: * Performs the low level UART initialization early in debug so that the - * serial console will be available during bootup. This must be called + * serial console will be available during boot up. This must be called * before mips_serialinit. NOTE: This function depends on GPIO pin * configuration performed in up_consoleinit() and main clock * initialization performed in up_clkinitialize(). diff --git a/arch/mips/src/pic32mz/hardware/pic32mz_osc.h b/arch/mips/src/pic32mz/hardware/pic32mz_osc.h index 604f735a5b..d3c2f7b880 100644 --- a/arch/mips/src/pic32mz/hardware/pic32mz_osc.h +++ b/arch/mips/src/pic32mz/hardware/pic32mz_osc.h @@ -150,7 +150,7 @@ #define SPLLCON_PLLMULT_SHIFT (16) /* Bits 16-22 <6:0>: System PLL Multiplier bits */ #define SPLLCON_PLLMULT_MASK (0x7f << SPLLCON_PLLMULT_SHIFT) -# define SPLLCON_PLLMULT(n) ((uint32_t)((n)-1) << SPLLCON_PLLMULT_SHIFT) /* Muliply by n, n=1..128 */ +# define SPLLCON_PLLMULT(n) ((uint32_t)((n)-1) << SPLLCON_PLLMULT_SHIFT) /* Multiply by n, n=1..128 */ #define SPLLCON_PLLODIV_SHIFT (24) /* Bits 24-26: System PLL Output Clock Divider bits */ #define SPLLCON_PLLODIV_MASK (7 << SPLLCON_PLLODIV_SHIFT) diff --git a/arch/mips/src/pic32mz/pic32mz_ethernet.c b/arch/mips/src/pic32mz/pic32mz_ethernet.c index 1baad21b5f..6ade32ef81 100644 --- a/arch/mips/src/pic32mz/pic32mz_ethernet.c +++ b/arch/mips/src/pic32mz/pic32mz_ethernet.c @@ -113,7 +113,7 @@ # define CONFIG_PIC32MZ_MULTICAST 1 #endif -/* Use defaults if the number of discriptors is not provided */ +/* Use defaults if the number of descriptors is not provided */ #ifndef CONFIG_PIC32MZ_ETH_NTXDESC # define CONFIG_PIC32MZ_ETH_NTXDESC 2 @@ -778,7 +778,7 @@ static inline void pic32mz_txdescinit(struct pic32mz_driver_s *priv) int i; /* Assign a buffer to each TX descriptor. For now, just mark each TX - * descriptor as owned by softare and not linked. + * descriptor as owned by software and not linked. */ for (i = 0; i < CONFIG_PIC32MZ_ETH_NTXDESC; i++) @@ -916,7 +916,7 @@ static inline void pic32mz_rxdescinit(struct pic32mz_driver_s *priv) * * Returned Value: * A pointer to the next available Tx descriptor on success; NULL if the - * next Tx dscriptor is not available. + * next Tx descriptor is not available. * ****************************************************************************/ diff --git a/arch/mips/src/pic32mz/pic32mz_i2c.c b/arch/mips/src/pic32mz/pic32mz_i2c.c index 9b0324a423..d0cbcac846 100644 --- a/arch/mips/src/pic32mz/pic32mz_i2c.c +++ b/arch/mips/src/pic32mz/pic32mz_i2c.c @@ -1200,7 +1200,7 @@ static int pic32mz_i2c_isr_process(struct pic32mz_i2c_priv_s *priv) } #endif - /* If an error interrupt has accured. */ + /* If an error interrupt has occurred. */ #ifndef CONFIG_I2C_POLLED if (mips_pending_irq(priv->config->er_irq)) @@ -1756,7 +1756,7 @@ static int pic32mz_i2c_reset(struct i2c_master_s *dev) out: - /* Release the port for re-use by other clients */ + /* Release the port for reuse by other clients */ nxmutex_unlock(&priv->lock); } diff --git a/arch/mips/src/pic32mz/pic32mz_serial.c b/arch/mips/src/pic32mz/pic32mz_serial.c index 0a59fdc09e..987d29908c 100644 --- a/arch/mips/src/pic32mz/pic32mz_serial.c +++ b/arch/mips/src/pic32mz/pic32mz_serial.c @@ -1338,7 +1338,7 @@ static bool up_txempty(struct uart_dev_s *dev) * * Description: * Performs the low level UART initialization early in debug so that the - * serial console will be available during bootup. This must be called + * serial console will be available during boot up. This must be called * before mips_serialinit. NOTE: This function depends on GPIO pin * configuration performed in up_consoleinit() and main clock * initialization performed in up_clkinitialize(). diff --git a/arch/misoc/src/common/misoc_serial.c b/arch/misoc/src/common/misoc_serial.c index 516f255944..a099f0dde5 100644 --- a/arch/misoc/src/common/misoc_serial.c +++ b/arch/misoc/src/common/misoc_serial.c @@ -526,7 +526,7 @@ static bool misoc_txempty(struct uart_dev_s *dev) * * Description: * Performs the low level UART initialization early in debug so that the - * serial console will be available during bootup. This must be called + * serial console will be available during boot up. This must be called * before misoc_serial_initialize. * ****************************************************************************/ diff --git a/arch/misoc/src/lm32/lm32_decodeirq.c b/arch/misoc/src/lm32/lm32_decodeirq.c index bce754ffc0..4955fa6ff8 100644 --- a/arch/misoc/src/lm32/lm32_decodeirq.c +++ b/arch/misoc/src/lm32/lm32_decodeirq.c @@ -86,7 +86,7 @@ uint32_t *lm32_decodeirq(uint32_t intstat, uint32_t *regs) /* Return the final task register save area. This will typically be the * same as the value of regs on input. In the event of a context switch, - * however, it will differ. It will refere to the register save are in the + * however, it will differ. It will refer to the register save are in the * TCB of the new thread. */ diff --git a/arch/misoc/src/minerva/minerva_decodeirq.c b/arch/misoc/src/minerva/minerva_decodeirq.c index ad9ddc0192..a8993537ce 100644 --- a/arch/misoc/src/minerva/minerva_decodeirq.c +++ b/arch/misoc/src/minerva/minerva_decodeirq.c @@ -87,7 +87,7 @@ uint32_t *minerva_decodeirq(uint32_t intstat, uint32_t * regs) /* Return the final task register save area. This will typically be the * same as the value of regs on input. In the event of a context switch, - * however, it will differ. It will refere to the register save are in + * however, it will differ. It will refer to the register save are in * the TCB of the new thread. */ diff --git a/arch/or1k/src/mor1kx/mor1kx_serial.c b/arch/or1k/src/mor1kx/mor1kx_serial.c index 93fb3af97f..fd6b416ba4 100644 --- a/arch/or1k/src/mor1kx/mor1kx_serial.c +++ b/arch/or1k/src/mor1kx/mor1kx_serial.c @@ -69,7 +69,7 @@ static spinlock_t g_serial_lock = SP_UNLOCKED; * * Description: * Performs the low level USART initialization early in debug so that the - * serial console will be available during bootup. This must be called + * serial console will be available during boot up. This must be called * before sam_serialinit. * ****************************************************************************/ diff --git a/arch/renesas/src/m16c/m16c_serial.c b/arch/renesas/src/m16c/m16c_serial.c index 29c6a40350..628d4175bf 100644 --- a/arch/renesas/src/m16c/m16c_serial.c +++ b/arch/renesas/src/m16c/m16c_serial.c @@ -1028,7 +1028,7 @@ static bool up_txready(struct uart_dev_s *dev) * Description: * Performs the low level UART initialization early in * debug so that the serial console will be available - * during bootup. This must be called before renesas_consoleinit. + * during boot up. This must be called before renesas_consoleinit. * ****************************************************************************/ diff --git a/arch/renesas/src/m16c/m16c_timerisr.c b/arch/renesas/src/m16c/m16c_timerisr.c index 6b8389538b..ab73970c2e 100644 --- a/arch/renesas/src/m16c/m16c_timerisr.c +++ b/arch/renesas/src/m16c/m16c_timerisr.c @@ -70,8 +70,8 @@ #define M16C_IDEAL_PRESCALER \ ((M16C_XIN_FREQ + M16C_DIVISOR - 1) / M16C_DIVISOR) -/* Now, given this idel prescaler value, - * pick between available choices: 1, 8, and 32 +/* Now, given this ideal prescaler value, + * pick between available choices: 1, 8, and 32. */ #if M16C_IDEAL_PRESCALER > 8 diff --git a/arch/renesas/src/rx65n/rx65n_dtc.c b/arch/renesas/src/rx65n/rx65n_dtc.c index 89bf8140d7..f9938d10ac 100644 --- a/arch/renesas/src/rx65n/rx65n_dtc.c +++ b/arch/renesas/src/rx65n/rx65n_dtc.c @@ -56,7 +56,7 @@ #define DTC_IP_VER_DTCa (1) #define DTC_IP_VER_DTCb (2) -/* Supportted DTC IP version and channel number */ +/* Supported DTC IP version and channel number */ #if defined(CONFIG_ARCH_BOARD_RX65N_RSK2MB) || defined(CONFIG_ARCH_BOARD_RX65N_GRROSE) #define DTC_IP_VER DTC_IP_VER_DTCb @@ -1789,7 +1789,7 @@ void rx65n_dtc_initialize(void) #endif - /* Configure read skip enable/disbale */ + /* Configure read skip enable/disable */ #if defined(CONFIG_RX65N_DTC_TRANSFER_DATA_READ_SKIP) /* Read-Skip Enable*/ rx65n_dtc_readskip_enable(dtchandle); #else /* Read-Skip disable*/ diff --git a/arch/renesas/src/rx65n/rx65n_eth.c b/arch/renesas/src/rx65n/rx65n_eth.c index 4fd8c330ea..1e5e262d4a 100644 --- a/arch/renesas/src/rx65n/rx65n_eth.c +++ b/arch/renesas/src/rx65n/rx65n_eth.c @@ -1057,7 +1057,7 @@ static int rx65n_txpoll(struct net_driver_s *dev) /* Check if the next TX descriptor is owned by the Ethernet DMA or * CPU. We cannot perform the TX poll if we are unable to accept - * another packet fo transmission. + * another packet for transmission. * * In a race condition, TACT may be cleared BUT still not available * because rx65n_freeframe() has not yet run. If rx65n_freeframe() @@ -1324,7 +1324,7 @@ static int rx65n_recvframe(struct rx65n_ethmac_s *priv) * 3) All of the TX descriptors are in flight. * * This last case is obscure. It is due to that fact that each packet - * that we receive can generate an unstoppable transmisson. So we have + * that we receive can generate an unstoppable transmission. So we have * to stop receiving when we can not longer transmit. In this case, the * transmit logic should also have disabled further RX interrupts. */ @@ -1602,7 +1602,7 @@ static void rx65n_receive(struct rx65n_ethmac_s *priv) } /* We are finished with the RX buffer. NOTE: If the buffer is - * re-used for transmission, the dev->d_buf field will have been + * reused for transmission, the dev->d_buf field will have been * nullified. */ diff --git a/arch/renesas/src/rx65n/rx65n_lowputc.c b/arch/renesas/src/rx65n/rx65n_lowputc.c index 5768854ce7..15ca18328c 100644 --- a/arch/renesas/src/rx65n/rx65n_lowputc.c +++ b/arch/renesas/src/rx65n/rx65n_lowputc.c @@ -141,7 +141,7 @@ #endif /* The full SMR setting also includes internal clocking with no divisor, - * aysnchronous operation and multiprocessor disabled: + * asynchronous operation and multiprocessor disabled: */ #define RX_SMR_VALUE (RX_SMR_MODE|RX_SMR_PARITY|RX_SMR_STOP) diff --git a/arch/renesas/src/rx65n/rx65n_riic.c b/arch/renesas/src/rx65n/rx65n_riic.c index 6d8aec7e3d..b7708078f6 100644 --- a/arch/renesas/src/rx65n/rx65n_riic.c +++ b/arch/renesas/src/rx65n/rx65n_riic.c @@ -84,7 +84,7 @@ enum rx65n_i2c_event_e { RIIC_EV_NONE = 0, RIIC_EV_GEN_START_COND, /* Called function of Start condition generation */ - RIIC_EV_INT_START, /* Interrupted start codition generation */ + RIIC_EV_INT_START, /* Interrupted start condition generation */ RIIC_EV_INT_ADD, /* Interrupted address sending */ RIIC_EV_INT_SEND, /* Interrupted data sending */ RIIC_EV_INT_RECEIVE, /* Interrupted data receiving */ @@ -483,7 +483,7 @@ static void rx65n_riic_setclock(struct rx65n_i2c_priv_s *priv, i2cinfo("Fast Plus Mode Selected - Transmission Rate: 1 Mbps\n"); if (l_time < 0.5E-6) { - /* Wnen L width less than 0.5us, subtract Rise up and down + /* If L width is less than 0.5us, subtract rise up and down * time for SCL from H/L width */ @@ -506,7 +506,7 @@ static void rx65n_riic_setclock(struct rx65n_i2c_priv_s *priv, i2cinfo("Fast Mode Selected - Transmission Rate: 400 kbps\n"); if (l_time < 1.3E-6) { - /* Wnen L width less than 1.3us, subtract Rise up and down + /* If L width is less than 1.3us, subtract rise up and down * time for SCL from H/L width */ @@ -1951,7 +1951,7 @@ static uint8_t rx65n_riic_read_data(struct rx65n_i2c_priv_s *priv) * Name: rx65n_riic_wait_set * * Description: - * Receive "last byte - 2bytes" Setting Proccesing. + * Receive "last byte - 2bytes" Setting Processing. * Sets ICMR3.WAIT bit. * ****************************************************************************/ diff --git a/arch/renesas/src/rx65n/rx65n_rspi.c b/arch/renesas/src/rx65n/rx65n_rspi.c index 9649baf5e8..daecb1870f 100644 --- a/arch/renesas/src/rx65n/rx65n_rspi.c +++ b/arch/renesas/src/rx65n/rx65n_rspi.c @@ -2267,7 +2267,7 @@ static void rspi_bus_initialize(struct rx65n_rspidev_s *priv) | RSPI_SSLP_SSL3P)); /* RSPCK is low when idle */ rspi_putreg8(priv, RX65N_RSPI_SSLP_OFFSET, regval8); - /* Inititalize frequency, frame size and SPI mode */ + /* Initialize frequency, frame size and SPI mode */ priv->frequency = 0; priv->mode = SPIDEV_MODE0; diff --git a/arch/renesas/src/rx65n/rx65n_rspi_sw.c b/arch/renesas/src/rx65n/rx65n_rspi_sw.c index bc8881354e..4551644a95 100644 --- a/arch/renesas/src/rx65n/rx65n_rspi_sw.c +++ b/arch/renesas/src/rx65n/rx65n_rspi_sw.c @@ -1871,7 +1871,7 @@ static void rspi_bus_initialize(struct rx65n_rspidev_s *priv) | RSPI_SSLP_SSL3P)); /* RSPCK is low when idle */ rspi_putreg8(priv, RX65N_RSPI_SSLP_OFFSET, regval8); - /* Inititalize frequency, frame size and SPI mode */ + /* Initialize frequency, frame size and SPI mode */ priv->frequency = 0; priv->mode = SPIDEV_MODE0; diff --git a/arch/renesas/src/rx65n/rx65n_rtc.c b/arch/renesas/src/rx65n/rx65n_rtc.c index 2e5f6b4497..10733b650b 100644 --- a/arch/renesas/src/rx65n/rx65n_rtc.c +++ b/arch/renesas/src/rx65n/rx65n_rtc.c @@ -578,7 +578,7 @@ int rx65n_rtc_setdatetime(const struct tm *tp) * tm_min 0-59 MIN (0-59) * tm_hour 0-23 HOUR (0-23) * - * *To allow for leap seconds. But these never actuall happen. + * *To allow for leap seconds. But these never actually happen. */ /* Stop all counters */ @@ -730,7 +730,7 @@ int up_rtc_settime(const struct timespec *tp) * tm_min 0-59 MIN (0-59) * tm_hour 0-23 HOUR (0-23) * - * *To allow for leap seconds. But these never actuall happen. + * *To allow for leap seconds. But these never actually happen. */ /* Stop all counters */ @@ -1314,7 +1314,7 @@ int up_rtc_getdatetime(struct tm *tp) * tm_min 0-59 MIN (0-59) * tm_hour 0-23 HOUR (0-23) * - * *To allow for leap seconds. But these never actuall happen. + * *To allow for leap seconds. But these never actually happen. */ /* Disable ICU CUP interrupt */ diff --git a/arch/renesas/src/rx65n/rx65n_serial.c b/arch/renesas/src/rx65n/rx65n_serial.c index 95fcb004c2..ecd31959d0 100644 --- a/arch/renesas/src/rx65n/rx65n_serial.c +++ b/arch/renesas/src/rx65n/rx65n_serial.c @@ -1515,7 +1515,7 @@ static bool up_txready(struct uart_dev_s *dev) * Description: * Performs the low level SCI initialization early in * debug so that the serial console will be available - * during bootup. This must be called before renesas_consoleinit. + * during boot up. This must be called before renesas_consoleinit. * ****************************************************************************/ diff --git a/arch/renesas/src/rx65n/rx65n_usbdev.c b/arch/renesas/src/rx65n/rx65n_usbdev.c index e27e9336cb..79c1ee13cd 100644 --- a/arch/renesas/src/rx65n/rx65n_usbdev.c +++ b/arch/renesas/src/rx65n/rx65n_usbdev.c @@ -5508,7 +5508,7 @@ void usb_pstd_brdy_pipe(uint16_t bitsts, struct rx65n_usbdev_s *priv, * which further, unblocks the semaphore waiting * on read() * Failing to invoke this function will result, - * in failiure of application specific read + * in failure of application specific read. * */ @@ -5970,7 +5970,7 @@ static int rx65n_usbinterrupt(int irq, void *context, void *arg) } else { - /* Vender Specific */ + /* Vendor Specific */ type = LSBYTE(rx65n_getreg16(RX65N_USB_USBREQ)); rx65n_ep0setup(priv); diff --git a/arch/renesas/src/rx65n/rx65n_usbhost.c b/arch/renesas/src/rx65n/rx65n_usbhost.c index b44885eaed..aade455f91 100644 --- a/arch/renesas/src/rx65n/rx65n_usbhost.c +++ b/arch/renesas/src/rx65n/rx65n_usbhost.c @@ -817,7 +817,7 @@ void hw_usb_hwrite_dcpctr(uint16_t data) /**************************************************************************** * Function Name : hw_usb_hset_sureq - * Description : Set te SUREQ-bit in the DCPCTR register + * Description : Set the SUREQ-bit in the DCPCTR register * : (Set SETUP packet send when HostController function * : is selected) * Arguments : none @@ -2186,7 +2186,7 @@ uint16_t usb_hstd_write_data_control_pipe(uint8_t * buf_add, /* Check data count to remain */ - /* Check if this affects any of the standard requrest commands... */ + /* Check if this affects any of the standard request commands... */ if (buf_size <= (uint32_t) size) { @@ -2535,7 +2535,7 @@ uint16_t usb_hstd_read_data_control_pipe(void) } else { - /* Continus Receive data */ + /* Continuous Receive data */ count = dtln; @@ -2634,7 +2634,7 @@ uint16_t usb_hstd_read_data(uint16_t pipe, uint16_t pipemode) } else { - /* Continus Receive data */ + /* Continuous Receive data */ count = dtln; @@ -2834,7 +2834,7 @@ void usb_hstd_brdy_pipe_process(uint16_t bitsts) } /* If still data is present - let the data - * transfer coninue + * transfer continue * */ @@ -5284,7 +5284,7 @@ static inline int rx65n_usbhost_addbulked(struct rx65n_usbhost_s *priv, g_usb_pipe_table[pipe_no].pipe_maxp = pipe_maxp; g_usb_pipe_table[pipe_no].pipe_peri = 0; - /* Now update these values in the requried pipe */ + /* Now update these values in the required pipe */ usb_cstd_pipe_init(pipe_no); leave_critical_section(flags); @@ -5508,7 +5508,7 @@ static inline int rx65n_usbhost_addinted(struct rx65n_usbhost_s *priv, g_usb_pipe_table[pipe_no].pipe_maxp = pipe_maxp; g_usb_pipe_table[pipe_no].pipe_peri = pipe_peri; - /* Now update these values in the requried pipe */ + /* Now update these values in the required pipe */ usb_cstd_pipe_init(pipe_no); @@ -6641,7 +6641,7 @@ static int rx65n_usbhost_epalloc(struct usbhost_driver_s *drvr, /* Take the ED descriptor from the list of ED Array - based on pipe num * Also note it down as part of ED structurie itself - * for futer use - if needed + * for futere use - if needed. * Take the next ED from the beginning of the free list */ @@ -6790,7 +6790,7 @@ static int rx65n_usbhost_epalloc(struct usbhost_driver_s *drvr, * Input Parameters: * drvr - The USB host driver instance obtained as a parameter from the * call to the class create() method. - * ep - The endpint to be freed. + * ep - The endpoint to be freed. * * Returned Value: * On success, zero (OK) is returned. On a failure, a negated errno @@ -6818,7 +6818,7 @@ static int rx65n_usbhost_epfree(struct usbhost_driver_s *drvr, nxmutex_lock(&priv->lock); - /* Remove the ED to the correct list depending on the trasfer type */ + /* Remove the ED to the correct list depending on the transfer type */ switch (ed->xfrtype) { @@ -7337,7 +7337,7 @@ static int rx65n_usbhost_dma_alloc(struct rx65n_usbhost_s *priv, { syslog(LOG_INFO, "Debug : %s(): Line : %d\n", __func__, __LINE__); - /* This need to be impemented if DMA is used */ + /* This need to be implemented if DMA is used */ return OK; } @@ -7434,7 +7434,7 @@ static ssize_t rx65n_usbhost_transfer(struct usbhost_driver_s *drvr, if (nrdy_retries[ed->pipenum] != 0) { - /* nRdy has occured alreday - just return with -ve value, + /* nRdy has occurred already - just return with -ve value, * so that file close is also completes with this error * */ diff --git a/arch/renesas/src/sh1/sh1_lowputc.c b/arch/renesas/src/sh1/sh1_lowputc.c index 48c8581ab7..36b2189ed9 100644 --- a/arch/renesas/src/sh1/sh1_lowputc.c +++ b/arch/renesas/src/sh1/sh1_lowputc.c @@ -98,7 +98,7 @@ #endif /* The full SMR setting also includes internal clocking with no divisor, - * aysnchronous operation and multiprocessor disabled: + * asynchronous operation and multiprocessor disabled: */ #define SH1_SMR_VALUE (SH1_SMR_MODE|SH1_SMR_PARITY|SH1_SMR_STOP) diff --git a/arch/renesas/src/sh1/sh1_serial.c b/arch/renesas/src/sh1/sh1_serial.c index 0313676947..f55179f7c1 100644 --- a/arch/renesas/src/sh1/sh1_serial.c +++ b/arch/renesas/src/sh1/sh1_serial.c @@ -820,7 +820,7 @@ static bool up_txready(struct uart_dev_s *dev) * Description: * Performs the low level SCI initialization early in * debug so that the serial console will be available - * during bootup. This must be called before renesas_consoleinit. + * during boot up. This must be called before renesas_consoleinit. * ****************************************************************************/ diff --git a/arch/risc-v/Kconfig b/arch/risc-v/Kconfig index ee182e05a5..0ee8c08354 100644 --- a/arch/risc-v/Kconfig +++ b/arch/risc-v/Kconfig @@ -708,7 +708,7 @@ config RISCV_SEMIHOSTING_HOSTFS_CACHE_COHERENCE bool "Cache coherence in semihosting hostfs" depends on ARCH_DCACHE ---help--- - Flush & Invalidte cache before & after bkpt instruction. + Flush & Invalidate cache before & after bkpt instruction. endif # RISCV_SEMIHOSTING_HOSTFS diff --git a/arch/risc-v/include/irq.h b/arch/risc-v/include/irq.h index 32710c7e29..d25089b5da 100644 --- a/arch/risc-v/include/irq.h +++ b/arch/risc-v/include/irq.h @@ -132,7 +132,7 @@ #define REG_EPC_NDX 0 -/* General pupose registers +/* General purpose registers * $0: Zero register does not need to be saved * $1: ra (return address) */ diff --git a/arch/risc-v/src/bl602/Kconfig b/arch/risc-v/src/bl602/Kconfig index 728fe9e1c3..d720ffd193 100644 --- a/arch/risc-v/src/bl602/Kconfig +++ b/arch/risc-v/src/bl602/Kconfig @@ -106,7 +106,7 @@ config BL602_WIRELESS_DEBUG default n config BL602_WIRELESS_CONTRY_CODE - string "WiFi Contry Code" + string "WiFi Country Code" depends on BL602_WIRELESS default "CN" diff --git a/arch/risc-v/src/bl602/bl602_dma.c b/arch/risc-v/src/bl602/bl602_dma.c index e19deb303e..23df307380 100644 --- a/arch/risc-v/src/bl602/bl602_dma.c +++ b/arch/risc-v/src/bl602/bl602_dma.c @@ -95,7 +95,7 @@ static int bl602_dma_int_handler(int irq, void *context, void *arg) { /* We need to ack the IRQ or a mess is made */ - /* Itterate over each of the channels checking for and clearing: + /* Iterate over each of the channels checking for and clearing: * DMA_INTTCSTATUS * DMA_INTERRORSTATUS */ @@ -240,7 +240,7 @@ int bl602_dma_channel_release(uint8_t channel_id) if (g_dmach[channel_id].inuse) { - /* This channel was infact in use, release it and increment the + /* This channel was in fact in use, release it and increment the * count of free channels for use. */ diff --git a/arch/risc-v/src/bl602/bl602_i2c.c b/arch/risc-v/src/bl602/bl602_i2c.c index 9d0162cbc7..2438e946b1 100644 --- a/arch/risc-v/src/bl602/bl602_i2c.c +++ b/arch/risc-v/src/bl602/bl602_i2c.c @@ -722,13 +722,13 @@ static int bl602_i2c_transfer(struct i2c_master_s *dev, priv->msgid = i; bl602_i2c_start_transfer(priv); - /* wait for transter finished */ + /* wait for transfer finished */ ret = nxsem_wait_uninterruptible(&priv->sem_isr); if (ret < 0) { - i2cerr("transter error\n"); + i2cerr("transfer error\n"); return ret; } diff --git a/arch/risc-v/src/bl602/bl602_netdev.c b/arch/risc-v/src/bl602/bl602_netdev.c index 779c987203..cda7d5492f 100644 --- a/arch/risc-v/src/bl602/bl602_netdev.c +++ b/arch/risc-v/src/bl602/bl602_netdev.c @@ -142,7 +142,7 @@ struct bl602_net_driver_s struct wlan_netif *wlan; - /* there is impossble to concurrency access these fields, so + /* there is impossible to concurrency access these fields, so * we use bit-field to save some little space :) */ @@ -596,7 +596,7 @@ static int bl602_launch_pending_rx(void) if (tx_buf_empty) { - /* we dont have tx buffer, so we cant go ahead, abort.. */ + /* we dont have tx buffer, so we can't go ahead, abort.. */ nwarn("tx buf empty!\n"); @@ -622,7 +622,7 @@ static int bl602_launch_pending_rx(void) ninfo("input stack rx data :%p %d\n", item->data, item->len); - /* now we have avaliable tx buffer and pending rx data, launch it */ + /* now we have available tx buffer and pending rx data, launch it */ DEBUGASSERT(item->priv != NULL); DEBUGASSERT(item->priv->net_dev.d_buf == NULL); @@ -1218,7 +1218,7 @@ static int bl602_ioctl_wifi_start(struct bl602_net_driver_s *priv, { UNUSED(arg); - /* preform connect ap */ + /* perform connect ap */ wifi_mgmr_t *mgmr = bl602_netdev_get_wifi_mgmr(priv); if (mgmr == NULL) @@ -1551,7 +1551,7 @@ bl602_net_ioctl(struct net_driver_s *dev, int cmd, unsigned long arg) } else { - wlwarn("WARNING: Unsupport mode:%ld\n", req->u.mode); + wlwarn("WARNING: Unsupported mode:%ld\n", req->u.mode); return -ENOSYS; } } @@ -1635,7 +1635,7 @@ bl602_net_ioctl(struct net_driver_s *dev, int cmd, unsigned long arg) } else { - wlinfo("unknow essid action: %d\n", req->u.essid.flags); + wlinfo("unknown essid action: %d\n", req->u.essid.flags); return -ENOSYS; } } diff --git a/arch/risc-v/src/bl602/bl602_oneshot_lowerhalf.c b/arch/risc-v/src/bl602/bl602_oneshot_lowerhalf.c index 0aa85123b4..53d49c2c1d 100644 --- a/arch/risc-v/src/bl602/bl602_oneshot_lowerhalf.c +++ b/arch/risc-v/src/bl602/bl602_oneshot_lowerhalf.c @@ -46,7 +46,7 @@ * Pre-processor Definitions ****************************************************************************/ -/* Private definetions */ +/* Private definitions */ #define TIMER_MAX_VALUE (0xFFFFFFFF) #define TIMER_CLK_DIV (160) #define TIMER_CLK_FREQ (160000000UL / (TIMER_CLK_DIV)) diff --git a/arch/risc-v/src/bl602/bl602_rtc.c b/arch/risc-v/src/bl602/bl602_rtc.c index b40007818d..a7e4c78213 100644 --- a/arch/risc-v/src/bl602/bl602_rtc.c +++ b/arch/risc-v/src/bl602/bl602_rtc.c @@ -90,7 +90,7 @@ void bl602_hbn_sel(uint8_t clk_type) void bl602_hbn_clear_rtc_int(void) { - /* Clear RTC commpare:bit1-3 for clearing Delayed RTC IRQ */ + /* Clear RTC compare:bit1-3 for clearing Delayed RTC IRQ */ modifyreg32(BL602_HBN_CTL, 0x7 << 1, 0); } @@ -103,9 +103,9 @@ void bl602_hbn_clear_rtc_int(void) * * Input Parameters: * delay: RTC interrupt delay 32 clocks - * compval_low: RTC interrupt commpare value low 32 bits - * compval_high: RTC interrupt commpare value high 32 bits - * comp_mode: RTC interrupt commpare + * compval_low: RTC interrupt compare value low 32 bits + * compval_high: RTC interrupt compare value high 32 bits + * comp_mode: RTC interrupt compare * * Returned Value: * None. diff --git a/arch/risc-v/src/bl602/bl602_serial.c b/arch/risc-v/src/bl602/bl602_serial.c index 4c8a5da506..22b4378547 100644 --- a/arch/risc-v/src/bl602/bl602_serial.c +++ b/arch/risc-v/src/bl602/bl602_serial.c @@ -820,7 +820,7 @@ static bool bl602_txempty(struct uart_dev_s *dev) * * Description: * Performs the low level UART initialization early in debug so that the - * serial console will be available during bootup. This must be called + * serial console will be available during boot up. This must be called * before riscv_serialinit. NOTE: This function depends on GPIO pin * configuration performed in up_consoleinit() and main clock * initialization performed in up_clkinitialize(). diff --git a/arch/risc-v/src/bl602/bl602_spi.c b/arch/risc-v/src/bl602/bl602_spi.c index 23f93402c6..ea03a7de01 100644 --- a/arch/risc-v/src/bl602/bl602_spi.c +++ b/arch/risc-v/src/bl602/bl602_spi.c @@ -1029,7 +1029,7 @@ static void bl602_spi_dma_exchange(struct bl602_spi_priv_s *priv, if (err < 0) { - spierr("Failed to initalize DMA LLI\n"); + spierr("Failed to initialize DMA LLI\n"); return; } diff --git a/arch/risc-v/src/bl602/bl602_tim.c b/arch/risc-v/src/bl602/bl602_tim.c index b24f7b964c..639fb39447 100644 --- a/arch/risc-v/src/bl602/bl602_tim.c +++ b/arch/risc-v/src/bl602/bl602_tim.c @@ -251,7 +251,7 @@ void bl602_timer_setcountmode(uint32_t timer_ch, uint8_t count_mode) * * Input Parameters: * timer_ch - TIMER channel type. - * cmp_no - TIMER macth comparator ID type. + * cmp_no - TIMER match comparator ID type. * * Returned Value: * None. diff --git a/arch/risc-v/src/bl602/bl602_tim.h b/arch/risc-v/src/bl602/bl602_tim.h index a5365d03f0..2ed0ddad4b 100644 --- a/arch/risc-v/src/bl602/bl602_tim.h +++ b/arch/risc-v/src/bl602/bl602_tim.h @@ -266,7 +266,7 @@ void bl602_timer_setcountmode(uint32_t timer_ch, uint8_t count_mode); * * Input Parameters: * timer_ch - TIMER channel type. - * cmp_no - TIMER macth comparator ID type. + * cmp_no - TIMER match comparator ID type. * * Returned Value: * None. diff --git a/arch/risc-v/src/bl808/bl808_i2c.c b/arch/risc-v/src/bl808/bl808_i2c.c index 1b7feaef7d..0f73417ec3 100644 --- a/arch/risc-v/src/bl808/bl808_i2c.c +++ b/arch/risc-v/src/bl808/bl808_i2c.c @@ -176,7 +176,7 @@ static struct bl808_i2c_s bl808_i2c3 = * Name: bl808_i2c_find_clock_dividers * * Description: - * Finds values for the clock divison registers to give the requested + * Finds values for the clock division registers to give the requested * frequency. Tries to keep period values small for better accuracy. * Warns when fails to match freq. * @@ -427,7 +427,7 @@ void bl808_i2c_transferbytes(struct bl808_i2c_s *priv) * * Description: * Configures I2C module according to message, enables relevant - * interrupts and intitiates the transaction. + * interrupts and initiates the transaction. * * Input Parameters: * priv - Private I2C device structure diff --git a/arch/risc-v/src/bl808/bl808_serial.c b/arch/risc-v/src/bl808/bl808_serial.c index 64accd5d9b..60f2964db1 100644 --- a/arch/risc-v/src/bl808/bl808_serial.c +++ b/arch/risc-v/src/bl808/bl808_serial.c @@ -941,7 +941,7 @@ static bool bl808_txempty(struct uart_dev_s *dev) * * Description: * Performs the low level UART initialization early in debug so that the - * serial console will be available during bootup. This must be called + * serial console will be available during boot up. This must be called * before riscv_serialinit. NOTE: This function depends on GPIO pin * configuration performed in up_consoleinit() and main clock * initialization performed in up_clkinitialize(). diff --git a/arch/risc-v/src/bl808/bl808_serial.h b/arch/risc-v/src/bl808/bl808_serial.h index 125956869a..b3d5e604b1 100644 --- a/arch/risc-v/src/bl808/bl808_serial.h +++ b/arch/risc-v/src/bl808/bl808_serial.h @@ -32,7 +32,7 @@ * * Description: * Performs the low level UART initialization early in debug so that the - * serial console will be available during bootup. This must be called + * serial console will be available during boot up. This must be called * before riscv_serialinit. NOTE: This function depends on GPIO pin * configuration performed in up_consoleinit() and main clock * initialization performed in up_clkinitialize(). diff --git a/arch/risc-v/src/bl808/bl808_spi.c b/arch/risc-v/src/bl808/bl808_spi.c index 40185d2acf..4da32fee44 100644 --- a/arch/risc-v/src/bl808/bl808_spi.c +++ b/arch/risc-v/src/bl808/bl808_spi.c @@ -1298,7 +1298,7 @@ static void bl808_spi_init(struct spi_dev_s *dev) * Name: bl808_spibus_initialize * * Description: - * Initialize and register the configured SPI busses + * Initialize and register the configured SPI buses * ****************************************************************************/ diff --git a/arch/risc-v/src/bl808/bl808_start.c b/arch/risc-v/src/bl808/bl808_start.c index 77323e9911..87f52501bb 100644 --- a/arch/risc-v/src/bl808/bl808_start.c +++ b/arch/risc-v/src/bl808/bl808_start.c @@ -296,7 +296,7 @@ void bl808_start(int mhartid) * * Description: * Performs the low level UART initialization early in debug so that the - * serial console will be available during bootup. This must be called + * serial console will be available during boot up. This must be called * before riscv_serialinit. NOTE: This function depends on GPIO pin * configuration performed in up_consoleinit() and main clock * initialization performed in up_clkinitialize(). diff --git a/arch/risc-v/src/c906/c906_serial.c b/arch/risc-v/src/c906/c906_serial.c index 270ddb204b..2f8618bdad 100644 --- a/arch/risc-v/src/c906/c906_serial.c +++ b/arch/risc-v/src/c906/c906_serial.c @@ -607,7 +607,7 @@ static bool up_txempty(struct uart_dev_s *dev) * * Description: * Performs the low level UART initialization early in debug so that the - * serial console will be available during bootup. This must be called + * serial console will be available during boot up. This must be called * before riscv_serialinit. NOTE: This function depends on GPIO pin * configuration performed in up_consoleinit() and main clock iniialization * performed in up_clkinitialize(). diff --git a/arch/risc-v/src/common/espressif/esp_adc.c b/arch/risc-v/src/common/espressif/esp_adc.c index 3ba045a136..308b35920a 100644 --- a/arch/risc-v/src/common/espressif/esp_adc.c +++ b/arch/risc-v/src/common/espressif/esp_adc.c @@ -114,7 +114,7 @@ struct esp_adc_dev_s struct esp_adc_dev_common_s *common; /* Common ADC driver data */ enum esp_adc_mode_e mode; /* ADC mode */ - adc_atten_t atten_mode; /* Attenuation paramenter */ + adc_atten_t atten_mode; /* Attenuation parameter */ uint32_t atten_k; /* Attenuation factor */ uint8_t channels; /* Total channels for this ADC */ uint8_t unit; /* ADC unit number */ diff --git a/arch/risc-v/src/common/espressif/esp_i2c.c b/arch/risc-v/src/common/espressif/esp_i2c.c index 84a6578501..319d874564 100644 --- a/arch/risc-v/src/common/espressif/esp_i2c.c +++ b/arch/risc-v/src/common/espressif/esp_i2c.c @@ -840,7 +840,7 @@ static int esp_i2c_sem_waitdone(struct esp_i2c_priv_s *priv) * priv - Pointer to the internal driver state structure. * * Returned Values: - * Zero (OK) is returned on successfull transfer. -ETIMEDOUT is returned + * Zero (OK) is returned on successful transfer. -ETIMEDOUT is returned * in case a transfer didn't finish within the timeout interval. And ERROR * is returned in case of any I2C error during the transfer has happened. * diff --git a/arch/risc-v/src/common/espressif/esp_i2c_slave.c b/arch/risc-v/src/common/espressif/esp_i2c_slave.c index 163ad409eb..97f33d5cb7 100644 --- a/arch/risc-v/src/common/espressif/esp_i2c_slave.c +++ b/arch/risc-v/src/common/espressif/esp_i2c_slave.c @@ -633,7 +633,7 @@ static int esp_i2c_slave_irq(int cpuint, void *context, void *arg) * priv - Pointer to the internal driver state structure. * * Returned Values: - * Zero (OK) is returned on successfull transfer. -ETIMEDOUT is returned + * Zero (OK) is returned on successful transfer. -ETIMEDOUT is returned * in case a transfer didn't finish within the timeout interval. * ****************************************************************************/ @@ -809,7 +809,7 @@ static void esp_i2c_process(struct esp_i2c_priv_s *priv, * * Parameters: * port - Port number of the I2C interface to be initialized. - * addr - Adress of the slave device + * addr - Address of the slave device * * Returned Value: * Pointer to valid I2C device structure is returned on success. diff --git a/arch/risc-v/src/common/espressif/esp_i2c_slave.h b/arch/risc-v/src/common/espressif/esp_i2c_slave.h index 29477bca77..b814eb078a 100644 --- a/arch/risc-v/src/common/espressif/esp_i2c_slave.h +++ b/arch/risc-v/src/common/espressif/esp_i2c_slave.h @@ -61,7 +61,7 @@ * * Input Parameters: * port - Port number (for hardware that has multiple I2C interfaces) - * addr - Adress of the slave device + * addr - Address of the slave device * * Returned Value: * Valid I2C device structure reference on success; a NULL on failure diff --git a/arch/risc-v/src/common/espressif/esp_i2s.c b/arch/risc-v/src/common/espressif/esp_i2s.c index 4b79c093a2..7fa1187947 100644 --- a/arch/risc-v/src/common/espressif/esp_i2s.c +++ b/arch/risc-v/src/common/espressif/esp_i2s.c @@ -1003,7 +1003,7 @@ static void IRAM_ATTR i2s_tx_schedule(struct esp_i2s_s *priv, /* Check if the DMA descriptor that generated an EOF interrupt is the * last descriptor of the current buffer container's DMA outlink. - * REVISIT: what to do if we miss syncronization and the descriptor + * REVISIT: what to do if we miss synchronization and the descriptor * that generated the interrupt is different from the expected (the * oldest of the list containing active transmissions)? */ @@ -2635,7 +2635,7 @@ static int i2s_receive(struct i2s_dev_s *dev, struct ap_buffer_s *apb, } i2sinfo("Prepared %d bytes to receive DMA buffers\n", apb->nmaxbytes); - i2s_dump_buffer("Recieved Audio pipeline buffer:", + i2s_dump_buffer("Received Audio pipeline buffer:", &apb->samp[apb->curbyte], apb->nbytes - apb->curbyte); @@ -2859,7 +2859,7 @@ struct i2s_dev_s *esp_i2sbus_initialize(int port) i2sinfo("port: %d\n", port); - /* Statically allocated I2S' device strucuture */ + /* Statically allocated I2S' device structure */ switch (port) { diff --git a/arch/risc-v/src/common/espressif/esp_ledc.c b/arch/risc-v/src/common/espressif/esp_ledc.c index 7a310133bc..c49c44b6b1 100644 --- a/arch/risc-v/src/common/espressif/esp_ledc.c +++ b/arch/risc-v/src/common/espressif/esp_ledc.c @@ -57,8 +57,8 @@ #define LEDC_IS_DIV_INVALID(div) ((div) <= LEDC_LL_FRACTIONAL_MAX || \ (div) > LEDC_TIMER_DIV_NUM_MAX) -/* Precision degree only affects RC_FAST, other clock sources' frequences are - * fixed values. For targets that do not support RC_FAST calibration, can +/* Precision degree only affects RC_FAST, other clock sources' frequencies + * are fixed values. For targets that do not support RC_FAST calibration, can * only use its approximate value. */ @@ -127,7 +127,7 @@ # define LEDC_TIM3_CHANS_OFF (LEDC_TIM2_CHANS_OFF + LEDC_TIM2_CHANS) #endif -/* Unititialized LEDC timer clock */ +/* Uninitialized LEDC timer clock */ #define LEDC_SLOW_CLK_UNINIT (-1) diff --git a/arch/risc-v/src/common/espressif/esp_nxdiag.c b/arch/risc-v/src/common/espressif/esp_nxdiag.c index 6b88b59917..3bd25518cc 100644 --- a/arch/risc-v/src/common/espressif/esp_nxdiag.c +++ b/arch/risc-v/src/common/espressif/esp_nxdiag.c @@ -169,7 +169,7 @@ int esp_nxdiag_read_flash_status(uint32_t *status) * Name: esp_nxdiag_read_mac * * Description: - * Read MAC adress. + * Read MAC address. * * Input Parameters: * mac - Mac address to return. @@ -234,7 +234,7 @@ static ssize_t esp_nxdiag_read(struct file *filep, ret = esp_nxdiag_read_mac(mac); if (ret != OK) { - printf("Failed to fetch MAC adress\n\n"); + printf("Failed to fetch MAC address\n\n"); } else { diff --git a/arch/risc-v/src/common/espressif/esp_rmt.c b/arch/risc-v/src/common/espressif/esp_rmt.c index 238ff5ca4f..7b2553550f 100644 --- a/arch/risc-v/src/common/espressif/esp_rmt.c +++ b/arch/risc-v/src/common/espressif/esp_rmt.c @@ -978,7 +978,7 @@ static int rmt_internal_config(rmt_dev_t *dev, spin_unlock_irqrestore(&g_rmtdev_common.rmt_spinlock, flags); - rmtinfo("Rmt Rx Channel %u|Gpio %u|Sclk_Hz %"PRIu32"|Div %u|Thresold " + rmtinfo("Rmt Rx Channel %u|Gpio %u|Sclk_Hz %"PRIu32"|Div %u|Threshold " "%u|Filter %u", channel, gpio_num, rmt_source_clk_hz, clk_div, threshold, filter_cnt); } diff --git a/arch/risc-v/src/common/espressif/esp_spiflash.c b/arch/risc-v/src/common/espressif/esp_spiflash.c index 2c157427c7..82ab91dbe3 100644 --- a/arch/risc-v/src/common/espressif/esp_spiflash.c +++ b/arch/risc-v/src/common/espressif/esp_spiflash.c @@ -265,7 +265,7 @@ static IRAM_ATTR void esp_spi_trans(uint32_t command, uint32_t rx_bytes, uint32_t dummy_bits) { - /* Initiliaze SPI user register */ + /* Initialize SPI user register */ spi_flash_ll_reset(dev); @@ -313,7 +313,7 @@ static IRAM_ATTR void esp_spi_trans(uint32_t command, spimem_flash_ll_suspend_cmd_setup(dev, 0); - /* Start transmision */ + /* Start transmission */ spi_flash_ll_user_start(dev); diff --git a/arch/risc-v/src/common/espressif/esp_spiflash_mtd.c b/arch/risc-v/src/common/espressif/esp_spiflash_mtd.c index 46e3b1a7a9..3708c34811 100644 --- a/arch/risc-v/src/common/espressif/esp_spiflash_mtd.c +++ b/arch/risc-v/src/common/espressif/esp_spiflash_mtd.c @@ -283,7 +283,7 @@ static ssize_t esp_bread(struct mtd_dev_s *dev, off_t startblock, * buffer - data buffer pointer * * Returned Value: - * Writen bytes if success or a negative value if fail. + * Written bytes if success or a negative value if fail. * ****************************************************************************/ @@ -337,7 +337,7 @@ static ssize_t esp_write(struct mtd_dev_s *dev, off_t offset, * buffer - data buffer pointer * * Returned Value: - * Writen block number if success or a negative value if fail. + * Written block number if success or a negative value if fail. * ****************************************************************************/ diff --git a/arch/risc-v/src/common/espressif/esp_temperature_sensor.c b/arch/risc-v/src/common/espressif/esp_temperature_sensor.c index a4e198c679..2e629cca46 100644 --- a/arch/risc-v/src/common/espressif/esp_temperature_sensor.c +++ b/arch/risc-v/src/common/espressif/esp_temperature_sensor.c @@ -214,7 +214,7 @@ static temperature_sensor_attribute_t * * Input Parameters: * p1 - First value to compare with other value - * p2 - Second value to compare with outher value + * p2 - Second value to compare with other value * * Returned Value: * Returns -1 if the first value has smaller error rate; 1 otherwise @@ -261,7 +261,7 @@ static int temperature_sensor_attribute_table_sort(void) * * Description: * This function selects least error rated temperature sensor attribute - * for given mesurement range. + * for given measurement range. * * Input Parameters: * priv - Pointer to the internal driver state structure. diff --git a/arch/risc-v/src/common/espressif/esp_wlan.c b/arch/risc-v/src/common/espressif/esp_wlan.c index dc0d879a46..fe7ce4c24d 100644 --- a/arch/risc-v/src/common/espressif/esp_wlan.c +++ b/arch/risc-v/src/common/espressif/esp_wlan.c @@ -1285,7 +1285,7 @@ static int esp_net_initialize(int devno, uint8_t *mac_addr, * * Description: * Wi-Fi station RX done callback function. If this is called, it means - * station receiveing packet. + * station receiving packet. * * Input Parameters: * buffer - Wi-Fi received packet buffer @@ -1339,7 +1339,7 @@ static void wlan_sta_tx_done(uint8_t ifidx, * * Description: * Wi-Fi softAP RX done callback function. If this is called, it means - * softAP receiveing packet. + * softAP receiving packet. * * Input Parameters: * buffer - Wi-Fi received packet buffer @@ -1694,7 +1694,7 @@ int esp_wlan_softap_initialize(void) * ifidx - The interface id that the tx callback has been triggered from * data - Pointer to the data transmitted * data_len - Length of the data transmitted - * txstatus - True:if the data was transmitted sucessfully False: if data + * txstatus - True:if the data was transmitted successfully False: if data * transmission failed * * Returned Value: diff --git a/arch/risc-v/src/common/espressif/esp_wlan.h b/arch/risc-v/src/common/espressif/esp_wlan.h index a3dfc83bab..f1972947a1 100644 --- a/arch/risc-v/src/common/espressif/esp_wlan.h +++ b/arch/risc-v/src/common/espressif/esp_wlan.h @@ -156,7 +156,7 @@ int esp_wlan_softap_initialize(void); * ifidx - The interface id that the tx callback has been triggered from * data - Pointer to the data transmitted * data_len - Length of the data transmitted - * txstatus - True:if the data was transmitted sucessfully False: if data + * txstatus - True:if the data was transmitted successfully False: if data * transmission failed * * Returned Value: diff --git a/arch/risc-v/src/common/riscv_exception_common.S b/arch/risc-v/src/common/riscv_exception_common.S index 1f9d649f7b..cae7250be2 100644 --- a/arch/risc-v/src/common/riscv_exception_common.S +++ b/arch/risc-v/src/common/riscv_exception_common.S @@ -80,7 +80,7 @@ # endif #endif -/* Provide a default section for the exeception handler. */ +/* Provide a default section for the exception handler. */ #ifndef EXCEPTION_SECTION # define EXCEPTION_SECTION .text diff --git a/arch/risc-v/src/common/riscv_macros.S b/arch/risc-v/src/common/riscv_macros.S index 4a0bddc1b9..7eed506328 100644 --- a/arch/risc-v/src/common/riscv_macros.S +++ b/arch/risc-v/src/common/riscv_macros.S @@ -384,7 +384,7 @@ * Name: riscv_set_inital_sp * * Description: - * Set inital sp for riscv core. This function should be only called + * Set initial sp for riscv core. This function should be only called * when initing. * * sp (stack top) = sp base + idle stack size * hart id diff --git a/arch/risc-v/src/common/riscv_pmp.c b/arch/risc-v/src/common/riscv_pmp.c index f20633b7b1..3a13c36485 100644 --- a/arch/risc-v/src/common/riscv_pmp.c +++ b/arch/risc-v/src/common/riscv_pmp.c @@ -418,7 +418,7 @@ static void pmp_read(uintptr_t region, pmp_entry_t * entry) * and the size must be power-of-two according to the the PMP spec. * * Returned Value: - * 0 on succeess; negated error on failure + * 0 on success; negated error on failure * ****************************************************************************/ diff --git a/arch/risc-v/src/common/riscv_tcbinfo.c b/arch/risc-v/src/common/riscv_tcbinfo.c index 1d46c89f55..de3b06360e 100644 --- a/arch/risc-v/src/common/riscv_tcbinfo.c +++ b/arch/risc-v/src/common/riscv_tcbinfo.c @@ -36,7 +36,7 @@ static const uint16_t g_reg_offs[] = { - TCB_REG_OFF(REG_EPC_NDX), /* X0, but it will be ommited by gdb client */ + TCB_REG_OFF(REG_EPC_NDX), /* X0, but it will be omitted by gdb client */ TCB_REG_OFF(REG_X1_NDX), TCB_REG_OFF(REG_X2_NDX), TCB_REG_OFF(REG_X3_NDX), diff --git a/arch/risc-v/src/common/supervisor/riscv_syscall.S b/arch/risc-v/src/common/supervisor/riscv_syscall.S index d6c113f0b0..fb421d0c74 100644 --- a/arch/risc-v/src/common/supervisor/riscv_syscall.S +++ b/arch/risc-v/src/common/supervisor/riscv_syscall.S @@ -62,7 +62,7 @@ * Assumes the context to return is already set up * * Returned Value: - * Return value of system call is returned into contex + * Return value of system call is returned into context * * Assumptions: * Task is running in privileged mode diff --git a/arch/risc-v/src/eic7700x/eic7700x_start.c b/arch/risc-v/src/eic7700x/eic7700x_start.c index b10d00c207..aa8a73490d 100644 --- a/arch/risc-v/src/eic7700x/eic7700x_start.c +++ b/arch/risc-v/src/eic7700x/eic7700x_start.c @@ -404,7 +404,7 @@ void eic7700x_start(int mhartid) * * Description: * Performs the low level UART initialization early in debug so that the - * serial console will be available during bootup. This must be called + * serial console will be available during boot up. This must be called * before riscv_serialinit. NOTE: This function depends on GPIO pin * configuration performed in up_consoleinit() and main clock * initialization performed in up_clkinitialize(). diff --git a/arch/risc-v/src/esp32c3-legacy/esp32c3_aes.c b/arch/risc-v/src/esp32c3-legacy/esp32c3_aes.c index f6d9e4ff65..128438bdea 100644 --- a/arch/risc-v/src/esp32c3-legacy/esp32c3_aes.c +++ b/arch/risc-v/src/esp32c3-legacy/esp32c3_aes.c @@ -491,7 +491,7 @@ int esp32c3_aes_xts_cypher(struct esp32c3_aes_xts_s *aes, bool encrypt, * Name: esp32c3_aes_setkey * * Description: - * Configurate AES key. + * Configure AES key. * * Input Parameters: * aes - AES object data pointer @@ -523,7 +523,7 @@ int esp32c3_aes_setkey(struct esp32c3_aes_s *aes, const void *keyptr, * Name: esp32c3_aes_xts_setkey * * Description: - * Configurate AES XTS key. + * Configure AES XTS key. * * Input Parameters: * aes - AES object data pointer diff --git a/arch/risc-v/src/esp32c3-legacy/esp32c3_aes.h b/arch/risc-v/src/esp32c3-legacy/esp32c3_aes.h index 22de8e4226..7dc19502a2 100644 --- a/arch/risc-v/src/esp32c3-legacy/esp32c3_aes.h +++ b/arch/risc-v/src/esp32c3-legacy/esp32c3_aes.h @@ -160,7 +160,7 @@ int esp32c3_aes_xts_cypher(struct esp32c3_aes_xts_s *aes, bool encrypt, * Name: esp32c3_aes_setkey * * Description: - * Configurate AES key. + * Configure AES key. * * Input Parameters: * aes - AES object data pointer @@ -179,7 +179,7 @@ int esp32c3_aes_setkey(struct esp32c3_aes_s *aes, const void *keyptr, * Name: esp32c3_aes_xts_setkey * * Description: - * Configurate AES XTS key. + * Configure AES XTS key. * * Input Parameters: * aes - AES object data pointer diff --git a/arch/risc-v/src/esp32c3-legacy/esp32c3_ble.c b/arch/risc-v/src/esp32c3-legacy/esp32c3_ble.c index 7e4595e2f8..8031fad940 100644 --- a/arch/risc-v/src/esp32c3-legacy/esp32c3_ble.c +++ b/arch/risc-v/src/esp32c3-legacy/esp32c3_ble.c @@ -107,7 +107,7 @@ static esp_vhci_host_callback_t vhci_host_cb = * Name: esp32c3_ble_send_ready * * Description: - * If the controller could send HCI comand will callback this function. + * If the controller could send HCI command will callback this function. * * Input Parameters: * None @@ -191,8 +191,8 @@ static int esp32c3_ble_recv_cb(uint8_t *data, uint16_t len) * Input Parameters: * drv - BT driver pointer * type - BT packet type - * data - BT packte data buffer pointer - * len - BT packte length + * data - BT packet data buffer pointer + * len - BT packet length * * Returned Value: * Sent bytes on success or a negated value on failure. diff --git a/arch/risc-v/src/esp32c3-legacy/esp32c3_ble_adapter.c b/arch/risc-v/src/esp32c3-legacy/esp32c3_ble_adapter.c index f34fc466a9..88337d0a98 100644 --- a/arch/risc-v/src/esp32c3-legacy/esp32c3_ble_adapter.c +++ b/arch/risc-v/src/esp32c3-legacy/esp32c3_ble_adapter.c @@ -1263,7 +1263,7 @@ static bool IRAM_ATTR is_in_isr_wrapper(void) * Malloc buffer * * Input Parameters: - * szie - buffer size + * size - buffer size * * Returned Value: * None @@ -1287,7 +1287,7 @@ static void *malloc_wrapper(size_t size) * Malloc buffer in DRAM * * Input Parameters: - * szie - buffer size + * size - buffer size * * Returned Value: * None @@ -1649,7 +1649,7 @@ static void coex_schm_status_bit_set_wrapper(uint32_t type, uint32_t status) * Description: * * Input Parameters: - * szie + * size * status * * Returned Value: diff --git a/arch/risc-v/src/esp32c3-legacy/esp32c3_efuse_table.c b/arch/risc-v/src/esp32c3-legacy/esp32c3_efuse_table.c index 59d81ddd19..b50100b219 100644 --- a/arch/risc-v/src/esp32c3-legacy/esp32c3_efuse_table.c +++ b/arch/risc-v/src/esp32c3-legacy/esp32c3_efuse_table.c @@ -502,7 +502,7 @@ static const efuse_desc_t FLASH_TPUW[] = static const efuse_desc_t DIS_DOWNLOAD_MODE[] = { { - 128, 1 /* Disble download mode include boot_mode[3:0] is 0 1 2 3 6 7, */ + 128, 1 /* Disable download mode include boot_mode[3:0] is 0 1 2 3 6 7, */ }, }; @@ -1150,7 +1150,7 @@ const efuse_desc_t *ESP_EFUSE_FLASH_TPUW[] = const efuse_desc_t *ESP_EFUSE_DIS_DOWNLOAD_MODE[] = { - &DIS_DOWNLOAD_MODE[0], /* Disble download mode include boot_mode[3:0] is 0 1 2 3 6 7 */ + &DIS_DOWNLOAD_MODE[0], /* Disable download mode include boot_mode[3:0] is 0 1 2 3 6 7 */ NULL }; diff --git a/arch/risc-v/src/esp32c3-legacy/esp32c3_i2c.c b/arch/risc-v/src/esp32c3-legacy/esp32c3_i2c.c index 309392c1a3..b63a9ef986 100644 --- a/arch/risc-v/src/esp32c3-legacy/esp32c3_i2c.c +++ b/arch/risc-v/src/esp32c3-legacy/esp32c3_i2c.c @@ -820,7 +820,7 @@ static int esp32c3_i2c_sem_waitdone(struct esp32c3_i2c_priv_s *priv) * priv - Pointer to the internal driver state structure. * * Returned Values: - * Zero (OK) is returned on successfull transfer. -ETIMEDOUT is returned + * Zero (OK) is returned on successful transfer. -ETIMEDOUT is returned * in case a transfer didn't finish within the timeout interval. And ERROR * is returned in case of any I2C error during the transfer has happened. * diff --git a/arch/risc-v/src/esp32c3-legacy/esp32c3_oneshot_lowerhalf.c b/arch/risc-v/src/esp32c3-legacy/esp32c3_oneshot_lowerhalf.c index 415d25ee2f..817cedbd70 100644 --- a/arch/risc-v/src/esp32c3-legacy/esp32c3_oneshot_lowerhalf.c +++ b/arch/risc-v/src/esp32c3-legacy/esp32c3_oneshot_lowerhalf.c @@ -162,9 +162,9 @@ static int oneshot_lh_max_delay(struct oneshot_lowerhalf_s *lower, DEBUGASSERT(ts != NULL); /* The real maximum delay surpass the limit that timespec can - * reprent. Even using the better case: a resolution of + * represent. Even using the better case: a resolution of * 1 us. - * Therefore, here, fulfill the timespec with the + * Therefore, here, fill the timespec with the * maximum value it can represent. */ diff --git a/arch/risc-v/src/esp32c3-legacy/esp32c3_pm.c b/arch/risc-v/src/esp32c3-legacy/esp32c3_pm.c index d9943d0694..d611d40632 100644 --- a/arch/risc-v/src/esp32c3-legacy/esp32c3_pm.c +++ b/arch/risc-v/src/esp32c3-legacy/esp32c3_pm.c @@ -225,7 +225,7 @@ static _Atomic uint32_t pm_wakelock = 0; inform_out_sleep_overhead_cb_t g_periph_inform_out_sleep_overhead_cb[PERIPH_INFORM_OUT_SLEEP_OVERHEAD_NO]; -/* Indicates if light sleep shoule be skipped by peripherals. */ +/* Indicates if light sleep should be skipped by peripherals. */ skip_light_sleep_cb_t g_periph_skip_sleep_cb[PERIPH_SKIP_SLEEP_NO]; @@ -674,7 +674,7 @@ static int IRAM_ATTR esp32c3_light_sleep_inner(uint32_t pd_flags, * Name: esp32c3_periph_should_skip_sleep * * Description: - * Indicates if light sleep shoule be skipped by peripherals + * Indicates if light sleep should be skipped by peripherals * * Input Parameters: * None @@ -768,7 +768,7 @@ int esp32c3_pm_unregister_skip_sleep_callback(skip_light_sleep_cb_t cb) * Name: esp32c3_should_skip_light_sleep * * Description: - * Indicates if light sleep shoule be skipped. + * Indicates if light sleep should be skipped. * * Input Parameters: * None @@ -958,8 +958,8 @@ int IRAM_ATTR esp32c3_light_sleep_start(uint64_t *sleep_time) esp32c3_rtc_clk_cal(RTC_CAL_RTC_MUX, RTC_CLK_SRC_CAL_CYCLES); /* Adjustment time consists of parts below: - * 1. Hardware time waiting for internal 8M oscilate clock and XTAL; - * 2. Hardware state swithing time of the rtc main state machine; + * 1. Hardware time waiting for internal 8M oscillate clock and XTAL; + * 2. Hardware state switching time of the rtc main state machine; * 3. Code execution time when clock is not stable; * 4. Code execution time which can be measured; */ diff --git a/arch/risc-v/src/esp32c3-legacy/esp32c3_pm.h b/arch/risc-v/src/esp32c3-legacy/esp32c3_pm.h index fce8da337d..a967393d47 100644 --- a/arch/risc-v/src/esp32c3-legacy/esp32c3_pm.h +++ b/arch/risc-v/src/esp32c3-legacy/esp32c3_pm.h @@ -195,7 +195,7 @@ void esp32c3_sleep_enable_wifi_wakeup(void); * Name: esp32c3_should_skip_light_sleep * * Description: - * Indicates if light sleep shoule be skipped. + * Indicates if light sleep should be skipped. * * Input Parameters: * None diff --git a/arch/risc-v/src/esp32c3-legacy/esp32c3_rtc.c b/arch/risc-v/src/esp32c3-legacy/esp32c3_rtc.c index 2c2603281f..b5603fc9d2 100644 --- a/arch/risc-v/src/esp32c3-legacy/esp32c3_rtc.c +++ b/arch/risc-v/src/esp32c3-legacy/esp32c3_rtc.c @@ -1952,7 +1952,7 @@ static uint32_t esp32c3_get_rtc_dbias_by_efuse(uint8_t chip_version, static void esp32c3_set_rtc_dig_dbias(void) { - /* A reasonable dig_dbias which by scaning pvt to make 160 CPU run + /* A reasonable dig_dbias which by scanning pvt to make 160 CPU run * successful stored in efuse, we store some value in efuse, include: * k_rtc_ldo (slope of rtc voltage & rtc_dbias); * k_dig_ldo (slope of digital voltage & digital_dbias); diff --git a/arch/risc-v/src/esp32c3-legacy/esp32c3_serial.c b/arch/risc-v/src/esp32c3-legacy/esp32c3_serial.c index 297ae92b42..f8ef3bff78 100644 --- a/arch/risc-v/src/esp32c3-legacy/esp32c3_serial.c +++ b/arch/risc-v/src/esp32c3-legacy/esp32c3_serial.c @@ -386,7 +386,7 @@ static int esp32c3_setup(struct uart_dev_s *dev) #endif #ifdef CONFIG_SERIAL_OFLOWCONTROL - /* Configure the ouput flow control */ + /* Configure the output flow control */ if (priv->oflow) { @@ -803,7 +803,7 @@ static int esp32c3_ioctl(struct file *filep, int cmd, unsigned long arg) termiosp->c_cflag |= (priv->iflow) ? CRTS_IFLOW : 0; #endif - /* Set the baud rate in ther termiosp using the + /* Set the baud rate in the termiosp using the * cfsetispeed interface. */ @@ -1033,7 +1033,7 @@ static bool esp32c3_rxflowcontrol(struct uart_dev_s *dev, * * Description: * Performs the low level UART initialization early in debug so that the - * serial console will be available during bootup. This must be called + * serial console will be available during boot up. This must be called * before riscv_serialinit. NOTE: This function depends on GPIO pin * configuration performed in up_consoleinit() and main clock * initialization performed in up_clkinitialize(). @@ -1057,7 +1057,7 @@ void riscv_earlyserialinit(void) #endif /* Configure console in early step. - * Setup for other serials will be perfomed when the serial driver is + * Setup for other serials will be performed when the serial driver is * open. */ diff --git a/arch/risc-v/src/esp32c3-legacy/esp32c3_spiflash.c b/arch/risc-v/src/esp32c3-legacy/esp32c3_spiflash.c index b675bd56cb..637836d6ab 100644 --- a/arch/risc-v/src/esp32c3-legacy/esp32c3_spiflash.c +++ b/arch/risc-v/src/esp32c3-legacy/esp32c3_spiflash.c @@ -350,7 +350,7 @@ int spi_flash_read_encrypted(uint32_t addr, void *buffer, uint32_t size) * func - Function pointer * * Returned Value: - * Absolute address if success or negtive value if failed. + * Absolute address if success or negative value if failed. * ****************************************************************************/ diff --git a/arch/risc-v/src/esp32c3-legacy/esp32c3_spiflash_mtd.c b/arch/risc-v/src/esp32c3-legacy/esp32c3_spiflash_mtd.c index ac850ed355..8bfae8c33a 100644 --- a/arch/risc-v/src/esp32c3-legacy/esp32c3_spiflash_mtd.c +++ b/arch/risc-v/src/esp32c3-legacy/esp32c3_spiflash_mtd.c @@ -409,7 +409,7 @@ static ssize_t esp32c3_bread_decrypt(struct mtd_dev_s *dev, * buffer - data buffer pointer * * Returned Value: - * Writen bytes if success or a negative value if fail. + * Written bytes if success or a negative value if fail. * ****************************************************************************/ @@ -463,7 +463,7 @@ static ssize_t esp32c3_write(struct mtd_dev_s *dev, off_t offset, * buffer - data buffer pointer * * Returned Value: - * Writen block number if success or a negative value if fail. + * Written block number if success or a negative value if fail. * ****************************************************************************/ @@ -512,7 +512,7 @@ static ssize_t esp32c3_bwrite(struct mtd_dev_s *dev, off_t startblock, * buffer - data buffer pointer * * Returned Value: - * Writen block number if success or a negative value if fail. + * Written block number if success or a negative value if fail. * ****************************************************************************/ diff --git a/arch/risc-v/src/esp32c3-legacy/esp32c3_wifi_adapter.c b/arch/risc-v/src/esp32c3-legacy/esp32c3_wifi_adapter.c index 33bf1a0683..c7119ebc8b 100644 --- a/arch/risc-v/src/esp32c3-legacy/esp32c3_wifi_adapter.c +++ b/arch/risc-v/src/esp32c3-legacy/esp32c3_wifi_adapter.c @@ -454,7 +454,7 @@ static bool g_softap_started; static wifi_txdone_cb_t g_softap_txdone_cb; #endif -/* Wi-Fi and BT coexistance OS adapter data */ +/* Wi-Fi and BT coexistence OS adapter data */ #ifdef CONFIG_ESP32C3_WIFI_BT_COEXIST coex_adapter_funcs_t g_coex_adapter_funcs = @@ -3351,7 +3351,7 @@ static uint32_t esp_rand(void) * faster than it is added, this function needs to wait for at least 16 APB * clock cycles after reading previous word. This implementation may * actually wait a bit longer due to extra time spent in arithmetic and - * branch statements. As a (probably unncessary) precaution to avoid + * branch statements. As a (probably unnecessary) precaution to avoid * returning the RNG state as-is, the result is XORed with additional * WDEV_RND_REG reads while waiting. * This code does not run in a critical section, so CPU frequency switch @@ -6883,7 +6883,7 @@ int esp_wifi_softap_rssi(struct iwreq *iwr, bool set) * Name: esp32c3_wifi_bt_coexist_init * * Description: - * Initialize ESP32-C3 Wi-Fi and BT coexistance module. + * Initialize ESP32-C3 Wi-Fi and BT coexistence module. * * Input Parameters: * None diff --git a/arch/risc-v/src/esp32c3-legacy/esp32c3_wifi_adapter.h b/arch/risc-v/src/esp32c3-legacy/esp32c3_wifi_adapter.h index 78b36d00f8..d7806d0584 100644 --- a/arch/risc-v/src/esp32c3-legacy/esp32c3_wifi_adapter.h +++ b/arch/risc-v/src/esp32c3-legacy/esp32c3_wifi_adapter.h @@ -823,7 +823,7 @@ int esp_wifi_softap_rssi(struct iwreq *iwr, bool set); * Name: esp32c3_wifi_bt_coexist_init * * Description: - * Initialize ESP32-C3 Wi-Fi and BT coexistance module. + * Initialize ESP32-C3 Wi-Fi and BT coexistence module. * * Input Parameters: * None diff --git a/arch/risc-v/src/esp32c3-legacy/esp32c3_wlan.c b/arch/risc-v/src/esp32c3-legacy/esp32c3_wlan.c index 2cb2a96ee0..2c17a644a3 100644 --- a/arch/risc-v/src/esp32c3-legacy/esp32c3_wlan.c +++ b/arch/risc-v/src/esp32c3-legacy/esp32c3_wlan.c @@ -1263,7 +1263,7 @@ static int esp32c3_net_initialize(int devno, uint8_t *mac_addr, * * Description: * Wi-Fi station RX done callback function. If this is called, it means - * station receiveing packet. + * station receiving packet. * * Input Parameters: * buffer - Wi-Fi received packet buffer @@ -1314,7 +1314,7 @@ static void wlan_sta_tx_done(uint8_t *data, uint16_t *len, bool status) * * Description: * Wi-Fi softAP RX done callback function. If this is called, it means - * softAP receiveing packet. + * softAP receiving packet. * * Input Parameters: * buffer - Wi-Fi received packet buffer diff --git a/arch/risc-v/src/esp32c3-legacy/hardware/esp32c3_aes.h b/arch/risc-v/src/esp32c3-legacy/hardware/esp32c3_aes.h index 442feba116..c4f8fc928e 100644 --- a/arch/risc-v/src/esp32c3-legacy/hardware/esp32c3_aes.h +++ b/arch/risc-v/src/esp32c3-legacy/hardware/esp32c3_aes.h @@ -647,7 +647,7 @@ #define AES_BLOCK_NUM_REG (DR_REG_AES_BASE + 0x98) /* AES_BLOCK_NUM : R/W; bitpos: [31:0]; default: 0; - * Stores the Block Number of plaintext or cipertext when the AES + * Stores the Block Number of plaintext or ciphertext when the AES * Accelerator operates under the DMA-AES working mode. For details, see * Section 1.5.4. */ diff --git a/arch/risc-v/src/esp32c3-legacy/hardware/esp32c3_rtccntl.h b/arch/risc-v/src/esp32c3-legacy/hardware/esp32c3_rtccntl.h index a124bcfb16..9c255e413f 100644 --- a/arch/risc-v/src/esp32c3-legacy/hardware/esp32c3_rtccntl.h +++ b/arch/risc-v/src/esp32c3-legacy/hardware/esp32c3_rtccntl.h @@ -2440,7 +2440,7 @@ /* RTC_CNTL_SWD_DISABLE : R/W ;bitpos:[30] ;default: 1'b0 ; */ -/* Description: disabel SWD */ +/* Description: disable SWD */ #define RTC_CNTL_SWD_DISABLE (BIT(30)) #define RTC_CNTL_SWD_DISABLE_M (BIT(30)) diff --git a/arch/risc-v/src/esp32c3-legacy/hardware/esp32c3_spi.h b/arch/risc-v/src/esp32c3-legacy/hardware/esp32c3_spi.h index d6ef19c47c..e8448b79e4 100644 --- a/arch/risc-v/src/esp32c3-legacy/hardware/esp32c3_spi.h +++ b/arch/risc-v/src/esp32c3-legacy/hardware/esp32c3_spi.h @@ -91,7 +91,7 @@ #define SPI_CTRL_REG (DR_REG_SPI2_BASE + 0x8) /* SPI_WR_BIT_ORDER : R/W; bitpos: [26]; default: 0; - * In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can + * In command address write-data (MOSI) phases 1: LSB first 0: MSB first. Can * be configured in CONF state. */ @@ -227,7 +227,7 @@ #define SPI_CLOCK_REG (DR_REG_SPI2_BASE + 0xc) /* SPI_CLK_EQU_SYSCLK : R/W; bitpos: [31]; default: 1; - * In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided + * In the master mode 1: spi_clk is equal to system 0: spi_clk is divided * from system clock. Can be configured in CONF state. */ @@ -2122,7 +2122,7 @@ /* SPI_CLK_MODE : R/W; bitpos: [1:0]; default: 0; * SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is * delayed one cycle after CS inactive 2: SPI clock is delayed two cycles - * after CS inactive 3: SPI clock is alwasy on. Can be configured in CONF + * after CS inactive 3: SPI clock is always on. Can be configured in CONF * state. */ diff --git a/arch/risc-v/src/esp32c3-legacy/hardware/esp32c3_uart.h b/arch/risc-v/src/esp32c3-legacy/hardware/esp32c3_uart.h index 08031de0ec..362caa60f2 100644 --- a/arch/risc-v/src/esp32c3-legacy/hardware/esp32c3_uart.h +++ b/arch/risc-v/src/esp32c3-legacy/hardware/esp32c3_uart.h @@ -505,7 +505,7 @@ #define UART_TX_BRK_DONE_INT_ST_S 12 /* UART_TX_BRK_IDLE_DONE_INT_ST : RO; bitpos: [13]; default: 0; - * This is the stauts bit for tx_brk_idle_done_int_raw when + * This is the status bit for tx_brk_idle_done_int_raw when * tx_brk_idle_done_int_ena is set to * 1. */ @@ -1120,7 +1120,7 @@ #define UART_SW_DTR_S 7 /* UART_TXD_BRK : R/W; bitpos: [8]; default: 0; - * Set this bit to enable transmitter to send NULL when the process of + * Set this bit to enable transmitter to send NULL when the process of * sending data is * done. */ diff --git a/arch/risc-v/src/esp32c3-legacy/rom/esp32c3_spiflash.h b/arch/risc-v/src/esp32c3-legacy/rom/esp32c3_spiflash.h index 2d9ebc7d4c..5ab89f9913 100644 --- a/arch/risc-v/src/esp32c3-legacy/rom/esp32c3_spiflash.h +++ b/arch/risc-v/src/esp32c3-legacy/rom/esp32c3_spiflash.h @@ -380,7 +380,7 @@ esp32c3_spiflash_read_statushigh(esp32c3_spiflash_chip_t *spi, * Name: esp32c3_spiflash_write_status * * Description: - * Write status to Falsh status register. + * Write status to Flash status register. * * Please do not call this function in SDK. * @@ -483,7 +483,7 @@ esp_rom_spiflash_config_clk(uint8_t freqdiv, * * Please do not call this function in SDK. * - * Input Paramater: + * Input Parameter: * esp_rom_spiflash_common_cmd_t *cmd : A struct to show the action of a * command. * diff --git a/arch/risc-v/src/esp32c3/esp_ble.c b/arch/risc-v/src/esp32c3/esp_ble.c index 92ccf74af3..7de8ef8c51 100644 --- a/arch/risc-v/src/esp32c3/esp_ble.c +++ b/arch/risc-v/src/esp32c3/esp_ble.c @@ -106,7 +106,7 @@ static esp_vhci_host_callback_t vhci_host_cb = * Name: esp_ble_send_ready * * Description: - * If the controller could send HCI comand will callback this function. + * If the controller could send HCI command will callback this function. * * Input Parameters: * None diff --git a/arch/risc-v/src/esp32c3/esp_coex_adapter.c b/arch/risc-v/src/esp32c3/esp_coex_adapter.c index e7fa08c3cd..36434859cb 100644 --- a/arch/risc-v/src/esp32c3/esp_coex_adapter.c +++ b/arch/risc-v/src/esp32c3/esp_coex_adapter.c @@ -316,7 +316,7 @@ void IRAM_ATTR esp_coex_common_task_yield_from_isr_wrapper(void) * Create and initialize semaphore * * Input Parameters: - * max - No meanining for NuttX + * max - No meaning for NuttX * init - semaphore initialization value * * Returned Value: diff --git a/arch/risc-v/src/esp32c3/esp_wifi_adapter.c b/arch/risc-v/src/esp32c3/esp_wifi_adapter.c index 533fb7c0b2..f468b99bf4 100644 --- a/arch/risc-v/src/esp32c3/esp_wifi_adapter.c +++ b/arch/risc-v/src/esp32c3/esp_wifi_adapter.c @@ -3567,7 +3567,7 @@ static int32_t xqueue_send_adapter(void *queue, * Create and initialize semaphore * * Input Parameters: - * max - No meanining for NuttX + * max - No meaning for NuttX * init - semaphore initialization value * * Returned Value: diff --git a/arch/risc-v/src/esp32c6/esp_coex_adapter.c b/arch/risc-v/src/esp32c6/esp_coex_adapter.c index 95df39e7a4..e5d97b50ee 100644 --- a/arch/risc-v/src/esp32c6/esp_coex_adapter.c +++ b/arch/risc-v/src/esp32c6/esp_coex_adapter.c @@ -316,7 +316,7 @@ void IRAM_ATTR esp_coex_common_task_yield_from_isr_wrapper(void) * Create and initialize semaphore * * Input Parameters: - * max - No meanining for NuttX + * max - No meaning for NuttX * init - semaphore initialization value * * Returned Value: diff --git a/arch/risc-v/src/esp32c6/esp_wifi_adapter.c b/arch/risc-v/src/esp32c6/esp_wifi_adapter.c index 9d42423a1f..4b1f803553 100644 --- a/arch/risc-v/src/esp32c6/esp_wifi_adapter.c +++ b/arch/risc-v/src/esp32c6/esp_wifi_adapter.c @@ -3521,7 +3521,7 @@ static int32_t xqueue_send_adapter(void *queue, * Create and initialize semaphore * * Input Parameters: - * max - No meanining for NuttX + * max - No meaning for NuttX * init - semaphore initialization value * * Returned Value: diff --git a/arch/risc-v/src/fe310/fe310_serial.c b/arch/risc-v/src/fe310/fe310_serial.c index fa74c65ff8..8e48ec61ac 100644 --- a/arch/risc-v/src/fe310/fe310_serial.c +++ b/arch/risc-v/src/fe310/fe310_serial.c @@ -597,7 +597,7 @@ static bool up_txempty(struct uart_dev_s *dev) * * Description: * Performs the low level UART initialization early in debug so that the - * serial console will be available during bootup. This must be called + * serial console will be available during boot up. This must be called * before riscv_serialinit. NOTE: This function depends on GPIO pin * configuration performed in up_consoleinit() and main clock * initialization performed in up_clkinitialize(). diff --git a/arch/risc-v/src/hpm6000/Kconfig b/arch/risc-v/src/hpm6000/Kconfig index eb912fce4c..9644189f64 100644 --- a/arch/risc-v/src/hpm6000/Kconfig +++ b/arch/risc-v/src/hpm6000/Kconfig @@ -34,15 +34,15 @@ config HPM_ENET menu "Watchdog" config HPM_WDOG0 - bool "WathDog" + bool "watchdog" default n config HPM_WDOG1 - bool "WathDog" + bool "watchdog" default n config HPM_WDOG2 - bool "WathDog" + bool "watchdog" default n endmenu # Watchdog diff --git a/arch/risc-v/src/hpm6000/hardware/hpm_gpio.h b/arch/risc-v/src/hpm6000/hardware/hpm_gpio.h index 6b59fb47ba..25c285c9b4 100644 --- a/arch/risc-v/src/hpm6000/hardware/hpm_gpio.h +++ b/arch/risc-v/src/hpm6000/hardware/hpm_gpio.h @@ -34,7 +34,7 @@ #include "hpm6300/hpm6300_ioc.h" #include "hpm6300/hpm6300_pinmux.h" #else -#error The selected HPM variant is not impelemented +#error The selected HPM variant is not implemented #endif /**************************************************************************** diff --git a/arch/risc-v/src/hpm6000/hpm_clockconfig.c b/arch/risc-v/src/hpm6000/hpm_clockconfig.c index 7312737ca7..32db287096 100644 --- a/arch/risc-v/src/hpm6000/hpm_clockconfig.c +++ b/arch/risc-v/src/hpm6000/hpm_clockconfig.c @@ -132,7 +132,7 @@ void hpm_clockconfig(void) putreg32(value, HPM_PLLCTLV2_PLL1_DIV0); while (getreg32(HPM_PLLCTLV2_PLL1_DIV0) & 0x80000000); #endif - /* Configure PLL1 clock frequencey */ + /* Configure PLL1 clock frequency */ value = PLL1_FREQ / PLLCTLV2_PLL_XTAL_FREQ - 1; putreg32(value, HPM_PLLCTLV2_PLL1_MFI); diff --git a/arch/risc-v/src/hpm6000/hpm_serial.c b/arch/risc-v/src/hpm6000/hpm_serial.c index 26d2a89e3b..0e30dd3fad 100644 --- a/arch/risc-v/src/hpm6000/hpm_serial.c +++ b/arch/risc-v/src/hpm6000/hpm_serial.c @@ -1223,7 +1223,7 @@ static bool hpm_txempty(struct uart_dev_s *dev) * * Description: * Performs the low level UART initialization early in debug so that the - * serial console will be available during bootup. This must be called + * serial console will be available during boot up. This must be called * before riscv_serialinit. NOTE: This function depends on GPIO pin * configuration performed in up_consoleinit() and main clock iniialization * performed in up_clkinitialize(). diff --git a/arch/risc-v/src/hpm6750/hardware/hpm6750_ioc.h b/arch/risc-v/src/hpm6750/hardware/hpm6750_ioc.h index d44f444b7e..aacd11b089 100644 --- a/arch/risc-v/src/hpm6750/hardware/hpm6750_ioc.h +++ b/arch/risc-v/src/hpm6750/hardware/hpm6750_ioc.h @@ -304,7 +304,7 @@ /* SMT (RW) * - * schmitt trigger enable, only avaiable in high-speed IO + * schmitt trigger enable, only available in high-speed IO * 0: disable * 1: enable */ diff --git a/arch/risc-v/src/hpm6750/hpm6750_serial.c b/arch/risc-v/src/hpm6750/hpm6750_serial.c index 7ceb953417..eceb857fce 100644 --- a/arch/risc-v/src/hpm6750/hpm6750_serial.c +++ b/arch/risc-v/src/hpm6750/hpm6750_serial.c @@ -798,7 +798,7 @@ static bool up_txempty(struct uart_dev_s *dev) * * Description: * Performs the low level UART initialization early in debug so that the - * serial console will be available during bootup. This must be called + * serial console will be available during boot up. This must be called * before riscv_serialinit. NOTE: This function depends on GPIO pin * configuration performed in up_consoleinit() and main clock iniialization * performed in up_clkinitialize(). diff --git a/arch/risc-v/src/jh7110/jh7110_timerisr.c b/arch/risc-v/src/jh7110/jh7110_timerisr.c index 663db35a4e..1817fae25b 100644 --- a/arch/risc-v/src/jh7110/jh7110_timerisr.c +++ b/arch/risc-v/src/jh7110/jh7110_timerisr.c @@ -64,7 +64,7 @@ static uint32_t g_stimer_pending = false; static int jh7110_ssoft_interrupt(int irq, void *context, void *arg) { - /* Cleaer Supervisor Software Interrupt */ + /* Clear Supervisor Software Interrupt */ CLEAR_CSR(CSR_SIP, SIP_SSIP); diff --git a/arch/risc-v/src/k210/k210_serial.c b/arch/risc-v/src/k210/k210_serial.c index e229dafb97..6b451b3fad 100644 --- a/arch/risc-v/src/k210/k210_serial.c +++ b/arch/risc-v/src/k210/k210_serial.c @@ -597,7 +597,7 @@ static bool up_txempty(struct uart_dev_s *dev) * * Description: * Performs the low level UART initialization early in debug so that the - * serial console will be available during bootup. This must be called + * serial console will be available during boot up. This must be called * before riscv_serialinit. NOTE: This function depends on GPIO pin * configuration performed in up_consoleinit() and main clock * initialization performed in up_clkinitialize(). diff --git a/arch/risc-v/src/litex/litex_emac.c b/arch/risc-v/src/litex/litex_emac.c index f180556b38..2537cdde60 100644 --- a/arch/risc-v/src/litex/litex_emac.c +++ b/arch/risc-v/src/litex/litex_emac.c @@ -1174,7 +1174,7 @@ static void litex_phydump(struct litex_emac_s *priv) * * Input Parameters: * priv - Reference to the private driver state structure - * phyaddr - MDIO address to try and find confgiured PHY IC + * phyaddr - MDIO address to try and find configured PHY IC * * Returned Value: * OK on success; Negated errno on failure. @@ -1255,7 +1255,7 @@ static int litex_phyfind(struct litex_emac_s *priv, uint8_t phyaddr) * priv - A reference to the private driver state structure * * Returned Value: - * Can currenly only return OK + * Can currently only return OK * ****************************************************************************/ diff --git a/arch/risc-v/src/litex/litex_sdio.c b/arch/risc-v/src/litex/litex_sdio.c index 03328624d8..0fde5d1ac1 100644 --- a/arch/risc-v/src/litex/litex_sdio.c +++ b/arch/risc-v/src/litex/litex_sdio.c @@ -597,7 +597,7 @@ static void litex_clock(struct sdio_dev_s *dev, enum sdio_clock_e rate) switch (rate) { - /* Return early - SDPHY doesnt support clock disabling */ + /* Return early - SDPHY does not support clock disabling */ default: case CLOCK_SDIO_DISABLED: diff --git a/arch/risc-v/src/litex/litex_serial.c b/arch/risc-v/src/litex/litex_serial.c index 72130df2fc..619a082374 100644 --- a/arch/risc-v/src/litex/litex_serial.c +++ b/arch/risc-v/src/litex/litex_serial.c @@ -629,7 +629,7 @@ static bool up_txempty(struct uart_dev_s *dev) * * Description: * Performs the low level UART initialization early in debug so that the - * serial console will be available during bootup. This must be called + * serial console will be available during boot up. This must be called * before riscv_serialinit. NOTE: This function depends on GPIO pin * configuration performed in up_consoleinit() and main clock * initialization performed in up_clkinitialize(). diff --git a/arch/risc-v/src/litex/litex_ticked.c b/arch/risc-v/src/litex/litex_ticked.c index 044b7a1472..09fa30cb98 100644 --- a/arch/risc-v/src/litex/litex_ticked.c +++ b/arch/risc-v/src/litex/litex_ticked.c @@ -100,4 +100,4 @@ void up_timer_initialize(void) up_enable_irq(LITEX_IRQ_TIMER0); } -#endif /* !defind(CONFIG_SCHED_TICKLESS) */ +#endif /* !defined(CONFIG_SCHED_TICKLESS) */ diff --git a/arch/risc-v/src/mpfs/Kconfig b/arch/risc-v/src/mpfs/Kconfig index fdb514625f..442a098da3 100644 --- a/arch/risc-v/src/mpfs/Kconfig +++ b/arch/risc-v/src/mpfs/Kconfig @@ -51,7 +51,7 @@ config MPFS_CLKINIT depends on MPFS_BOOTLOADER default y ---help--- - This initilizes the system clocks at mpfs_start.c file. The option may be also turned off + This initializes the system clocks at mpfs_start.c file. The option may be also turned off if some other entity has already set them up. config MPFS_L2_CLEAR diff --git a/arch/risc-v/src/mpfs/hardware/mpfs250t_484_pinmap.h b/arch/risc-v/src/mpfs/hardware/mpfs250t_484_pinmap.h index 6062c07c70..3b8d2886c3 100644 --- a/arch/risc-v/src/mpfs/hardware/mpfs250t_484_pinmap.h +++ b/arch/risc-v/src/mpfs/hardware/mpfs250t_484_pinmap.h @@ -81,7 +81,7 @@ #define MSSIO_MUX_BANK_REG(bank,pin) (MPFS_SYSREG_BASE + \ MSSIO_MUX_BANK_REG_OFFSET(bank,pin)) -/* Drive strenght configuration in mA +/* Drive strength configuration in mA * The following bit combinations are from the reference design. */ diff --git a/arch/risc-v/src/mpfs/hardware/mpfs_gpio.h b/arch/risc-v/src/mpfs/hardware/mpfs_gpio.h index 292cbc2e25..97532336f8 100644 --- a/arch/risc-v/src/mpfs/hardware/mpfs_gpio.h +++ b/arch/risc-v/src/mpfs/hardware/mpfs_gpio.h @@ -33,7 +33,7 @@ #if defined(CONFIG_ARCH_CHIP_MPFS250T_FCVG484) || defined(CONFIG_ARCH_CHIP_MPFS250T_FCG484) #include "hardware/mpfs250t_484_pinmap.h" #else -#error The selected MPFS variant is not impelemented +#error The selected MPFS variant is not implemented #endif /**************************************************************************** @@ -76,7 +76,7 @@ #define MPFS_GPIO_CONFIG_31_OFFSET 0x007C /* GPIO Config 31 */ #define MPFS_GPIO_INTR_OFFSET 0x0080 /* GPIO Irq state */ #define MPFS_GPIO_GPIN_OFFSET 0x0084 /* GPIO Input states */ -#define MPFS_GPIO_GPOUT_OFFSET 0x0088 /* GPIO Ouput states */ +#define MPFS_GPIO_GPOUT_OFFSET 0x0088 /* GPIO Output states */ #define MPFS_GPIO_CONFIG_ALL_OFFSET 0x008C /* GPIO set all configs */ #define MPFS_GPIO_CONFIG_BYTE0_OFFSET 0x0090 /* GPIO set all configs in byte-0 */ #define MPFS_GPIO_CONFIG_BYTE1_OFFSET 0x0094 /* GPIO set all configs in byte-1 */ diff --git a/arch/risc-v/src/mpfs/hardware/mpfs_ihc.h b/arch/risc-v/src/mpfs/hardware/mpfs_ihc.h index 7ea0030ade..9ee6f1e067 100644 --- a/arch/risc-v/src/mpfs/hardware/mpfs_ihc.h +++ b/arch/risc-v/src/mpfs/hardware/mpfs_ihc.h @@ -65,7 +65,7 @@ struct ihc_sbi_rx_msg_s # error Harts misconfigured. Cannot use the same harts. #endif -/* Contex A and B hart ID's used in this system. Context A is the master. */ +/* Context A and B hart ID's used in this system. Context A is the master. */ #if CONFIG_MPFS_IHC_LINUX_ON_HART1 == 1 #define CONTEXTA_HARTID 0x01 diff --git a/arch/risc-v/src/mpfs/hardware/mpfs_wdog.h b/arch/risc-v/src/mpfs/hardware/mpfs_wdog.h index a2059e1f41..80b032858f 100644 --- a/arch/risc-v/src/mpfs/hardware/mpfs_wdog.h +++ b/arch/risc-v/src/mpfs/hardware/mpfs_wdog.h @@ -56,10 +56,10 @@ ****************************************************************************/ #define WDOG_CONTROL_INTEN_MSVP_MASK (1 << 0) /* Bit 0: Enable MVRP interrupt when MVRP level is passed */ -#define WDOG_CONTROL_INTEN_TRIG_MASK (1 << 1) /* Bit 1: Enable NMI interrupt. This bit is permanenty set */ +#define WDOG_CONTROL_INTEN_TRIG_MASK (1 << 1) /* Bit 1: Enable NMI interrupt. This bit is permanently set */ #define WDOG_CONTROL_INTEN_SLEEP_MASK (1 << 2) /* Bit 2: Enable MVRP interrupt when MVRP level is passed and M3 is sleeping */ #define WDOG_CONTROL_ACTIVE_SLEEP_MASK (1 << 3) /* Bit 3: Set WDOG operational during CPU sleep */ -#define WDOG_CONTROL_ENABLE_FORBITTEN_MASK (1 << 4) /* Bit 4: Enable trigger wdog from write during forbitten window */ +#define WDOG_CONTROL_ENABLE_FORBITTEN_MASK (1 << 4) /* Bit 4: Enable trigger wdog from write during forbidden window */ /**************************************************************************** * Status register masks @@ -67,7 +67,7 @@ #define WDOG_STATUS_MVRP_TRIPPED_MASK (1 << 0) /* Bit 0: MVRP level has passed. Write to clear interrupt */ #define WDOG_STATUS_WDOG_TRIPPED_MASK (1 << 1) /* Bit 1: TRIGGER level has passed and NMI is asserted. Write to clear interrupt */ -#define WDOG_STATUS_FORBITTEN_MASK (1 << 2) /* Bit 2: Watchdog in forbitten window */ +#define WDOG_STATUS_FORBITTEN_MASK (1 << 2) /* Bit 2: Watchdog in forbidden window */ #define WDOG_STATUS_TRIGGERED_MASK (1 << 3) /* Bit 3: Watchdog has triggered */ #define WDOG_STATUS_LOCKED_MASK (1 << 4) /* Bit 4: Following registers are locked and cannot be changed */ #define WDOG_STATUS_DEVRST_MASK (1 << 5) /* Bit 5: DEVRST caused NMI */ diff --git a/arch/risc-v/src/mpfs/mpfs_coremmc.c b/arch/risc-v/src/mpfs/mpfs_coremmc.c index 13f0b7a04b..f6038526e9 100644 --- a/arch/risc-v/src/mpfs/mpfs_coremmc.c +++ b/arch/risc-v/src/mpfs/mpfs_coremmc.c @@ -1843,7 +1843,7 @@ static int mpfs_check_recverror(struct mpfs_dev_s *priv) * Input Parameters: * dev - An instance of the SDIO device interface * cmd - Command - * rshort - Buffer for reveiving the response + * rshort - Buffer for receiving the response * * Returned Value: * OK on success; a negated errno on failure. @@ -1887,7 +1887,7 @@ static int mpfs_recvshortcrc(struct sdio_dev_s *dev, uint32_t cmd, * Input Parameters: * dev - An instance of the SDIO device interface * cmd - Command - * rshort - Buffer for reveiving the response + * rshort - Buffer for receiving the response * * Returned Value: * OK on success; a negated errno on failure. @@ -1931,7 +1931,7 @@ static int mpfs_recvshort(struct sdio_dev_s *dev, uint32_t cmd, * Input Parameters: * dev - An instance of the SDIO device interface * cmd - Command - * rlong - Buffer for reveiving the response + * rlong - Buffer for receiving the response * * Returned Value: * OK on success; a negated errno on failure. diff --git a/arch/risc-v/src/mpfs/mpfs_ddr.c b/arch/risc-v/src/mpfs/mpfs_ddr.c index e9c0a2f330..f0e3ea729c 100644 --- a/arch/risc-v/src/mpfs/mpfs_ddr.c +++ b/arch/risc-v/src/mpfs/mpfs_ddr.c @@ -579,7 +579,7 @@ static void mpfs_set_ddr_rpc_regs(struct mpfs_ddr_priv_s *priv) putreg32(0, MPFS_CFG_DDR_SGMII_PHY_RPC20); - /* Each lane has its own FIFO. This paramater adjusts offset for + /* Each lane has its own FIFO. This parameter adjusts offset for * all lanes. */ diff --git a/arch/risc-v/src/mpfs/mpfs_dma.c b/arch/risc-v/src/mpfs/mpfs_dma.c index 24f2afd66f..2f5e89fda6 100644 --- a/arch/risc-v/src/mpfs/mpfs_dma.c +++ b/arch/risc-v/src/mpfs/mpfs_dma.c @@ -421,7 +421,7 @@ int mpfs_dma_get_complete_status(unsigned int channel) * * Returned Value: * 0 - No Error - * 1 - Transfer Errror + * 1 - Transfer Error * ****************************************************************************/ @@ -490,7 +490,7 @@ int mpfs_dma_clear_complete_status(unsigned int channel) * * Returned Value: * 0 - No Error - * 1 - Transfer Errror + * 1 - Transfer Error * ****************************************************************************/ diff --git a/arch/risc-v/src/mpfs/mpfs_emmcsd.c b/arch/risc-v/src/mpfs/mpfs_emmcsd.c index c723223a59..1e375e799a 100644 --- a/arch/risc-v/src/mpfs/mpfs_emmcsd.c +++ b/arch/risc-v/src/mpfs/mpfs_emmcsd.c @@ -2532,7 +2532,7 @@ static int mpfs_check_recverror(struct mpfs_dev_s *priv) * Input Parameters: * dev - An instance of the SDIO device interface * cmd - Command - * rshort - Buffer for reveiving the response + * rshort - Buffer for receiving the response * * Returned Value: * OK on success; a negated errno on failure. @@ -2570,7 +2570,7 @@ static int mpfs_recvshortcrc(struct sdio_dev_s *dev, uint32_t cmd, * Input Parameters: * dev - An instance of the SDIO device interface * cmd - Command - * rshort - Buffer for reveiving the response + * rshort - Buffer for receiving the response * * Returned Value: * OK on success; a negated errno on failure. @@ -2606,7 +2606,7 @@ static int mpfs_recvshort(struct sdio_dev_s *dev, uint32_t cmd, * Input Parameters: * dev - An instance of the SDIO device interface * cmd - Command - * rlong - Buffer for reveiving the response + * rlong - Buffer for receiving the response * * Returned Value: * OK on success; a negated errno on failure. diff --git a/arch/risc-v/src/mpfs/mpfs_ethernet.c b/arch/risc-v/src/mpfs/mpfs_ethernet.c index 82102f9eec..6ad88a75ed 100644 --- a/arch/risc-v/src/mpfs/mpfs_ethernet.c +++ b/arch/risc-v/src/mpfs/mpfs_ethernet.c @@ -1129,7 +1129,7 @@ static void mpfs_interrupt_work(void *arg) *priv->queue[queue].int_status = 0xffffffff; mac_putreg(priv, RECEIVE_STATUS, 0xffffffff); - /* rxreset disables reveiver so re-enable it */ + /* rxreset disables receiver so re-enable it */ regval = mac_getreg(priv, NETWORK_CONTROL); regval |= NETWORK_CONTROL_ENABLE_RECEIVE; diff --git a/arch/risc-v/src/mpfs/mpfs_ihc.c b/arch/risc-v/src/mpfs/mpfs_ihc.c index 9284014e2c..84dcd92a25 100644 --- a/arch/risc-v/src/mpfs/mpfs_ihc.c +++ b/arch/risc-v/src/mpfs/mpfs_ihc.c @@ -577,7 +577,7 @@ static void mpfs_ihc_rx_message(ihc_channel_t channel, uint32_t mhartid, * * Description: * This is called from the interrupt handler. This figures out the actions - * based on the information retieved from the subsequent functions. + * based on the information retrieved from the subsequent functions. * * Input Parameters: * None @@ -1175,7 +1175,7 @@ static int mpfs_echo_ping_init(struct rpmsg_device *rdev, * * Description: * Callback that is called when the underlying rpmsg device has been - * created. This is used to initialize the ping enpoint at the proper + * created. This is used to initialize the ping endpoint at the proper * time. * * Input Parameters: diff --git a/arch/risc-v/src/mpfs/mpfs_opensbi.c b/arch/risc-v/src/mpfs/mpfs_opensbi.c index 55a4ec4cfb..3e41e0da9d 100644 --- a/arch/risc-v/src/mpfs/mpfs_opensbi.c +++ b/arch/risc-v/src/mpfs/mpfs_opensbi.c @@ -431,7 +431,7 @@ static int mpfs_early_init(bool cold_boot) * 2. MPFS_IRQ_MTIMER * * U-boot will reuse eMMC and loads the kernel from there. OpenSBI will - * use CLINT timer. Upstream u-boot doesn't turn the clocks on itsef. + * use CLINT timer. Upstream u-boot doesn't turn the clocks on itself. */ if (!cold_boot) diff --git a/arch/risc-v/src/mpfs/mpfs_opensbi_trap.S b/arch/risc-v/src/mpfs/mpfs_opensbi_trap.S index 46090ab952..d78b7546fb 100644 --- a/arch/risc-v/src/mpfs/mpfs_opensbi_trap.S +++ b/arch/risc-v/src/mpfs/mpfs_opensbi_trap.S @@ -128,7 +128,7 @@ mpfs_global_pointer: REG_S t0, SBI_TRAP_REGS_OFFSET(mstatus)(sp) REG_S zero, SBI_TRAP_REGS_OFFSET(mstatusH)(sp) - /* Save all general regisers except SP and T0 */ + /* Save all general registers except SP and T0 */ REG_S zero, SBI_TRAP_REGS_OFFSET(zero)(sp) REG_S ra, SBI_TRAP_REGS_OFFSET(ra)(sp) @@ -171,7 +171,7 @@ mpfs_global_pointer: add a0, sp, zero call sbi_trap_handler - /* Restore all general regisers except A0 and T0 */ + /* Restore all general registers except A0 and T0 */ REG_L ra, SBI_TRAP_REGS_OFFSET(ra)(a0) REG_L sp, SBI_TRAP_REGS_OFFSET(sp)(a0) diff --git a/arch/risc-v/src/mpfs/mpfs_plic.c b/arch/risc-v/src/mpfs/mpfs_plic.c index 2e984596df..b012553859 100644 --- a/arch/risc-v/src/mpfs/mpfs_plic.c +++ b/arch/risc-v/src/mpfs/mpfs_plic.c @@ -320,7 +320,7 @@ void mpfs_plic_clear_and_enable_irq(int extirq) putreg32(claim, claim_address); - /* Return the irq priority to mininum */ + /* Return the irq priority to minimum */ putreg32(MPFS_PLIC_PRIO_MIN, MPFS_PLIC_PRIORITY + (4 * extirq)); } diff --git a/arch/risc-v/src/mpfs/mpfs_serial.c b/arch/risc-v/src/mpfs/mpfs_serial.c index c457eca44d..f168bd2401 100644 --- a/arch/risc-v/src/mpfs/mpfs_serial.c +++ b/arch/risc-v/src/mpfs/mpfs_serial.c @@ -1162,7 +1162,7 @@ static bool up_txempty(struct uart_dev_s *dev) * * Description: * Performs the low level UART initialization early in debug so that the - * serial console will be available during bootup. This must be called + * serial console will be available during boot up. This must be called * before riscv_serialinit. NOTE: This function depends on * main clock initialization performed in up_clkinitialize(). * diff --git a/arch/risc-v/src/mpfs/mpfs_usb.c b/arch/risc-v/src/mpfs/mpfs_usb.c index fc18378458..0bb816bbee 100644 --- a/arch/risc-v/src/mpfs/mpfs_usb.c +++ b/arch/risc-v/src/mpfs/mpfs_usb.c @@ -1678,7 +1678,7 @@ static int mpfs_ep_disable(struct usbdev_ep_s *ep) * ep - USB device endpoint (unused) * * Returned Value: - * New allocated request struct or NULL if no mempry + * New allocated request struct or NULL if no memory * ****************************************************************************/ @@ -2225,7 +2225,7 @@ static struct usbdev_ep_s *mpfs_allocep(struct usbdev_s *dev, uint8_t epno, * * Description: * The endpoint is no longer in use. It will be unreserved and can be - * re-used if needed. + * reused if needed. * * Input Parameters: * priv - USB device abstraction diff --git a/arch/risc-v/src/nuttsbi/sbi_internal.h b/arch/risc-v/src/nuttsbi/sbi_internal.h index 35e8b5ae78..32456fdd91 100644 --- a/arch/risc-v/src/nuttsbi/sbi_internal.h +++ b/arch/risc-v/src/nuttsbi/sbi_internal.h @@ -114,7 +114,7 @@ void sbi_start(void) noreturn_function; * Send an inter-processor interrupt to all the harts defined * * Input Parameters: - * hmask - Mask fo CPU to send IPI + * hmask - Mask for CPU to send IPI * hbase - The firset CPU id to send * ****************************************************************************/ diff --git a/arch/risc-v/src/nuttsbi/sbi_mtrap.S b/arch/risc-v/src/nuttsbi/sbi_mtrap.S index cf5a208cf4..acd338c3e6 100644 --- a/arch/risc-v/src/nuttsbi/sbi_mtrap.S +++ b/arch/risc-v/src/nuttsbi/sbi_mtrap.S @@ -147,7 +147,7 @@ machine_trap: * Description: * Allocate separate stack(s) for machine mode interrupts, only if kernel * runs in S-mode. Separate stacks are needed as M-mode interrupts can - * pre-empt S-mode interrupts. + * preempt S-mode interrupts. * ****************************************************************************/ diff --git a/arch/risc-v/src/qemu-rv/qemu_rv_rptun.c b/arch/risc-v/src/qemu-rv/qemu_rv_rptun.c index c525333b80..5bfa39cbe1 100644 --- a/arch/risc-v/src/qemu-rv/qemu_rv_rptun.c +++ b/arch/risc-v/src/qemu-rv/qemu_rv_rptun.c @@ -174,12 +174,12 @@ int rp_init_ipi(void) while (*ptr != '\0' && *ptr != ',') { - ptr++; /* seek delimeter */ + ptr++; /* seek delimiter */ } if (*ptr) { - ptr++; /* skip delimeter */ + ptr++; /* skip delimiter */ } i++; diff --git a/arch/risc-v/src/rv32m1/hardware/rv32m1_lpit.h b/arch/risc-v/src/rv32m1/hardware/rv32m1_lpit.h index 265c2791f5..b971aa8858 100644 --- a/arch/risc-v/src/rv32m1/hardware/rv32m1_lpit.h +++ b/arch/risc-v/src/rv32m1/hardware/rv32m1_lpit.h @@ -37,7 +37,7 @@ #define RV32M1_LPIT_PARAM_OFFSET 0x0004 /* Parameter */ #define RV32M1_LPIT_MCR_OFFSET 0x0008 /* Module Control */ #define RV32M1_LPIT_MSR_OFFSET 0x000c /* Module Status Register */ -#define RV32M1_LPIT_MIER_OFFSET 0x0010 /* Moduel Interrupt Enable */ +#define RV32M1_LPIT_MIER_OFFSET 0x0010 /* Module Interrupt Enable */ #define RV32M1_LPIT_SETTEN_OFFSET 0x0014 /* Set Timer Enable */ #define RV32M1_LPIT_CLRTEN_OFFSET 0x0018 /* Clear Timer Enable */ #define RV32M1_LPIT_TVAL0_OFFSET 0x0020 /* Timer Channel 0 Value */ diff --git a/arch/risc-v/src/rv32m1/hardware/rv32m1_lpuart.h b/arch/risc-v/src/rv32m1/hardware/rv32m1_lpuart.h index a6acb40d21..8ea052a0e7 100644 --- a/arch/risc-v/src/rv32m1/hardware/rv32m1_lpuart.h +++ b/arch/risc-v/src/rv32m1/hardware/rv32m1_lpuart.h @@ -130,7 +130,7 @@ #define LPUART_STAT_RXEDGIF (1 << 30) /* Bit30: RXD Pin Active Edge Interrupt Flag */ #define LPUART_STAT_MSBF (1 << 29) /* Bit29: MSB First */ #define LPUART_STAT_RXINV (1 << 28) /* Bit28: Receive Data Inversion */ -#define LPUART_STAT_RWUID (1 << 27) /* Bit27: Receive Wake Up Idel Detect */ +#define LPUART_STAT_RWUID (1 << 27) /* Bit27: Receive Wake Up Idle Detect */ #define LPUART_STAT_BRK13 (1 << 26) /* Bit26: Break Character Generation Length */ #define LPUART_STAT_LBKDE (1 << 25) /* Bit25: Lin Break Detection Enable */ #define LPUART_STAT_RAF (1 << 24) /* Bit24: Receiver Active Flag */ diff --git a/arch/risc-v/src/rv32m1/hardware/rv32m1ri5cy_scg.h b/arch/risc-v/src/rv32m1/hardware/rv32m1ri5cy_scg.h index ca0118ba0a..23c586870f 100644 --- a/arch/risc-v/src/rv32m1/hardware/rv32m1ri5cy_scg.h +++ b/arch/risc-v/src/rv32m1/hardware/rv32m1ri5cy_scg.h @@ -39,7 +39,7 @@ #define RV32M1_SCG_SIRCCSR_OFFSET 0x0200 /* Slow IRC Control Status */ #define RV32M1_SCG_SIRCDIV_OFFSET 0x0204 /* Slow IRC Divider */ #define RV32M1_SCG_SIRCCFG_OFFSET 0x0208 /* Slow IRC Configuration */ -#define RV32M1_SCG_FIRCCSR_OFFSET 0x0300 /* Fast IRC Constrol Status */ +#define RV32M1_SCG_FIRCCSR_OFFSET 0x0300 /* Fast IRC Control Status */ #define RV32M1_SCG_FIRCDIV_OFFSET 0x0304 /* Fast IRC Divider */ #define RV32M1_SCG_FIRCCFG_OFFSET 0x0308 /* Fast IRC Configuration */ #define RV32M1_SCG_FIRCTCFG_OFFSET 0x030c /* Fast IRC Trim Configuration */ @@ -483,7 +483,7 @@ /* FIRC Trim Configuration */ -#define SCG_FIRCTCFG_TRIMDIV_SHIFT (8) /* Divide the System OSC down for Fast IRC Triming */ +#define SCG_FIRCTCFG_TRIMDIV_SHIFT (8) /* Divide the System OSC down for Fast IRC Trimming */ #define SCG_FIRCTCFG_TRIMDIV_MASK (7 << SCG_FIRCTCFG_TRIMDIV_SHIFT) #define SCG_FIRCTCFG_TRIMDIV_DIVBY1 (0 << SCG_FIRCTCFG_TRIMDIV_SHIFT) #define SCG_FIRCTCFG_TRIMDIV_DIVBY128 (1 << SCG_FIRCTCFG_TRIMDIV_SHIFT) diff --git a/arch/risc-v/src/rv32m1/rv32m1_clockconfig.c b/arch/risc-v/src/rv32m1/rv32m1_clockconfig.c index 7a5dddaca3..77d612ba3b 100644 --- a/arch/risc-v/src/rv32m1/rv32m1_clockconfig.c +++ b/arch/risc-v/src/rv32m1/rv32m1_clockconfig.c @@ -386,7 +386,7 @@ void rv32m1_clockconfig(void) * Name: rv32m1_clockfreq * * Description: - * Query the frequecy of a given clock source. + * Query the frequency of a given clock source. * ****************************************************************************/ diff --git a/arch/risc-v/src/rv32m1/rv32m1_delay.c b/arch/risc-v/src/rv32m1/rv32m1_delay.c index 9e82cf6ae4..1f39c7a6d5 100644 --- a/arch/risc-v/src/rv32m1/rv32m1_delay.c +++ b/arch/risc-v/src/rv32m1/rv32m1_delay.c @@ -191,7 +191,7 @@ void up_mdelay(unsigned int milliseconds) /* When Timer Service is up, and its frequency isn't less than 1KHz, * the granularity of Timer Service can provide 1 ms accuracy. In - * other cases, sofware delay timer is preferred. + * other cases, software delay timer is preferred. */ if (!rv32m1_timersvc_up() || freq < 1000u || !period) @@ -224,7 +224,7 @@ void up_udelay(useconds_t microseconds) /* When Timer Service is up, and its frequency isn't less than 1MHz, * the granularity of Timer Service can provide 1 us accuracy. In - * other cases, sofware delay timer is preferred. + * other cases, software delay timer is preferred. */ if (!rv32m1_timersvc_up() || freq < 1000000u || !period) diff --git a/arch/risc-v/src/rv32m1/rv32m1_gpio.c b/arch/risc-v/src/rv32m1/rv32m1_gpio.c index e53eb70bc7..5a4acc9c5a 100644 --- a/arch/risc-v/src/rv32m1/rv32m1_gpio.c +++ b/arch/risc-v/src/rv32m1/rv32m1_gpio.c @@ -344,7 +344,7 @@ static int rv32m1_gpio_interrupt(int irq, void *context, void *arg) { priv = container_of(e, const struct rv32m1_isr_s, link); - /* Dispatch services to whom has subcribed(registered) the + /* Dispatch services to whom has subscribed(registered) the * corresponding pin. */ @@ -422,7 +422,7 @@ int rv32m1_gpio_config(uint32_t cfgset) rv32m1_pcc_clock_enable(g_ctrlbase[port].gpiogate); } - /* Cofigure Open Drain, Pull Up/Down, Filter and Slew Rate abilities */ + /* Configure Open Drain, Pull Up/Down, Filter and Slew Rate abilities */ rv32m1_gpio_portconfig(cfgset); diff --git a/arch/risc-v/src/rv32m1/rv32m1_serial.c b/arch/risc-v/src/rv32m1/rv32m1_serial.c index 62783dd0dd..385700ffe7 100644 --- a/arch/risc-v/src/rv32m1/rv32m1_serial.c +++ b/arch/risc-v/src/rv32m1/rv32m1_serial.c @@ -998,7 +998,7 @@ static bool up_txempty(struct uart_dev_s *dev) * * Description: * Performs the low level UART initialization early in debug so that the - * serial console will be available during bootup. This must be called + * serial console will be available during boot up. This must be called * before riscv_serialinit. NOTE: This function depends on GPIO pin * configuration performed in up_consoleinit() and main clock * initialization performed in up_clkinitialize(). @@ -1064,7 +1064,7 @@ void riscv_serialinit(void) /* Place a dummy One as a Place holder to avoid uartdevs * to be empty when All above uart devices are undefined, - * in which case a complier error will raise. + * in which case a compiler error will raise. */ { diff --git a/arch/risc-v/src/rv32m1/rv32m1_timersvc.c b/arch/risc-v/src/rv32m1/rv32m1_timersvc.c index fc07db94cf..c191dec88b 100644 --- a/arch/risc-v/src/rv32m1/rv32m1_timersvc.c +++ b/arch/risc-v/src/rv32m1/rv32m1_timersvc.c @@ -91,7 +91,7 @@ uint32_t rv32m1_timersvc_value(void) uint64_t value = *(volatile uint64_t *)(RV32M1_TSTMR_BASE); - /* It is ok to return the ONLY low valud caused the it is accumulated + /* It is ok to return ONLY the low value because the it is accumulated * outside. */ diff --git a/arch/risc-v/src/sg2000/sg2000_start.c b/arch/risc-v/src/sg2000/sg2000_start.c index 2ecb844e40..3d768a45d3 100644 --- a/arch/risc-v/src/sg2000/sg2000_start.c +++ b/arch/risc-v/src/sg2000/sg2000_start.c @@ -295,7 +295,7 @@ void sg2000_start(int mhartid) * * Description: * Performs the low level UART initialization early in debug so that the - * serial console will be available during bootup. This must be called + * serial console will be available during boot up. This must be called * before riscv_serialinit. NOTE: This function depends on GPIO pin * configuration performed in up_consoleinit() and main clock * initialization performed in up_clkinitialize(). diff --git a/arch/sim/src/sim/posix/sim_linuxi2c.c b/arch/sim/src/sim/posix/sim_linuxi2c.c index 101b5cdd2b..639ee2e85c 100644 --- a/arch/sim/src/sim/posix/sim_linuxi2c.c +++ b/arch/sim/src/sim/posix/sim_linuxi2c.c @@ -218,7 +218,7 @@ static int linux_i2cbus_transfer(struct i2c_master_s *dev, } else { - /* Many busses cannot handle more than 2 messages */ + /* Many buses cannot handle more than 2 messages */ return -1; } diff --git a/arch/sim/src/sim/posix/sim_linuxspi.c b/arch/sim/src/sim/posix/sim_linuxspi.c index 6ab42841f9..78a3212389 100644 --- a/arch/sim/src/sim/posix/sim_linuxspi.c +++ b/arch/sim/src/sim/posix/sim_linuxspi.c @@ -112,7 +112,7 @@ static int linux_spi_transfer(struct spi_dev_s *dev, const void *txbuffer, static struct spi_ops_s spi_linux_ops = { /* The operations below are the same as those in nuttx/spi/spi.h. - * Some perations are dummy, merely for compatiablity with nuttx spi. + * Some operations are dummy, merely for compatibility with nuttx spi. */ .lock = linux_spi_lock, /* Dummy for compatibility. */ @@ -221,14 +221,14 @@ static void linux_spi_select(struct spi_dev_s *dev, uint32_t devid, * Description: * Provide spi setfrequency, used for set SPI clock frequency. * Note that only MAX_SPEED_HZ could be configured out of a transfer for a - * Linux SPI port. The Linux SPI may set a exact frequecy using the value + * Linux SPI port. The Linux SPI may set a exact frequency using the value * of spi_ioc_transfer.speed_hz when transferring. If the * spi_ioc_transfer.speed_hz is 0, the MAX_SPEED_HZ is used. In practice, - * the real frequecy on the CLK wire will be affected by the hardware. + * the real frequency on the CLK wire will be affected by the hardware. * * Input Parameters: * dev - A pointer to instance of Linux SPI device. - * frequency - The frequencey of SPI clock in Hz. + * frequency - The frequency of SPI clock in Hz. * * Returned Value: * Returns the actual frequency in Hz. @@ -288,7 +288,7 @@ static int linux_spi_setdelay(struct spi_dev_s *dev, uint32_t startdelay, * * Description: * Provide spi setmode. - * SPI mode defination in nuttx is almost the same to that in Linux. + * SPI mode definition in nuttx is almost the same to that in Linux. * * Input Parameters: * dev - A pointer to instance of Linux SPI device. @@ -416,7 +416,7 @@ static int linux_spi_hwfeatures(struct spi_dev_s *dev, * Among them, features on bit 1, 2, 4 is supported. * And CS_ACTIVE/INACTIVE can not be set immediately until calling * linux_spi_transfer. Here it's recorded in linux_spi_dev_s.hwfeatures - * for furture use. + * for future use. */ priv->hwfeatures = features; diff --git a/arch/sim/src/sim/sim_lcd.c b/arch/sim/src/sim/sim_lcd.c index 76b05acb58..9d06b16a34 100644 --- a/arch/sim/src/sim/sim_lcd.c +++ b/arch/sim/src/sim/sim_lcd.c @@ -263,7 +263,7 @@ static int sim_putrun(struct lcd_dev_s *dev, fb_coord_t row, fb_coord_t col, * buffer - The buffer containing the area to be written to the LCD * stride - Length of a line in bytes. This parameter may be necessary * to allow the LCD driver to calculate the offset for partial - * writes when the buffer needs to be splited for row-by-row + * writes when the buffer needs to be split for row-by-row * writing. * ****************************************************************************/ diff --git a/arch/sim/src/sim/sim_offload.h b/arch/sim/src/sim/sim_offload.h index cc21a93faa..274cd0e203 100644 --- a/arch/sim/src/sim/sim_offload.h +++ b/arch/sim/src/sim/sim_offload.h @@ -50,7 +50,7 @@ typedef struct sim_codec_ops_s void *(*init)(struct audio_info_s *info); - /* return how much samples return from deocde. + /* return how much samples return from decode. * or encoder needed. * */ diff --git a/arch/sim/src/sim/sim_rpmsg_virtio.c b/arch/sim/src/sim/sim_rpmsg_virtio.c index 6e459c1263..fbedcf8bd5 100644 --- a/arch/sim/src/sim/sim_rpmsg_virtio.c +++ b/arch/sim/src/sim/sim_rpmsg_virtio.c @@ -124,7 +124,7 @@ sim_rpmsg_virtio_get_resource(struct rpmsg_virtio_lite_s *dev) } else { - /* Wait untils master is ready */ + /* Wait until master is ready */ while (priv->shmem->base == 0) { diff --git a/arch/sim/src/sim/sim_rptun.c b/arch/sim/src/sim/sim_rptun.c index c240ad05b6..399506c5b5 100644 --- a/arch/sim/src/sim/sim_rptun.c +++ b/arch/sim/src/sim/sim_rptun.c @@ -172,7 +172,7 @@ sim_rptun_get_resource(struct rptun_dev_s *dev) priv->shmem->boots = SIM_RPTUN_STATUS_BOOT; - /* Wait untils master is ready */ + /* Wait until master is ready */ while (!(priv->shmem->bootm & SIM_RPTUN_STATUS_OK)) { diff --git a/arch/sim/src/sim/sim_usbdev.c b/arch/sim/src/sim/sim_usbdev.c index f04e84a582..eb086d3344 100644 --- a/arch/sim/src/sim/sim_usbdev.c +++ b/arch/sim/src/sim/sim_usbdev.c @@ -853,7 +853,7 @@ static struct sim_ep_s *sim_ep_reserve(struct sim_usbdev_s *priv, * * Description: * The endpoint is no long in-used. It will be un-reserved and can be - * re-used if needed. + * reused if needed. * ****************************************************************************/ diff --git a/arch/sim/src/sim/sim_wifidriver.c b/arch/sim/src/sim/sim_wifidriver.c index 1303424ad9..5c00d1de01 100644 --- a/arch/sim/src/sim/sim_wifidriver.c +++ b/arch/sim/src/sim/sim_wifidriver.c @@ -855,7 +855,7 @@ get_scan: p = realloc(rbuf, size); if (p == NULL) { - nerr("get scan faied in realloc!\n"); + nerr("get scan failed in realloc!\n"); free(rbuf); return -ENOMEM; } @@ -1482,7 +1482,7 @@ static int wifidriver_start_connect(struct sim_netdev_s *wifidev) { case IW_MODE_INFRA: - /* If wlan is connected, should be disconnect before connectting. */ + /* If wlan is connected, should be disconnect before connecting. */ set_cmd(wifidev, "select_network %d", wifidev->network_id); set_cmd(wifidev, "disconnect"); @@ -1495,7 +1495,7 @@ static int wifidriver_start_connect(struct sim_netdev_s *wifidev) wifidev->psk_flag = 0; } - /* Wait the connect sucess. */ + /* Wait the connect success. */ while (timeout--) { diff --git a/arch/sparc/include/sparc_v8/irq.h b/arch/sparc/include/sparc_v8/irq.h index ed0f07aab8..701df770f3 100644 --- a/arch/sparc/include/sparc_v8/irq.h +++ b/arch/sparc/include/sparc_v8/irq.h @@ -162,28 +162,28 @@ #define REG_Y (18) #define REG_FSR (19) -/* %l0: loacal 0 */ +/* %l0: local 0 */ #define REG_L0 (52) -/* %l1: loacal 1 */ +/* %l1: local 1 */ #define REG_L1 (53) -/* %l2: loacal 2 */ +/* %l2: local 2 */ #define REG_L2 (54) -/* %l3: loacal 3 */ +/* %l3: local 3 */ #define REG_L3 (55) -/* %l4: loacal 4 */ +/* %l4: local 4 */ #define REG_L4 (56) -/* %l5: loacal 5 */ +/* %l5: local 5 */ #define REG_L5 (57) -/* %l6: loacal 6 */ +/* %l6: local 6 */ #define REG_L6 (58) -/* %l7: loacal 7 */ +/* %l7: local 7 */ #define REG_L7 (59) /* %o0: outgoing param 0, incoming return value */ @@ -503,7 +503,7 @@ struct xcptcontext */ #define sparc_get_tbr( _tbr ) \ do { \ - (_tbr) = 0; /* to avoid unitialized warnings */ \ + (_tbr) = 0; /* to avoid uninitialized warnings */ \ __asm__ volatile( "rd %%tbr, %0" : "=r" (_tbr) : "0" (_tbr) ); \ } while ( 0 ) @@ -555,7 +555,7 @@ struct xcptcontext */ #define sparc_get_asr17( _asr17 ) \ do { \ - (_asr17) = 0; /* to avoid unitialized warnings */ \ + (_asr17) = 0; /* to avoid uninitialized warnings */ \ __asm__ volatile( "rd %%asr17, %0" : "=r" (_asr17) : "0" (_asr17) ); \ } while ( 0 ) diff --git a/arch/sparc/src/bm3803/bm3803-irq.c b/arch/sparc/src/bm3803/bm3803-irq.c index fd0a9b0eb6..dd740ee0fc 100644 --- a/arch/sparc/src/bm3803/bm3803-irq.c +++ b/arch/sparc/src/bm3803/bm3803-irq.c @@ -89,7 +89,7 @@ void up_irqinitialize(void) /* And finally, enable interrupts */ - /* Interrupts are enabled by setting the te bit in the psr status + /* Interrupts are enabled by setting the the bit in the psr status * register */ diff --git a/arch/sparc/src/bm3803/bm3803-serial.c b/arch/sparc/src/bm3803/bm3803-serial.c index cf6f2719ab..4a4e014306 100644 --- a/arch/sparc/src/bm3803/bm3803-serial.c +++ b/arch/sparc/src/bm3803/bm3803-serial.c @@ -823,7 +823,7 @@ static bool up_txempty(struct uart_dev_s *dev) * * Description: * Performs the low level UART initialization early in debug so that the - * serial console will be available during bootup. This must be called + * serial console will be available during boot up. This must be called * before sparc_serialinit. NOTE: This function depends on GPIO pin * configuration performed in sparc_consoleinit() and main clock * iniialization performed in up_clkinitialize(). diff --git a/arch/sparc/src/bm3803/bm3803.h b/arch/sparc/src/bm3803/bm3803.h index 5215ee68fa..a3f3a03081 100644 --- a/arch/sparc/src/bm3803/bm3803.h +++ b/arch/sparc/src/bm3803/bm3803.h @@ -441,7 +441,7 @@ static inline unsigned int bm3803_r32_no_cache(uintptr_t addr) * Name: up_clkinit * * Description: - * Initialiaze clock/PLL settings per the definitions in the board.h file. + * Initialize clock/PLL settings per the definitions in the board.h file. * ****************************************************************************/ diff --git a/arch/sparc/src/bm3823/bm3823-irq.c b/arch/sparc/src/bm3823/bm3823-irq.c index af373b8b20..c064724c56 100644 --- a/arch/sparc/src/bm3823/bm3823-irq.c +++ b/arch/sparc/src/bm3823/bm3823-irq.c @@ -94,7 +94,7 @@ void up_irqinitialize(void) /* And finally, enable interrupts */ - /* Interrupts are enabled by setting the te bit in the psr status + /* Interrupts are enabled by setting the the bit in the psr status * register */ diff --git a/arch/sparc/src/bm3823/bm3823-serial.c b/arch/sparc/src/bm3823/bm3823-serial.c index a7942c4232..a56901bee6 100644 --- a/arch/sparc/src/bm3823/bm3823-serial.c +++ b/arch/sparc/src/bm3823/bm3823-serial.c @@ -818,7 +818,7 @@ static bool up_txempty(struct uart_dev_s *dev) * * Description: * Performs the low level UART initialization early in debug so that the - * serial console will be available during bootup. This must be called + * serial console will be available during boot up. This must be called * before sparc_serialinit. NOTE: This function depends on GPIO pin * configuration performed in sparc_consoleinit() and main clock * iniialization performed in up_clkinitialize(). diff --git a/arch/sparc/src/bm3823/bm3823.h b/arch/sparc/src/bm3823/bm3823.h index 832915e29a..e5c3741c83 100644 --- a/arch/sparc/src/bm3823/bm3823.h +++ b/arch/sparc/src/bm3823/bm3823.h @@ -519,7 +519,7 @@ static inline unsigned int bm3823_r32_no_cache(uintptr_t addr) * Name: up_clkinit * * Description: - * Initialiaze clock/PLL settings per the definitions in the board.h file. + * Initialize clock/PLL settings per the definitions in the board.h file. * ****************************************************************************/ diff --git a/arch/sparc/src/s698pm/s698pm-irq.c b/arch/sparc/src/s698pm/s698pm-irq.c index 61173e5631..c58ef08d74 100644 --- a/arch/sparc/src/s698pm/s698pm-irq.c +++ b/arch/sparc/src/s698pm/s698pm-irq.c @@ -230,10 +230,10 @@ int s698pm_setup_irq(int cpu, int irq, int priority) } else if (irq > S698PM_IRQ_LAST && irq < NR_IRQS) { - /* Second level interrupt share a IRQ and connnect to a interrupt 14 + /* Second level interrupt share a IRQ and connect to a interrupt 14 * of first level interrupt(that is IRQ 0x1E), We extend Second level * interrupt to IRQ 0x100~0x10F. because first level interrupt in the - * interrupt reister is bit 0~15 and second level interrupt is bit 16 + * interrupt register is bit 0~15 and second level interrupt is bit 16 * ~31, so cpuint of second level interrupt is irq - 256 + * S698PM_EXTENDED_START */ diff --git a/arch/sparc/src/s698pm/s698pm-serial.c b/arch/sparc/src/s698pm/s698pm-serial.c index 0e1294bdd2..6c7840b04e 100644 --- a/arch/sparc/src/s698pm/s698pm-serial.c +++ b/arch/sparc/src/s698pm/s698pm-serial.c @@ -883,7 +883,7 @@ static bool up_txempty(struct uart_dev_s *dev) * * Description: * Performs the low level UART initialization early in debug so that the - * serial console will be available during bootup. This must be called + * serial console will be available during boot up. This must be called * before sparc_serialinit. NOTE: This function depends on GPIO pin * configuration performed in sparc_consoleinit() and main clock * iniialization performed in up_clkinitialize(). diff --git a/arch/sparc/src/s698pm/s698pm-timerisr.c b/arch/sparc/src/s698pm/s698pm-timerisr.c index a3de76ed6e..e6203ff3b8 100644 --- a/arch/sparc/src/s698pm/s698pm-timerisr.c +++ b/arch/sparc/src/s698pm/s698pm-timerisr.c @@ -71,7 +71,7 @@ #define TIMCTR_LOAD_COUNTER (1 << 2) -/* Bit 3: Set 1, will triger underflow interrupt each underflow */ +/* Bit 3: Set 1, will trigger underflow interrupt each underflow */ #define TIMCTR_ENABLE_INT (1 << 3) diff --git a/arch/sparc/src/s698pm/s698pm.h b/arch/sparc/src/s698pm/s698pm.h index 238413dbfb..5727696bb6 100644 --- a/arch/sparc/src/s698pm/s698pm.h +++ b/arch/sparc/src/s698pm/s698pm.h @@ -290,7 +290,7 @@ static inline unsigned int s698pm_r32_no_cache(uintptr_t addr) * Name: up_clkinit * * Description: - * Initialiaze clock/PLL settings per the definitions in the board.h file. + * Initialize clock/PLL settings per the definitions in the board.h file. * ****************************************************************************/ diff --git a/arch/sparc/src/s698pm/s698pm_exceptions.S b/arch/sparc/src/s698pm/s698pm_exceptions.S index ec4d0f7d9d..6ab764856d 100644 --- a/arch/sparc/src/s698pm/s698pm_exceptions.S +++ b/arch/sparc/src/s698pm/s698pm_exceptions.S @@ -67,7 +67,7 @@ * l3 = trap type * * NOTE: By an executive defined convention, trap type is between 0 and 255 if - * it is an asynchonous trap and 256 and 511 if it is synchronous. + * it is an asynchronous trap and 256 and 511 if it is synchronous. */ _ISR_Handler: diff --git a/arch/sparc/src/s698pm/s698pm_head.S b/arch/sparc/src/s698pm/s698pm_head.S index 2dbeedc208..519c2412a6 100644 --- a/arch/sparc/src/s698pm/s698pm_head.S +++ b/arch/sparc/src/s698pm/s698pm_head.S @@ -31,7 +31,7 @@ #define RTRAP(_vector, _handler) mov %g0, %l0 ; sethi %hi(_handler), %l4 ; jmp %l4+%lo(_handler); mov _vector, %l3 #define TRAP(_vector, _handler) mov %psr, %l0; sethi %hi(_handler), %l4 ; jmp %l4+%lo(_handler); mov _vector, %l3 -/* Unexcpected trap will halt the processor by forcing it to error state */ +/* Unexpected trap will halt the processor by forcing it to error state */ #define BAD_TRAP ta 0; nop; nop; nop; #define SOFT_TRAP BAD_TRAP /* Software trap. Treat as BAD_TRAP */ diff --git a/arch/sparc/src/sparc_v8/sparc_v8_romgetc.c b/arch/sparc/src/sparc_v8/sparc_v8_romgetc.c index c59f01a640..e10c5c72f2 100644 --- a/arch/sparc/src/sparc_v8/sparc_v8_romgetc.c +++ b/arch/sparc/src/sparc_v8/sparc_v8_romgetc.c @@ -52,7 +52,7 @@ * * Description: * In Harvard architectures, data accesses and instruction accesses occur - * on different busses, perhaps concurrently. All data accesses are + * on different buses, perhaps concurrently. All data accesses are * performed on the data bus unless special machine instructions are * used to read data from the instruction address space. Also, in the * typical MCU, the available SRAM data memory is much smaller that the diff --git a/arch/sparc/src/sparc_v8/sparc_v8_sigdeliver.c b/arch/sparc/src/sparc_v8/sparc_v8_sigdeliver.c index 71da93a450..3091182948 100644 --- a/arch/sparc/src/sparc_v8/sparc_v8_sigdeliver.c +++ b/arch/sparc/src/sparc_v8/sparc_v8_sigdeliver.c @@ -189,7 +189,7 @@ retry: /* Then restore the correct state for this thread of execution. This is an * unusual case that must be handled by up_fullcontextresore. This case is - * unusal in two ways: + * unusual in two ways: * * 1. It is not a context switch between threads. Rather, * sparc_fullcontextrestore must behave more it more like a longjmp diff --git a/arch/tricore/src/common/Ifx_Cfg_Trap.h b/arch/tricore/src/common/Ifx_Cfg_Trap.h index f8f74f9b3f..8de6fa7d81 100644 --- a/arch/tricore/src/common/Ifx_Cfg_Trap.h +++ b/arch/tricore/src/common/Ifx_Cfg_Trap.h @@ -37,7 +37,7 @@ * Pre-processor Definitions ****************************************************************************/ -/* Trap Hook defination */ +/* Trap Hook definition */ /* Trap Call */ diff --git a/arch/tricore/src/tc3xx/tc3xx_libc.c b/arch/tricore/src/tc3xx/tc3xx_libc.c index af9b976f2b..4e55d90c5e 100644 --- a/arch/tricore/src/tc3xx/tc3xx_libc.c +++ b/arch/tricore/src/tc3xx/tc3xx_libc.c @@ -72,7 +72,7 @@ void _doexit(void) { } -/* BUG, Workaroud for tasking compiler: +/* BUG, Workaround for tasking compiler: * * ltc E106: unresolved external: regulator_gpio_init - * (drivers_initialize.o) diff --git a/arch/tricore/src/tc3xx/tc3xx_serial.c b/arch/tricore/src/tc3xx/tc3xx_serial.c index 0e40fdc622..e1eb8c0e81 100644 --- a/arch/tricore/src/tc3xx/tc3xx_serial.c +++ b/arch/tricore/src/tc3xx/tc3xx_serial.c @@ -676,7 +676,7 @@ void tricore_lowputc(char ch) * * Description: * Performs the low level UART initialization early in debug so that the - * serial console will be available during bootup. This must be called + * serial console will be available during boot up. This must be called * before tricore_serialinit. NOTE: This function depends on GPIO pin * configuration performed in up_consoleinit() and main clock * initialization performed in up_clkinitialize(). diff --git a/arch/x86_64/include/acpi.h b/arch/x86_64/include/acpi.h index 93b6522d07..ab2355f2b9 100644 --- a/arch/x86_64/include/acpi.h +++ b/arch/x86_64/include/acpi.h @@ -176,7 +176,7 @@ begin_packed_struct struct acpi_rsdt_s uint32_t table_ptrs; } end_packed_struct; -/* Extended System Descriptior Table */ +/* Extended System Descriptor Table */ begin_packed_struct struct acpi_xsdt_s { @@ -269,7 +269,7 @@ int acpi_init(uintptr_t rsdp); * Name: acpi_madt_get * * Description: - * Find the n'th occurence of a MADT entry with a given type. + * Find the n'th occurrence of a MADT entry with a given type. * ****************************************************************************/ diff --git a/arch/x86_64/include/intel64/arch.h b/arch/x86_64/include/intel64/arch.h index f3f8890e90..dd0051b04d 100644 --- a/arch/x86_64/include/intel64/arch.h +++ b/arch/x86_64/include/intel64/arch.h @@ -515,7 +515,7 @@ begin_packed_struct struct ist_s begin_packed_struct struct tss_s { - struct ist_s ist; /* IST */ + struct ist_s ist; /* Interrupt Stack Table */ void *cpu; /* CPU private data */ } end_packed_struct; diff --git a/arch/x86_64/src/common/x86_64_acpi.c b/arch/x86_64/src/common/x86_64_acpi.c index 81b1374398..0685ea5c93 100644 --- a/arch/x86_64/src/common/x86_64_acpi.c +++ b/arch/x86_64/src/common/x86_64_acpi.c @@ -248,7 +248,7 @@ static int acpi_rsdp_parse(struct acpi_rsdp_s *rsdp) g_acpi.xsdt = xsdt; - /* Map all talbes */ + /* Map all tables */ acpi_map_xsdt(); } @@ -302,12 +302,12 @@ static bool acpi_rsdp_find_bios(struct acpi_s *acpi) static bool acpi_rsdp_find(struct acpi_s *acpi) { - /* For now ony ACPI from BIOS region us supported */ + /* For now only ACPI from BIOS region is supported */ #ifdef CONFIG_ARCH_X86_64_ACPI_BIOS return acpi_rsdp_find_bios(acpi); #else -# error For now ony ACPI from BIOS region is supported +# error For now only ACPI from BIOS region is supported #endif } @@ -484,7 +484,7 @@ int acpi_init(uintptr_t rsdp) * Name: acpi_madt_get * * Description: - * Find the n'th occurence of a MADT entry with a given type. + * Find the n'th occurrence of a MADT entry with a given type. * ****************************************************************************/ @@ -562,7 +562,7 @@ void acpi_dump(void) int i = 0; int ret = 0; - /* Dump entires */ + /* Dump entries */ if (g_acpi.xsdt != 0) { diff --git a/arch/x86_64/src/common/x86_64_addrenv.c b/arch/x86_64/src/common/x86_64_addrenv.c index 4ab796ee5d..1de1ff927d 100644 --- a/arch/x86_64/src/common/x86_64_addrenv.c +++ b/arch/x86_64/src/common/x86_64_addrenv.c @@ -92,7 +92,7 @@ (CONFIG_ARCH_DATA_VBASE & 0xffffffffffe00000)) || \ ((CONFIG_ARCH_TEXT_VBASE & 0xffffffffffe00000) != \ (CONFIG_ARCH_HEAP_VBASE & 0xffffffffffe00000))) -# error VBASE address must use the same PML4, PDT adn PD +# error VBASE address must use the same PML4, PDT and PD #endif /**************************************************************************** diff --git a/arch/x86_64/src/common/x86_64_hwdebug.c b/arch/x86_64/src/common/x86_64_hwdebug.c index f849b689ed..d86440176b 100644 --- a/arch/x86_64/src/common/x86_64_hwdebug.c +++ b/arch/x86_64/src/common/x86_64_hwdebug.c @@ -293,7 +293,7 @@ static void x86_64_set_dr(uint8_t i, uint8_t g, uint8_t rw, uint8_t len, default: { - _err("unsuported DR %d\n", i); + _err("unsupported DR %d\n", i); PANIC(); } } @@ -409,7 +409,7 @@ int up_debugpoint_add(int type, void *addr, size_t size, default: { - _err("unsuported debugpoint type %d\n", type); + _err("unsupported debugpoint type %d\n", type); PANIC(); } } @@ -510,7 +510,7 @@ int up_debugpoint_remove(int type, void *addr, size_t size) * Name: x86_64_hwdebug_init * * Description: - * One-time initializtion for hardware debug interface. + * One-time initialization for hardware debug interface. * ****************************************************************************/ diff --git a/arch/x86_64/src/common/x86_64_hwdebug.h b/arch/x86_64/src/common/x86_64_hwdebug.h index e128f08048..a55fe2e779 100644 --- a/arch/x86_64/src/common/x86_64_hwdebug.h +++ b/arch/x86_64/src/common/x86_64_hwdebug.h @@ -39,7 +39,7 @@ * Name: x86_64_hwdebug_init * * Description: - * One-time initializtion for hardware debug interface. + * One-time initialization for hardware debug interface. * ****************************************************************************/ diff --git a/arch/x86_64/src/intel64/Kconfig b/arch/x86_64/src/intel64/Kconfig index b89dcb6c1a..7ea9fde9fe 100644 --- a/arch/x86_64/src/intel64/Kconfig +++ b/arch/x86_64/src/intel64/Kconfig @@ -145,7 +145,7 @@ config INTEL64_HPET_CHANNELS default 2 range 1 3 ---help--- - Configure the number of supported HPET channles (called HPET timers + Configure the number of supported HPET channels (called HPET timers in HPET spec). We use HPET legacy replacement for interrupts which means that Timer 0 and Timer 1 interrupts are hardcoded, but Timer 2 needs additional attention to configure interrupt routing. @@ -155,7 +155,7 @@ config INTEL64_HPET_MIN_DELAY int "HPET minimum supported delay in micro-seconds" default 1000 ---help--- - HPET use free runnin up-counter and a comparators which generate events + HPET use free running up-counter and a comparators which generate events only on a equal event. This can results in event miss if we set too small delay. In that case we must set a minimum value for delay that always work. For the QEMU target this value should be as high as 1000, but for real diff --git a/arch/x86_64/src/intel64/intel64_check_capability.c b/arch/x86_64/src/intel64/intel64_check_capability.c index b8dd8444e5..ca64229756 100644 --- a/arch/x86_64/src/intel64/intel64_check_capability.c +++ b/arch/x86_64/src/intel64/intel64_check_capability.c @@ -68,7 +68,7 @@ void x86_64_check_and_enable_capability(void) require |= X86_64_CPUID_01_SSE3; #endif - /* Check Suplement SSE3 instructions availability */ + /* Check Supplement SSE3 instructions availability */ #ifdef CONFIG_ARCH_X86_64_SSEE3 require |= X86_64_CPUID_01_SSEE3; diff --git a/arch/x86_64/src/intel64/intel64_cpu.c b/arch/x86_64/src/intel64/intel64_cpu.c index c665422b50..d1650da176 100644 --- a/arch/x86_64/src/intel64/intel64_cpu.c +++ b/arch/x86_64/src/intel64/intel64_cpu.c @@ -124,7 +124,7 @@ void x86_64_cpu_tss_init(int cpu) tss = x86_64_cpu_tss_get(cpu); - /* Setup IST pointer */ + /* Setup Interrupt Stack Table pointer */ ist64 = &tss->ist; @@ -133,7 +133,7 @@ void x86_64_cpu_tss_init(int cpu) memset(&tss_l, 0, sizeof(tss_l)); memset(&tss_h, 0, sizeof(tss_h)); - /* Segment limit = IST size - 1 */ + /* Segment limit = Interrupt Stack Table size - 1 */ tss_l.limit_low = ((X86_IST_SIZE - 1) & 0xffff); @@ -146,7 +146,7 @@ void x86_64_cpu_tss_init(int cpu) tss_l.base_high = (((uintptr_t)ist64 & 0xff000000) >> 24); tss_l.P = 1; - /* Set type as IST */ + /* Set type as Interrupt Stack Table */ tss_l.AC = 1; tss_l.EX = 1; @@ -260,7 +260,7 @@ void x86_64_cpu_init(void) else { /* We want to fail early when NCPUS doesn't match the number - * of availalbe CPUs + * of available CPUs */ /* Panic if not found */ diff --git a/arch/x86_64/src/intel64/intel64_fbterm.c b/arch/x86_64/src/intel64/intel64_fbterm.c index a299c9f545..5a07578f68 100644 --- a/arch/x86_64/src/intel64/intel64_fbterm.c +++ b/arch/x86_64/src/intel64/intel64_fbterm.c @@ -96,7 +96,7 @@ static struct fb_term_s g_fb_term; * Name: fb_draw_pixel * * Description: - * Draw a pixel on the framebuffer. Note that the color paramter must + * Draw a pixel on the framebuffer. Note that the color parameter must * be in the format specified by the bpp of the framebuffer. * ****************************************************************************/ diff --git a/arch/x86_64/src/intel64/intel64_fpucmp.c b/arch/x86_64/src/intel64/intel64_fpucmp.c index 8d8335f972..6ff5a7c583 100644 --- a/arch/x86_64/src/intel64/intel64_fpucmp.c +++ b/arch/x86_64/src/intel64/intel64_fpucmp.c @@ -64,7 +64,7 @@ bool up_fpucmp(const void *saveregs1, const void *saveregs2) /* IMPORTANT: * - * With aggresive optimization enabled (-O2/-O3), ostest FPU test will + * With aggressive optimization enabled (-O2/-O3), ostest FPU test will * fail. This is because the compiler will generate additional vector * instructions between subsequent up_fpucmp() calls (loop vectorization * somewhere in usleep() call), which will consequently overwrite diff --git a/arch/x86_64/src/intel64/intel64_head.S b/arch/x86_64/src/intel64/intel64_head.S index 5dc73c3398..154c849344 100644 --- a/arch/x86_64/src/intel64/intel64_head.S +++ b/arch/x86_64/src/intel64/intel64_head.S @@ -270,7 +270,7 @@ start32: movl %eax, g_mb_magic #endif - /* Jump to 64 bit initialiation if this is AP core */ + /* Jump to 64 bit initialization if this is AP core */ mov bsp_done, %eax cmp $0, %eax jne start64_init @@ -373,7 +373,7 @@ start64_init: .code64 start64: - /* Set Segement Registers for proper iret, etc. operation */ + /* Set Segment Registers for proper iret, etc. operation */ mov $(X86_GDT_DATA_SEL), %ax mov %ax, %ss mov %ax, %ds @@ -611,7 +611,7 @@ no_kstack_switch: #else # ifdef CONFIG_ARCH_CHIP_INTEL64_QEMU /* BUGFIX for QEMU: make sure that xsave header is zeroed! - * QEMU desn't clear these fields during xsave, so if the memory region + * QEMU doesn't clear these fields during xsave, so if the memory region * for xsave state was not cleared before use, there may be junk data there, * that cause xrstor to crash later. */ diff --git a/arch/x86_64/src/intel64/intel64_hpet.c b/arch/x86_64/src/intel64/intel64_hpet.c index bc7b5ba769..6ad584910b 100644 --- a/arch/x86_64/src/intel64/intel64_hpet.c +++ b/arch/x86_64/src/intel64/intel64_hpet.c @@ -557,7 +557,7 @@ struct intel64_tim_dev_s *intel64_hpet_init(uint64_t base) /* Configure legacy mode. * * There is no way to disable PIT interrupts (?) other than enable - * legacy mode for HPET. Otherwise unwanted PIT interupts will + * legacy mode for HPET. Otherwise unwanted PIT interrupts will * interfere with HPET interrupts, making them useless. */ diff --git a/arch/x86_64/src/intel64/intel64_initialstate.c b/arch/x86_64/src/intel64/intel64_initialstate.c index 7ebb6788a8..60460d3948 100644 --- a/arch/x86_64/src/intel64/intel64_initialstate.c +++ b/arch/x86_64/src/intel64/intel64_initialstate.c @@ -69,7 +69,7 @@ * function is called to initialize the processor specific portions of the * new TCB. * - * This function must setup the intial architecture registers and/or stack + * This function must setup the initial architecture registers and/or stack * so that execution will begin at tcb->start on the next context switch. * ****************************************************************************/ diff --git a/arch/x86_64/src/intel64/intel64_irq.c b/arch/x86_64/src/intel64/intel64_irq.c index 733f9a3e9f..c1dced6723 100644 --- a/arch/x86_64/src/intel64/intel64_irq.c +++ b/arch/x86_64/src/intel64/intel64_irq.c @@ -245,7 +245,7 @@ static void up_apic_init(void) write_msr(MSR_X2APIC_LINT0, MSR_X2APIC_MASKED); write_msr(MSR_X2APIC_LINT1, MSR_X2APIC_MASKED); - /* Disable performance counter overflow interrupts on machines tha + /* Disable performance counter overflow interrupts on machines which * provide that interrupt entry. */ @@ -349,7 +349,7 @@ static void up_idtentry(unsigned int index, uint64_t base, uint16_t sel, entry->zero = 0; /* We don't use software interrupts from user-space (INT) so DPL level - * can be set to privilage level 0. DPL bits have no effect on hardware + * can be set to privilege level 0. DPL bits have no effect on hardware * interrupts. */ diff --git a/arch/x86_64/src/intel64/intel64_oneshot.c b/arch/x86_64/src/intel64/intel64_oneshot.c index 4d2d7d47bd..f4cc0afcf4 100644 --- a/arch/x86_64/src/intel64/intel64_oneshot.c +++ b/arch/x86_64/src/intel64/intel64_oneshot.c @@ -219,7 +219,7 @@ int intel64_oneshot_initialize(struct intel64_oneshot_s *oneshot, int chan, oneshot->arg = NULL; #ifdef CONFIG_INTEL64_HPET_FSB - /* IMPORTENT: HPET in edge triggered mode is broken on some hardware + /* IMPORTANT: HPET in edge triggered mode is broken on some hardware * and generate spurious interrupts when we enable timer. On the other * hand FSB works only with edge triggered mode. * @@ -318,7 +318,7 @@ int intel64_oneshot_start(struct intel64_oneshot_s *oneshot, usec = (uint64_t)ts->tv_sec * USEC_PER_SEC + (uint64_t)(ts->tv_nsec / NSEC_PER_USEC); - /* HPET use free runnin up-counter and a comparators which generate events + /* HPET use free running up-counter and a comparators which generate events * only on a equal event. This can results in event miss if we set too * small delay. In that case we just set a minimum value for delay that * seem to work. @@ -346,7 +346,7 @@ int intel64_oneshot_start(struct intel64_oneshot_s *oneshot, oneshot, false); #endif - /* Set comparator ahed of the current counter */ + /* Set comparator ahead of the current counter */ compare += INTEL64_TIM_GETCOUNTER(oneshot->tch); INTEL64_TIM_SETCOMPARE(oneshot->tch, oneshot->chan, compare); diff --git a/arch/x86_64/src/intel64/intel64_regdump.c b/arch/x86_64/src/intel64/intel64_regdump.c index 667f253e93..b5cc2d2e8e 100644 --- a/arch/x86_64/src/intel64/intel64_regdump.c +++ b/arch/x86_64/src/intel64/intel64_regdump.c @@ -113,7 +113,7 @@ void up_dump_register(void *dumpregs) ::"m"(cr2):"memory", "rax"); _alert("----------------CUT HERE-----------------\n"); - _alert("Gerneral Informations:\n"); + _alert("General Information:\n"); _alert("CPL: %" PRId64 ", RPL: %" PRId64 "\n", regs[REG_CS] & 0x3, regs[REG_DS] & 0x3); _alert("RIP: %016" PRIx64 ", RSP: %016" PRIx64 "\n", diff --git a/arch/x86_64/src/intel64/intel64_serial.c b/arch/x86_64/src/intel64/intel64_serial.c index 5205308d5d..fe963abf37 100644 --- a/arch/x86_64/src/intel64/intel64_serial.c +++ b/arch/x86_64/src/intel64/intel64_serial.c @@ -35,7 +35,7 @@ #include "chip.h" #include "x86_64_internal.h" -/* This is a "stub" file to suppport up_putc if no real serial driver is +/* This is a "stub" file to support up_putc if no real serial driver is * configured. Normally, drivers/serial/uart_16550.c provides the serial * driver for this platform. */ diff --git a/arch/x86_64/src/intel64/intel64_smpcall.c b/arch/x86_64/src/intel64/intel64_smpcall.c index b45dad2856..8db77c53cd 100644 --- a/arch/x86_64/src/intel64/intel64_smpcall.c +++ b/arch/x86_64/src/intel64/intel64_smpcall.c @@ -73,7 +73,7 @@ int x86_64_smp_call_handler(int irq, void *c, void *arg) * * 1. It saves the current task state at the head of the current assigned * task list. - * 2. It porcess g_delivertasks + * 2. It processes g_delivertasks * 3. Returns from interrupt, restoring the state of the new task at the * head of the ready to run list. * diff --git a/arch/x86_64/src/intel64/intel64_start.c b/arch/x86_64/src/intel64/intel64_start.c index 1787925001..7aad7a8a91 100644 --- a/arch/x86_64/src/intel64/intel64_start.c +++ b/arch/x86_64/src/intel64/intel64_start.c @@ -111,7 +111,7 @@ static void x86_64_mb2_config(void) { /* We have to postpone frame buffer initialization because * at this boot stage we can't map >4GB memory yet and it's - * possible that frame bufer address is above 4GB. + * possible that frame buffer address is above 4GB. */ g_mb_fb_tag = (struct multiboot_tag_framebuffer *)tag; diff --git a/arch/x86_64/src/intel64/intel64_tsc_tickless.c b/arch/x86_64/src/intel64/intel64_tsc_tickless.c index 2e41744330..c85e7c465a 100644 --- a/arch/x86_64/src/intel64/intel64_tsc_tickless.c +++ b/arch/x86_64/src/intel64/intel64_tsc_tickless.c @@ -193,7 +193,7 @@ static inline void up_tmr_sync_down(void) * when clockid is CLOCK_MONOTONIC. * * This function provides the basis for reporting the current time and - * also is used to eliminate error build-up from small erros in interval + * also is used to eliminate error build-up from small errors in interval * time calculations. * * Provided by platform-specific code and called from the RTOS base code. diff --git a/arch/x86_64/src/intel64/intel64_vectors.S b/arch/x86_64/src/intel64/intel64_vectors.S index c74264990f..b3aaefe285 100644 --- a/arch/x86_64/src/intel64/intel64_vectors.S +++ b/arch/x86_64/src/intel64/intel64_vectors.S @@ -60,7 +60,7 @@ vector_isr\intno: cli /* Disable interrupts firstly. */ - /* CPU has sawitched to the ISR stack using IST */ + /* CPU has sawitched to the ISR stack using Interrupt Stack Table */ pushq $0 /* Push a dummy error code. */ @@ -80,7 +80,7 @@ vector_isr\intno: vector_isr\intno: cli /* Disable interrupts firstly. */ - /* CPU has sawitched to the ISR stack using IST */ + /* CPU has sawitched to the ISR stack using Interrupt Stack Table */ /* Save rdi, rsi */ pushq %rdi @@ -98,7 +98,7 @@ vector_isr\intno: vector_irq\irqno: cli /* Disable interrupts firstly. */ - /* CPU has switched to the IRQ stack using IST */ + /* CPU has switched to the IRQ stack using Interrupt Stack Table */ pushq $0 /* Push a dummy error code. */ @@ -813,7 +813,7 @@ irq_common: movq $0x0, (8*REG_AUX)(%rdi) - /* A context swith will be performed. RAX holds the address of the new + /* A context switch will be performed. RAX holds the address of the new * register save structure. * * Jump to x86_64_fullcontextrestore(). We perform a call here, but that function diff --git a/arch/xtensa/Kconfig b/arch/xtensa/Kconfig index a2caaa9e3d..d7cb000b15 100644 --- a/arch/xtensa/Kconfig +++ b/arch/xtensa/Kconfig @@ -286,7 +286,7 @@ config XTENSA_TARGET_ISS default n ---help--- This setting determines whether the target is Cadence Instruction - Set Simulator, which might have some sepecial characteristics such + Set Simulator, which might have some special characteristics such as how to open a file nonblock. if XTENSA_SEMIHOSTING_HOSTFS @@ -295,7 +295,7 @@ config XTENSA_SEMIHOSTING_HOSTFS_CACHE_COHERENCE bool "Cache coherence in semihosting hostfs" depends on ARCH_DCACHE ---help--- - Flush & Invalidte cache before & after sim call. + Flush & Invalidate cache before & after sim call. endif diff --git a/arch/xtensa/include/arch.h b/arch/xtensa/include/arch.h index 7c076590d5..cb68d08070 100644 --- a/arch/xtensa/include/arch.h +++ b/arch/xtensa/include/arch.h @@ -90,7 +90,7 @@ void xtensa_imm_initialize(void); * size - Size (in bytes) of the memory region to be allocated. * * Return Value: - * Adress of the allocated memory space. NULL, if allocation fails. + * Address of the allocated memory space. NULL, if allocation fails. * ****************************************************************************/ @@ -108,7 +108,7 @@ void *xtensa_imm_malloc(size_t size); * elem_size - Size (in bytes) of the type to be allocated. * * Return Value: - * Adress of the allocated memory space. NULL, if allocation fails. + * Address of the allocated memory space. NULL, if allocation fails. * ****************************************************************************/ @@ -121,11 +121,11 @@ void *xtensa_imm_calloc(size_t n, size_t elem_size); * Reallocate memory from the internal heap. * * Input Parameters: - * ptr - Adress to be reallocate. + * ptr - Address to be reallocate. * size - Size (in bytes) to be reallocate. * * Return Value: - * Adress of the possibly moved memory space. NULL, if allocation fails. + * Address of the possibly moved memory space. NULL, if allocation fails. * ****************************************************************************/ @@ -141,7 +141,7 @@ void *xtensa_imm_realloc(void *ptr, size_t size); * size - Size (in bytes) of the memory region to be allocated. * * Return Value: - * Adress of the allocated memory space. NULL, if allocation fails. + * Address of the allocated memory space. NULL, if allocation fails. * ****************************************************************************/ @@ -154,7 +154,7 @@ void *xtensa_imm_zalloc(size_t size); * Free memory from the internal heap. * * Input Parameters: - * mem - Adress to be freed. + * mem - Address to be freed. * * Returned Value: * None. @@ -179,7 +179,7 @@ void xtensa_imm_free(void *mem); * size - Size (in bytes) of the memory region to be allocated. * * Return Value: - * Adress of the allocated adress. NULL, if allocation fails. + * Address of the allocated address. NULL, if allocation fails. * ****************************************************************************/ diff --git a/arch/xtensa/include/simcall.h b/arch/xtensa/include/simcall.h index 6f3fd8a8a7..fb979391a7 100644 --- a/arch/xtensa/include/simcall.h +++ b/arch/xtensa/include/simcall.h @@ -40,7 +40,7 @@ /* fcntl O_xxx constants for simcall. * * Someone with the official spec should fix this and qemu. - * I made this CONFIG_HOST_xxx dependant because: + * I made this CONFIG_HOST_xxx dependent because: * - the qemu implementation just pass them to the host OS * - I don't have an official documentation. * - I build NuttX and run qemu on the same host. diff --git a/arch/xtensa/src/common/espressif/esp_adc.c b/arch/xtensa/src/common/espressif/esp_adc.c index fcfdbc06c5..756f652f80 100644 --- a/arch/xtensa/src/common/espressif/esp_adc.c +++ b/arch/xtensa/src/common/espressif/esp_adc.c @@ -139,7 +139,7 @@ struct esp_adc_dev_s struct esp_adc_dev_common_s *common; /* Common ADC driver data */ enum esp_adc_mode_e mode; /* ADC mode */ - adc_atten_t atten_mode; /* Attenuation paramenter */ + adc_atten_t atten_mode; /* Attenuation parameter */ uint32_t atten_k; /* Attenuation factor */ uint8_t channels; /* Total channels for this ADC */ uint8_t unit; /* ADC unit number */ diff --git a/arch/xtensa/src/common/espressif/esp_i2c_slave.c b/arch/xtensa/src/common/espressif/esp_i2c_slave.c index 34d39bf9d1..7c44369742 100644 --- a/arch/xtensa/src/common/espressif/esp_i2c_slave.c +++ b/arch/xtensa/src/common/espressif/esp_i2c_slave.c @@ -692,7 +692,7 @@ static int esp_i2c_slave_irq(int cpuint, void *context, void *arg) * priv - Pointer to the internal driver state structure. * * Returned Values: - * Zero (OK) is returned on successfull transfer. -ETIMEDOUT is returned + * Zero (OK) is returned on successful transfer. -ETIMEDOUT is returned * in case a transfer didn't finish within the timeout interval. * ****************************************************************************/ @@ -868,7 +868,7 @@ static void esp_i2c_process(struct esp_i2c_priv_s *priv, * * Parameters: * port - Port number of the I2C interface to be initialized. - * addr - Adress of the slave device + * addr - Address of the slave device * * Returned Value: * Pointer to valid I2C device structure is returned on success. diff --git a/arch/xtensa/src/common/espressif/esp_i2c_slave.h b/arch/xtensa/src/common/espressif/esp_i2c_slave.h index a404d9cf2f..0c437b7dac 100644 --- a/arch/xtensa/src/common/espressif/esp_i2c_slave.h +++ b/arch/xtensa/src/common/espressif/esp_i2c_slave.h @@ -61,7 +61,7 @@ * * Input Parameters: * port - Port number (for hardware that has multiple I2C interfaces) - * addr - Adress of the slave device + * addr - Address of the slave device * * Returned Value: * Valid I2C device structure reference on success; a NULL on failure diff --git a/arch/xtensa/src/common/espressif/esp_i2s.c b/arch/xtensa/src/common/espressif/esp_i2s.c index 209b662d52..2470d518b9 100644 --- a/arch/xtensa/src/common/espressif/esp_i2s.c +++ b/arch/xtensa/src/common/espressif/esp_i2s.c @@ -1236,7 +1236,7 @@ static void IRAM_ATTR i2s_tx_schedule(struct esp_i2s_s *priv, /* Check if the DMA descriptor that generated an EOF interrupt is the * last descriptor of the current buffer container's DMA outlink. - * REVISIT: what to do if we miss syncronization and the descriptor + * REVISIT: what to do if we miss synchronization and the descriptor * that generated the interrupt is different from the expected (the * oldest of the list containing active transmissions)? */ @@ -2923,7 +2923,7 @@ static int i2s_receive(struct i2s_dev_s *dev, struct ap_buffer_s *apb, } i2sinfo("Prepared %d bytes to receive DMA buffers\n", apb->nmaxbytes); - i2s_dump_buffer("Recieved Audio pipeline buffer:", + i2s_dump_buffer("Received Audio pipeline buffer:", &apb->samp[apb->curbyte], apb->nbytes - apb->curbyte); @@ -3191,7 +3191,7 @@ struct i2s_dev_s *esp_i2sbus_initialize(int port) i2sinfo("port: %d\n", port); - /* Statically allocated I2S' device strucuture */ + /* Statically allocated I2S' device structure */ switch (port) { diff --git a/arch/xtensa/src/common/espressif/esp_nxdiag.c b/arch/xtensa/src/common/espressif/esp_nxdiag.c index 0d4e08e2c1..70e0d7b210 100644 --- a/arch/xtensa/src/common/espressif/esp_nxdiag.c +++ b/arch/xtensa/src/common/espressif/esp_nxdiag.c @@ -176,7 +176,7 @@ int esp_nxdiag_read_flash_status(uint32_t *status) * Name: esp_nxdiag_read_mac * * Description: - * Read MAC adress. + * Read MAC address. * * Input Parameters: * mac - Mac address to return. @@ -241,7 +241,7 @@ static ssize_t esp_nxdiag_read(struct file *filep, ret = esp_nxdiag_read_mac(mac); if (ret != OK) { - printf("Failed to fetch MAC adress\n\n"); + printf("Failed to fetch MAC address\n\n"); } else { diff --git a/arch/xtensa/src/common/espressif/esp_openeth.c b/arch/xtensa/src/common/espressif/esp_openeth.c index 06d096093d..0a310ef7f4 100644 --- a/arch/xtensa/src/common/espressif/esp_openeth.c +++ b/arch/xtensa/src/common/espressif/esp_openeth.c @@ -113,7 +113,7 @@ typedef struct { uint16_t cs : 1; /* !< Carrier sense lost (flag set by HW) */ uint16_t df : 1; /* !< Defer indication (flag set by HW) */ - uint16_t lc : 1; /* !< Late collision occured (flag set by HW) */ + uint16_t lc : 1; /* !< Late collision occurred (flag set by HW) */ uint16_t rl : 1; /* !< TX failed due to retransmission limit (flag set by HW) */ uint16_t rtry : 4; /* !< Number of retries before the frame was sent (set by HW) */ uint16_t ur : 1; /* !< Underrun status (flag set by HW) */ diff --git a/arch/xtensa/src/common/espressif/esp_rmt.c b/arch/xtensa/src/common/espressif/esp_rmt.c index 7ac58ba4ab..77ad248fed 100644 --- a/arch/xtensa/src/common/espressif/esp_rmt.c +++ b/arch/xtensa/src/common/espressif/esp_rmt.c @@ -1025,7 +1025,7 @@ static int rmt_internal_config(rmt_dev_t *dev, spin_unlock_irqrestore(&g_rmtdev_common.rmt_spinlock, flags); - rmtinfo("Rmt Rx Channel %u|Gpio %u|Sclk_Hz %"PRIu32"|Div %u|Thresold " + rmtinfo("Rmt Rx Channel %u|Gpio %u|Sclk_Hz %"PRIu32"|Div %u|Threshold " "%u|Filter %u", channel, gpio_num, rmt_source_clk_hz, clk_div, threshold, filter_cnt); } diff --git a/arch/xtensa/src/common/espressif/esp_spiflash.c b/arch/xtensa/src/common/espressif/esp_spiflash.c index 2e88da565b..24084dc107 100644 --- a/arch/xtensa/src/common/espressif/esp_spiflash.c +++ b/arch/xtensa/src/common/espressif/esp_spiflash.c @@ -274,7 +274,7 @@ static IRAM_ATTR void esp_spi_trans(uint32_t command, uint32_t rx_bytes, uint32_t dummy_bits) { - /* Initiliaze SPI user register */ + /* Initialize SPI user register */ spi_flash_ll_reset(dev); @@ -322,7 +322,7 @@ static IRAM_ATTR void esp_spi_trans(uint32_t command, spimem_flash_ll_suspend_cmd_setup(dev, 0); - /* Start transmision */ + /* Start transmission */ spi_flash_ll_user_start(dev); diff --git a/arch/xtensa/src/common/espressif/esp_spiflash_mtd.c b/arch/xtensa/src/common/espressif/esp_spiflash_mtd.c index 1451cb3d2a..9d5af8df18 100644 --- a/arch/xtensa/src/common/espressif/esp_spiflash_mtd.c +++ b/arch/xtensa/src/common/espressif/esp_spiflash_mtd.c @@ -295,7 +295,7 @@ static ssize_t esp_bread(struct mtd_dev_s *dev, off_t startblock, * buffer - data buffer pointer * * Returned Value: - * Writen bytes if success or a negative value if fail. + * Written bytes if success or a negative value if fail. * ****************************************************************************/ @@ -349,7 +349,7 @@ static ssize_t esp_write(struct mtd_dev_s *dev, off_t offset, * buffer - data buffer pointer * * Returned Value: - * Writen block number if success or a negative value if fail. + * Written block number if success or a negative value if fail. * ****************************************************************************/ diff --git a/arch/xtensa/src/common/espressif/esp_temperature_sensor.c b/arch/xtensa/src/common/espressif/esp_temperature_sensor.c index 6c72db2562..648fbf7c33 100644 --- a/arch/xtensa/src/common/espressif/esp_temperature_sensor.c +++ b/arch/xtensa/src/common/espressif/esp_temperature_sensor.c @@ -213,7 +213,7 @@ static temperature_sensor_attribute_t * * Input Parameters: * p1 - First value to compare with other value - * p2 - Second value to compare with outher value + * p2 - Second value to compare with other value * * Returned Value: * Returns -1 if the first value has smaller error rate; 1 otherwise @@ -260,7 +260,7 @@ static int temperature_sensor_attribute_table_sort(void) * * Description: * This function selects least error rated temperature sensor attribute - * for given mesurement range. + * for given measurement range. * * Input Parameters: * priv - Pointer to the internal driver state structure. diff --git a/arch/xtensa/src/common/espressif/esp_wireless.c b/arch/xtensa/src/common/espressif/esp_wireless.c index 1df1563cdd..188be3b7f9 100644 --- a/arch/xtensa/src/common/espressif/esp_wireless.c +++ b/arch/xtensa/src/common/espressif/esp_wireless.c @@ -603,7 +603,7 @@ static uint8_t phy_find_bin_type_according_country(const char *country) if (i == num) { phy_init_data_type = ESP_PHY_INIT_DATA_TYPE_DEFAULT; - wlerr("Use the default certification code beacuse %c%c doesn't " + wlerr("Use the default certification code because %c%c doesn't " "have a certificate\n", country[0], country[1]); } @@ -618,7 +618,7 @@ static uint8_t phy_find_bin_type_according_country(const char *country) * * Input Parameters: * output_data - Output data buffer pointer - * control_info - PHY init data control infomation + * control_info - PHY init data control information * input_data - Input data buffer pointer * init_data_type - PHY init data type * diff --git a/arch/xtensa/src/common/espressif/esp_wlan.c b/arch/xtensa/src/common/espressif/esp_wlan.c index 61d4d0b19e..f45194e30b 100644 --- a/arch/xtensa/src/common/espressif/esp_wlan.c +++ b/arch/xtensa/src/common/espressif/esp_wlan.c @@ -876,7 +876,7 @@ static void wlan_rxpoll(void *arg) } /* We are finished with the RX buffer. NOTE: If the buffer is - * re-used for transmission, the dev->d_buf field will have been + * reused for transmission, the dev->d_buf field will have been * nullified. */ @@ -1609,7 +1609,7 @@ static int esp_net_initialize(int devno, uint8_t *mac_addr, * * Description: * Wi-Fi station RX done callback function. If this is called, it means - * station receiveing packet. + * station receiving packet. * * Input Parameters: * buffer - Wi-Fi received packet buffer @@ -1659,7 +1659,7 @@ static void wlan_sta_tx_done(uint8_t *data, uint16_t *len, bool status) * * Description: * Wi-Fi softAP RX done callback function. If this is called, it means - * softAP receiveing packet. + * softAP receiving packet. * * Input Parameters: * buffer - Wi-Fi received packet buffer diff --git a/arch/xtensa/src/common/xtensa_assert.c b/arch/xtensa/src/common/xtensa_assert.c index c6fbbfd4e9..399b161174 100644 --- a/arch/xtensa/src/common/xtensa_assert.c +++ b/arch/xtensa/src/common/xtensa_assert.c @@ -132,7 +132,7 @@ void xtensa_panic(int xptcode, uint32_t *regs) * 17 InstTLBMultiHitCause * Multiple instruction TLB entries matched * 18 InstFetchPrivilegeCause - * An instruction fetch referenced a virtual address at a ring leve + * An instruction fetch referenced a virtual address at a ring level * less than CRING. * 19 Reserved for Cadence * 20 InstFetchProhibitedCause diff --git a/arch/xtensa/src/common/xtensa_backtrace.c b/arch/xtensa/src/common/xtensa_backtrace.c index e562d88663..0ab11d8c7e 100644 --- a/arch/xtensa/src/common/xtensa_backtrace.c +++ b/arch/xtensa/src/common/xtensa_backtrace.c @@ -43,7 +43,7 @@ * addressing instructions within a 1GB region. To convert the return address * to a valid PC, we need to add the base address of the instruction region. * The following macro is used to define the base address of the 1GB region, - * which may not start in 0x00000000. This macro can be overriden in + * which may not start in 0x00000000. This macro can be overridden in * `chip_memory.h` of the chip directory. */ diff --git a/arch/xtensa/src/esp32/esp32_aes.c b/arch/xtensa/src/esp32/esp32_aes.c index 6a2885f35c..7feb364dc2 100644 --- a/arch/xtensa/src/esp32/esp32_aes.c +++ b/arch/xtensa/src/esp32/esp32_aes.c @@ -482,7 +482,7 @@ int esp32_aes_xts_cypher(struct esp32_aes_xts_s *aes, bool encrypt, * Name: esp32_aes_setkey * * Description: - * Configurate AES key. + * Configure AES key. * * Input Parameters: * aes - AES object data pointer @@ -514,7 +514,7 @@ int esp32_aes_setkey(struct esp32_aes_s *aes, const void *keyptr, * Name: esp32_aes_xts_setkey * * Description: - * Configurate AES XTS key. + * Configure AES XTS key. * * Input Parameters: * aes - AES object data pointer diff --git a/arch/xtensa/src/esp32/esp32_aes.h b/arch/xtensa/src/esp32/esp32_aes.h index f30093c275..b742619b43 100644 --- a/arch/xtensa/src/esp32/esp32_aes.h +++ b/arch/xtensa/src/esp32/esp32_aes.h @@ -157,7 +157,7 @@ int esp32_aes_xts_cypher(struct esp32_aes_xts_s *aes, bool encrypt, * Name: esp32_aes_setkey * * Description: - * Configurate AES key. + * Configure AES key. * * Input Parameters: * aes - AES object data pointer @@ -176,7 +176,7 @@ int esp32_aes_setkey(struct esp32_aes_s *aes, const void *keyptr, * Name: esp32_aes_xts_setkey * * Description: - * Configurate AES XTS key. + * Configure AES XTS key. * * Input Parameters: * aes - AES object data pointer diff --git a/arch/xtensa/src/esp32/esp32_ble_adapter.c b/arch/xtensa/src/esp32/esp32_ble_adapter.c index af94226855..b965f5d272 100644 --- a/arch/xtensa/src/esp32/esp32_ble_adapter.c +++ b/arch/xtensa/src/esp32/esp32_ble_adapter.c @@ -1625,7 +1625,7 @@ static void *malloc_wrapper(size_t size) * Malloc buffer in DRAM * * Input Parameters: - * szie - buffer size + * size - buffer size * * Returned Value: * None @@ -2905,7 +2905,7 @@ int esp32_bt_controller_init(void) } /* Initialize list of interrupt flags to enable chained critical sections - * to return sucessfully. + * to return successfully. */ sq_init(&g_ble_int_flags_free); @@ -3179,7 +3179,7 @@ int esp32_bt_controller_enable(esp_bt_mode_t mode) sdk_config_set_bt_pll_track_enable(true); - /* inititalize bluetooth baseband */ + /* initialize bluetooth baseband */ btdm_check_and_init_bb(); diff --git a/arch/xtensa/src/esp32/esp32_cpustart.c b/arch/xtensa/src/esp32/esp32_cpustart.c index 114343b892..0c80b31ff9 100644 --- a/arch/xtensa/src/esp32/esp32_cpustart.c +++ b/arch/xtensa/src/esp32/esp32_cpustart.c @@ -229,7 +229,7 @@ int up_cpu_start(int cpu) sched_note_cpu_start(this_task(), cpu); #endif - /* Unstall the APP CPU */ + /* Un-stall the APP CPU */ regval = getreg32(RTC_CNTL_SW_CPU_STALL_REG); regval &= ~RTC_CNTL_SW_STALL_APPCPU_C1_M; diff --git a/arch/xtensa/src/esp32/esp32_emac.c b/arch/xtensa/src/esp32/esp32_emac.c index 4b56425392..33b163a519 100644 --- a/arch/xtensa/src/esp32/esp32_emac.c +++ b/arch/xtensa/src/esp32/esp32_emac.c @@ -809,7 +809,7 @@ static void emac_deinit_dma(struct esp32_emac_s *priv) * 0 is returned on success. Otherwise, a negated errno value is * returned indicating the nature of the failure: * - * -EBUSY is returned if no TX descrption is valid. + * -EBUSY is returned if no TX description is valid. * ****************************************************************************/ diff --git a/arch/xtensa/src/esp32/esp32_himem.c b/arch/xtensa/src/esp32/esp32_himem.c index 07590b87b0..7e0e3a1791 100644 --- a/arch/xtensa/src/esp32/esp32_himem.c +++ b/arch/xtensa/src/esp32/esp32_himem.c @@ -573,7 +573,7 @@ int esp_himem_unmap(esp_himem_rangehandle_t range, void *ptr, /* Note: doesn't actually unmap, just clears cache and marks blocks as * unmapped. * Future optimization: could actually lazy-unmap here: essentially, do - * nothing and only clear the cache when we re-use the block for a + * nothing and only clear the cache when we reuse the block for a * different physical address. */ diff --git a/arch/xtensa/src/esp32/esp32_himem_chardev.c b/arch/xtensa/src/esp32/esp32_himem_chardev.c index 276fd06664..540dfbf63e 100644 --- a/arch/xtensa/src/esp32/esp32_himem_chardev.c +++ b/arch/xtensa/src/esp32/esp32_himem_chardev.c @@ -408,7 +408,7 @@ int himem_chardev_unregister(char *name) } nxmutex_unlock(&lock); - merr("dev=%s is not registerd.\n", name); + merr("dev=%s is not registered.\n", name); return -1; } diff --git a/arch/xtensa/src/esp32/esp32_i2c.c b/arch/xtensa/src/esp32/esp32_i2c.c index dd0b1a640d..59040c07e7 100644 --- a/arch/xtensa/src/esp32/esp32_i2c.c +++ b/arch/xtensa/src/esp32/esp32_i2c.c @@ -750,7 +750,7 @@ static int esp32_i2c_sem_waitdone(struct esp32_i2c_priv_s *priv) * priv - Pointer to the internal driver state structure. * * Returned Values: - * Zero (OK) is returned on successfull transfer. -ETIMEDOUT is returned + * Zero (OK) is returned on successful transfer. -ETIMEDOUT is returned * in case a transfer didn't finish within the timeout interval. And ERROR * is returned in case of any I2C error during the transfer has happened. * diff --git a/arch/xtensa/src/esp32/esp32_i2s.c b/arch/xtensa/src/esp32/esp32_i2s.c index 0688d44f91..a52f57a689 100644 --- a/arch/xtensa/src/esp32/esp32_i2s.c +++ b/arch/xtensa/src/esp32/esp32_i2s.c @@ -1028,7 +1028,7 @@ static void i2s_tx_schedule(struct esp32_i2s_s *priv, /* Check if the DMA descriptor that generated an EOF interrupt is the * last descriptor of the current buffer container's DMA outlink. - * REVISIT: what to do if we miss syncronization and the descriptor + * REVISIT: what to do if we miss synchronization and the descriptor * that generated the interrupt is different from the expected (the * oldest of the list containing active transmissions)? */ @@ -1127,7 +1127,7 @@ static void i2s_rx_schedule(struct esp32_i2s_s *priv, /* Check if the DMA descriptor that generated an EOF interrupt is the * last descriptor of the current buffer container's DMA inlink. - * REVISIT: what to do if we miss syncronization and the descriptor + * REVISIT: what to do if we miss synchronization and the descriptor * that generated the interrupt is different from the expected (the * oldest of the list containing active transmissions)? */ @@ -1735,7 +1735,7 @@ static void i2s_configure(struct esp32_i2s_s *priv) } } - /* Congfigure RX chan bit, audio data bit and mono mode. + /* Configure RX chan bit, audio data bit and mono mode. * On ESP32, sample_bit should equals to data_bit. */ @@ -3047,7 +3047,7 @@ struct i2s_dev_s *esp32_i2sbus_initialize(int port) i2sinfo("port: %d\n", port); - /* Statically allocated I2S' device strucuture */ + /* Statically allocated I2S' device structure */ switch (port) { diff --git a/arch/xtensa/src/esp32/esp32_oneshot_lowerhalf.c b/arch/xtensa/src/esp32/esp32_oneshot_lowerhalf.c index 8a434b7396..b98f075832 100644 --- a/arch/xtensa/src/esp32/esp32_oneshot_lowerhalf.c +++ b/arch/xtensa/src/esp32/esp32_oneshot_lowerhalf.c @@ -163,9 +163,9 @@ static int esp32_max_lh_delay(struct oneshot_lowerhalf_s *lower, DEBUGASSERT(ts != NULL); /* The real maximum delay surpass the limit that timespec can - * reprent. Even using the better case: a resolution of + * represent. Even using the better case: a resolution of * 1 us. - * Therefore, here, fulfill the timespec with the + * Therefore, here, fill the timespec with the * maximum value it can represent. */ diff --git a/arch/xtensa/src/esp32/esp32_psram.c b/arch/xtensa/src/esp32/esp32_psram.c index e86636656d..bedf346d68 100644 --- a/arch/xtensa/src/esp32/esp32_psram.c +++ b/arch/xtensa/src/esp32/esp32_psram.c @@ -1511,7 +1511,7 @@ psram_enable(int mode, int vaddrmode) /* psram init */ { struct rtc_vddsdio_config_s cfg; - /* Let's assume we are not worring about OTA issue and ignore for now */ + /* Let's assume we are not worrying about OTA issue and ignore for now */ psram_io_t psram_io = { diff --git a/arch/xtensa/src/esp32/esp32_rtc.c b/arch/xtensa/src/esp32/esp32_rtc.c index c4bdfc5c37..b7b0e62474 100644 --- a/arch/xtensa/src/esp32/esp32_rtc.c +++ b/arch/xtensa/src/esp32/esp32_rtc.c @@ -498,7 +498,7 @@ static uint32_t IRAM_ATTR esp32_rtc_clk_cal_internal( modifyreg32(RTC_CNTL_CLK_CONF_REG, clks_mask, clks_state); - /* Verify if this calibration occured within the timeout */ + /* Verify if this calibration occurred within the timeout */ if (timeout_us == 0) { diff --git a/arch/xtensa/src/esp32/esp32_serial.c b/arch/xtensa/src/esp32/esp32_serial.c index 60b5fb2dfe..bb45a49759 100644 --- a/arch/xtensa/src/esp32/esp32_serial.c +++ b/arch/xtensa/src/esp32/esp32_serial.c @@ -195,7 +195,7 @@ #endif /* Semaphores to control access to each DMA. - * Theses semaphores ensure a new transfer is + * These semaphores ensure a new transfer is * triggered only after the previous one is completed, * and it also avoids competing issues with multiple UART * instances requesting to the same DMA. @@ -1936,7 +1936,7 @@ static void esp32_config_pins(struct esp32_dev_s *priv) * line and to stop receiving data. This is very similar to the concept * behind upper watermark level. The hardware threshold is used here * to control the RTS line. When setting the threshold to zero, RTS will - * imediately be asserted. If nbuffered = 0 or the lower watermark is + * immediately be asserted. If nbuffered = 0 or the lower watermark is * crossed and the serial driver decides to disable RX flow control, the * threshold will be changed to UART_RX_FLOW_THRHD_VALUE, which is almost * half the HW RX FIFO capacity. It keeps some space to keep the data @@ -1983,7 +1983,7 @@ static bool esp32_rxflowcontrol(struct uart_dev_s *dev, { /* If the RX buffer is not zero and watermarks are not enabled, * then this function is called to announce RX buffer is full. - * The first thing it should do is to imediately assert RTS. + * The first thing it should do is to immediately assert RTS. */ modifyreg32(UART_CONF1_REG(priv->config->id), UART_RX_FLOW_THRHD_M, @@ -2034,7 +2034,7 @@ void esp32_lowsetup(void) * * Description: * Performs the low level UART initialization early in debug so that the - * serial console will be available during bootup. This must be called + * serial console will be available during boot up. This must be called * before xtensa_serialinit. * ****************************************************************************/ diff --git a/arch/xtensa/src/esp32/esp32_spiflash.c b/arch/xtensa/src/esp32/esp32_spiflash.c index d58005663e..9622fc77bf 100644 --- a/arch/xtensa/src/esp32/esp32_spiflash.c +++ b/arch/xtensa/src/esp32/esp32_spiflash.c @@ -2111,7 +2111,7 @@ static ssize_t esp32_write(struct mtd_dev_s *dev, off_t offset, * buffer - data buffer pointer * * Returned Value: - * Writen bytes if success or a negative value if fail. + * Written bytes if success or a negative value if fail. * ****************************************************************************/ @@ -2451,7 +2451,7 @@ static int esp32_ioctl_encrypt(struct mtd_dev_s *dev, int cmd, * Disable the non-IRAM interrupts on the other core (the one that isn't * handling the SPI flash operation) and notify that the SPI flash * operation can start. Wait on a busy loop until it's finished and then - * reenable the non-IRAM interrups. + * re-enable the non-IRAM interrupts. * * Input Parameters: * argc - Not used. diff --git a/arch/xtensa/src/esp32/esp32_touch.c b/arch/xtensa/src/esp32/esp32_touch.c index 9d8284c7a4..5f008dd7fb 100644 --- a/arch/xtensa/src/esp32/esp32_touch.c +++ b/arch/xtensa/src/esp32/esp32_touch.c @@ -203,7 +203,7 @@ static void touch_restore_irq(void *arg) { if (touch_last_irq > 0 && touch_release_cb != NULL) { - /* Call the button interrup handler again so we can detect touch pad + /* Call the button interrupt handler again so we can detect touch pad * releases */ @@ -281,7 +281,7 @@ static void touch_init(void) * * Input Parameters: * in_now - Raw value to be filtered; - * out_last - Last value outputed; + * out_last - Last value outputted; * k - The filter coefficient. * * Returned Value: diff --git a/arch/xtensa/src/esp32/esp32_wifi_adapter.c b/arch/xtensa/src/esp32/esp32_wifi_adapter.c index 399c54b96f..08f60222e6 100644 --- a/arch/xtensa/src/esp32/esp32_wifi_adapter.c +++ b/arch/xtensa/src/esp32/esp32_wifi_adapter.c @@ -4145,8 +4145,8 @@ static unsigned long esp_random_ulong(void) * ifidx - The interface id that the tx callback has been triggered from * data - Pointer to the data transmitted * data_len - Length of the data transmitted - * txstatus - True:if the data was transmitted sucessfully False: if data - * transmission failed + * txstatus - True: if the data was transmitted successfully, False: if + * data transmission failed. * * Returned Value: * none @@ -6688,7 +6688,7 @@ int esp_wifi_softap_rssi(struct iwreq *iwr, bool set) * Name: esp32_wifi_bt_coexist_init * * Description: - * Initialize ESP32 Wi-Fi and BT coexistance module. + * Initialize ESP32 Wi-Fi and BT coexistence module. * * Input Parameters: * None diff --git a/arch/xtensa/src/esp32/hardware/esp32_i2s.h b/arch/xtensa/src/esp32/hardware/esp32_i2s.h index 4f6ed1def6..ebb461f10e 100644 --- a/arch/xtensa/src/esp32/hardware/esp32_i2s.h +++ b/arch/xtensa/src/esp32/hardware/esp32_i2s.h @@ -1641,7 +1641,7 @@ /* I2S_TX_STOP_EN : R/W; bitpos: [8]; default: 0; * Set this bit to stop disable output BCK signal and WS signal when tx FIFO - * is emtpy + * is empty. */ #define I2S_TX_STOP_EN (BIT(8)) diff --git a/arch/xtensa/src/esp32/hardware/esp32_ledc.h b/arch/xtensa/src/esp32/hardware/esp32_ledc.h index 29a3448ee8..ba67d947a3 100644 --- a/arch/xtensa/src/esp32/hardware/esp32_ledc.h +++ b/arch/xtensa/src/esp32/hardware/esp32_ledc.h @@ -92,7 +92,7 @@ /* LEDC_DUTY_HSCH0 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ /* Description: The register is used to control output duty. - * When hstimerx(x=[0 3]) choosed by high speed channel0 + * When hstimerx(x=[0 3]) chosen by high speed channel0 * has reached reg_lpoint_hsch0 the output signal changes to low. * reg_lpoint_hsch0=(reg_hpoint_hsch0[19:0]+reg_duty_hsch0[24:4]) (1) * reg_lpoint_hsch0=(reg_hpoint_hsch0[19:0]+reg_duty_hsch0[24:4] + 1) (2) @@ -234,7 +234,7 @@ /* LEDC_DUTY_HSCH1 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ /* Description: The register is used to control output duty. - * When hstimerx(x=[0 3]) choosed by high speed channel1 has reached + * When hstimerx(x=[0 3]) chosen by high speed channel1 has reached * reg_lpoint_hsch1 the output signal changes to low. * reg_lpoint_hsch1=(reg_hpoint_hsch1[19:0]+reg_duty_hsch1[24:4]) (1) * reg_lpoint_hsch1=(reg_hpoint_hsch1[19:0]+reg_duty_hsch1[24:4] + 1) (2) @@ -377,7 +377,7 @@ /* LEDC_DUTY_HSCH2 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ /* Description: The register is used to control output duty. - * When hstimerx(x=[0 3]) choosed by high speed channel2 has reached + * When hstimerx(x=[0 3]) chosen by high speed channel2 has reached * reg_lpoint_hsch2 the output signal changes to low. * reg_lpoint_hsch2=(reg_hpoint_hsch2[19:0]+reg_duty_hsch2[24:4]) (1) * reg_lpoint_hsch2=(reg_hpoint_hsch2[19:0]+reg_duty_hsch2[24:4] + 1) (2) @@ -520,7 +520,7 @@ /* LEDC_DUTY_HSCH3 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ /* Description: The register is used to control output duty. - * When hstimerx(x=[0 3]) choosed by high speed channel3 has reached + * When hstimerx(x=[0 3]) chosen by high speed channel3 has reached * reg_lpoint_hsch3 the output signal changes to low. * reg_lpoint_hsch3=(reg_hpoint_hsch3[19:0]+reg_duty_hsch3[24:4]) (1) * reg_lpoint_hsch3=(reg_hpoint_hsch3[19:0]+reg_duty_hsch3[24:4] + 1) (2) @@ -664,7 +664,7 @@ /* LEDC_DUTY_HSCH4 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ /* Description: The register is used to control output duty. - * When hstimerx(x=[0 3]) choosed by high speed channel4 has reached + * When hstimerx(x=[0 3]) chosen by high speed channel4 has reached * reg_lpoint_hsch4 the output signal changes to low. * reg_lpoint_hsch4=(reg_hpoint_hsch4[19:0]+reg_duty_hsch4[24:4]) (1) * reg_lpoint_hsch4=(reg_hpoint_hsch4[19:0]+reg_duty_hsch4[24:4] + 1) (2) @@ -807,7 +807,7 @@ /* LEDC_DUTY_HSCH5 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ /* Description: The register is used to control output duty. - * When hstimerx(x=[0 3]) choosed by high speed channel5 has reached + * When hstimerx(x=[0 3]) chosen by high speed channel5 has reached * reg_lpoint_hsch5 the output signal changes to low. * reg_lpoint_hsch5=(reg_hpoint_hsch5[19:0]+reg_duty_hsch5[24:4]) (1) * reg_lpoint_hsch5=(reg_hpoint_hsch5[19:0]+reg_duty_hsch5[24:4] + 1) (2) @@ -951,7 +951,7 @@ /* LEDC_DUTY_HSCH6 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ /* Description: The register is used to control output duty. - * When hstimerx(x=[0 3]) choosed by high speed channel6 has reached + * When hstimerx(x=[0 3]) chosen by high speed channel6 has reached * reg_lpoint_hsch6 the output signal changes to low. * reg_lpoint_hsch6=(reg_hpoint_hsch6[19:0]+reg_duty_hsch6[24:4]) (1) * reg_lpoint_hsch6=(reg_hpoint_hsch6[19:0]+reg_duty_hsch6[24:4] + 1) (2) @@ -1095,7 +1095,7 @@ /* LEDC_DUTY_HSCH7 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ /* Description: The register is used to control output duty. - * When hstimerx(x=[0 3]) choosed by high speed channel7 has reached + * When hstimerx(x=[0 3]) chosen by high speed channel7 has reached * reg_lpoint_hsch7 the output signal changes to low. * reg_lpoint_hsch7=(reg_hpoint_hsch7[19:0]+reg_duty_hsch7[24:4]) (1) * reg_lpoint_hsch7=(reg_hpoint_hsch7[19:0]+reg_duty_hsch7[24:4] + 1) (2) @@ -1250,7 +1250,7 @@ /* LEDC_DUTY_LSCH0 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ /* Description: The register is used to control output duty. - * When lstimerx(x=[0 3]) choosed by low speed channel0 has reached + * When lstimerx(x=[0 3]) chosen by low speed channel0 has reached * reg_lpoint_lsch0 the output signal changes to low. * reg_lpoint_lsch0=(reg_hpoint_lsch0[19:0]+reg_duty_lsch0[24:4]) (1) * reg_lpoint_lsch0=(reg_hpoint_lsch0[19:0]+reg_duty_lsch0[24:4] + 1) (2) @@ -1406,7 +1406,7 @@ /* LEDC_DUTY_LSCH1 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ /* Description: The register is used to control output duty. - * When lstimerx(x=[0 3]) choosed by low speed channel1 has reached + * When lstimerx(x=[0 3]) chosen by low speed channel1 has reached * reg_lpoint_lsch1 the output signal changes to low. * reg_lpoint_lsch1=(reg_hpoint_lsch1[19:0]+reg_duty_lsch1[24:4]) (1) * reg_lpoint_lsch1=(reg_hpoint_lsch1[19:0]+reg_duty_lsch1[24:4] + 1) (2) @@ -1561,7 +1561,7 @@ /* LEDC_DUTY_LSCH2 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ /* Description: The register is used to control output duty. - * When lstimerx(x=[0 3]) choosed by low speed channel2 has reached + * When lstimerx(x=[0 3]) chosen by low speed channel2 has reached * reg_lpoint_lsch2 the output signal changes to low. * reg_lpoint_lsch2=(reg_hpoint_lsch2[19:0]+reg_duty_lsch2[24:4]) (1) * reg_lpoint_lsch2=(reg_hpoint_lsch2[19:0]+reg_duty_lsch2[24:4] + 1) (2) @@ -1716,7 +1716,7 @@ /* LEDC_DUTY_LSCH3 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ /* Description: The register is used to control output duty. - * When lstimerx(x=[0 3]) choosed by low speed channel3 has reached + * When lstimerx(x=[0 3]) chosen by low speed channel3 has reached * reg_lpoint_lsch3 the output signal changes to low. * reg_lpoint_lsch3=(reg_hpoint_lsch3[19:0]+reg_duty_lsch3[24:4]) (1) * reg_lpoint_lsch3=(reg_hpoint_lsch3[19:0]+reg_duty_lsch3[24:4] + 1) (2) @@ -1871,7 +1871,7 @@ /* LEDC_DUTY_LSCH4 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ /* Description: The register is used to control output duty. - * When lstimerx(x=[0 3]) choosed by low speed channel4 has reached + * When lstimerx(x=[0 3]) chosen by low speed channel4 has reached * reg_lpoint_lsch4 the output signal changes to low. * reg_lpoint_lsch4=(reg_hpoint_lsch4[19:0]+reg_duty_lsch4[24:4]) (1) * reg_lpoint_lsch4=(reg_hpoint_lsch4[19:0]+reg_duty_lsch4[24:4] +1) (2) @@ -2026,7 +2026,7 @@ /* LEDC_DUTY_LSCH5 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ /* Description: The register is used to control output duty. - * When lstimerx(x=[0 3]) choosed by low speed channel5 has reached + * When lstimerx(x=[0 3]) chosen by low speed channel5 has reached * reg_lpoint_lsch5 the output signal changes to low. * reg_lpoint_lsch5=(reg_hpoint_lsch5[19:0]+reg_duty_lsch5[24:4]) (1) * reg_lpoint_lsch5=(reg_hpoint_lsch5[19:0]+reg_duty_lsch5[24:4] + 1) (2) @@ -2181,7 +2181,7 @@ /* LEDC_DUTY_LSCH6 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ /* Description: The register is used to control output duty. - * When lstimerx(x=[0 3]) choosed by low speed channel6 has reached + * When lstimerx(x=[0 3]) chosen by low speed channel6 has reached * reg_lpoint_lsch6 the output signal changes to low. * reg_lpoint_lsch6=(reg_hpoint_lsch6[19:0]+reg_duty_lsch6[24:4]) (1) * reg_lpoint_lsch6=(reg_hpoint_lsch6[19:0]+reg_duty_lsch6[24:4] + 1) (2) @@ -2336,7 +2336,7 @@ /* LEDC_DUTY_LSCH7 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ /* Description: The register is used to control output duty. - * When lstimerx(x=[0 3]) choosed by low speed channel7 has reached + * When lstimerx(x=[0 3]) chosen by low speed channel7 has reached * reg_lpoint_lsch7 the output signal changes to low. * reg_lpoint_lsch7=(reg_hpoint_lsch7[19:0]+reg_duty_lsch7[24:4]) (1) * reg_lpoint_lsch7=(reg_hpoint_lsch7[19:0]+reg_duty_lsch7[24:4] + 1) (2) diff --git a/arch/xtensa/src/esp32/hardware/esp32_pcnt.h b/arch/xtensa/src/esp32/hardware/esp32_pcnt.h index c7df221ab2..c083ff3aff 100644 --- a/arch/xtensa/src/esp32/hardware/esp32_pcnt.h +++ b/arch/xtensa/src/esp32/hardware/esp32_pcnt.h @@ -1087,7 +1087,7 @@ #define PCNT_FILTER_EN_U4_S 10 /* PCNT_FILTER_THRES_U4 : R/W ;bitpos:[9:0] ;default: 10'h10 ; - * Description: This register is used to filter pluse whose width is smaller + * Description: This register is used to filter pulses whose width is smaller * than this value for unit4. */ @@ -1119,7 +1119,7 @@ #define PCNT_U4_CONF2_REG (DR_REG_PCNT_BASE + 0x0038) /* PCNT_CNT_L_LIM_U4 : R/W ;bitpos:[31:16] ;default: 10'h0 ; - * Description: This register is used to confiugre thr_l_lim value for unit4. + * Description: This register is used to configure thr_l_lim value for unit4. */ #define PCNT_CNT_L_LIM_U4 0x0000FFFF @@ -1304,7 +1304,7 @@ #define PCNT_FILTER_EN_U5_S 10 /* PCNT_FILTER_THRES_U5 : R/W ;bitpos:[9:0] ;default: 10'h10 ; - * Description: This register is used to filter pluse whose width is smaller + * Description: This register is used to filter pulses whose width is smaller * than this value for unit5. */ @@ -1336,7 +1336,7 @@ #define PCNT_U5_CONF2_REG (DR_REG_PCNT_BASE + 0x0044) /* PCNT_CNT_L_LIM_U5 : R/W ;bitpos:[31:16] ;default: 10'h0 ; - * Description: This register is used to confiugre thr_l_lim value for unit5. + * Description: This register is used to configure thr_l_lim value for unit5. */ #define PCNT_CNT_L_LIM_U5 0x0000FFFF @@ -1519,7 +1519,7 @@ #define PCNT_FILTER_EN_U6_S 10 /* PCNT_FILTER_THRES_U6 : R/W ;bitpos:[9:0] ;default: 10'h10 ; - * Description: This register is used to filter pluse whose width is + * Description: This register is used to filter pulses whose width is * smaller than this value for unit6. */ @@ -1551,7 +1551,7 @@ #define PCNT_U6_CONF2_REG (DR_REG_PCNT_BASE + 0x0050) /* PCNT_CNT_L_LIM_U6 : R/W ;bitpos:[31:16] ;default: 10'h0 ; - * Description: This register is used to confiugre thr_l_lim value for unit6. + * Description: This register is used to configure thr_l_lim value for unit6. */ #define PCNT_CNT_L_LIM_U6 0x0000FFFF @@ -1737,7 +1737,7 @@ #define PCNT_FILTER_EN_U7_S 10 /* PCNT_FILTER_THRES_U7 : R/W ;bitpos:[9:0] ;default: 10'h10 ; - * Description: This register is used to filter pluse whose width is smaller + * Description: This register is used to filter pulses whose width is smaller * than this value for unit7. */ @@ -1769,7 +1769,7 @@ #define PCNT_U7_CONF2_REG (DR_REG_PCNT_BASE + 0x005c) /* PCNT_CNT_L_LIM_U7 : R/W ;bitpos:[31:16] ;default: 10'h0 ; - * Description: This register is used to confiugre thr_l_lim value for unit7. + * Description: This register is used to configure thr_l_lim value for unit7. */ #define PCNT_CNT_L_LIM_U7 0x0000FFFF diff --git a/arch/xtensa/src/esp32/hardware/esp32_rtc_io.h b/arch/xtensa/src/esp32/hardware/esp32_rtc_io.h index 6a019265f8..a6de7312c6 100644 --- a/arch/xtensa/src/esp32/hardware/esp32_rtc_io.h +++ b/arch/xtensa/src/esp32/hardware/esp32_rtc_io.h @@ -2099,7 +2099,7 @@ /* RTC_IO_TOUCH_PAD1_TO_GPIO : R/W ;bitpos:[12] ;default: 1'd0 ; */ /* Description: connect the rtc pad input to digital pad input - * '0' is availbale.GPIO0 + * '0' is available.GPIO0 */ #define RTC_IO_TOUCH_PAD1_TO_GPIO (BIT(12)) @@ -2250,7 +2250,7 @@ /* RTC_IO_TOUCH_PAD2_TO_GPIO : R/W ;bitpos:[12] ;default: 1'd0 ; */ /* Description: connect the rtc pad input to digital pad input - * '0' is availbale.GPIO2 + * '0' is available.GPIO2 */ #define RTC_IO_TOUCH_PAD2_TO_GPIO (BIT(12)) @@ -2401,7 +2401,7 @@ /* RTC_IO_TOUCH_PAD3_TO_GPIO : R/W ;bitpos:[12] ;default: 1'd0 ; */ /* Description: connect the rtc pad input to digital pad input - * '0' is availbale. MTDO + * '0' is available. MTDO */ #define RTC_IO_TOUCH_PAD3_TO_GPIO (BIT(12)) @@ -2552,7 +2552,7 @@ /* RTC_IO_TOUCH_PAD4_TO_GPIO : R/W ;bitpos:[12] ;default: 1'd0 ; */ /* Description: connect the rtc pad input to digital pad input - * '0' is availbale.MTCK + * '0' is available.MTCK */ #define RTC_IO_TOUCH_PAD4_TO_GPIO (BIT(12)) @@ -2703,7 +2703,7 @@ /* RTC_IO_TOUCH_PAD5_TO_GPIO : R/W ;bitpos:[12] ;default: 1'd0 ; */ /* Description: connect the rtc pad input to digital pad input - * '0' is availbale.MTDI + * '0' is available.MTDI */ #define RTC_IO_TOUCH_PAD5_TO_GPIO (BIT(12)) @@ -2854,7 +2854,7 @@ /* RTC_IO_TOUCH_PAD6_TO_GPIO : R/W ;bitpos:[12] ;default: 1'd0 ; */ /* Description: connect the rtc pad input to digital pad input - * '0' is availbale.MTMS + * '0' is available.MTMS */ #define RTC_IO_TOUCH_PAD6_TO_GPIO (BIT(12)) @@ -3005,7 +3005,7 @@ /* RTC_IO_TOUCH_PAD7_TO_GPIO : R/W ;bitpos:[12] ;default: 1'd0 ; */ /* Description: connect the rtc pad input to digital pad input - * '0' is availbale.GPIO27 + * '0' is available.GPIO27 */ #define RTC_IO_TOUCH_PAD7_TO_GPIO (BIT(12)) @@ -3113,7 +3113,7 @@ /* RTC_IO_TOUCH_PAD9_TO_GPIO : R/W ;bitpos:[19] ;default: 1'd0 ; */ /* Description: connect the rtc pad input to digital pad input - * '0' is availbale + * '0' is available */ #define RTC_IO_TOUCH_PAD9_TO_GPIO (BIT(19)) diff --git a/arch/xtensa/src/esp32/hardware/esp32_uart.h b/arch/xtensa/src/esp32/hardware/esp32_uart.h index 32f4e6245f..16637d1f3d 100644 --- a/arch/xtensa/src/esp32/hardware/esp32_uart.h +++ b/arch/xtensa/src/esp32/hardware/esp32_uart.h @@ -321,7 +321,7 @@ /* UART_TX_BRK_IDLE_DONE_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */ -/* Description: This is the stauts bit for tx_brk_idle_done_int_raw when +/* Description: This is the status bit for tx_brk_idle_done_int_raw when * tx_brk_idle_done_int_ena is set to 1. */ diff --git a/arch/xtensa/src/esp32/hardware/esp32_uhci.h b/arch/xtensa/src/esp32/hardware/esp32_uhci.h index ae859fa1ff..db88c2be05 100644 --- a/arch/xtensa/src/esp32/hardware/esp32_uhci.h +++ b/arch/xtensa/src/esp32/hardware/esp32_uhci.h @@ -1194,7 +1194,7 @@ #define UHCI_AHB_TESTADDR_S 4 /* UHCI_AHB_TESTMODE : RW; bitpos: [2:0]; default: 0; - * bit2 is ahb bus test enable ,bit1 is used to choose wrtie(1) or read(0) + * bit2 is ahb bus test enable ,bit1 is used to choose write(1) or read(0) * mode. bit0 is used to choose test only once(1) or continue(0) */ @@ -1669,7 +1669,7 @@ #define UHCI_ESC_CONF0_REG(i) (REG_UHCI_BASE(i) + 0xb0) /* UHCI_SEPER_ESC_CHAR1 : RW; bitpos: [23:16]; default: 220; - * This register stores the second char used to replace seperator char in + * This register stores the second char used to replace separator char in * data . 0xdc 0xdb replace 0xc0 by default. */ @@ -1679,7 +1679,7 @@ #define UHCI_SEPER_ESC_CHAR1_S 16 /* UHCI_SEPER_ESC_CHAR0 : RW; bitpos: [15:8]; default: 219; - * This register stores thee first char used to replace seperator char in + * This register stores thee first char used to replace separator char in * data. */ @@ -1689,8 +1689,8 @@ #define UHCI_SEPER_ESC_CHAR0_S 8 /* UHCI_SEPER_CHAR : RW; bitpos: [7:0]; default: 192; - * This register stores the seperator char seperator char is used to - * seperate the data frame. + * This register stores the separator char separator char is used to + * separate the data frame. */ #define UHCI_SEPER_CHAR 0x000000FF @@ -1723,7 +1723,7 @@ /* UHCI_ESC_SEQ0 : RW; bitpos: [7:0]; default: 219; * This register stores the first substitute char used to replace the - * seperator char. + * separator char. */ #define UHCI_ESC_SEQ0 0x000000FF diff --git a/arch/xtensa/src/esp32/rom/esp32_spiflash.h b/arch/xtensa/src/esp32/rom/esp32_spiflash.h index a61461a85f..8bdf0c17b2 100644 --- a/arch/xtensa/src/esp32/rom/esp32_spiflash.h +++ b/arch/xtensa/src/esp32/rom/esp32_spiflash.h @@ -351,7 +351,7 @@ esp_rom_spiflash_read_statushigh(esp32_spiflash_chip_t *spi, * Name: esp32_spiflash_write_status * * Description: - * Write status to Falsh status register. + * Write status to Flash status register. * * Please do not call this function in SDK. * diff --git a/arch/xtensa/src/esp32s2/esp32s2_efuse_table.c b/arch/xtensa/src/esp32s2/esp32s2_efuse_table.c index 45bfcb39f5..18e3cda477 100644 --- a/arch/xtensa/src/esp32s2/esp32s2_efuse_table.c +++ b/arch/xtensa/src/esp32s2/esp32s2_efuse_table.c @@ -514,7 +514,7 @@ static const efuse_desc_t FLASH_TPUW[] = static const efuse_desc_t DIS_DOWNLOAD_MODE[] = { { - 128, 1 /* Disble download mode include boot_mode[3:0] is 0 1 2 3 6 7, */ + 128, 1 /* Disable download mode include boot_mode[3:0] is 0 1 2 3 6 7, */ }, }; @@ -1153,7 +1153,7 @@ const efuse_desc_t *ESP_EFUSE_FLASH_TPUW[] = const efuse_desc_t *ESP_EFUSE_DIS_DOWNLOAD_MODE[] = { - &DIS_DOWNLOAD_MODE[0], /* Disble download mode include boot_mode[3:0] is 0 1 2 3 6 7 */ + &DIS_DOWNLOAD_MODE[0], /* Disable download mode include boot_mode[3:0] is 0 1 2 3 6 7 */ NULL }; diff --git a/arch/xtensa/src/esp32s2/esp32s2_i2c.c b/arch/xtensa/src/esp32s2/esp32s2_i2c.c index 1bd19ab5b0..8d2aab4a6b 100644 --- a/arch/xtensa/src/esp32s2/esp32s2_i2c.c +++ b/arch/xtensa/src/esp32s2/esp32s2_i2c.c @@ -830,7 +830,7 @@ static int i2c_sem_waitdone(struct esp32s2_i2c_priv_s *priv) * priv - Pointer to the internal driver state structure. * * Returned Values: - * Zero (OK) is returned on successfull transfer. -ETIMEDOUT is returned + * Zero (OK) is returned on successful transfer. -ETIMEDOUT is returned * in case a transfer didn't finish within the timeout interval. And ERROR * is returned in case of any I2C error during the transfer has happened. * diff --git a/arch/xtensa/src/esp32s2/esp32s2_i2s.c b/arch/xtensa/src/esp32s2/esp32s2_i2s.c index c6b1f230dc..71df6cf021 100644 --- a/arch/xtensa/src/esp32s2/esp32s2_i2s.c +++ b/arch/xtensa/src/esp32s2/esp32s2_i2s.c @@ -917,7 +917,7 @@ static void i2s_tx_schedule(struct esp32s2_i2s_s *priv, /* Check if the DMA descriptor that generated an EOF interrupt is the * last descriptor of the current buffer container's DMA outlink. - * REVISIT: what to do if we miss syncronization and the descriptor + * REVISIT: what to do if we miss synchronization and the descriptor * that generated the interrupt is different from the expected (the * oldest of the list containing active transmissions)? */ @@ -1016,7 +1016,7 @@ static void i2s_rx_schedule(struct esp32s2_i2s_s *priv, /* Check if the DMA descriptor that generated an EOF interrupt is the * last descriptor of the current buffer container's DMA inlink. - * REVISIT: what to do if we miss syncronization and the descriptor + * REVISIT: what to do if we miss synchronization and the descriptor * that generated the interrupt is different from the expected (the * oldest of the list containing active transmissions)? */ @@ -1496,7 +1496,7 @@ static void i2s_configure(struct esp32s2_i2s_s *priv) modifyreg32(I2S_CONF_REG, I2S_RX_SLAVE_MOD, 0); } - /* Congfigure RX chan bit, audio data bit and mono mode. + /* Configure RX chan bit, audio data bit and mono mode. * On ESP32-S2, sample_bit should equals to data_bit. */ @@ -2687,7 +2687,7 @@ struct i2s_dev_s *esp32s2_i2sbus_initialize(void) struct esp32s2_i2s_s *priv = NULL; irqstate_t flags; - /* Statically allocated I2S' device strucuture */ + /* Statically allocated I2S' device structure */ priv = &esp32s2_i2s0_priv; diff --git a/arch/xtensa/src/esp32s2/esp32s2_psram.h b/arch/xtensa/src/esp32s2/esp32s2_psram.h index b56114a942..6588bd9514 100644 --- a/arch/xtensa/src/esp32s2/esp32s2_psram.h +++ b/arch/xtensa/src/esp32s2/esp32s2_psram.h @@ -81,7 +81,7 @@ int psram_get_physical_size(uint32_t *out_size_bytes); * Note: For now ECC is only enabled on ESP32S2 Octal PSRAM * * Input Parameters: - * out_size_bytes - availabe physical psram size in bytes. + * out_size_bytes - available physical psram size in bytes. * * Returned Value: * 0 if success or a negative value if fail. diff --git a/arch/xtensa/src/esp32s2/esp32s2_rtc.c b/arch/xtensa/src/esp32s2/esp32s2_rtc.c index be9dd3f91b..5cef4398e9 100644 --- a/arch/xtensa/src/esp32s2/esp32s2_rtc.c +++ b/arch/xtensa/src/esp32s2/esp32s2_rtc.c @@ -586,7 +586,7 @@ static uint32_t IRAM_ATTR esp32s2_rtc_clk_cal_internal( clks_state &= clks_mask; /* On ESP32S2, choosing RTC_CAL_RTC_MUX results in calibration of - * the 150k RTC clock regardless of the currenlty selected SLOW_CLK. + * the 150k RTC clock regardless of the currently selected SLOW_CLK. * The following code emulates ESP32 behavior */ diff --git a/arch/xtensa/src/esp32s2/esp32s2_rtcheap.c b/arch/xtensa/src/esp32s2/esp32s2_rtcheap.c index 947aaa32bb..c5bb8e9391 100644 --- a/arch/xtensa/src/esp32s2/esp32s2_rtcheap.c +++ b/arch/xtensa/src/esp32s2/esp32s2_rtcheap.c @@ -76,7 +76,7 @@ void esp32s2_rtcheap_initialize(void) * size - Size (in bytes) of the memory region to be allocated. * * Return Value: - * Adress of the allocated memory space. NULL, if allocation fails. + * Address of the allocated memory space. NULL, if allocation fails. * ****************************************************************************/ @@ -97,7 +97,7 @@ void *esp32s2_rtcheap_malloc(size_t size) * elem_size - Size (in bytes) of the type to be allocated. * * Return Value: - * Adress of the allocated memory space. NULL, if allocation fails. + * Address of the allocated memory space. NULL, if allocation fails. * ****************************************************************************/ @@ -113,11 +113,11 @@ void *esp32s2_rtcheap_calloc(size_t n, size_t elem_size) * Reallocate memory from the RTC heap. * * Parameters: - * ptr - Adress to be reallocate. + * ptr - Address to be reallocate. * size - Size (in bytes) to be reallocate. * * Return Value: - * Adress of the possibly moved memory space. NULL, if allocation fails. + * Address of the possibly moved memory space. NULL, if allocation fails. * ****************************************************************************/ @@ -136,7 +136,7 @@ void *esp32s2_rtcheap_realloc(void *ptr, size_t size) * size - Size (in bytes) of the memory region to be allocated. * * Return Value: - * Adress of the allocated memory space. NULL, if allocation fails. + * Address of the allocated memory space. NULL, if allocation fails. * ****************************************************************************/ @@ -152,7 +152,7 @@ void *esp32s2_rtcheap_zalloc(size_t size) * Free memory from the RTC heap. * * Parameters: - * mem - Adress to be freed. + * mem - Address to be freed. * ****************************************************************************/ @@ -177,7 +177,7 @@ void esp32s2_rtcheap_free(void *mem) * size - Size (in bytes) of the memory region to be allocated. * * Return Value: - * Adress of the allocated adress. NULL, if allocation fails. + * Address of the allocated address. NULL, if allocation fails. * ****************************************************************************/ diff --git a/arch/xtensa/src/esp32s2/esp32s2_rtcheap.h b/arch/xtensa/src/esp32s2/esp32s2_rtcheap.h index fce10cac63..99326e2800 100644 --- a/arch/xtensa/src/esp32s2/esp32s2_rtcheap.h +++ b/arch/xtensa/src/esp32s2/esp32s2_rtcheap.h @@ -55,7 +55,7 @@ void esp32s2_rtcheap_initialize(void); * size - Size (in bytes) of the memory region to be allocated. * * Return Value: - * Adress of the allocated memory space. NULL, if allocation fails. + * Address of the allocated memory space. NULL, if allocation fails. * ****************************************************************************/ @@ -73,7 +73,7 @@ void *esp32s2_rtcheap_malloc(size_t size); * elem_size - Size (in bytes) of the type to be allocated. * * Return Value: - * Adress of the allocated memory space. NULL, if allocation fails. + * Address of the allocated memory space. NULL, if allocation fails. * ****************************************************************************/ @@ -86,11 +86,11 @@ void *esp32s2_rtcheap_calloc(size_t n, size_t elem_size); * Reallocate memory from the RTC heap. * * Parameters: - * ptr - Adress to be reallocate. + * ptr - Address to be reallocate. * size - Size (in bytes) to be reallocate. * * Return Value: - * Adress of the possibly moved memory space. NULL, if allocation fails. + * Address of the possibly moved memory space. NULL, if allocation fails. * ****************************************************************************/ @@ -106,7 +106,7 @@ void *esp32s2_rtcheap_realloc(void *ptr, size_t size); * size - Size (in bytes) of the memory region to be allocated. * * Return Value: - * Adress of the allocated memory space. NULL, if allocation fails. + * Address of the allocated memory space. NULL, if allocation fails. * ****************************************************************************/ @@ -119,7 +119,7 @@ void *esp32s2_rtcheap_zalloc(size_t size); * Free memory from the RTC heap. * * Parameters: - * mem - Adress to be freed. + * mem - Address to be freed. * ****************************************************************************/ @@ -141,7 +141,7 @@ void esp32s2_rtcheap_free(void *mem); * size - Size (in bytes) of the memory region to be allocated. * * Return Value: - * Adress of the allocated adress. NULL, if allocation fails. + * Address of the allocated address. NULL, if allocation fails. * ****************************************************************************/ diff --git a/arch/xtensa/src/esp32s2/esp32s2_serial.c b/arch/xtensa/src/esp32s2/esp32s2_serial.c index c1b72790f0..3be9834e38 100644 --- a/arch/xtensa/src/esp32s2/esp32s2_serial.c +++ b/arch/xtensa/src/esp32s2/esp32s2_serial.c @@ -373,7 +373,7 @@ static int esp32s2_setup(struct uart_dev_s *dev) #endif #ifdef CONFIG_SERIAL_OFLOWCONTROL - /* Configure the ouput flow control */ + /* Configure the output flow control */ if (priv->oflow) { @@ -1058,7 +1058,7 @@ static bool esp32s2_rxflowcontrol(struct uart_dev_s *dev, * * Description: * Performs the low level UART initialization early in debug so that the - * serial console will be available during bootup. This must be called + * serial console will be available during boot up. This must be called * before xtensa_serialinit. NOTE: This function depends on GPIO pin * configuration performed in esp32s2_lowsetup. * @@ -1078,7 +1078,7 @@ void xtensa_earlyserialinit(void) #endif /* Configure console in early step. - * Setup for other serials will be perfomed when the serial driver is + * Setup for other serials will be performed when the serial driver is * open. */ diff --git a/arch/xtensa/src/esp32s2/esp32s2_spiram.c b/arch/xtensa/src/esp32s2/esp32s2_spiram.c index e3941bcbac..9ec56672ef 100644 --- a/arch/xtensa/src/esp32s2/esp32s2_spiram.c +++ b/arch/xtensa/src/esp32s2/esp32s2_spiram.c @@ -208,7 +208,7 @@ void IRAM_ATTR esp_spiram_init_cache(void) } /* After mapping, we DON'T care about the PSRAM PHYSICAL - * ADDRESSS ANYMORE! + * ADDRESS ANYMORE! */ g_allocable_vaddr_start = g_mapped_vaddr_start; diff --git a/arch/xtensa/src/esp32s2/esp32s2_textheap.c b/arch/xtensa/src/esp32s2/esp32s2_textheap.c index e46b9916ad..b6b6d2e504 100644 --- a/arch/xtensa/src/esp32s2/esp32s2_textheap.c +++ b/arch/xtensa/src/esp32s2/esp32s2_textheap.c @@ -63,7 +63,7 @@ * size - Size (in bytes) of the memory region to be allocated. * * Return Value: - * Adress of the allocated adress. NULL, if allocation fails. + * Address of the allocated address. NULL, if allocation fails. * ****************************************************************************/ @@ -102,7 +102,7 @@ void *up_textheap_memalign(size_t align, size_t size) * Free memory from the text heap. * * Parameters: - * mem - Adress to be freed. + * mem - Address to be freed. * ****************************************************************************/ diff --git a/arch/xtensa/src/esp32s2/esp32s2_tim_lowerhalf.c b/arch/xtensa/src/esp32s2/esp32s2_tim_lowerhalf.c index 9c1099ebf1..88afe5f2af 100644 --- a/arch/xtensa/src/esp32s2/esp32s2_tim_lowerhalf.c +++ b/arch/xtensa/src/esp32s2/esp32s2_tim_lowerhalf.c @@ -440,7 +440,7 @@ static int esp32s2_timer_maxtimeout(struct timer_lowerhalf_s *lower, * Name: esp32s2_setcallback * * Description: - * Set the provided callback to be called at timeout from withing the + * Set the provided callback to be called at timeout from within the * ISR. * * Input Parameters: diff --git a/arch/xtensa/src/esp32s2/esp32s2_touch.c b/arch/xtensa/src/esp32s2/esp32s2_touch.c index 8e52dd1c6f..dfe93e75c7 100644 --- a/arch/xtensa/src/esp32s2/esp32s2_touch.c +++ b/arch/xtensa/src/esp32s2/esp32s2_touch.c @@ -221,7 +221,7 @@ static void touch_restore_irq(void *arg) { if (touch_last_irq > 0 && touch_release_cb != NULL) { - /* Call the button interrup handler again so we can detect touch pad + /* Call the button interrupt handler again so we can detect touch pad * releases */ diff --git a/arch/xtensa/src/esp32s2/esp32s2_touch_lowerhalf.h b/arch/xtensa/src/esp32s2/esp32s2_touch_lowerhalf.h index a7177c5d3d..024bb2cea8 100644 --- a/arch/xtensa/src/esp32s2/esp32s2_touch_lowerhalf.h +++ b/arch/xtensa/src/esp32s2/esp32s2_touch_lowerhalf.h @@ -1862,7 +1862,7 @@ static inline enum touch_pad_e touch_lh_waterproof_get_guard_pad(void) * Name: touch_lh_waterproof_set_sheild_driver * * Description: - * Set max equivalent capacitance for sheild channel. + * Set max equivalent capacitance for shield channel. * The equivalent capacitance of the shielded channel can be calculated * from the reading of denoise channel. * @@ -1886,7 +1886,7 @@ static inline void * Name: touch_lh_waterproof_get_sheild_driver * * Description: - * Set max equivalent capacitance for sheild channel. + * Set max equivalent capacitance for shield channel. * The equivalent capacitance of the shielded channel can be calculated * from the reading of denoise channel. * diff --git a/arch/xtensa/src/esp32s2/esp32s2_wifi_adapter.c b/arch/xtensa/src/esp32s2/esp32s2_wifi_adapter.c index ccbb3d6651..59455020b5 100644 --- a/arch/xtensa/src/esp32s2/esp32s2_wifi_adapter.c +++ b/arch/xtensa/src/esp32s2/esp32s2_wifi_adapter.c @@ -3936,8 +3936,8 @@ static unsigned long esp_random_ulong(void) * ifidx - The interface id that the tx callback has been triggered from * data - Pointer to the data transmitted * data_len - Length of the data transmitted - * txstatus - True:if the data was transmitted sucessfully False: if data - * transmission failed + * txstatus - True: if the data was transmitted successfully, False: if + * data transmission failed. * * Returned Value: * none diff --git a/arch/xtensa/src/esp32s2/hardware/esp32s2_aes.h b/arch/xtensa/src/esp32s2/hardware/esp32s2_aes.h index 68dd21450c..d9792fd6b2 100644 --- a/arch/xtensa/src/esp32s2/hardware/esp32s2_aes.h +++ b/arch/xtensa/src/esp32s2/hardware/esp32s2_aes.h @@ -645,7 +645,7 @@ #define AES_BLOCK_NUM_REG (DR_REG_AES_BASE + 0x98) /* AES_BLOCK_NUM : R/W; bitpos: [31:0]; default: 0; - * Stores the Block Number of plaintext or cipertext when the AES + * Stores the Block Number of plaintext or ciphertext when the AES * Accelerator operates under the DMA-AES working mode. For details, see * Section 1.5.4. */ diff --git a/arch/xtensa/src/esp32s2/hardware/esp32s2_rtccntl.h b/arch/xtensa/src/esp32s2/hardware/esp32s2_rtccntl.h index bd1b16ef42..f175d24d8a 100644 --- a/arch/xtensa/src/esp32s2/hardware/esp32s2_rtccntl.h +++ b/arch/xtensa/src/esp32s2/hardware/esp32s2_rtccntl.h @@ -827,7 +827,7 @@ #define RTC_CNTL_INT_ENA_RTC_REG (DR_REG_RTCCNTL_BASE + 0x40) /* RTC_CNTL_GLITCH_DET_INT_ENA : R/W; bitpos: [19]; default: 0; - * enbale gitch det interrupt + * enable gitch det interrupt */ #define RTC_CNTL_GLITCH_DET_INT_ENA (BIT(19)) @@ -3411,7 +3411,7 @@ #define RTC_CNTL_SWD_AUTO_FEED_EN_S 31 /* RTC_CNTL_SWD_DISABLE : R/W; bitpos: [30]; default: 0; - * disabel SWD + * disable SWD */ #define RTC_CNTL_SWD_DISABLE (BIT(30)) @@ -4268,7 +4268,7 @@ #define RTC_CNTL_XTAL32K_RESTART_WAIT_S 4 /* RTC_CNTL_XTAL32K_RETURN_WAIT : R/W; bitpos: [3:0]; default: 0; - * cycles to wait to return noral xtal 32k + * cycles to wait to return normal xtal 32k */ #define RTC_CNTL_XTAL32K_RETURN_WAIT 0x0000000F diff --git a/arch/xtensa/src/esp32s2/hardware/esp32s2_soc.h b/arch/xtensa/src/esp32s2/hardware/esp32s2_soc.h index c604a87392..71957dc6a3 100644 --- a/arch/xtensa/src/esp32s2/hardware/esp32s2_soc.h +++ b/arch/xtensa/src/esp32s2/hardware/esp32s2_soc.h @@ -460,7 +460,7 @@ static inline bool IRAM_ATTR esp32s2_ptr_exec(const void *p) * Check if the buffer comes from the RTC RAM. * * Parameters: - * p - Adress of the buffer. + * p - Address of the buffer. * * Return Value: * True if given buffer comes from RTC RAM. False if not. diff --git a/arch/xtensa/src/esp32s2/hardware/esp32s2_spi_mem_reg.h b/arch/xtensa/src/esp32s2/hardware/esp32s2_spi_mem_reg.h index 3d2903cbe1..0139d3fac5 100644 --- a/arch/xtensa/src/esp32s2/hardware/esp32s2_spi_mem_reg.h +++ b/arch/xtensa/src/esp32s2/hardware/esp32s2_spi_mem_reg.h @@ -934,7 +934,7 @@ extern "C" /* SPI_MEM_TRANS_END_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/* Description: The bit is used to enable the intterrupt of SPI +/* Description: The bit is used to enable the interrupt of SPI * transmitting done. */ diff --git a/arch/xtensa/src/esp32s2/hardware/esp32s2_system.h b/arch/xtensa/src/esp32s2/hardware/esp32s2_system.h index 189d6a30b1..bc429e6181 100644 --- a/arch/xtensa/src/esp32s2/hardware/esp32s2_system.h +++ b/arch/xtensa/src/esp32s2/hardware/esp32s2_system.h @@ -357,7 +357,7 @@ #define SYSTEM_SPI4_CLK_EN_S 31 /* SYSTEM_ADC2_ARB_CLK_EN : R/W; bitpos: [30]; default: 1; - * Set this bit to enable clock of aribiter of ADC2. + * Set this bit to enable clock of arbiter of ADC2. */ #define SYSTEM_ADC2_ARB_CLK_EN (BIT(30)) @@ -711,7 +711,7 @@ #define SYSTEM_SPI4_RST_S 31 /* SYSTEM_ADC2_ARB_RST : R/W; bitpos: [30]; default: 0; - * Set this bit to reset aribiter of ADC2. + * Set this bit to reset arbiter of ADC2. */ #define SYSTEM_ADC2_ARB_RST (BIT(30)) diff --git a/arch/xtensa/src/esp32s2/rom/esp32s2_opi_flash.h b/arch/xtensa/src/esp32s2/rom/esp32s2_opi_flash.h index 5d9f609019..bcd7a2c89d 100644 --- a/arch/xtensa/src/esp32s2/rom/esp32s2_opi_flash.h +++ b/arch/xtensa/src/esp32s2/rom/esp32s2_opi_flash.h @@ -43,8 +43,8 @@ typedef struct uint32_t addr_bit_len; /* !< Address byte length */ uint32_t *tx_data; /* !< Point to send data buffer */ uint32_t tx_data_bit_len; /* !< Send data byte length. */ - uint32_t *rx_data; /* !< Point to recevie data buffer */ - uint32_t rx_data_bit_len; /* !< Recevie Data byte length. */ + uint32_t *rx_data; /* !< Point to receive data buffer */ + uint32_t rx_data_bit_len; /* !< Receive Data byte length. */ uint32_t dummy_bit_len; } esp_rom_spi_cmd_t; diff --git a/arch/xtensa/src/esp32s2/rom/esp32s2_spiflash.h b/arch/xtensa/src/esp32s2/rom/esp32s2_spiflash.h index 66ecaf6ed8..51cebf211e 100644 --- a/arch/xtensa/src/esp32s2/rom/esp32s2_spiflash.h +++ b/arch/xtensa/src/esp32s2/rom/esp32s2_spiflash.h @@ -369,7 +369,7 @@ esp32s2_spiflash_read_statushigh(esp32s2_spiflash_chip_t *spi, * Name: esp32s2_spiflash_write_status * * Description: - * Write status to Falsh status register. + * Write status to Flash status register. * * Please do not call this function in SDK. * diff --git a/arch/xtensa/src/esp32s3/esp32s3_aes.c b/arch/xtensa/src/esp32s3/esp32s3_aes.c index 3530c7e5f0..1d0f3a411f 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_aes.c +++ b/arch/xtensa/src/esp32s3/esp32s3_aes.c @@ -895,7 +895,7 @@ int esp32s3_aes_xts_cypher(struct esp32s3_aes_xts_s *aes, bool encrypt, * Name: esp32s3_aes_setkey * * Description: - * Configurate AES key. + * Configure AES key. * * Input Parameters: * aes - AES object data pointer @@ -927,7 +927,7 @@ int esp32s3_aes_setkey(struct esp32s3_aes_s *aes, const void *keyptr, * Name: esp32s3_aes_xts_setkey * * Description: - * Configurate AES XTS key. + * Configure AES XTS key. * * Input Parameters: * aes - AES object data pointer diff --git a/arch/xtensa/src/esp32s3/esp32s3_aes.h b/arch/xtensa/src/esp32s3/esp32s3_aes.h index 5b6e8c9aaa..22d1f4fe3e 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_aes.h +++ b/arch/xtensa/src/esp32s3/esp32s3_aes.h @@ -158,7 +158,7 @@ int esp32s3_aes_xts_cypher(struct esp32s3_aes_xts_s *aes, bool encrypt, * Name: esp32s3_aes_setkey * * Description: - * Configurate AES key. + * Configure AES key. * * Input Parameters: * aes - AES object data pointer @@ -177,7 +177,7 @@ int esp32s3_aes_setkey(struct esp32s3_aes_s *aes, const void *keyptr, * Name: esp32s3_aes_xts_setkey * * Description: - * Configurate AES XTS key. + * Configure AES XTS key. * * Input Parameters: * aes - AES object data pointer diff --git a/arch/xtensa/src/esp32s3/esp32s3_ble.c b/arch/xtensa/src/esp32s3/esp32s3_ble.c index 8010cb4371..4f4c979893 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_ble.c +++ b/arch/xtensa/src/esp32s3/esp32s3_ble.c @@ -101,7 +101,7 @@ static esp_vhci_host_callback_t vhci_host_cb = * Name: esp32s3_ble_send_ready * * Description: - * If the controller could send HCI comand will callback this function. + * If the controller could send HCI command will callback this function. * * Input Parameters: * None diff --git a/arch/xtensa/src/esp32s3/esp32s3_efuse_table.c b/arch/xtensa/src/esp32s3/esp32s3_efuse_table.c index 8f60c2ff3a..50f87b4538 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_efuse_table.c +++ b/arch/xtensa/src/esp32s3/esp32s3_efuse_table.c @@ -535,7 +535,7 @@ static const efuse_desc_t FLASH_TPUW[] = static const efuse_desc_t DIS_DOWNLOAD_MODE[] = { { - 128, 1 /* Disble download mode include boot_mode[3:0] is 0 1 2 3 6 7, */ + 128, 1 /* Disable download mode include boot_mode[3:0] is 0 1 2 3 6 7, */ }, }; @@ -1213,7 +1213,7 @@ const efuse_desc_t *ESP_EFUSE_FLASH_TPUW[] = const efuse_desc_t *ESP_EFUSE_DIS_DOWNLOAD_MODE[] = { - &DIS_DOWNLOAD_MODE[0], /* Disble download mode include boot_mode[3:0] is 0 1 2 3 6 7 */ + &DIS_DOWNLOAD_MODE[0], /* Disable download mode include boot_mode[3:0] is 0 1 2 3 6 7 */ NULL }; diff --git a/arch/xtensa/src/esp32s3/esp32s3_himem.c b/arch/xtensa/src/esp32s3/esp32s3_himem.c index 7b84890bc5..478f106c43 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_himem.c +++ b/arch/xtensa/src/esp32s3/esp32s3_himem.c @@ -967,7 +967,7 @@ int esp_himem_unmap(esp_himem_rangehandle_t range, void *ptr, size_t len) /* Note: doesn't actually unmap, just clears cache and marks blocks as * unmapped. * Future optimization: could actually lazy-unmap here: essentially, do - * nothing and only clear the cache when we re-use the block for a + * nothing and only clear the cache when we reuse the block for a * different physical address. */ diff --git a/arch/xtensa/src/esp32s3/esp32s3_i2c.c b/arch/xtensa/src/esp32s3/esp32s3_i2c.c index 1a36db003f..238605878a 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_i2c.c +++ b/arch/xtensa/src/esp32s3/esp32s3_i2c.c @@ -862,7 +862,7 @@ static int i2c_sem_waitdone(struct esp32s3_i2c_priv_s *priv) * priv - Pointer to the internal driver state structure. * * Returned Values: - * Zero (OK) is returned on successfull transfer. -ETIMEDOUT is returned + * Zero (OK) is returned on successful transfer. -ETIMEDOUT is returned * in case a transfer didn't finish within the timeout interval. And ERROR * is returned in case of any I2C error during the transfer has happened. * diff --git a/arch/xtensa/src/esp32s3/esp32s3_lcd.c b/arch/xtensa/src/esp32s3/esp32s3_lcd.c index 3dcf48f00e..5cf54210d8 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_lcd.c +++ b/arch/xtensa/src/esp32s3/esp32s3_lcd.c @@ -339,14 +339,14 @@ static struct fb_vtable_s g_base_vtable = * Name: max_common_divisor * * Description: - * Calculate maxium common divisor. + * Calculate maximum common divisor. * * Input Parameters: * a - Calculation parameter a * b - Calculation parameter b * * Returned Value: - * Maxium common divisor. + * Maximum common divisor. * ****************************************************************************/ @@ -377,7 +377,7 @@ static inline uint32_t max_common_divisor(uint32_t a, uint32_t b) * * Returned Value: * true: This is the first register access of this type. - * flase: This is the same as the preceding register access. + * false: This is the same as the preceding register access. * ****************************************************************************/ @@ -429,10 +429,10 @@ static bool esp32s3_lcd_checkreg(bool wr, * Read any 32-bit register using an absolute * * Input Parameters: - * address - Regster address + * address - Register address * * Returned Value: - * Regster value. + * Register value. * ****************************************************************************/ @@ -457,8 +457,8 @@ static uint32_t esp32s3_lcd_getreg(uintptr_t address) * Write to any 32-bit register using an absolute address * * Input Parameters: - * address - Regster address - * regval - Regster value + * address - Register address + * regval - Register value * * Returned Value: * None @@ -900,8 +900,8 @@ static int esp32s3_lcd_config(void) regval |= LCD_CAM_LCD_VSYNC_INT_ENA_M; esp32s3_lcd_putreg(LCD_CAM_LC_DMA_INT_ENA_REG, regval); - /* Set LCD screem parameters: - * 1. RGB mode, ouput VSYNC/HSYNC/DE signal + /* Set LCD screen parameters: + * 1. RGB mode, output VSYNC/HSYNC/DE signal * 2. VT height * 3. VA height * 4. HB front diff --git a/arch/xtensa/src/esp32s3/esp32s3_ledc.c b/arch/xtensa/src/esp32s3/esp32s3_ledc.c index 740eb5b0ae..f01926eb65 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_ledc.c +++ b/arch/xtensa/src/esp32s3/esp32s3_ledc.c @@ -489,7 +489,7 @@ static void setup_timer(struct esp32s3_ledc_s *priv) } } - /* Caculate the prescaler */ + /* Calculate the prescaler */ prescaler = (float)pwmclk / priv->frequency / reload; diff --git a/arch/xtensa/src/esp32s3/esp32s3_otg_device.c b/arch/xtensa/src/esp32s3/esp32s3_otg_device.c index adf58f5e34..6f98a3d7b3 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_otg_device.c +++ b/arch/xtensa/src/esp32s3/esp32s3_otg_device.c @@ -2167,8 +2167,8 @@ static void esp32s3_ep0out_testmode(struct esp32s3_usbdev_s *priv, * Name: esp32s3_ep0out_stdrequest * * Description: - * Handle a stanard request on EP0. Pick off the things of interest to the - * USB device controller driver; pass what is left to the class driver. + * Handle a standard request on EP0. Pick off the things of interest to + * the USB device controller driver; pass what is left to the class driver. * ****************************************************************************/ @@ -5636,7 +5636,7 @@ void xtensa_usbinitialize(void) xtensa_usbuninitialize(); - /* Initialie the driver data structure */ + /* Initialize the driver data structure */ esp32s3_swinitialize(priv); diff --git a/arch/xtensa/src/esp32s3/esp32s3_pm.c b/arch/xtensa/src/esp32s3/esp32s3_pm.c index b89aadb405..bb019a53fd 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_pm.c +++ b/arch/xtensa/src/esp32s3/esp32s3_pm.c @@ -224,7 +224,7 @@ static _Atomic uint32_t pm_wakelock = 0; inform_out_sleep_overhead_cb_t g_periph_inform_out_sleep_overhead_cb[PERIPH_INFORM_OUT_SLEEP_OVERHEAD_NO]; -/* Indicates if light sleep shoule be skipped by peripherals. */ +/* Indicates if light sleep should be skipped by peripherals. */ skip_light_sleep_cb_t g_periph_skip_sleep_cb[PERIPH_SKIP_SLEEP_NO]; @@ -662,7 +662,7 @@ static int IRAM_ATTR esp32s3_light_sleep_inner(uint32_t pd_flags, * Name: esp32s3_periph_should_skip_sleep * * Description: - * Indicates if light sleep shoule be skipped by peripherals + * Indicates if light sleep should be skipped by peripherals * * Input Parameters: * None @@ -756,7 +756,7 @@ int esp32s3_pm_unregister_skip_sleep_callback(skip_light_sleep_cb_t cb) * Name: esp32s3_should_skip_light_sleep * * Description: - * Indicates if light sleep shoule be skipped. + * Indicates if light sleep should be skipped. * * Input Parameters: * None @@ -948,8 +948,8 @@ int IRAM_ATTR esp32s3_light_sleep_start(uint64_t *sleep_time) esp32s3_rtc_clk_cal(RTC_CAL_RTC_MUX, RTC_CLK_SRC_CAL_CYCLES); /* Adjustment time consists of parts below: - * 1. Hardware time waiting for internal 8M oscilate clock and XTAL; - * 2. Hardware state swithing time of the rtc main state machine; + * 1. Hardware time waiting for internal 8M oscillate clock and XTAL; + * 2. Hardware state switching time of the rtc main state machine; * 3. Code execution time when clock is not stable; * 4. Code execution time which can be measured; */ diff --git a/arch/xtensa/src/esp32s3/esp32s3_pm.h b/arch/xtensa/src/esp32s3/esp32s3_pm.h index 00076170a3..98c34638c0 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_pm.h +++ b/arch/xtensa/src/esp32s3/esp32s3_pm.h @@ -211,7 +211,7 @@ void esp32s3_sleep_enable_wifi_wakeup(void); * Name: esp32s3_should_skip_light_sleep * * Description: - * Indicates if light sleep shoule be skipped. + * Indicates if light sleep should be skipped. * * Input Parameters: * None diff --git a/arch/xtensa/src/esp32s3/esp32s3_psram.h b/arch/xtensa/src/esp32s3/esp32s3_psram.h index 0c4d381d8f..9d6ba93c5f 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_psram.h +++ b/arch/xtensa/src/esp32s3/esp32s3_psram.h @@ -85,7 +85,7 @@ int psram_get_physical_size(uint32_t *out_size_bytes); * Note: For now ECC is only enabled on ESP32S3 Octal PSRAM * * Input Parameters: - * out_size_bytes - availabe physical psram size in bytes. + * out_size_bytes - available physical psram size in bytes. * * Returned Value: * 0 if success or a negative value if fail. diff --git a/arch/xtensa/src/esp32s3/esp32s3_qspi.c b/arch/xtensa/src/esp32s3/esp32s3_qspi.c index fbf3a9cc22..57c8d621e4 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_qspi.c +++ b/arch/xtensa/src/esp32s3/esp32s3_qspi.c @@ -212,8 +212,8 @@ struct esp32s3_qspi_priv_s uint8_t nbits; /* Actual QSPI send/receive bits once transmission */ uint8_t dummies; /* Number of dummy cycles of command transfer */ - uint8_t addr_lines; /* Number of address transmiting I/O pins */ - uint8_t data_lines; /* Number of data transmiting I/O pins */ + uint8_t addr_lines; /* Number of address transmitting I/O pins */ + uint8_t data_lines; /* Number of data transmitting I/O pins */ }; /**************************************************************************** @@ -723,7 +723,7 @@ static int esp32s3_qspi_command(struct qspi_dev_s *dev, } } - /* Initiliaze QSPI user register */ + /* Initialize QSPI user register */ #ifdef CONFIG_ESP32S3_SPI_DMA @@ -858,7 +858,7 @@ static int esp32s3_qspi_command(struct qspi_dev_s *dev, ; } - /* Start transmision */ + /* Start transmission */ regval = getreg32(SPI_CMD_REG(id)); regval |= SPI_USR_M; @@ -931,7 +931,7 @@ static int esp32s3_qspi_memory(struct qspi_dev_s *dev, regval &= ~QSPI_DMA_RESET_MASK; putreg32(regval, SPI_DMA_CONF_REG(id)); - /* Initiliaze QSPI user register */ + /* Initialize QSPI user register */ user_reg &= ~(SPI_USR_MOSI_M | SPI_USR_MISO_M | @@ -1075,13 +1075,13 @@ static int esp32s3_qspi_memory(struct qspi_dev_s *dev, ; } - /* Start transmision */ + /* Start transmission */ regval = getreg32(SPI_CMD_REG(id)); regval |= SPI_USR_M; putreg32(regval, SPI_CMD_REG(id)); - /* Wait for transmision done */ + /* Wait for transmission done */ esp32s3_qspi_wait_sem(priv); @@ -1486,8 +1486,8 @@ static int esp32s3_qspi_interrupt(int irq, void *context, void *arg) * dev - Device-specific state data * dummies - Number of dummy cycles, this only works in command * transfer, not works in memory transfer - * addr_lines - Number of address transmiting I/O pins - * data_lines - Number of data transmiting I/O pins + * addr_lines - Number of address transmitting I/O pins + * data_lines - Number of data transmitting I/O pins * * Returned Value: * Zero (OK) is returned on success. Otherwise -1 (ERROR). diff --git a/arch/xtensa/src/esp32s3/esp32s3_qspi.h b/arch/xtensa/src/esp32s3/esp32s3_qspi.h index 838a2b8f19..6a4b1817b2 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_qspi.h +++ b/arch/xtensa/src/esp32s3/esp32s3_qspi.h @@ -71,8 +71,8 @@ extern "C" * dev - Device-specific state data * dummies - Number of dummy cycles, this only works in command * transfer, not works in memory transfer - * addr_lines - Number of address transmiting I/O pins - * data_lines - Number of data transmiting I/O pins + * addr_lines - Number of address transmitting I/O pins + * data_lines - Number of data transmitting I/O pins * * Returned Value: * Zero (OK) is returned on success. Otherwise -1 (ERROR). diff --git a/arch/xtensa/src/esp32s3/esp32s3_rtc.c b/arch/xtensa/src/esp32s3/esp32s3_rtc.c index 61ea04905e..7f64bf4b15 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_rtc.c +++ b/arch/xtensa/src/esp32s3/esp32s3_rtc.c @@ -563,7 +563,7 @@ static uint32_t IRAM_ATTR esp32s3_rtc_clk_cal_internal( clks_state &= clks_mask; /* On ESP32S3, choosing RTC_CAL_RTC_MUX results in calibration of - * the 150k RTC clock regardless of the currenlty selected SLOW_CLK. + * the 150k RTC clock regardless of the currently selected SLOW_CLK. * The following code emulates ESP32 behavior */ @@ -957,7 +957,7 @@ static void IRAM_ATTR esp32s3_rtc_clk_cpu_freq_to_pll_mhz( int cpu_freq_mhz) { /* There are totally 6 LDO slaves(all on by default). At the moment of - * swithing LDO slave, LDO voltage will also change instantaneously. + * switching LDO slave, LDO voltage will also change instantaneously. * LDO slave can reduce the voltage change caused by switching frequency. * CPU frequency <= 40M : just open 3 LDO slaves; CPU frequency = 80M : * open 4 LDO slaves; CPU frequency = 160M : open 5 LDO slaves; diff --git a/arch/xtensa/src/esp32s3/esp32s3_rtcheap.c b/arch/xtensa/src/esp32s3/esp32s3_rtcheap.c index 87946e7344..908a2c3507 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_rtcheap.c +++ b/arch/xtensa/src/esp32s3/esp32s3_rtcheap.c @@ -177,7 +177,7 @@ void esp32s3_rtcheap_free(void *mem) * size - Size (in bytes) of the memory region to be allocated. * * Return Value: - * Address of the allocated adddress. NULL, if allocation fails. + * Address of the allocated address. NULL, if allocation fails. * ****************************************************************************/ diff --git a/arch/xtensa/src/esp32s3/esp32s3_rtcheap.h b/arch/xtensa/src/esp32s3/esp32s3_rtcheap.h index edd8d56c3c..0de6d25953 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_rtcheap.h +++ b/arch/xtensa/src/esp32s3/esp32s3_rtcheap.h @@ -141,7 +141,7 @@ void esp32s3_rtcheap_free(void *mem); * size - Size (in bytes) of the memory region to be allocated. * * Return Value: - * Address of the allocated adddress. NULL, if allocation fails. + * Address of the allocated address. NULL, if allocation fails. * ****************************************************************************/ diff --git a/arch/xtensa/src/esp32s3/esp32s3_sdmmc.c b/arch/xtensa/src/esp32s3/esp32s3_sdmmc.c index e8432eedff..d49bc0e479 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_sdmmc.c +++ b/arch/xtensa/src/esp32s3/esp32s3_sdmmc.c @@ -2064,7 +2064,7 @@ static int esp32s3_waitresponse(struct sdio_dev_s *dev, uint32_t cmd) * * Returned Value: * Number of bytes sent on success; a negated errno on failure. Here a - * failure means only a faiure to obtain the requested response (due to + * failure means only a failure to obtain the requested response (due to * transport problem -- timeout, CRC, etc.). The implementation only * assures that the response is returned intacta and does not check errors * within the response itself. @@ -2162,7 +2162,7 @@ static int esp32s3_recvshortcrc(struct sdio_dev_s *dev, uint32_t cmd, * * Returned Value: * Number of bytes sent on success; a negated errno on failure. Here a - * failure means only a faiure to obtain the requested response (due to + * failure means only a failure to obtain the requested response (due to * transport problem -- timeout, CRC, etc.). The implementation only * assures that the response is returned intacta and does not check errors * within the response itself. @@ -2242,7 +2242,7 @@ static int esp32s3_recvlong(struct sdio_dev_s *dev, uint32_t cmd, * * Returned Value: * Number of bytes sent on success; a negated errno on failure. Here a - * failure means only a faiure to obtain the requested response (due to + * failure means only a failure to obtain the requested response (due to * transport problem -- timeout, CRC, etc.). The implementation only * assures that the response is returned intacta and does not check errors * within the response itself. diff --git a/arch/xtensa/src/esp32s3/esp32s3_serial.c b/arch/xtensa/src/esp32s3/esp32s3_serial.c index c83dc19f55..69d9189003 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_serial.c +++ b/arch/xtensa/src/esp32s3/esp32s3_serial.c @@ -446,7 +446,7 @@ static int esp32s3_setup(struct uart_dev_s *dev) #endif #ifdef CONFIG_SERIAL_OFLOWCONTROL - /* Configure the ouput flow control */ + /* Configure the output flow control */ if (priv->oflow) { @@ -901,7 +901,7 @@ static int esp32s3_ioctl(struct file *filep, int cmd, unsigned long arg) termiosp->c_cflag |= priv->iflow != 0 ? CRTS_IFLOW : 0; #endif - /* Set the baud rate in ther termiosp using the + /* Set the baud rate in the termiosp using the * cfsetispeed interface. */ @@ -1131,7 +1131,7 @@ static bool esp32s3_rxflowcontrol(struct uart_dev_s *dev, * * Description: * Performs the low level UART initialization early in debug so that the - * serial console will be available during bootup. This must be called + * serial console will be available during boot up. This must be called * before xtensa_serialinit. NOTE: This function depends on GPIO pin * configuration performed in xtensa_consoleinit() and main clock * initialization performed in up_clkinitialize(). @@ -1159,7 +1159,7 @@ void xtensa_earlyserialinit(void) #endif /* Configure console in early step. - * Setup for other serials will be perfomed when the serial driver is + * Setup for other serials will be performed when the serial driver is * open. */ diff --git a/arch/xtensa/src/esp32s3/esp32s3_spiflash.c b/arch/xtensa/src/esp32s3/esp32s3_spiflash.c index f34aa60114..65fe62fc47 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_spiflash.c +++ b/arch/xtensa/src/esp32s3/esp32s3_spiflash.c @@ -475,7 +475,7 @@ static void esp32s3_spi_trans(uint32_t command, uint32_t user1_reg = getreg32(SPI_MEM_USER1_REG(SPI_PORT)); uint32_t user_reg = getreg32(SPI_MEM_USER_REG(SPI_PORT)); - /* Initiliaze SPI user register */ + /* Initialize SPI user register */ user_reg &= ~(SPI_MEM_USR_DUMMY_M | SPI_MEM_USR_MOSI_M | SPI_MEM_USR_MISO_M | SPI_MEM_USR_ADDR_M); @@ -629,7 +629,7 @@ static void esp32s3_spi_trans(uint32_t command, cmd_reg |= SPI_MEM_FLASH_PE_M; } - /* Start transmision */ + /* Start transmission */ cmd_reg |= SPI_MEM_USR_M; putreg32(cmd_reg, SPI_MEM_CMD_REG(SPI_PORT)); @@ -919,7 +919,7 @@ static void spi_flash_restore_cache(void) * Disable the non-IRAM interrupts on the other core (the one that isn't * handling the SPI flash operation) and notify that the SPI flash * operation can start. Wait on a busy loop until it's finished and then - * reenable the non-IRAM interrups. + * re-enable the non-IRAM interrupts. * * Input Parameters: * argc - Not used. diff --git a/arch/xtensa/src/esp32s3/esp32s3_spiflash_mtd.c b/arch/xtensa/src/esp32s3/esp32s3_spiflash_mtd.c index dd3020cf2e..ab0a0d596c 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_spiflash_mtd.c +++ b/arch/xtensa/src/esp32s3/esp32s3_spiflash_mtd.c @@ -236,7 +236,7 @@ static inline bool IRAM_ATTR stack_is_psram(void) #endif /** - * Choose type of chip you want to encrypt manully + * Choose type of chip you want to encrypt manually * * esp-idf/components/hal/esp32s3/include/hal/spi_flash_encrypted_ll.h * @@ -294,7 +294,7 @@ static inline void spi_flash_encrypt_ll_disable(void) * Name: spi_flash_encrypt_ll_type * * Description: - * Choose type of chip you want to encrypt manully + * Choose type of chip you want to encrypt manually * * Input Parameters: * type - The type of chip to be encrypted @@ -1222,7 +1222,7 @@ static int esp32s3_writedata_encrypt(struct mtd_dev_s *dev, off_t offset, * buffer - data buffer pointer * * Returned Value: - * Writen bytes if success or a negative value if fail. + * Written bytes if success or a negative value if fail. * ****************************************************************************/ @@ -1252,8 +1252,8 @@ static ssize_t esp32s3_write_encrypt(struct mtd_dev_s *dev, off_t offset, for (n = 0; n < nbytes; n += step) { - /* The temporary buffer need to be seperated into - * 16-bytes, 32-bytes, 64-bytes(if supported). + /* The temporary buffer needs to be separated into + * 16-bytes, 32-bytes, 64-bytes (if supported). */ addr = offset + n; @@ -1304,7 +1304,7 @@ static ssize_t esp32s3_write_encrypt(struct mtd_dev_s *dev, off_t offset, * buffer - data buffer pointer * * Returned Value: - * Writen bytes if success or a negative value if fail. + * Written bytes if success or a negative value if fail. * ****************************************************************************/ @@ -1375,7 +1375,7 @@ static ssize_t esp32s3_write(struct mtd_dev_s *dev, off_t offset, * buffer - data buffer pointer * * Returned Value: - * Writen block number if success or a negative value if fail. + * Written block number if success or a negative value if fail. * ****************************************************************************/ @@ -1440,7 +1440,7 @@ static ssize_t esp32s3_bwrite_encrypt(struct mtd_dev_s *dev, * buffer - data buffer pointer * * Returned Value: - * Writen block number if success or a negative value if fail. + * Written block number if success or a negative value if fail. * ****************************************************************************/ diff --git a/arch/xtensa/src/esp32s3/esp32s3_touch.c b/arch/xtensa/src/esp32s3/esp32s3_touch.c index df9d0cbd48..c5bd070155 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_touch.c +++ b/arch/xtensa/src/esp32s3/esp32s3_touch.c @@ -172,7 +172,7 @@ static void touch_restore_irq(void *arg) { if (touch_last_irq > 0 && touch_release_cb != NULL) { - /* Call the button interrup handler again so we can detect touch pad + /* Call the button interrupt handler again so we can detect touch pad * releases */ diff --git a/arch/xtensa/src/esp32s3/esp32s3_touch_lowerhalf.h b/arch/xtensa/src/esp32s3/esp32s3_touch_lowerhalf.h index 74efccaf79..fe8bca8f23 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_touch_lowerhalf.h +++ b/arch/xtensa/src/esp32s3/esp32s3_touch_lowerhalf.h @@ -1920,7 +1920,7 @@ static inline enum touch_pad_e touch_lh_waterproof_get_guard_pad(void) * Name: touch_lh_waterproof_set_sheild_driver * * Description: - * Set max equivalent capacitance for sheild channel. + * Set max equivalent capacitance for shield channel. * The equivalent capacitance of the shielded channel can be calculated * from the reading of denoise channel. * @@ -1944,7 +1944,7 @@ static inline void * Name: touch_lh_waterproof_get_sheild_driver * * Description: - * Set max equivalent capacitance for sheild channel. + * Set max equivalent capacitance for shield channel. * The equivalent capacitance of the shielded channel can be calculated * from the reading of denoise channel. * diff --git a/arch/xtensa/src/esp32s3/esp32s3_wifi_adapter.c b/arch/xtensa/src/esp32s3/esp32s3_wifi_adapter.c index fb199087b7..e13b6f0cf2 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_wifi_adapter.c +++ b/arch/xtensa/src/esp32s3/esp32s3_wifi_adapter.c @@ -4182,8 +4182,8 @@ static unsigned long esp_random_ulong(void) * ifidx - The interface id that the tx callback has been triggered from * data - Pointer to the data transmitted * data_len - Length of the data transmitted - * txstatus - True:if the data was transmitted sucessfully False: if data - * transmission failed + * txstatus - True: if the data was transmitted successfully, False: if + * data transmission failed. * * Returned Value: * none @@ -6733,7 +6733,7 @@ int esp_wifi_softap_rssi(struct iwreq *iwr, bool set) * Name: esp_wifi_bt_coexist_init * * Description: - * Initialize ESP32-S3 Wi-Fi and BT coexistance module. + * Initialize ESP32-S3 Wi-Fi and BT coexistence module. * * Input Parameters: * None diff --git a/arch/xtensa/src/esp32s3/esp32s3_wifi_adapter.h b/arch/xtensa/src/esp32s3/esp32s3_wifi_adapter.h index 373ccd86a5..351125df0f 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_wifi_adapter.h +++ b/arch/xtensa/src/esp32s3/esp32s3_wifi_adapter.h @@ -828,7 +828,7 @@ int esp_wifi_softap_rssi(struct iwreq *iwr, bool set); * Name: esp_wifi_bt_coexist_init * * Description: - * Initialize ESP32-S3 Wi-Fi and BT coexistance module. + * Initialize ESP32-S3 Wi-Fi and BT coexistence module. * * Input Parameters: * None diff --git a/arch/xtensa/src/esp32s3/hardware/esp32s3_aes.h b/arch/xtensa/src/esp32s3/hardware/esp32s3_aes.h index a017ebd886..4b4b7beb56 100644 --- a/arch/xtensa/src/esp32s3/hardware/esp32s3_aes.h +++ b/arch/xtensa/src/esp32s3/hardware/esp32s3_aes.h @@ -645,7 +645,7 @@ #define AES_BLOCK_NUM_REG (DR_REG_AES_BASE + 0x98) /* AES_BLOCK_NUM : R/W; bitpos: [31:0]; default: 0; - * Stores the Block Number of plaintext or cipertext when the AES + * Stores the Block Number of plaintext or ciphertext when the AES * Accelerator operates under the DMA-AES working mode. For details, see * Section 1.5.4. */ diff --git a/arch/xtensa/src/esp32s3/hardware/esp32s3_efuse.h b/arch/xtensa/src/esp32s3/hardware/esp32s3_efuse.h index 45dcedce38..4e5b54de1f 100644 --- a/arch/xtensa/src/esp32s3/hardware/esp32s3_efuse.h +++ b/arch/xtensa/src/esp32s3/hardware/esp32s3_efuse.h @@ -817,7 +817,7 @@ #define EFUSE_FLASH_ECC_MODE_S 3 /* EFUSE_UART_PRINT_CHANNEL : RO; bitpos: [2]; default: 0; - * Selectes the default UART print channel. 0: UART0. 1: UART1. + * Selects the default UART print channel. 0: UART0. 1: UART1. */ #define EFUSE_UART_PRINT_CHANNEL (BIT(2)) @@ -2917,7 +2917,7 @@ #define EFUSE_EFUSE_MEM_FORCE_PD_S 0 /* EFUSE_CONF_REG register - * eFuse operation mode configuraiton register + * eFuse operation mode configuration register */ #define EFUSE_CONF_REG (DR_REG_EFUSE_BASE + 0x1cc) diff --git a/arch/xtensa/src/esp32s3/hardware/esp32s3_i2s.h b/arch/xtensa/src/esp32s3/hardware/esp32s3_i2s.h index 014fd358bd..393b44fd9a 100644 --- a/arch/xtensa/src/esp32s3/hardware/esp32s3_i2s.h +++ b/arch/xtensa/src/esp32s3/hardware/esp32s3_i2s.h @@ -523,7 +523,7 @@ /* I2S_TX_STOP_EN : R/W ;bitpos:[13] ;default: 1'h1 ; */ /* Description: Set this bit to stop disable output BCK signal and WS - * signal when tx FIFO is emtpy. + * signal when tx FIFO is empty. */ #define I2S_TX_STOP_EN (BIT(13)) diff --git a/arch/xtensa/src/esp32s3/hardware/esp32s3_interrupt_core0.h b/arch/xtensa/src/esp32s3/hardware/esp32s3_interrupt_core0.h index 909074a7e6..ddd31be8cc 100644 --- a/arch/xtensa/src/esp32s3/hardware/esp32s3_interrupt_core0.h +++ b/arch/xtensa/src/esp32s3/hardware/esp32s3_interrupt_core0.h @@ -1700,7 +1700,7 @@ #define INTERRUPT_CORE0_CLOCK_GATE_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x19c) /* INTERRUPT_CORE0_REG_CLK_EN : R/W; bitpos: [0]; default: 1; - * this register uesd to control clock-gating interupt martrix + * this register used to control clock-gating interrupt martrix */ #define INTERRUPT_CORE0_REG_CLK_EN (BIT(0)) diff --git a/arch/xtensa/src/esp32s3/hardware/esp32s3_interrupt_core1.h b/arch/xtensa/src/esp32s3/hardware/esp32s3_interrupt_core1.h index 6cdc5e04f6..df53d648a8 100644 --- a/arch/xtensa/src/esp32s3/hardware/esp32s3_interrupt_core1.h +++ b/arch/xtensa/src/esp32s3/hardware/esp32s3_interrupt_core1.h @@ -184,7 +184,7 @@ #define INTERRUPT_CORE1_RWBT_NMI_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x24) /* INTERRUPT_CORE1_RWBT_NMI_MAP : R/W; bitpos: [4:0]; default: 16; - * this register used to map rwbt_nmi interupt to one of core1's external + * this register used to map rwbt_nmi interrupt to one of core1's external * interrupt */ @@ -1700,7 +1700,7 @@ #define INTERRUPT_CORE1_CLOCK_GATE_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x19c) /* INTERRUPT_CORE1_REG_CLK_EN : R/W; bitpos: [0]; default: 1; - * this register uesd to control clock-gating interupt martrix + * this register used to control clock-gating interrupt martrix */ #define INTERRUPT_CORE1_REG_CLK_EN (BIT(0)) diff --git a/arch/xtensa/src/esp32s3/hardware/esp32s3_lcd_cam.h b/arch/xtensa/src/esp32s3/hardware/esp32s3_lcd_cam.h index 5865a42d18..e585d1d730 100644 --- a/arch/xtensa/src/esp32s3/hardware/esp32s3_lcd_cam.h +++ b/arch/xtensa/src/esp32s3/hardware/esp32s3_lcd_cam.h @@ -763,7 +763,7 @@ #define LCD_CAM_LCD_VFK_CYCLELEN_S 6 /* LCD_CAM_LCD_AFIFO_THRESHOLD_NUM : R/W; bitpos: [5:1]; default: 11; - * The awfull threshold number of lcd_afifo. + * The awful threshold number of lcd_afifo. */ #define LCD_CAM_LCD_AFIFO_THRESHOLD_NUM 0x0000001f diff --git a/arch/xtensa/src/esp32s3/hardware/esp32s3_rtccntl.h b/arch/xtensa/src/esp32s3/hardware/esp32s3_rtccntl.h index 8b26a01a81..7fc7ef4b38 100644 --- a/arch/xtensa/src/esp32s3/hardware/esp32s3_rtccntl.h +++ b/arch/xtensa/src/esp32s3/hardware/esp32s3_rtccntl.h @@ -985,7 +985,7 @@ #define RTC_CNTL_RTC_TOUCH_APPROACH_LOOP_DONE_INT_ENA_S 20 /* RTC_CNTL_RTC_GLITCH_DET_INT_ENA : R/W; bitpos: [19]; default: 0; - * enbale gitch det interrupt + * enable gitch det interrupt */ #define RTC_CNTL_RTC_GLITCH_DET_INT_ENA (BIT(19)) @@ -2049,13 +2049,13 @@ #define RTC_CNTL_RTC_SLEEP_REJECT_ENA_S 12 /* RTC_CNTL_RTC_CPU_PERIOD_CONF_REG register - * conigure cpu freq + * configure cpu freq */ #define RTC_CNTL_RTC_CPU_PERIOD_CONF_REG (DR_REG_RTCCNTL_BASE + 0x6c) /* RTC_CNTL_RTC_CPUPERIOD_SEL : R/W; bitpos: [31:30]; default: 0; - * conigure cpu freq + * configure cpu freq */ #define RTC_CNTL_RTC_CPUPERIOD_SEL 0x00000003 @@ -2971,7 +2971,7 @@ #define RTC_CNTL_LSLP_MEM_FORCE_PD_S 3 /* RTC_CNTL_DIG_ISO_REG register - * congigure digital power isolation + * configure digital power isolation */ #define RTC_CNTL_DIG_ISO_REG (DR_REG_RTCCNTL_BASE + 0x94) @@ -3365,7 +3365,7 @@ #define RTC_CNTL_WDT_WKEY_S 0 /* RTC_CNTL_RTC_SWD_CONF_REG register - * congfigure super watch dog + * configure super watch dog */ #define RTC_CNTL_RTC_SWD_CONF_REG (DR_REG_RTCCNTL_BASE + 0xb4) @@ -3380,7 +3380,7 @@ #define RTC_CNTL_SWD_AUTO_FEED_EN_S 31 /* RTC_CNTL_SWD_DISABLE : R/W; bitpos: [30]; default: 0; - * disabel SWD + * disable SWD */ #define RTC_CNTL_SWD_DISABLE (BIT(30)) @@ -4075,7 +4075,7 @@ #define RTC_CNTL_EXT_WAKEUP1_STATUS_S 0 /* RTC_CNTL_RTC_BROWN_OUT_REG register - * congfigure brownout + * configure brownout */ #define RTC_CNTL_RTC_BROWN_OUT_REG (DR_REG_RTCCNTL_BASE + 0xe8) @@ -4249,7 +4249,7 @@ #define RTC_CNTL_XTAL32K_RESTART_WAIT_S 4 /* RTC_CNTL_XTAL32K_RETURN_WAIT : R/W; bitpos: [3:0]; default: 0; - * cycles to wait to return noral xtal 32k + * cycles to wait to return normal xtal 32k */ #define RTC_CNTL_XTAL32K_RETURN_WAIT 0x0000000f @@ -5080,7 +5080,7 @@ #define RTC_CNTL_TOUCH_TIMEOUT_NUM_S 0 /* RTC_CNTL_RTC_SLP_REJECT_CAUSE_REG register - * get reject casue + * get reject cause */ #define RTC_CNTL_RTC_SLP_REJECT_CAUSE_REG (DR_REG_RTCCNTL_BASE + 0x128) @@ -5147,7 +5147,7 @@ /* RTC_CNTL_RTC_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TS : WO; bitpos: [20]; * default: 0; - * enbale touch approach_loop done interrupt + * enable touch approach_loop done interrupt */ #define RTC_CNTL_RTC_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TS (BIT(20)) @@ -5156,7 +5156,7 @@ #define RTC_CNTL_RTC_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TS_S 20 /* RTC_CNTL_RTC_GLITCH_DET_INT_ENA_W1TS : WO; bitpos: [19]; default: 0; - * enbale gitch det interrupt + * enable gitch det interrupt */ #define RTC_CNTL_RTC_GLITCH_DET_INT_ENA_W1TS (BIT(19)) @@ -5343,7 +5343,7 @@ /* RTC_CNTL_RTC_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TC : WO; bitpos: [20]; * default: 0; - * enbale touch approach_loop done interrupt + * enable touch approach_loop done interrupt */ #define RTC_CNTL_RTC_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TC (BIT(20)) @@ -5352,7 +5352,7 @@ #define RTC_CNTL_RTC_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TC_S 20 /* RTC_CNTL_RTC_GLITCH_DET_INT_ENA_W1TC : WO; bitpos: [19]; default: 0; - * enbale gitch det interrupt + * enable gitch det interrupt */ #define RTC_CNTL_RTC_GLITCH_DET_INT_ENA_W1TC (BIT(19)) @@ -5583,7 +5583,7 @@ #define RTC_CNTL_RETENTION_CLK_SEL_S 16 /* RTC_CNTL_RETENTION_TARGET : R/W; bitpos: [15:14]; default: 0; - * congfigure retention target cpu and/or tag + * configure retention target cpu and/or tag */ #define RTC_CNTL_RETENTION_TARGET 0x00000003 @@ -5814,13 +5814,13 @@ #define RTC_CNTL_TOUCH_PAD14_DAC_S 17 /* RTC_CNTL_RTC_COCPU_DISABLE_REG register - * configure ulp diable + * configure ulp disable */ #define RTC_CNTL_RTC_COCPU_DISABLE_REG (DR_REG_RTCCNTL_BASE + 0x154) /* RTC_CNTL_DISABLE_RTC_CPU : R/W; bitpos: [31]; default: 0; - * configure ulp diable + * configure ulp disable */ #define RTC_CNTL_DISABLE_RTC_CPU (BIT(31)) diff --git a/arch/xtensa/src/esp32s3/hardware/esp32s3_sensitive.h b/arch/xtensa/src/esp32s3/hardware/esp32s3_sensitive.h index 1e246d1c3b..9177744fe6 100644 --- a/arch/xtensa/src/esp32s3/hardware/esp32s3_sensitive.h +++ b/arch/xtensa/src/esp32s3/hardware/esp32s3_sensitive.h @@ -263,7 +263,7 @@ #define SENSITIVE_CACHE_TAG_ACCESS_1_REG (DR_REG_SENSITIVE_BASE + 0x2c) /* SENSITIVE_PRO_D_TAG_WR_ACS : R/W; bitpos: [3]; default: 1; - * Set 1 to enable Dcache wrtie access tag memory. + * Set 1 to enable Dcache write access tag memory. */ #define SENSITIVE_PRO_D_TAG_WR_ACS (BIT(3)) @@ -281,7 +281,7 @@ #define SENSITIVE_PRO_D_TAG_RD_ACS_S 2 /* SENSITIVE_PRO_I_TAG_WR_ACS : R/W; bitpos: [1]; default: 1; - * Set 1 to enable Icache wrtie access tag memory. + * Set 1 to enable Icache write access tag memory. */ #define SENSITIVE_PRO_I_TAG_WR_ACS (BIT(1)) @@ -2621,7 +2621,7 @@ /* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS : R/W; bitpos: * [27:26]; default: 3; - * core0/core1's permission(sotre,load) of rom in world1. + * core0/core1's permission (store,load) of rom in world1. */ #define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS 0x00000003 @@ -2631,7 +2631,7 @@ /* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS : R/W; bitpos: * [25:24]; default: 3; - * core0/core1's permission(sotre,load) of rom in world0. + * core0/core1's permission (store,load) of rom in world0. */ #define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS 0x00000003 @@ -4874,7 +4874,7 @@ /* SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE : RO; bitpos: * [4:2]; default: 0; - * Record access type when core0 initate illegal access. + * Record access type when core0 initiates an illegal access. */ #define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE 0x00000007 @@ -6988,7 +6988,7 @@ /* SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE : RO; bitpos: * [4:2]; default: 0; - * Record access type when core1 initate illegal access. + * Record access type when core1 initiates an illegal access. */ #define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE 0x00000007 @@ -7887,7 +7887,7 @@ /* SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HSIZE : RO; bitpos: * [5:3]; default: 0; - * Record access type when BackUp initate illegal access. + * Record access type when BackUp initiates an illegal access. */ #define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HSIZE 0x00000007 @@ -7897,7 +7897,7 @@ /* SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HTRANS : RO; bitpos: * [2:1]; default: 0; - * Record htrans when BackUp initate illegal access. + * Record htrans when BackUp initiates an illegal access. */ #define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HTRANS 0x00000003 diff --git a/arch/xtensa/src/esp32s3/hardware/esp32s3_spi.h b/arch/xtensa/src/esp32s3/hardware/esp32s3_spi.h index dda9f666c1..2fc6b451ce 100644 --- a/arch/xtensa/src/esp32s3/hardware/esp32s3_spi.h +++ b/arch/xtensa/src/esp32s3/hardware/esp32s3_spi.h @@ -89,7 +89,7 @@ #define SPI_CTRL_REG(i) (REG_SPI_BASE(i) + 0x8) /* SPI_WR_BIT_ORDER : R/W; bitpos: [26:25]; default: 0; - * In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can + * In command address write-data (MOSI) phases 1: LSB first 0: MSB first. Can * be configured in CONF state. */ @@ -256,7 +256,7 @@ #define SPI_CLOCK_REG(i) (REG_SPI_BASE(i) + 0xc) /* SPI_CLK_EQU_SYSCLK : R/W; bitpos: [31]; default: 1; - * In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided + * In the master mode 1: spi_clk is equal to system 0: spi_clk is divided * from system clock. Can be configured in CONF state. */ @@ -2581,7 +2581,7 @@ /* SPI_CLK_MODE : R/W; bitpos: [1:0]; default: 0; * SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is * delayed one cycle after CS inactive 2: SPI clock is delayed two cycles - * after CS inactive 3: SPI clock is alwasy on. Can be configured in CONF + * after CS inactive 3: SPI clock is always on. Can be configured in CONF * state. */ diff --git a/arch/xtensa/src/esp32s3/hardware/esp32s3_syscon.h b/arch/xtensa/src/esp32s3/hardware/esp32s3_syscon.h index ba516f382d..6b29fe7f24 100644 --- a/arch/xtensa/src/esp32s3/hardware/esp32s3_syscon.h +++ b/arch/xtensa/src/esp32s3/hardware/esp32s3_syscon.h @@ -264,7 +264,7 @@ #define SYSTEM_MACPWR_RST BIT(8) #define SYSTEM_RW_BTMAC_RST BIT(9) /* Bluetooth MAC */ #define SYSTEM_RW_BTLP_RST BIT(10) /* Bluetooth Low Power Module */ -#define SYSTEM_RW_BTMAC_REG_RST BIT(11) /* Bluetooth MAC Regsiters */ +#define SYSTEM_RW_BTMAC_REG_RST BIT(11) /* Bluetooth MAC Registers */ #define SYSTEM_RW_BTLP_REG_RST BIT(12) /* Bluetooth Low Power Registers */ #define SYSTEM_BTBB_REG_RST BIT(13) /* Bluetooth Baseband Registers */ diff --git a/arch/xtensa/src/esp32s3/hardware/esp32s3_uart.h b/arch/xtensa/src/esp32s3/hardware/esp32s3_uart.h index b893811de1..6153ec5571 100644 --- a/arch/xtensa/src/esp32s3/hardware/esp32s3_uart.h +++ b/arch/xtensa/src/esp32s3/hardware/esp32s3_uart.h @@ -154,7 +154,7 @@ #define UART_SW_XOFF_INT_RAW_S 10 /* UART_SW_XON_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; - * This interrupt raw bit turns to high level when receiver recevies Xon + * This interrupt raw bit turns to high level when receiver receives Xon * char when uart_sw_flow_con_en is set to 1. */ @@ -320,7 +320,7 @@ #define UART_TX_DONE_INT_ST_S 14 /* UART_TX_BRK_IDLE_DONE_INT_ST : RO; bitpos: [13]; default: 0; - * This is the stauts bit for tx_brk_idle_done_int_raw when + * This is the status bit for tx_brk_idle_done_int_raw when * tx_brk_idle_done_int_ena is set to 1. */ @@ -1148,7 +1148,7 @@ #define UART_IRDA_DPLX_S 9 /* UART_TXD_BRK : R/W; bitpos: [8]; default: 0; - * Set this bit to enbale transmitter to send NULL when the process of + * Set this bit to enable transmitter to send NULL when the process of * sending data is done. */ @@ -1220,7 +1220,7 @@ #define UART_CONF1_REG(i) (REG_UART_BASE(i) + 0x24) /* UART_RX_TOUT_EN : R/W; bitpos: [23]; default: 0; - * This is the enble bit for uart receiver's timeout function. + * This is the enable bit for uart receiver's timeout function. */ #define UART_RX_TOUT_EN (BIT(23)) diff --git a/arch/xtensa/src/esp32s3/rom/esp32s3_spiflash.h b/arch/xtensa/src/esp32s3/rom/esp32s3_spiflash.h index 57bba4ebbe..bde9025248 100644 --- a/arch/xtensa/src/esp32s3/rom/esp32s3_spiflash.h +++ b/arch/xtensa/src/esp32s3/rom/esp32s3_spiflash.h @@ -278,7 +278,7 @@ esp32s3_spiflash_read_statushigh(esp_rom_spiflash_chip_t *spi, * Name: esp32s3_spiflash_write_status * * Description: - * Write status to Falsh status register. + * Write status to Flash status register. * * Please do not call this function in SDK. * @@ -381,7 +381,7 @@ esp_rom_spiflash_config_clk(uint8_t freqdiv, * * Please do not call this function in SDK. * - * Input Paramater: + * Input Parameter: * esp_rom_spiflash_common_cmd_t *cmd : A struct to show the action of a * command. * diff --git a/arch/z16/src/z16f/z16f_espi.c b/arch/z16/src/z16f/z16f_espi.c index 9a441f2e84..d075115825 100644 --- a/arch/z16/src/z16f/z16f_espi.c +++ b/arch/z16/src/z16f/z16f_espi.c @@ -175,7 +175,7 @@ static struct z16f_spi_s g_espi = * * Returned Value: * true: This is the first register access of this type. - * flase: This is the same as the preceding register access. + * false: This is the same as the preceding register access. * ****************************************************************************/ diff --git a/arch/z80/src/Makefile.clang b/arch/z80/src/Makefile.clang index 4c7fcd139a..ac4f581687 100644 --- a/arch/z80/src/Makefile.clang +++ b/arch/z80/src/Makefile.clang @@ -50,7 +50,7 @@ AOBJS = $(ASRCS:$(ASMEXT)=$(OBJEXT)) CSRCS = $(CHIP_CSRCS) $(CMN_CSRCS) COBJS = $(CSRCS:.c=$(OBJEXT)) -# All sources and objcts +# All sources and objects SRCS = $(ASRCS) $(CSRCS) OBJS = $(AOBJS) $(COBJS) diff --git a/arch/z80/src/Makefile.sdccl b/arch/z80/src/Makefile.sdccl index a36e35786d..db8de5a267 100644 --- a/arch/z80/src/Makefile.sdccl +++ b/arch/z80/src/Makefile.sdccl @@ -48,7 +48,7 @@ AOBJS = $(ASRCS:$(ASMEXT)=$(OBJEXT)) CSRCS = $(CHIP_CSRCS) $(CMN_CSRCS) COBJS = $(CSRCS:.c=$(OBJEXT)) -# All sources and objcts +# All sources and objects SRCS = $(ASRCS) $(CSRCS) OBJS = $(AOBJS) $(COBJS) diff --git a/arch/z80/src/Makefile.sdccw b/arch/z80/src/Makefile.sdccw index 44a9cb3a60..9f76c32479 100644 --- a/arch/z80/src/Makefile.sdccw +++ b/arch/z80/src/Makefile.sdccw @@ -45,7 +45,7 @@ AOBJS = $(ASRCS:$(ASMEXT)=$(OBJEXT)) CSRCS = $(CHIP_CSRCS) $(CMN_CSRCS) COBJS = $(CSRCS:.c=$(OBJEXT)) -# All sources and objcts +# All sources and objects SRCS = $(ASRCS) $(CSRCS) OBJS = $(AOBJS) $(COBJS) diff --git a/arch/z80/src/ez80/ez80F91.inc b/arch/z80/src/ez80/ez80F91.inc index e98ca14936..1799cfe988 100644 --- a/arch/z80/src/ez80/ez80F91.inc +++ b/arch/z80/src/ez80/ez80F91.inc @@ -358,7 +358,7 @@ UARTINSTS_CTO EQU 00ch ; 110: Character timeout * UARTINSTS_TC EQU 00ah ; 101: Transmission complete * UARTINSTS_RLS EQU 006h ; 011: Receiver line status * UARTINSTS_RDR EQU 004h ; 010: Receive data ready or trigger level * -UARTINSTS_TBE EQU 002h ; 001: Transmisson buffer empty * +UARTINSTS_TBE EQU 002h ; 001: Transmission buffer empty * UARTINSTS_MS EQU 000h ; 000: Modem status * UARTIIR_INTBIT EQU 001h ; Bit 0: Active interrupt source * UARTIIR_CAUSEMASK EQU 00fh diff --git a/arch/z80/src/ez80/ez80f91.h b/arch/z80/src/ez80/ez80f91.h index 2ca85e36cf..448c80b85a 100644 --- a/arch/z80/src/ez80/ez80f91.h +++ b/arch/z80/src/ez80/ez80f91.h @@ -350,7 +350,7 @@ # define EZ80_UARTINSTS_TC 0x0a /* 101: Transmission complete */ # define EZ80_UARTINSTS_RLS 0x06 /* 011: Receiver line status */ # define EZ80_UARTINSTS_RDR 0x04 /* 010: Receive data ready or trigger level */ -# define EZ80_UARTINSTS_TBE 0x02 /* 001: Transmisson buffer empty */ +# define EZ80_UARTINSTS_TBE 0x02 /* 001: Transmission buffer empty */ # define EZ80_UARTINSTS_MS 0x00 /* 000: Modem status */ #define EZ80_UARTIIR_INTBIT 0x01 /* Bit 0: Active interrupt source */ #define EZ80_UARTIIR_CAUSEMASK 0x0f diff --git a/arch/z80/src/ez80/ez80f91_emac.h b/arch/z80/src/ez80/ez80f91_emac.h index b2dedd3123..40dfe571af 100644 --- a/arch/z80/src/ez80/ez80f91_emac.h +++ b/arch/z80/src/ez80/ez80f91_emac.h @@ -157,7 +157,7 @@ #define EMAC_FFLAGS_RFF 0x08 /* Bit 0: 1=Receive FIFO full */ #define EMAC_FFLAGS_TFE 0x10 /* Bit 0: 1=Transmit FIFO empty */ #define EMAC_FFLAGS_TFAE 0x20 /* Bit 0: 1=Transmit FIFO almost empty */ -#define EMAC_FFLAGS_TFF 0x80 /* Bit 0: 1=Trasnmit FIFO full */ +#define EMAC_FFLAGS_TFF 0x80 /* Bit 0: 1=Transmit FIFO full */ /* EMAC Transmit Descriptor Status ******************************************/ diff --git a/arch/z80/src/ez80/ez80f92.h b/arch/z80/src/ez80/ez80f92.h index a9a4f63b29..d744f0d41b 100644 --- a/arch/z80/src/ez80/ez80f92.h +++ b/arch/z80/src/ez80/ez80f92.h @@ -212,7 +212,7 @@ # define EZ80_UARTINSTS_TC 0x0a /* 101: Transmission complete */ # define EZ80_UARTINSTS_RLS 0x06 /* 011: Receiver line status */ # define EZ80_UARTINSTS_RDR 0x04 /* 010: Receive data ready or trigger level */ -# define EZ80_UARTINSTS_TBE 0x02 /* 001: Transmisson buffer empty */ +# define EZ80_UARTINSTS_TBE 0x02 /* 001: Transmission buffer empty */ # define EZ80_UARTINSTS_MS 0x00 /* 000: Modem status */ #define EZ80_UARTIIR_INTBIT 0x01 /* Bit 0: (NOT) Active interrupt source */ #define EZ80_UARTIIR_CAUSEMASK 0x0f diff --git a/arch/z80/src/z180/z180_mmu.c b/arch/z80/src/z180/z180_mmu.c index 7266c1d951..27e5577460 100644 --- a/arch/z80/src/z180/z180_mmu.c +++ b/arch/z80/src/z180/z180_mmu.c @@ -319,7 +319,7 @@ int up_addrenv_destroy(FAR arch_addrenv_t *addrenv) gran_free(g_physhandle, (FAR void *)cbr->cbr, cbr->pages); - /* And make the CBR structure available for re-use */ + /* And make the CBR structure available for reuse */ z180_mmu_freecbr(cbr); return OK; diff --git a/audio/audio.c b/audio/audio.c index 5c85f4a6f3..5753e3e36d 100644 --- a/audio/audio.c +++ b/audio/audio.c @@ -240,7 +240,7 @@ errout: * Name: audio_read * * Description: - * A dummy read method. This is provided only to satsify the VFS layer. + * A dummy read method. This is provided only to satisfy the VFS layer. * ****************************************************************************/ @@ -268,7 +268,7 @@ static ssize_t audio_read(FAR struct file *filep, * Name: audio_write * * Description: - * A dummy write method. This is provided only to satsify the VFS layer. + * A dummy write method. This is provided only to satisfy the VFS layer. * ****************************************************************************/ @@ -687,7 +687,7 @@ static int audio_ioctl(FAR struct file *filep, int cmd, unsigned long arg) * Input Parameters: * handle - This is the handle that was provided to the lower-half * start() method. - * apb - A pointer to the previsously enqueued ap_buffer_s + * apb - A pointer to the previously enqueued ap_buffer_s * status - Status of the dequeue operation * * Returned Value: @@ -801,7 +801,7 @@ static inline void audio_message(FAR struct audio_upperhalf_s *upper, * * Description: * Send an AUDIO_MSG_IOERR message to the client to indicate that - * audio dirver have io error. The lower-half driver initiates this + * audio driver have io error. The lower-half driver initiates this * call via its callback pointer to our upper-half driver. * ****************************************************************************/ @@ -880,7 +880,7 @@ static inline void audio_underrun(FAR struct audio_upperhalf_s *upper, * Input Parameters: * priv - Private context data owned by the upper-half * reason - The reason code for the callback - * apb - A pointer to the previsously enqueued ap_buffer_s + * apb - A pointer to the previously enqueued ap_buffer_s * status - Status information associated with the callback * * Returned Value: diff --git a/boards/arm/at32/at32f437-mini/src/at32_usb.c b/boards/arm/at32/at32f437-mini/src/at32_usb.c index 1cc42c3615..b98ea01a98 100644 --- a/boards/arm/at32/at32f437-mini/src/at32_usb.c +++ b/boards/arm/at32/at32f437-mini/src/at32_usb.c @@ -122,7 +122,7 @@ static int usbhost_waiter(int argc, char *argv[]) * Name: at32_usbinitialize * * Description: - * Called from at32_usbinitialize very early in inialization to setup + * Called from at32_usbinitialize very early in initialization to setup * USB-related GPIO pins for the AT32F407_MINIvery board. * ****************************************************************************/ diff --git a/boards/arm/at32/at32f437-mini/src/at32f437-mini.h b/boards/arm/at32/at32f437-mini/src/at32f437-mini.h index ebf2eb61b2..7c9bfc510a 100644 --- a/boards/arm/at32/at32f437-mini/src/at32f437-mini.h +++ b/boards/arm/at32/at32f437-mini/src/at32f437-mini.h @@ -144,7 +144,7 @@ #elif defined(CONFIG_AT32_UART8_HCIUART) # define HCIUART_SERDEV HCIUART8 #else -# error No HCI UART specifified +# error No HCI UART specified #endif /* AT32F4 Mini GPIOs ********************************************************/ diff --git a/boards/arm/cxd56xx/drivers/audio/cxd56_audio_ac_reg.c b/boards/arm/cxd56xx/drivers/audio/cxd56_audio_ac_reg.c index d11548c234..d6d5f19eef 100644 --- a/boards/arm/cxd56xx/drivers/audio/cxd56_audio_ac_reg.c +++ b/boards/arm/cxd56xx/drivers/audio/cxd56_audio_ac_reg.c @@ -1058,7 +1058,7 @@ CXD56_AUDIO_ECODE cxd56_audio_ac_reg_set_alcspc(void) } else if (CXD56_AUDIO_CFG_ALCSPC == CXD56_AUDIO_CFG_ALCSPC_SPC) { - /* Set sound pressure conter */ + /* Set sound pressure counter */ ret = set_spc_param(); if (ret != CXD56_AUDIO_ECODE_OK) diff --git a/boards/arm/cxd56xx/drivers/audio/cxd56_audio_filter.c b/boards/arm/cxd56xx/drivers/audio/cxd56_audio_filter.c index 4bd8b9c995..9a63dc39e6 100644 --- a/boards/arm/cxd56xx/drivers/audio/cxd56_audio_filter.c +++ b/boards/arm/cxd56xx/drivers/audio/cxd56_audio_filter.c @@ -65,7 +65,7 @@ void cxd56_audio_filter_set_dnc(cxd56_audio_dnc_id_t id, bool en, cxd56_audio_dnc_bin_t *bin) { - /* Desable DNC. */ + /* Disable DNC. */ cxd56_audio_ac_reg_disable_dnc(id); diff --git a/boards/arm/cxd56xx/spresense/Kconfig b/boards/arm/cxd56xx/spresense/Kconfig index 15b15edfc5..d7818d9d04 100644 --- a/boards/arm/cxd56xx/spresense/Kconfig +++ b/boards/arm/cxd56xx/spresense/Kconfig @@ -409,7 +409,7 @@ endmenu endif # CXD56_AUDIO_ALC_SPC_SEL_ALC if CXD56_AUDIO_ALC_SPC_SEL_SPC -menu "Sound Pressure Conter setting" +menu "Sound Pressure Counter setting" config CXD56_AUDIO_SPC_LIMIT int "Limit levels of Sound Pressure Counter.[(1/10)dB]" default 0 diff --git a/boards/arm/cxd56xx/spresense/include/board.h b/boards/arm/cxd56xx/spresense/include/board.h index f5e0abfbb8..6e292d33bb 100644 --- a/boards/arm/cxd56xx/spresense/include/board.h +++ b/boards/arm/cxd56xx/spresense/include/board.h @@ -302,7 +302,7 @@ enum board_power_device * supply current value. * signal returns "usbdev_notify_s" struct pointer in sival_ptr. * - * Arg: Value of sinal number + * Arg: Value of signal number */ #define BOARDIOC_USBDEV_SETNOTIFYSIG (BOARDIOC_USER+0x0001) diff --git a/boards/arm/cxd56xx/spresense/src/cxd56_bringup.c b/boards/arm/cxd56xx/spresense/src/cxd56_bringup.c index e6846a46e3..57fa6c7a69 100644 --- a/boards/arm/cxd56xx/spresense/src/cxd56_bringup.c +++ b/boards/arm/cxd56xx/spresense/src/cxd56_bringup.c @@ -243,7 +243,7 @@ int cxd56_bringup(void) ret = cxd56_pm_bootup(); if (ret < 0) { - _err("ERROR: Failed to powermgr bootup.\n"); + _err("ERROR: Failed to powermgr boot up.\n"); } #endif diff --git a/boards/arm/cxd56xx/spresense/src/cxd56_composite.c b/boards/arm/cxd56xx/spresense/src/cxd56_composite.c index 0305277d72..e848658b34 100644 --- a/boards/arm/cxd56xx/spresense/src/cxd56_composite.c +++ b/boards/arm/cxd56xx/spresense/src/cxd56_composite.c @@ -168,7 +168,7 @@ static int board_mscclassobject(int minor, * that is called form the composite device logic. * * Input Parameters: - * classdev - The class driver instrance previously give to the composite + * classdev - The class driver instance previously given to the composite * driver by board_mscclassobject(). * * Returned Value: diff --git a/boards/arm/cxd56xx/spresense/src/cxd56_power.c b/boards/arm/cxd56xx/spresense/src/cxd56_power.c index 175e89ea13..b52c90165c 100644 --- a/boards/arm/cxd56xx/spresense/src/cxd56_power.c +++ b/boards/arm/cxd56xx/spresense/src/cxd56_power.c @@ -542,7 +542,7 @@ int board_reset(int status) { board_power_control(PMIC_TYPE_GPO | g_reset_gpo_targets, false); - /* Restore the original state for bootup after power cycle */ + /* Restore the original state for boot up after power cycle */ if (!up_interrupt_context()) { diff --git a/boards/arm/gd32f4/gd32f450zk-aiotbox/src/gd32f4xx_i2c.c b/boards/arm/gd32f4/gd32f450zk-aiotbox/src/gd32f4xx_i2c.c index 0f51fb1e38..db7e43382e 100644 --- a/boards/arm/gd32f4/gd32f450zk-aiotbox/src/gd32f4xx_i2c.c +++ b/boards/arm/gd32f4/gd32f450zk-aiotbox/src/gd32f4xx_i2c.c @@ -50,7 +50,7 @@ void gd32_i2c_initialize(void) if (i2c == NULL) { - i2cerr("init i2c0 faild.\n"); + i2cerr("init i2c0 failed.\n"); return; } else @@ -59,11 +59,11 @@ void gd32_i2c_initialize(void) if (ret < 0) { - i2cerr("registering i2c0 faild.\n"); + i2cerr("registering i2c0 failed.\n"); } else { - i2cinfo("registering i2c0 successed.\n"); + i2cinfo("registering i2c0 succeeded.\n"); } } @@ -74,7 +74,7 @@ void gd32_i2c_initialize(void) if (i2c == NULL) { - i2cerr("init i2c1 faild.\n"); + i2cerr("init i2c1 failed.\n"); return; } else @@ -83,11 +83,11 @@ void gd32_i2c_initialize(void) if (ret < 0) { - i2cerr("registering i2c1 faild.\n"); + i2cerr("registering i2c1 failed.\n"); } else { - i2cinfo("registering i2c1 successed.\n"); + i2cinfo("registering i2c1 succeeded.\n"); } } diff --git a/boards/arm/gd32f4/gd32f470zk-aiotbox/src/gd32f4xx_i2c.c b/boards/arm/gd32f4/gd32f470zk-aiotbox/src/gd32f4xx_i2c.c index 676b77e891..773149cf4d 100644 --- a/boards/arm/gd32f4/gd32f470zk-aiotbox/src/gd32f4xx_i2c.c +++ b/boards/arm/gd32f4/gd32f470zk-aiotbox/src/gd32f4xx_i2c.c @@ -50,7 +50,7 @@ void gd32_i2c_initialize(void) if (i2c == NULL) { - i2cerr("init i2c0 faild.\n"); + i2cerr("init i2c0 failed.\n"); return; } else @@ -59,11 +59,11 @@ void gd32_i2c_initialize(void) if (ret < 0) { - i2cerr("registering i2c0 faild.\n"); + i2cerr("registering i2c0 failed.\n"); } else { - i2cinfo("registering i2c0 successed.\n"); + i2cinfo("registering i2c0 succeeded.\n"); } } @@ -74,7 +74,7 @@ void gd32_i2c_initialize(void) if (i2c == NULL) { - i2cerr("init i2c1 faild.\n"); + i2cerr("init i2c1 failed.\n"); return; } else @@ -83,11 +83,11 @@ void gd32_i2c_initialize(void) if (ret < 0) { - i2cerr("registering i2c1 faild.\n"); + i2cerr("registering i2c1 failed.\n"); } else { - i2cinfo("registering i2c1 successed.\n"); + i2cinfo("registering i2c1 succeeded.\n"); } } diff --git a/boards/arm/imxrt/imxrt1020-evk/src/imxrt_flexspi_nor_flash.h b/boards/arm/imxrt/imxrt1020-evk/src/imxrt_flexspi_nor_flash.h index 511bf90074..917bca8441 100644 --- a/boards/arm/imxrt/imxrt1020-evk/src/imxrt_flexspi_nor_flash.h +++ b/boards/arm/imxrt/imxrt1020-evk/src/imxrt_flexspi_nor_flash.h @@ -239,7 +239,7 @@ enum flash_misc_feature_e FLEXSPIMISC_OFFSET_WORD_ADDRESSABLE_EN = 3, /* Bit for Word Addressable enable */ FLEXSPIMISC_OFFSET_SAFECONFIG_FREQ_EN = 4, /* Bit for Safe Configuration Frequency enable */ FLEXSPIMISC_OFFSET_PAD_SETTING_OVERRIDE_EN = 5, /* Bit for Pad setting override enable */ - FLEXSPIMISC_OFFSET_DDR_MODE_EN = 6, /* Bit for DDR clock confiuration indication. */ + FLEXSPIMISC_OFFSET_DDR_MODE_EN = 6, /* Bit for DDR clock configuration indication. */ }; /* Flash Type Definition */ diff --git a/boards/arm/imxrt/imxrt1050-evk/src/imxrt_flexspi_nor_flash.h b/boards/arm/imxrt/imxrt1050-evk/src/imxrt_flexspi_nor_flash.h index f7568d4cd1..eb8b7e0da5 100644 --- a/boards/arm/imxrt/imxrt1050-evk/src/imxrt_flexspi_nor_flash.h +++ b/boards/arm/imxrt/imxrt1050-evk/src/imxrt_flexspi_nor_flash.h @@ -237,7 +237,7 @@ enum flash_misc_feature_e FLEXSPIMISC_OFFSET_WORD_ADDRESSABLE_EN = 3, /* Bit for Word Addressable enable */ FLEXSPIMISC_OFFSET_SAFECONFIG_FREQ_EN = 4, /* Bit for Safe Configuration Frequency enable */ FLEXSPIMISC_OFFSET_PAD_SETTING_OVERRIDE_EN = 5, /* Bit for Pad setting override enable */ - FLEXSPIMISC_OFFSET_DDR_MODE_EN = 6, /* Bit for DDR clock confiuration indication. */ + FLEXSPIMISC_OFFSET_DDR_MODE_EN = 6, /* Bit for DDR clock configuration indication. */ }; /* Flash Type Definition */ diff --git a/boards/arm/imxrt/imxrt1060-evk/scripts/flash-ocram.ld b/boards/arm/imxrt/imxrt1060-evk/scripts/flash-ocram.ld index b532c1cc60..67d6116ef2 100644 --- a/boards/arm/imxrt/imxrt1060-evk/scripts/flash-ocram.ld +++ b/boards/arm/imxrt/imxrt1060-evk/scripts/flash-ocram.ld @@ -37,7 +37,7 @@ * This is the OCRAM inker script. * The NXP ROM bootloader will move the FLASH image to OCRAM. * We must reserve 32K for the bootloader' OCRAM usage from the OCRAM Size - * and an additinal 8K for the ivt_s which is IVT_SIZE(8K) This 40K can be + * and an additional 8K for the ivt_s which is IVT_SIZE(8K) This 40K can be * reused once the application is running. * * 0x2020:A000 to 0x202d:ffff - The application Image's vector table diff --git a/boards/arm/imxrt/imxrt1060-evk/src/imxrt_flexspi_nor_flash.h b/boards/arm/imxrt/imxrt1060-evk/src/imxrt_flexspi_nor_flash.h index 768773fdbb..3e6fc96f29 100644 --- a/boards/arm/imxrt/imxrt1060-evk/src/imxrt_flexspi_nor_flash.h +++ b/boards/arm/imxrt/imxrt1060-evk/src/imxrt_flexspi_nor_flash.h @@ -239,7 +239,7 @@ enum flash_misc_feature_e FLEXSPIMISC_OFFSET_WORD_ADDRESSABLE_EN = 3, /* Bit for Word Addressable enable */ FLEXSPIMISC_OFFSET_SAFECONFIG_FREQ_EN = 4, /* Bit for Safe Configuration Frequency enable */ FLEXSPIMISC_OFFSET_PAD_SETTING_OVERRIDE_EN = 5, /* Bit for Pad setting override enable */ - FLEXSPIMISC_OFFSET_DDR_MODE_EN = 6, /* Bit for DDR clock confiuration indication. */ + FLEXSPIMISC_OFFSET_DDR_MODE_EN = 6, /* Bit for DDR clock configuration indication. */ }; /* Flash Type Definition */ diff --git a/boards/arm/imxrt/imxrt1064-evk/scripts/flash-ocram.ld b/boards/arm/imxrt/imxrt1064-evk/scripts/flash-ocram.ld index e203b2a32f..77d2db0638 100644 --- a/boards/arm/imxrt/imxrt1064-evk/scripts/flash-ocram.ld +++ b/boards/arm/imxrt/imxrt1064-evk/scripts/flash-ocram.ld @@ -37,7 +37,7 @@ * This is the OCRAM inker script. * The NXP ROM bootloader will move the FLASH image to OCRAM. * We must reserve 32K for the bootloader' OCRAM usage from the OCRAM Size - * and an additinal 8K for the ivt_s which is IVT_SIZE(8K) This 40K can be + * and an additional 8K for the ivt_s which is IVT_SIZE(8K) This 40K can be * reused once the application is running. * * 0x2020:A000 to 0x202d:ffff - The application Image's vector table diff --git a/boards/arm/imxrt/imxrt1064-evk/src/imxrt_flexspi_nor_flash.h b/boards/arm/imxrt/imxrt1064-evk/src/imxrt_flexspi_nor_flash.h index 7bf87159ca..2d97710fbb 100644 --- a/boards/arm/imxrt/imxrt1064-evk/src/imxrt_flexspi_nor_flash.h +++ b/boards/arm/imxrt/imxrt1064-evk/src/imxrt_flexspi_nor_flash.h @@ -231,7 +231,7 @@ enum flash_misc_feature_e FLEXSPIMISC_OFFSET_WORD_ADDRESSABLE_EN = 3, /* Bit for Word Addressable enable */ FLEXSPIMISC_OFFSET_SAFECONFIG_FREQ_EN = 4, /* Bit for Safe Configuration Frequency enable */ FLEXSPIMISC_OFFSET_PAD_SETTING_OVERRIDE_EN = 5, /* Bit for Pad setting override enable */ - FLEXSPIMISC_OFFSET_DDR_MODE_EN = 6, /* Bit for DDR clock confiuration indication. */ + FLEXSPIMISC_OFFSET_DDR_MODE_EN = 6, /* Bit for DDR clock configuration indication. */ }; /* Flash Type Definition */ diff --git a/boards/arm/imxrt/imxrt1170-evk/scripts/flash-ocram.ld b/boards/arm/imxrt/imxrt1170-evk/scripts/flash-ocram.ld index 8e9efc650d..a2f450b518 100644 --- a/boards/arm/imxrt/imxrt1170-evk/scripts/flash-ocram.ld +++ b/boards/arm/imxrt/imxrt1170-evk/scripts/flash-ocram.ld @@ -31,13 +31,13 @@ * 256Kib to OCRRAM, 128Kib ITCM and 128Kib DTCM. * This can be changed by using a dcd by minipulating * IOMUX GPR16 and GPR17. - * The configuartion we will use is 384Kib to OCRRAM, 0Kib ITCM and + * The configuration we will use is 384Kib to OCRRAM, 0Kib ITCM and * 128Kib DTCM. * * This is the OCRAM inker script. * The NXP ROM bootloader will move the FLASH image to OCRAM. * We must reserve 32K for the bootloader' OCRAM usage from the OCRAM Size - * and an additinal 8K for the ivt_s which is IVT_SIZE(8K) This 40K can be + * and an additional 8K for the ivt_s which is IVT_SIZE(8K) This 40K can be * reused once the application is running. * * 0x2020:A000 to 0x202d:ffff - The application Image's vector table diff --git a/boards/arm/imxrt/imxrt1170-evk/src/imxrt_boot.c b/boards/arm/imxrt/imxrt1170-evk/src/imxrt_boot.c index 801b7cf626..c2b0a31c73 100644 --- a/boards/arm/imxrt/imxrt1170-evk/src/imxrt_boot.c +++ b/boards/arm/imxrt/imxrt1170-evk/src/imxrt_boot.c @@ -79,7 +79,7 @@ void imxrt_ocram_initialize(void) * Name: imxrt_flexram_partition * * Description: - * Sets FlexRAM paritioning + * Sets FlexRAM partitioning * ****************************************************************************/ diff --git a/boards/arm/imxrt/imxrt1170-evk/src/imxrt_flexspi_nor_flash.h b/boards/arm/imxrt/imxrt1170-evk/src/imxrt_flexspi_nor_flash.h index b4cb3f2d7c..68c113d248 100644 --- a/boards/arm/imxrt/imxrt1170-evk/src/imxrt_flexspi_nor_flash.h +++ b/boards/arm/imxrt/imxrt1170-evk/src/imxrt_flexspi_nor_flash.h @@ -231,7 +231,7 @@ enum flash_misc_feature_e FLEXSPIMISC_OFFSET_WORD_ADDRESSABLE_EN = 3, /* Bit for Word Addressable enable */ FLEXSPIMISC_OFFSET_SAFECONFIG_FREQ_EN = 4, /* Bit for Safe Configuration Frequency enable */ FLEXSPIMISC_OFFSET_PAD_SETTING_OVERRIDE_EN = 5, /* Bit for Pad setting override enable */ - FLEXSPIMISC_OFFSET_DDR_MODE_EN = 6, /* Bit for DDR clock confiuration indication. */ + FLEXSPIMISC_OFFSET_DDR_MODE_EN = 6, /* Bit for DDR clock configuration indication. */ }; /* Flash Type Definition */ diff --git a/boards/arm/imxrt/teensy-4.x/Kconfig b/boards/arm/imxrt/teensy-4.x/Kconfig index 70fcecbf4c..27134502cf 100644 --- a/boards/arm/imxrt/teensy-4.x/Kconfig +++ b/boards/arm/imxrt/teensy-4.x/Kconfig @@ -33,7 +33,7 @@ config IMXRT_FLEXCAN3_AS_CAN0 config NET_USE_OTP_ETHERNET_MAC bool "Use Ethernet MAC address stored in OCOTP_MAC0 and OCOTP_MAC1" ---help--- - The teensy 4.1 board has an "offical" unique MAC address stored in OCOTP (One-Time-Programmable) memory. + The teensy 4.1 board has an "official" unique MAC address stored in OCOTP (One-Time-Programmable) memory. When enabling this option, it is read and used when the ethernet peripheral is initialized. If so, the 'ifconfig eth0' HWaddr should start with 04:e9:e5:... (the vendor ID of 'PJRC.COM, LLC') when this feature is enabled. @@ -44,7 +44,7 @@ if TEENSY_41 config TEENSY_41_PIKRON_BB bool "Base board for Teensy 4.1 configuration" ---help--- - Configuration pikron-bb contains setup for open hardware based board fo Teensy 4.1. This option + Configuration pikron-bb contains setup for open hardware based board for Teensy 4.1. This option sets up HW pinout as ADC channels for example. endif diff --git a/boards/arm/imxrt/teensy-4.x/scripts/flash-ocram.ld b/boards/arm/imxrt/teensy-4.x/scripts/flash-ocram.ld index 82cb194299..1bc6ec8549 100644 --- a/boards/arm/imxrt/teensy-4.x/scripts/flash-ocram.ld +++ b/boards/arm/imxrt/teensy-4.x/scripts/flash-ocram.ld @@ -37,7 +37,7 @@ * This is the OCRAM inker script. * The NXP ROM bootloader will move the FLASH image to OCRAM. * We must reserve 32K for the bootloader' OCRAM usage from the OCRAM Size - * and an additinal 8K for the ivt_s which is IVT_SIZE(8K) This 40K can be + * and an additional 8K for the ivt_s which is IVT_SIZE(8K) This 40K can be * reused once the application is running. * * 0x2020:A000 to 0x202d:ffff - The application Image's vector table diff --git a/boards/arm/imxrt/teensy-4.x/src/imxrt_flexspi_nor_flash.h b/boards/arm/imxrt/teensy-4.x/src/imxrt_flexspi_nor_flash.h index 09c5b33651..4e184cd2e7 100644 --- a/boards/arm/imxrt/teensy-4.x/src/imxrt_flexspi_nor_flash.h +++ b/boards/arm/imxrt/teensy-4.x/src/imxrt_flexspi_nor_flash.h @@ -236,7 +236,7 @@ enum flash_misc_feature_e FLEXSPIMISC_OFFSET_PAD_SETTING_OVERRIDE_EN = 5, /* Bit for Pad setting * override enable */ - FLEXSPIMISC_OFFSET_DDR_MODE_EN = 6, /* Bit for DDR clock confiuration + FLEXSPIMISC_OFFSET_DDR_MODE_EN = 6, /* Bit for DDR clock configuration * indication. */ }; diff --git a/boards/arm/kinetis/freedom-k28f/src/freedom-k28f.h b/boards/arm/kinetis/freedom-k28f/src/freedom-k28f.h index 70b2db4b29..3e56ecf70f 100644 --- a/boards/arm/kinetis/freedom-k28f/src/freedom-k28f.h +++ b/boards/arm/kinetis/freedom-k28f/src/freedom-k28f.h @@ -268,7 +268,7 @@ extern void weak_function k28_usbdev_initialize(void); * Name: k28_usbhost_initialize * * Description: - * Inititialize USB High Speed Host + * Initialize USB High Speed Host * ****************************************************************************/ @@ -282,7 +282,7 @@ int k28_usbhost_initialize(void); * Name: k28_sdhc_initialize * * Description: - * Inititialize the SDHC SD card slot + * Initialize the SDHC SD card slot * ****************************************************************************/ diff --git a/boards/arm/kinetis/freedom-k28f/src/k28_sdhc.c b/boards/arm/kinetis/freedom-k28f/src/k28_sdhc.c index f44f65050f..40d4966298 100644 --- a/boards/arm/kinetis/freedom-k28f/src/k28_sdhc.c +++ b/boards/arm/kinetis/freedom-k28f/src/k28_sdhc.c @@ -145,7 +145,7 @@ static int k28_cdinterrupt(int irq, void *context, void *arg) * Name: k28_sdhc_initialize * * Description: - * Inititialize the SDHC SD card slot + * Initialize the SDHC SD card slot * ****************************************************************************/ diff --git a/boards/arm/kinetis/freedom-k64f/src/freedom-k64f.h b/boards/arm/kinetis/freedom-k64f/src/freedom-k64f.h index 41766df5a2..e5b3974908 100644 --- a/boards/arm/kinetis/freedom-k64f/src/freedom-k64f.h +++ b/boards/arm/kinetis/freedom-k64f/src/freedom-k64f.h @@ -260,7 +260,7 @@ int k64_bringup(void); * Name: k64_sdhc_initialize * * Description: - * Inititialize the SDHC SD card slot + * Initialize the SDHC SD card slot * ****************************************************************************/ diff --git a/boards/arm/kinetis/freedom-k64f/src/k64_sdhc.c b/boards/arm/kinetis/freedom-k64f/src/k64_sdhc.c index 18121fdc7f..efeeeb0fa2 100644 --- a/boards/arm/kinetis/freedom-k64f/src/k64_sdhc.c +++ b/boards/arm/kinetis/freedom-k64f/src/k64_sdhc.c @@ -145,7 +145,7 @@ static int k64_cdinterrupt(int irq, void *context, void *arg) * Name: k64_sdhc_initialize * * Description: - * Inititialize the SDHC SD card slot + * Initialize the SDHC SD card slot * ****************************************************************************/ diff --git a/boards/arm/kinetis/freedom-k66f/src/freedom-k66f.h b/boards/arm/kinetis/freedom-k66f/src/freedom-k66f.h index 796e00a0b6..36859ecbda 100644 --- a/boards/arm/kinetis/freedom-k66f/src/freedom-k66f.h +++ b/boards/arm/kinetis/freedom-k66f/src/freedom-k66f.h @@ -290,7 +290,7 @@ int k66_bringup(void); * Name: k66_sdhc_initialize * * Description: - * Inititialize the SDHC SD card slot + * Initialize the SDHC SD card slot * ****************************************************************************/ diff --git a/boards/arm/kinetis/kwikstik-k40/src/k40_appinit.c b/boards/arm/kinetis/kwikstik-k40/src/k40_appinit.c index f1f93bd3cd..fde1e6c9b0 100644 --- a/boards/arm/kinetis/kwikstik-k40/src/k40_appinit.c +++ b/boards/arm/kinetis/kwikstik-k40/src/k40_appinit.c @@ -100,7 +100,7 @@ ****************************************************************************/ /* This structure encapsulates the global variable used in this file and - * reduces the probability of name collistions. + * reduces the probability of name collisions. */ #ifdef NSH_HAVEMMCSD diff --git a/boards/arm/kinetis/twr-k60n512/src/k60_appinit.c b/boards/arm/kinetis/twr-k60n512/src/k60_appinit.c index eb57401206..eaab1f213d 100644 --- a/boards/arm/kinetis/twr-k60n512/src/k60_appinit.c +++ b/boards/arm/kinetis/twr-k60n512/src/k60_appinit.c @@ -102,7 +102,7 @@ ****************************************************************************/ /* This structure encapsulates the global variable used in this file and - * reduces the probability of name collistions. + * reduces the probability of name collisions. */ #ifdef NSH_HAVEMMCSD diff --git a/boards/arm/kinetis/twr-k64f120m/src/k64_leds.c b/boards/arm/kinetis/twr-k64f120m/src/k64_leds.c index 485bcda1f2..3de7a3ceeb 100644 --- a/boards/arm/kinetis/twr-k64f120m/src/k64_leds.c +++ b/boards/arm/kinetis/twr-k64f120m/src/k64_leds.c @@ -214,7 +214,7 @@ void board_autoled_initialize(void) * Name: board_autoled_on * * Description: - * Puts on the relevants LEDs for one of the LED_condition (see board.h) + * Puts on the relevant LEDs for one of the LED_condition (see board.h) ****************************************************************************/ void board_autoled_on(int led) @@ -226,7 +226,7 @@ void board_autoled_on(int led) * Name: board_autoled_off * * Description: - * Puts off the relevants LEDs for one of the LED_condition (see board.h) + * Puts off the relevant LEDs for one of the LED_condition (see board.h) ****************************************************************************/ void board_autoled_off(int led) diff --git a/boards/arm/kinetis/twr-k64f120m/src/k64_sdhc.c b/boards/arm/kinetis/twr-k64f120m/src/k64_sdhc.c index 361ae7f768..4485b6f3dc 100644 --- a/boards/arm/kinetis/twr-k64f120m/src/k64_sdhc.c +++ b/boards/arm/kinetis/twr-k64f120m/src/k64_sdhc.c @@ -141,7 +141,7 @@ static int k64_cdinterrupt(int irq, void *context, void *arg) * Name: k64_sdhc_initialize * * Description: - * Inititialize the SDHC SD card slot + * Initialize the SDHC SD card slot * ****************************************************************************/ diff --git a/boards/arm/kinetis/twr-k64f120m/src/twrk64.h b/boards/arm/kinetis/twr-k64f120m/src/twrk64.h index 653351fd8b..1f3fc2242d 100644 --- a/boards/arm/kinetis/twr-k64f120m/src/twrk64.h +++ b/boards/arm/kinetis/twr-k64f120m/src/twrk64.h @@ -283,7 +283,7 @@ int k64_bringup(void); * Name: k64_sdhc_initialize * * Description: - * Inititialize the SDHC SD card slot + * Initialize the SDHC SD card slot * ****************************************************************************/ diff --git a/boards/arm/kl/freedom-kl25z/src/freedom-kl25z.h b/boards/arm/kl/freedom-kl25z/src/freedom-kl25z.h index bd76d0c4b6..db3fa3729a 100644 --- a/boards/arm/kl/freedom-kl25z/src/freedom-kl25z.h +++ b/boards/arm/kl/freedom-kl25z/src/freedom-kl25z.h @@ -108,7 +108,7 @@ void weak_function kl_spidev_initialize(void); * Name: kl_usbinitialize * * Description: - * Called from kl_usbinitialize very early in inialization to setup + * Called from kl_usbinitialize very early in initialization to setup * USB-related GPIO pins for the Freedom KL25Z board. * ****************************************************************************/ diff --git a/boards/arm/kl/freedom-kl26z/src/freedom-kl26z.h b/boards/arm/kl/freedom-kl26z/src/freedom-kl26z.h index 00641b7a83..547fed6757 100644 --- a/boards/arm/kl/freedom-kl26z/src/freedom-kl26z.h +++ b/boards/arm/kl/freedom-kl26z/src/freedom-kl26z.h @@ -108,7 +108,7 @@ void weak_function kl_spidev_initialize(void); * Name: kl_usbinitialize * * Description: - * Called from kl_usbinitialize very early in inialization to setup + * Called from kl_usbinitialize very early in initialization to setup * USB-related GPIO pins for the Freedom KL26Z board. * ****************************************************************************/ diff --git a/boards/arm/lpc17xx_40xx/lincoln60/include/board.h b/boards/arm/lpc17xx_40xx/lincoln60/include/board.h index 16a977aea5..703ea42105 100644 --- a/boards/arm/lpc17xx_40xx/lincoln60/include/board.h +++ b/boards/arm/lpc17xx_40xx/lincoln60/include/board.h @@ -53,7 +53,7 @@ /* This is the clock setup we configure for: * * SYSCLK = BOARD_OSCCLK_FREQUENCY = 12MHz -> Main oscillator for source - * PLL0CLK = (2 * 20 * SYSCLK) / 1 = 480MHz -> multipler=20, pre-divider=1 + * PLL0CLK = (2 * 20 * SYSCLK) / 1 = 480MHz -> multiplier=20, pre-divider=1 * CCLCK = 480MHz / 6 = 80MHz -> divider = 6 */ diff --git a/boards/arm/lpc17xx_40xx/lpc4088-devkit/include/board.h b/boards/arm/lpc17xx_40xx/lpc4088-devkit/include/board.h index 1a0fbe59d3..c1309b59b4 100644 --- a/boards/arm/lpc17xx_40xx/lpc4088-devkit/include/board.h +++ b/boards/arm/lpc17xx_40xx/lpc4088-devkit/include/board.h @@ -57,7 +57,7 @@ * * SYSCLK = BOARD_OSCCLK_FREQUENCY = 12MHz -> Select Main oscillator for * source - * PLL0CLK = (10 * SYSCLK) / 1 = 120MHz -> PLL0 multipler=10, pre-divider=1 + * PLL0CLK = (10 * SYSCLK) / 1 = 120MHz -> PLL0 multiplier=10, pre-divider=1 * CCLCK = 120MHz -> CCLK divider = 1 */ diff --git a/boards/arm/lpc17xx_40xx/lpc4088-quickstart/include/board.h b/boards/arm/lpc17xx_40xx/lpc4088-quickstart/include/board.h index b0ea4a203f..7fd8bbff59 100644 --- a/boards/arm/lpc17xx_40xx/lpc4088-quickstart/include/board.h +++ b/boards/arm/lpc17xx_40xx/lpc4088-quickstart/include/board.h @@ -56,7 +56,7 @@ * * SYSCLK = BOARD_OSCCLK_FREQUENCY = 12MHz -> Select Main oscillator for * source - * PLL0CLK = (10 * SYSCLK) / 1 = 120MHz -> PLL0 multipler=10, pre-divider=1 + * PLL0CLK = (10 * SYSCLK) / 1 = 120MHz -> PLL0 multiplier=10, pre-divider=1 * CCLCK = 120MHz -> CCLK divider = 1 */ diff --git a/boards/arm/lpc17xx_40xx/lpcxpresso-lpc1768/include/board.h b/boards/arm/lpc17xx_40xx/lpcxpresso-lpc1768/include/board.h index 1d847d886e..dd659f7067 100644 --- a/boards/arm/lpc17xx_40xx/lpcxpresso-lpc1768/include/board.h +++ b/boards/arm/lpc17xx_40xx/lpcxpresso-lpc1768/include/board.h @@ -50,7 +50,7 @@ * * SYSCLK = BOARD_OSCCLK_FREQUENCY = 12MHz -> Select Main oscillator for * source - * PLL0CLK = (2 * 20 * SYSCLK) / 1 = 480MHz -> PLL0 multipler=20, + * PLL0CLK = (2 * 20 * SYSCLK) / 1 = 480MHz -> PLL0 multiplier=20, * pre-divider=1 * CCLCK = 480MHz / 6 = 80MHz -> CCLK divider = 6 */ diff --git a/boards/arm/lpc17xx_40xx/lx_cpu/include/board.h b/boards/arm/lpc17xx_40xx/lx_cpu/include/board.h index 13009d2e58..24e7a4cc74 100644 --- a/boards/arm/lpc17xx_40xx/lx_cpu/include/board.h +++ b/boards/arm/lpc17xx_40xx/lx_cpu/include/board.h @@ -57,7 +57,8 @@ * * SYSCLK = BOARD_OSCCLK_FREQUENCY = 12MHz -> Select Main oscillator for * source - * PLL0CLK = (12 * SYSCLK) / 1 = 144MHz -> PLL0 multipler=12, pre-divider=1 + * PLL0CLK = (12 * SYSCLK) / 1 = 144MHz -> PLL0 multiplier=12, + * pre-divider=1 * CCLCK = 72MHz -> CCLK divider = 2 */ diff --git a/boards/arm/lpc17xx_40xx/olimex-lpc1766stk/include/board.h b/boards/arm/lpc17xx_40xx/olimex-lpc1766stk/include/board.h index a2190cff18..84d4082e1c 100644 --- a/boards/arm/lpc17xx_40xx/olimex-lpc1766stk/include/board.h +++ b/boards/arm/lpc17xx_40xx/olimex-lpc1766stk/include/board.h @@ -55,7 +55,7 @@ * * SYSCLK = BOARD_OSCCLK_FREQUENCY = 12MHz -> Select Main oscillator for * source - * PLL0CLK = (2 * 20 * SYSCLK) / 1 = 480MHz -> PLL0 multipler=20, + * PLL0CLK = (2 * 20 * SYSCLK) / 1 = 480MHz -> PLL0 multiplier=20, * pre-divider=1 * CCLCK = 480MHz / 6 = 80MHz -> CCLK divider = 6 */ diff --git a/boards/arm/lpc17xx_40xx/open1788/include/board.h b/boards/arm/lpc17xx_40xx/open1788/include/board.h index 616f19151c..1531503541 100644 --- a/boards/arm/lpc17xx_40xx/open1788/include/board.h +++ b/boards/arm/lpc17xx_40xx/open1788/include/board.h @@ -57,7 +57,7 @@ * * SYSCLK = BOARD_OSCCLK_FREQUENCY = 12MHz -> Select Main oscillator for * source - * PLL0CLK = (10 * SYSCLK) / 1 = 120MHz -> PLL0 multipler=10, + * PLL0CLK = (10 * SYSCLK) / 1 = 120MHz -> PLL0 multiplier=10, * pre-divider=1 * CCLCK = 120MHz -> CCLK divider = 1 */ diff --git a/boards/arm/lpc17xx_40xx/pnev5180b/include/board.h b/boards/arm/lpc17xx_40xx/pnev5180b/include/board.h index fc737745b9..61c0e0fc8c 100644 --- a/boards/arm/lpc17xx_40xx/pnev5180b/include/board.h +++ b/boards/arm/lpc17xx_40xx/pnev5180b/include/board.h @@ -55,7 +55,7 @@ * * SYSCLK = BOARD_OSCCLK_FREQUENCY = 12MHz -> Select Main oscillator for * source - * PLL0CLK = (2 * 20 * SYSCLK) / 1 = 480MHz -> PLL0 multipler=20, + * PLL0CLK = (2 * 20 * SYSCLK) / 1 = 480MHz -> PLL0 multiplier=20, * pre-divider=1 * CCLCK = 480MHz / 4 = 120MHz -> CCLK divider = 4 */ diff --git a/boards/arm/lpc17xx_40xx/u-blox-c027/include/board.h b/boards/arm/lpc17xx_40xx/u-blox-c027/include/board.h index a3c2111c35..e7eead719d 100644 --- a/boards/arm/lpc17xx_40xx/u-blox-c027/include/board.h +++ b/boards/arm/lpc17xx_40xx/u-blox-c027/include/board.h @@ -65,7 +65,7 @@ * SYSCLK = BOARD_OSCCLK_FREQUENCY = 12MHz -> * Select Main oscillator for source * PLL0CLK = (2 * 20 * SYSCLK) / 1 = 480MHz -> - * PLL0 multipler=20, pre-divider=1 + * PLL0 multiplier=20, pre-divider=1 * CCLCK = 480MHz / 6 = 80MHz -> CCLK divider = 6 */ diff --git a/boards/arm/lpc17xx_40xx/zkit-arm-1769/include/board.h b/boards/arm/lpc17xx_40xx/zkit-arm-1769/include/board.h index 30f5e27a6e..15047ec472 100644 --- a/boards/arm/lpc17xx_40xx/zkit-arm-1769/include/board.h +++ b/boards/arm/lpc17xx_40xx/zkit-arm-1769/include/board.h @@ -56,7 +56,7 @@ * SYSCLK = BOARD_OSCCLK_FREQUENCY = 12MHz -> * Select Main oscillator for source * PLL0CLK = (2 * 20 * SYSCLK) / 1 = 480MHz -> - * PLL0 multipler=20, pre-divider=1 + * PLL0 multiplier=20, pre-divider=1 * CCLCK = 480MHz / 6 = 80MHz -> CCLK divider = 6 */ diff --git a/boards/arm/lpc214x/mcu123-lpc214x/src/lpc2148_composite.c b/boards/arm/lpc214x/mcu123-lpc214x/src/lpc2148_composite.c index ff45f1a003..3c871e6b60 100644 --- a/boards/arm/lpc214x/mcu123-lpc214x/src/lpc2148_composite.c +++ b/boards/arm/lpc214x/mcu123-lpc214x/src/lpc2148_composite.c @@ -144,7 +144,7 @@ static int board_mscclassobject(int minor, * form the composite device logic. * * Input Parameters: - * classdev - The class driver instrance previously give to the composite + * classdev - The class driver instance previously given to the composite * driver by board_mscclassobject(). * * Returned Value: diff --git a/boards/arm/lpc31xx/ea3131/src/ea3131.h b/boards/arm/lpc31xx/ea3131/src/ea3131.h index f6a581ce51..1c72275d98 100644 --- a/boards/arm/lpc31xx/ea3131/src/ea3131.h +++ b/boards/arm/lpc31xx/ea3131/src/ea3131.h @@ -103,7 +103,7 @@ void weak_function lpc31_usbdev_initialize(void); * Name: lpc31_usbhost_bootinitialize * * Description: - * Called from lpc31_boardinitialize very early in inialization to setup + * Called from lpc31_boardinitialize very early in initialization to setup * USB host-related GPIO pins for the EA3131 board. * ****************************************************************************/ diff --git a/boards/arm/lpc31xx/ea3131/src/lpc31_usbhost.c b/boards/arm/lpc31xx/ea3131/src/lpc31_usbhost.c index 2c2527d10e..102ad056b1 100644 --- a/boards/arm/lpc31xx/ea3131/src/lpc31_usbhost.c +++ b/boards/arm/lpc31xx/ea3131/src/lpc31_usbhost.c @@ -118,7 +118,7 @@ static int ehci_waiter(int argc, char *argv[]) * Name: lpc31_usbhost_bootinitialize * * Description: - * Called from lpc31_boardinitialize very early in inialization to setup + * Called from lpc31_boardinitialize very early in initialization to setup * USB host-related GPIO pins for the EA3131 board. * * USB host VBUS power is controlled by a Micrel USB power switch. diff --git a/boards/arm/lpc31xx/ea3131/tools/lpchdr.c b/boards/arm/lpc31xx/ea3131/tools/lpchdr.c index 9fef74cacf..a581ffe96d 100644 --- a/boards/arm/lpc31xx/ea3131/tools/lpchdr.c +++ b/boards/arm/lpc31xx/ea3131/tools/lpchdr.c @@ -73,7 +73,7 @@ static void parse_args(int argc, char **argv) break; case ':': - fprintf(stderr, "Missing option argumen\n"); + fprintf(stderr, "Missing option argument\n"); show_usage(argv[0], 1); case '?': diff --git a/boards/arm/lpc31xx/ea3131/tools/lpchdr.h b/boards/arm/lpc31xx/ea3131/tools/lpchdr.h index 8c74757d7d..2604ddc82e 100644 --- a/boards/arm/lpc31xx/ea3131/tools/lpchdr.h +++ b/boards/arm/lpc31xx/ea3131/tools/lpchdr.h @@ -67,7 +67,7 @@ struct lpc31_header_s * image is built. Note, this field is not used * by boot ROM but is provided to track the image * versions. */ - uint32_t sbzbootparameter; /* 0x2c hould be zero. */ + uint32_t sbzbootparameter; /* 0x2c Should be zero. */ uint32_t cust_reserved[15]; /* 0x30-0x68: Reserved for customer use (60 bytes) */ uint32_t header_crc32; /* 0x6c CRC32 value of the header (bytes 0x00 to 0x6C * of the image). If the 'image_type' is set diff --git a/boards/arm/lpc31xx/ea3152/tools/lpchdr.c b/boards/arm/lpc31xx/ea3152/tools/lpchdr.c index 0887f3325a..05abb55c40 100644 --- a/boards/arm/lpc31xx/ea3152/tools/lpchdr.c +++ b/boards/arm/lpc31xx/ea3152/tools/lpchdr.c @@ -73,7 +73,7 @@ static void parse_args(int argc, char **argv) break; case ':': - fprintf(stderr, "Missing option argumen\n"); + fprintf(stderr, "Missing option argument\n"); show_usage(argv[0], 1); case '?': diff --git a/boards/arm/lpc31xx/ea3152/tools/lpchdr.h b/boards/arm/lpc31xx/ea3152/tools/lpchdr.h index cd7fd78f2c..57e7007847 100644 --- a/boards/arm/lpc31xx/ea3152/tools/lpchdr.h +++ b/boards/arm/lpc31xx/ea3152/tools/lpchdr.h @@ -78,7 +78,7 @@ struct lpc31_header_s * not used by boot ROM but is provided to * track the image versions. */ - uint32_t sbzbootparameter; /* 0x2c hould be zero. */ + uint32_t sbzbootparameter; /* 0x2c Should be zero. */ uint32_t cust_reserved[15]; /* 0x30-0x68: Reserved for customer use * (60 bytes) */ diff --git a/boards/arm/lpc31xx/olimex-lpc-h3131/src/lpc31_usbhost.c b/boards/arm/lpc31xx/olimex-lpc-h3131/src/lpc31_usbhost.c index b3e3632b0e..9fd5939b46 100644 --- a/boards/arm/lpc31xx/olimex-lpc-h3131/src/lpc31_usbhost.c +++ b/boards/arm/lpc31xx/olimex-lpc-h3131/src/lpc31_usbhost.c @@ -124,7 +124,7 @@ static int ehci_waiter(int argc, char *argv[]) * Name: lpc31_usbhost_bootinitialize * * Description: - * Called from lpc31_boardinitialize very early in inialization to setup + * Called from lpc31_boardinitialize very early in initialization to setup * USB host-related GPIO pins for the LPC-H3131 board. * * SIGNAL GPIO diff --git a/boards/arm/lpc31xx/olimex-lpc-h3131/src/lpc_h3131.h b/boards/arm/lpc31xx/olimex-lpc-h3131/src/lpc_h3131.h index faacabe094..0aab4d691c 100644 --- a/boards/arm/lpc31xx/olimex-lpc-h3131/src/lpc_h3131.h +++ b/boards/arm/lpc31xx/olimex-lpc-h3131/src/lpc_h3131.h @@ -168,7 +168,7 @@ void weak_function lpc31_usbdev_initialize(void); * Name: lpc31_usbhost_bootinitialize * * Description: - * Called from lpc31_boardinitialize very early in inialization to setup + * Called from lpc31_boardinitialize very early in initialization to setup * USB host-related GPIO pins for the LPC-H3131 board. * ****************************************************************************/ diff --git a/boards/arm/lpc31xx/olimex-lpc-h3131/tools/lpchdr.c b/boards/arm/lpc31xx/olimex-lpc-h3131/tools/lpchdr.c index c772211e31..df08faa31b 100644 --- a/boards/arm/lpc31xx/olimex-lpc-h3131/tools/lpchdr.c +++ b/boards/arm/lpc31xx/olimex-lpc-h3131/tools/lpchdr.c @@ -73,7 +73,7 @@ static void parse_args(int argc, char **argv) break; case ':': - fprintf(stderr, "Missing option argumen\n"); + fprintf(stderr, "Missing option argument\n"); show_usage(argv[0], 1); case '?': diff --git a/boards/arm/lpc31xx/olimex-lpc-h3131/tools/lpchdr.h b/boards/arm/lpc31xx/olimex-lpc-h3131/tools/lpchdr.h index 12582f2f50..86c534cd05 100644 --- a/boards/arm/lpc31xx/olimex-lpc-h3131/tools/lpchdr.h +++ b/boards/arm/lpc31xx/olimex-lpc-h3131/tools/lpchdr.h @@ -67,7 +67,7 @@ struct lpc31_header_s * image is built. Note, this field is not used * by boot ROM but is provided to track the image * versions. */ - uint32_t sbzbootparameter; /* 0x2c hould be zero. */ + uint32_t sbzbootparameter; /* 0x2c Should be zero. */ uint32_t cust_reserved[15]; /* 0x30-0x68: Reserved for customer use (60 bytes) */ uint32_t header_crc32; /* 0x6c CRC32 value of the header (bytes 0x00 to 0x6C * of the image). If the 'image_type' is set diff --git a/boards/arm/lpc43xx/bambino-200e/include/board.h b/boards/arm/lpc43xx/bambino-200e/include/board.h index 2588726a29..b89d63cb6a 100644 --- a/boards/arm/lpc43xx/bambino-200e/include/board.h +++ b/boards/arm/lpc43xx/bambino-200e/include/board.h @@ -133,7 +133,7 @@ /* This is the clock setup we configure for: * * SYSCLK = BOARD_OSCCLK_FREQUENCY = 12MHz -> Main oscillator for source - * PLL0CLK = (2 * 20 * SYSCLK) / 1 = 480MHz -> multipler=20, pre-divider=1 + * PLL0CLK = (2 * 20 * SYSCLK) / 1 = 480MHz -> multiplier=20, pre-divider=1 * CCLCK = 480MHz / 6 = 80MHz -> divider = 6 */ diff --git a/boards/arm/lpc43xx/lpc4330-xplorer/include/board.h b/boards/arm/lpc43xx/lpc4330-xplorer/include/board.h index 0465f49f98..cb2b033aa1 100644 --- a/boards/arm/lpc43xx/lpc4330-xplorer/include/board.h +++ b/boards/arm/lpc43xx/lpc4330-xplorer/include/board.h @@ -132,7 +132,7 @@ /* This is the clock setup we configure for: * * SYSCLK = BOARD_OSCCLK_FREQUENCY = 12MHz -> Main oscillator for source - * PLL0CLK = (2 * 20 * SYSCLK) / 1 = 480MHz -> multipler=20, pre-divider=1 + * PLL0CLK = (2 * 20 * SYSCLK) / 1 = 480MHz -> multiplier=20, pre-divider=1 * CCLCK = 480MHz / 6 = 80MHz -> divider = 6 */ diff --git a/boards/arm/lpc43xx/lpc4357-evb/include/board.h b/boards/arm/lpc43xx/lpc4357-evb/include/board.h index ac234d2857..cb95a68423 100644 --- a/boards/arm/lpc43xx/lpc4357-evb/include/board.h +++ b/boards/arm/lpc43xx/lpc4357-evb/include/board.h @@ -132,7 +132,7 @@ /* This is the clock setup we configure for: * * SYSCLK = BOARD_OSCCLK_FREQUENCY = 12MHz -> Main oscillator for source - * PLL0CLK = (2 * 20 * SYSCLK) / 1 = 480MHz-> multipler=20, pre-divider=1 + * PLL0CLK = (2 * 20 * SYSCLK) / 1 = 480MHz-> multiplier=20, pre-divider=1 * CCLCK = 480MHz / 6 = 80MHz -> divider = 6 */ diff --git a/boards/arm/lpc54xx/lpcxpresso-lpc54628/src/lpc54_sdram.c b/boards/arm/lpc54xx/lpcxpresso-lpc54628/src/lpc54_sdram.c index e4739e19a3..56c559a62d 100644 --- a/boards/arm/lpc54xx/lpcxpresso-lpc54628/src/lpc54_sdram.c +++ b/boards/arm/lpc54xx/lpcxpresso-lpc54628/src/lpc54_sdram.c @@ -141,7 +141,7 @@ void lpc54_sdram_initialize(void) lpc54_gpio_config(g_emc_pinset[i]); } - /* EMC Dynamc memory configuration. */ + /* EMC Dynamic memory configuration. */ lpc54_emc_sdram_initialize(&g_emc_dynconfig, &g_emc_dynchipconfig, 1); } diff --git a/boards/arm/moxart/moxa/include/board.h b/boards/arm/moxart/moxa/include/board.h index c3c411de4b..3475e3caa1 100644 --- a/boards/arm/moxart/moxa/include/board.h +++ b/boards/arm/moxart/moxa/include/board.h @@ -64,7 +64,7 @@ /* PLLA configuration. * * Divider = 1 - * Multipler = 14 + * Multiplier = 14 */ #define BOARD_CKGR_PLLAR_MUL (13 << PMC_CKGR_PLLAR_MUL_SHIFT) diff --git a/boards/arm/nrf52/common/src/nrf52_ieee802154.c b/boards/arm/nrf52/common/src/nrf52_ieee802154.c index e6bc68966b..2545d26d74 100644 --- a/boards/arm/nrf52/common/src/nrf52_ieee802154.c +++ b/boards/arm/nrf52/common/src/nrf52_ieee802154.c @@ -75,7 +75,7 @@ int nrf52_ieee802154_initialize(void) #ifdef CONFIG_IEEE802154_NETDEV /* Use the IEEE802.15.4 MAC interface instance to create a 6LoWPAN - * network interface by wrapping the MAC intrface instance in a + * network interface by wrapping the MAC interface instance in a * network device driver via mac802154dev_register(). */ diff --git a/boards/arm/nrf52/common/src/nrf52_mrf24j40.c b/boards/arm/nrf52/common/src/nrf52_mrf24j40.c index fefa8160d2..79a18e7b7b 100644 --- a/boards/arm/nrf52/common/src/nrf52_mrf24j40.c +++ b/boards/arm/nrf52/common/src/nrf52_mrf24j40.c @@ -106,7 +106,7 @@ int nrf52_mrf24j40_devsetup(struct nrf52_mrf24j40_s *priv) #ifdef CONFIG_IEEE802154_NETDEV /* Use the IEEE802.15.4 MAC interface instance to create a 6LoWPAN - * network interface by wrapping the MAC intrface instance in a + * network interface by wrapping the MAC interface instance in a * network device driver via mac802154dev_register(). */ diff --git a/boards/arm/nrf52/nrf52840-dk/src/nrf52840-dk.h b/boards/arm/nrf52/nrf52840-dk/src/nrf52840-dk.h index 35845e55db..8d932f5235 100644 --- a/boards/arm/nrf52/nrf52840-dk/src/nrf52840-dk.h +++ b/boards/arm/nrf52/nrf52840-dk/src/nrf52840-dk.h @@ -195,7 +195,7 @@ int nrf52_adc_setup(void); * Name: nrf52_mx25_initialize * * Description: - * Initialize the MX25RXX QSPI memeory + * Initialize the MX25RXX QSPI memory * ****************************************************************************/ diff --git a/boards/arm/nrf52/nrf52840-dk/src/nrf52_adc.c b/boards/arm/nrf52/nrf52840-dk/src/nrf52_adc.c index 019986e996..2a02a5cf86 100644 --- a/boards/arm/nrf52/nrf52840-dk/src/nrf52_adc.c +++ b/boards/arm/nrf52/nrf52840-dk/src/nrf52_adc.c @@ -40,7 +40,7 @@ * Pre-processor Definitions ****************************************************************************/ -/* Only one channel supported if TIMER triger enabled */ +/* Only one channel supported if TIMER trigger enabled */ #ifdef CONFIG_NRF52_SAADC_TIMER # define ADC_NCHANNELS (1) diff --git a/boards/arm/nrf52/nrf52840-dk/src/nrf52_mx25.c b/boards/arm/nrf52/nrf52840-dk/src/nrf52_mx25.c index 09372d0595..f7dcc7f09a 100644 --- a/boards/arm/nrf52/nrf52840-dk/src/nrf52_mx25.c +++ b/boards/arm/nrf52/nrf52840-dk/src/nrf52_mx25.c @@ -44,7 +44,7 @@ * Name: nrf52_mx25_initialize * * Description: - * Initialize the MX25RXX QSPI memeory + * Initialize the MX25RXX QSPI memory * ****************************************************************************/ diff --git a/boards/arm/nrf53/nrf5340-dk/src/nrf5340-dk.h b/boards/arm/nrf53/nrf5340-dk/src/nrf5340-dk.h index a687d952a6..8a714b4007 100644 --- a/boards/arm/nrf53/nrf5340-dk/src/nrf5340-dk.h +++ b/boards/arm/nrf53/nrf5340-dk/src/nrf5340-dk.h @@ -141,7 +141,7 @@ int nrf53_adc_setup(void); * Name: nrf53_mx25_initialize * * Description: - * Initialize the MX25RXX QSPI memeory + * Initialize the MX25RXX QSPI memory * ****************************************************************************/ diff --git a/boards/arm/nrf53/nrf5340-dk/src/nrf53_adc.c b/boards/arm/nrf53/nrf5340-dk/src/nrf53_adc.c index ef1b264fb3..db0c813bee 100644 --- a/boards/arm/nrf53/nrf5340-dk/src/nrf53_adc.c +++ b/boards/arm/nrf53/nrf5340-dk/src/nrf53_adc.c @@ -40,7 +40,7 @@ * Pre-processor Definitions ****************************************************************************/ -/* Only one channel supported if TIMER triger enabled */ +/* Only one channel supported if TIMER trigger enabled */ #ifdef CONFIG_NRF53_SAADC_TIMER # define ADC_NCHANNELS (1) diff --git a/boards/arm/nrf53/nrf5340-dk/src/nrf53_mx25.c b/boards/arm/nrf53/nrf5340-dk/src/nrf53_mx25.c index bb6e1b66c6..8f961ca57c 100644 --- a/boards/arm/nrf53/nrf5340-dk/src/nrf53_mx25.c +++ b/boards/arm/nrf53/nrf5340-dk/src/nrf53_mx25.c @@ -44,7 +44,7 @@ * Name: nrf53_mx25_initialize * * Description: - * Initialize the MX25RXX QSPI memeory + * Initialize the MX25RXX QSPI memory * ****************************************************************************/ diff --git a/boards/arm/nuc1xx/nutiny-nuc120/src/nuc_boardinitialize.c b/boards/arm/nuc1xx/nutiny-nuc120/src/nuc_boardinitialize.c index f46b4b8d74..ff5aec826f 100644 --- a/boards/arm/nuc1xx/nutiny-nuc120/src/nuc_boardinitialize.c +++ b/boards/arm/nuc1xx/nutiny-nuc120/src/nuc_boardinitialize.c @@ -72,7 +72,7 @@ void nuc_boardinitialize(void) /* Initialize USB if the 1) USB device controller is in the configuration * and 2) disabled, and 3) the weak function nuc_usbinitialize() has been * brought into the build. - * Presumeably either CONFIG_USBDEV is also selected. + * Presumably either CONFIG_USBDEV is also selected. */ #ifdef CONFIG_NUC1XX_USB diff --git a/boards/arm/nuc1xx/nutiny-nuc120/src/nutiny-nuc120.h b/boards/arm/nuc1xx/nutiny-nuc120/src/nutiny-nuc120.h index 1aa18aa9e4..38f36dda1a 100644 --- a/boards/arm/nuc1xx/nutiny-nuc120/src/nutiny-nuc120.h +++ b/boards/arm/nuc1xx/nutiny-nuc120/src/nutiny-nuc120.h @@ -97,7 +97,7 @@ void weak_function nuc_spidev_initialize(void); * Name: nuc_usbinitialize * * Description: - * Called from nuc_usbinitialize very early in inialization to setup + * Called from nuc_usbinitialize very early in initialization to setup * USB-related GPIO pins for the NuTiny-EVB-120 board. * ****************************************************************************/ diff --git a/boards/arm/rp2040/common/src/rp2040_composite.c b/boards/arm/rp2040/common/src/rp2040_composite.c index 9ad2a7adfa..446470d3a1 100644 --- a/boards/arm/rp2040/common/src/rp2040_composite.c +++ b/boards/arm/rp2040/common/src/rp2040_composite.c @@ -128,7 +128,7 @@ static int board_mscclassobject(int minor, * that is called form the composite device logic. * * Input Parameters: - * classdev - The class driver instrance previously give to the composite + * classdev - The class driver instance previously given to the composite * driver by board_mscclassobject(). * * Returned Value: diff --git a/boards/arm/rp2040/common/src/rp2040_firmware.c b/boards/arm/rp2040/common/src/rp2040_firmware.c index 3aa0ac477b..ba981bf67d 100644 --- a/boards/arm/rp2040/common/src/rp2040_firmware.c +++ b/boards/arm/rp2040/common/src/rp2040_firmware.c @@ -109,7 +109,7 @@ const unsigned int g_cyw43439_nvram_len = sizeof(g_cyw43439_nvram_image); /* These are defined as array because the symbols name an actual address * not a pointer to an address. This is not one of the many cases where - * pointers and arrays are interchangable in C. + * pointers and arrays are interchangeable in C. */ extern const uint8_t g_cyw43439_firmware_image[]; @@ -122,7 +122,7 @@ extern const unsigned int g_cyw43439_clm_blob_len; * - Copies the firmware image file data to that location. * - Defines g_cyw43439_firmware_end as the location directly beyond * that data. - * - Defines g_cyw43439_clm_blob_image as a location withing that + * - Defines g_cyw43439_clm_blob_image as a location within that * data where the clm_blob begins. * - Force 4-byte alignment * - Allocates an integer named g_cyw43439_clm_blob_len that diff --git a/boards/arm/rp2040/common/src/rp2040_uniqueid.c b/boards/arm/rp2040/common/src/rp2040_uniqueid.c index 78e213f454..18093272bc 100644 --- a/boards/arm/rp2040/common/src/rp2040_uniqueid.c +++ b/boards/arm/rp2040/common/src/rp2040_uniqueid.c @@ -331,7 +331,7 @@ void rp2040_uniqueid_initialize(void) * length. * * Returned Value: - * Zero (OK) is returned on success. Otherwize a negated errno value is + * Zero (OK) is returned on success. Otherwise a negated errno value is * returned indicating the nature of the failure. * ****************************************************************************/ diff --git a/boards/arm/rp2040/w5500-evb-pico/include/board.h b/boards/arm/rp2040/w5500-evb-pico/include/board.h index 4f1ecc318b..788c31fd27 100644 --- a/boards/arm/rp2040/w5500-evb-pico/include/board.h +++ b/boards/arm/rp2040/w5500-evb-pico/include/board.h @@ -150,7 +150,7 @@ extern "C" * Description: * This is mostly a wrapper around the early board initialization code * common to all boards based on the RP2040. This implementation does - * additionaly set the board's status LED. + * additionally set the board's status LED. * ****************************************************************************/ diff --git a/boards/arm/rp23xx/common/src/rp23xx_composite.c b/boards/arm/rp23xx/common/src/rp23xx_composite.c index 34baf05c20..116d1c20aa 100644 --- a/boards/arm/rp23xx/common/src/rp23xx_composite.c +++ b/boards/arm/rp23xx/common/src/rp23xx_composite.c @@ -126,7 +126,7 @@ static int board_mscclassobject(int minor, * that is called form the composite device logic. * * Input Parameters: - * classdev - The class driver instrance previously give to the composite + * classdev - The class driver instance previously given to the composite * driver by board_mscclassobject(). * * Returned Value: diff --git a/boards/arm/rp23xx/common/src/rp23xx_uniqueid.c b/boards/arm/rp23xx/common/src/rp23xx_uniqueid.c index afc8d6f315..0089de7716 100644 --- a/boards/arm/rp23xx/common/src/rp23xx_uniqueid.c +++ b/boards/arm/rp23xx/common/src/rp23xx_uniqueid.c @@ -129,7 +129,7 @@ void rp23xx_uniqueid_initialize(void) * length. * * Returned Value: - * Zero (OK) is returned on success. Otherwize a negated errno value is + * Zero (OK) is returned on success. Otherwise a negated errno value is * returned indicating the nature of the failure. * ****************************************************************************/ diff --git a/boards/arm/s32k1xx/rddrone-bms772/src/s32k1xx_smbus_sbd.c b/boards/arm/s32k1xx/rddrone-bms772/src/s32k1xx_smbus_sbd.c index 41eaa523d1..742421a298 100644 --- a/boards/arm/s32k1xx/rddrone-bms772/src/s32k1xx_smbus_sbd.c +++ b/boards/arm/s32k1xx/rddrone-bms772/src/s32k1xx_smbus_sbd.c @@ -723,7 +723,7 @@ static int smbus_sbd_callback(void *arg, i2c_slave_complete_t state, } /* Install the (re)filled write buffer. Technically this buffer needs to - * be constant, but we want to be able to re-use the same buffer for the + * be constant, but we want to be able to reuse the same buffer for the * next request, so we just cast the buffer to const. This should not * cause any problems, because the write buffer is only changed when the * I2C slave driver invokes this callback, which only happens when a new diff --git a/boards/arm/s32k3xx/mr-canhubk3/src/s32k3xx_bringup.c b/boards/arm/s32k3xx/mr-canhubk3/src/s32k3xx_bringup.c index 3451e088cb..d309eefb00 100644 --- a/boards/arm/s32k3xx/mr-canhubk3/src/s32k3xx_bringup.c +++ b/boards/arm/s32k3xx/mr-canhubk3/src/s32k3xx_bringup.c @@ -183,7 +183,7 @@ int s32k3xx_bringup(void) # ifdef CONFIG_FS_LITTLEFS else { - _info("register_mtddriver() succesful\n"); + _info("register_mtddriver() successful\n"); ret = nx_mount("/dev/progmem0", "/mnt/progmem", "littlefs", 0, NULL); @@ -198,7 +198,7 @@ int s32k3xx_bringup(void) } else { - _info("nx_mount() succesful\n"); + _info("nx_mount() successful\n"); } } } diff --git a/boards/arm/sam34/arduino-due/include/board.h b/boards/arm/sam34/arduino-due/include/board.h index 6db95df42b..ae024b21e9 100644 --- a/boards/arm/sam34/arduino-due/include/board.h +++ b/boards/arm/sam34/arduino-due/include/board.h @@ -67,7 +67,7 @@ /* PLLA configuration. * * Divider = 1 - * Multipler = 14 + * Multiplier = 14 */ #define BOARD_CKGR_PLLAR_MUL (13 << PMC_CKGR_PLLAR_MUL_SHIFT) @@ -209,7 +209,7 @@ * That problem was resolved as follows: * * "... The issue was in my hardware. I found the difference between Arduino - * Due shematics (revision R2) and actual PCB layout of my Arduino + * Due schematics (revision R2) and actual PCB layout of my Arduino * (revision R3). * On a schematics which I download from arduino.cc was shown that 2nd * pin of IC10 is connected to the ground, but on my Arduino the 2nd pin diff --git a/boards/arm/sam34/sam3u-ek/include/board.h b/boards/arm/sam34/sam3u-ek/include/board.h index 9794b3e9db..21f2bdc6a8 100644 --- a/boards/arm/sam34/sam3u-ek/include/board.h +++ b/boards/arm/sam34/sam3u-ek/include/board.h @@ -63,7 +63,7 @@ /* PLLA configuration. * * Divider = 1 - * Multipler = 16 + * Multiplier = 16 */ #define BOARD_CKGR_PLLAR_MUL (15 << PMC_CKGR_PLLAR_MUL_SHIFT) diff --git a/boards/arm/sama5/giant-board/src/sam_boot.c b/boards/arm/sama5/giant-board/src/sam_boot.c index 407447b85f..4a5548bbf2 100644 --- a/boards/arm/sama5/giant-board/src/sam_boot.c +++ b/boards/arm/sama5/giant-board/src/sam_boot.c @@ -52,7 +52,7 @@ void sam_boardinitialize(void) /* Initialize USB if the 1) the HS host or device controller is in the * configuration and 2) the weak function sam_usbinitialize() has been * brought into the build. - * Presumeably either CONFIG_USBDEV or CONFIG_USBHOST is also selected. + * Presumably either CONFIG_USBDEV or CONFIG_USBHOST is also selected. */ #if defined(CONFIG_SAMA5_UHPHS) || defined(CONFIG_SAMA5_UDPHS) diff --git a/boards/arm/sama5/giant-board/src/sam_sdram.c b/boards/arm/sama5/giant-board/src/sam_sdram.c index 95a64c491e..56119b5b90 100644 --- a/boards/arm/sama5/giant-board/src/sam_sdram.c +++ b/boards/arm/sama5/giant-board/src/sam_sdram.c @@ -244,7 +244,7 @@ void sam_sdram_config(void) MPDDRC_CR_OCD_EXIT | /* Off-chip Driver */ MPDDRC_CR_8BANKS | /* Number of Banks */ MPDDRC_CR_NDQS | /* Not DQS */ - MPDDRC_CR_UNAL; /* upport Unaligned Access */ + MPDDRC_CR_UNAL; /* support Unaligned Access */ #else # error Unknown SDRAM type diff --git a/boards/arm/sama5/giant-board/src/sam_usb.c b/boards/arm/sama5/giant-board/src/sam_usb.c index 79f1aec694..333b0bb8e2 100644 --- a/boards/arm/sama5/giant-board/src/sam_usb.c +++ b/boards/arm/sama5/giant-board/src/sam_usb.c @@ -175,7 +175,7 @@ static int ehci_waiter(int argc, char *argv[]) * Name: sam_usbinitialize * * Description: - * Called from sam_usbinitialize very early in inialization to setup + * Called from sam_usbinitialize very early in initialization to setup * USB-related GPIO pins for the SAMA5D3-Xplained board. * * USB Ports diff --git a/boards/arm/sama5/jupiter-nano/include/board_384mhz.h b/boards/arm/sama5/jupiter-nano/include/board_384mhz.h index 26fd0de611..be57e481dc 100644 --- a/boards/arm/sama5/jupiter-nano/include/board_384mhz.h +++ b/boards/arm/sama5/jupiter-nano/include/board_384mhz.h @@ -61,7 +61,7 @@ /* PLLA configuration. * - * Multipler = 64: PLLACK = 64 * 12MHz = 768MHz + * Multiplier = 64: PLLACK = 64 * 12MHz = 768MHz */ #define BOARD_CKGR_PLLAR_COUNT (63 << PMC_CKGR_PLLAR_COUNT_SHIFT) diff --git a/boards/arm/sama5/jupiter-nano/include/board_396mhz.h b/boards/arm/sama5/jupiter-nano/include/board_396mhz.h index 29fe39907e..067ee5959b 100644 --- a/boards/arm/sama5/jupiter-nano/include/board_396mhz.h +++ b/boards/arm/sama5/jupiter-nano/include/board_396mhz.h @@ -58,7 +58,7 @@ /* PLLA configuration. * - * Multipler = 66: PLLACK = 66 * 12MHz = 792MHz + * Multiplier = 66: PLLACK = 66 * 12MHz = 792MHz */ #define BOARD_CKGR_PLLAR_COUNT (63 << PMC_CKGR_PLLAR_COUNT_SHIFT) diff --git a/boards/arm/sama5/jupiter-nano/include/board_498mhz.h b/boards/arm/sama5/jupiter-nano/include/board_498mhz.h index 074a052810..56ffa7920c 100644 --- a/boards/arm/sama5/jupiter-nano/include/board_498mhz.h +++ b/boards/arm/sama5/jupiter-nano/include/board_498mhz.h @@ -57,7 +57,7 @@ /* PLLA configuration. * - * Multipler = 43+1: PLLACK = 44 * 12MHz = 498MHz + * Multiplier = 43+1: PLLACK = 44 * 12MHz = 498MHz */ #define BOARD_CKGR_PLLAR_COUNT (63 << PMC_CKGR_PLLAR_COUNT_SHIFT) diff --git a/boards/arm/sama5/jupiter-nano/include/board_528mhz.h b/boards/arm/sama5/jupiter-nano/include/board_528mhz.h index 320204500f..c14eadc9ae 100644 --- a/boards/arm/sama5/jupiter-nano/include/board_528mhz.h +++ b/boards/arm/sama5/jupiter-nano/include/board_528mhz.h @@ -57,7 +57,7 @@ /* PLLA configuration. * - * Multipler = 43+1: PLLACK = 44 * 12MHz = 528MHz + * Multiplier = 43+1: PLLACK = 44 * 12MHz = 528MHz */ #define BOARD_CKGR_PLLAR_COUNT (63 << PMC_CKGR_PLLAR_COUNT_SHIFT) diff --git a/boards/arm/sama5/jupiter-nano/src/sam_boot.c b/boards/arm/sama5/jupiter-nano/src/sam_boot.c index c128e47c96..96021ba6cb 100644 --- a/boards/arm/sama5/jupiter-nano/src/sam_boot.c +++ b/boards/arm/sama5/jupiter-nano/src/sam_boot.c @@ -60,7 +60,7 @@ void sam_boardinitialize(void) /* Initialize USB if the 1) the HS host or device controller is in the * configuration and 2) the weak function sam_usbinitialize() has been * brought into the build. - * Presumeably either CONFIG_USBDEV or CONFIG_USBHOST is also selected. + * Presumably either CONFIG_USBDEV or CONFIG_USBHOST is also selected. */ #if defined(CONFIG_SAMA5_UHPHS) || defined(CONFIG_SAMA5_UDPHS) diff --git a/boards/arm/sama5/jupiter-nano/src/sam_sdram.c b/boards/arm/sama5/jupiter-nano/src/sam_sdram.c index 15d3d26c4f..c141602ac1 100644 --- a/boards/arm/sama5/jupiter-nano/src/sam_sdram.c +++ b/boards/arm/sama5/jupiter-nano/src/sam_sdram.c @@ -258,7 +258,7 @@ void sam_sdram_config(void) MPDDRC_CR_OCD_EXIT | /* Off-chip Driver */ MPDDRC_CR_8BANKS | /* Number of Banks */ MPDDRC_CR_NDQS | /* Not DQS */ - MPDDRC_CR_UNAL; /* upport Unaligned Access */ + MPDDRC_CR_UNAL; /* support Unaligned Access */ #elif defined(CONFIG_SAMA5D3XPLAINED_MT47H64M16HR) /* For MT47H64M16HR @@ -285,7 +285,7 @@ void sam_sdram_config(void) MPDDRC_CR_OCD_EXIT | /* Off-chip Driver */ MPDDRC_CR_8BANKS | /* Number of Banks */ MPDDRC_CR_NDQS | /* Not DQS */ - MPDDRC_CR_UNAL; /* upport Unaligned Access */ + MPDDRC_CR_UNAL; /* support Unaligned Access */ #else # error Unknown SDRAM type diff --git a/boards/arm/sama5/jupiter-nano/src/sam_usb.c b/boards/arm/sama5/jupiter-nano/src/sam_usb.c index 1eeb6de55d..eab7886c9a 100644 --- a/boards/arm/sama5/jupiter-nano/src/sam_usb.c +++ b/boards/arm/sama5/jupiter-nano/src/sam_usb.c @@ -174,7 +174,7 @@ static int ehci_waiter(int argc, char *argv[]) * Name: sam_usbinitialize * * Description: - * Called from sam_usbinitialize very early in inialization to setup + * Called from sam_usbinitialize very early in initialization to setup * USB-related GPIO pins for the SAMA5D3-Xplained board. * * USB Ports diff --git a/boards/arm/sama5/sama5d2-xult/include/board_384mhz.h b/boards/arm/sama5/sama5d2-xult/include/board_384mhz.h index 60ffc21d6a..26ce756a60 100644 --- a/boards/arm/sama5/sama5d2-xult/include/board_384mhz.h +++ b/boards/arm/sama5/sama5d2-xult/include/board_384mhz.h @@ -61,7 +61,7 @@ /* PLLA configuration. * - * Multipler = 64: PLLACK = 64 * 12MHz = 768MHz + * Multiplier = 64: PLLACK = 64 * 12MHz = 768MHz */ #define BOARD_CKGR_PLLAR_COUNT (63 << PMC_CKGR_PLLAR_COUNT_SHIFT) diff --git a/boards/arm/sama5/sama5d2-xult/include/board_396mhz.h b/boards/arm/sama5/sama5d2-xult/include/board_396mhz.h index d6070cb1d6..ac89a719cf 100644 --- a/boards/arm/sama5/sama5d2-xult/include/board_396mhz.h +++ b/boards/arm/sama5/sama5d2-xult/include/board_396mhz.h @@ -58,7 +58,7 @@ /* PLLA configuration. * - * Multipler = 66: PLLACK = 66 * 12MHz = 792MHz + * Multiplier = 66: PLLACK = 66 * 12MHz = 792MHz */ #define BOARD_CKGR_PLLAR_COUNT (63 << PMC_CKGR_PLLAR_COUNT_SHIFT) diff --git a/boards/arm/sama5/sama5d2-xult/include/board_498mhz.h b/boards/arm/sama5/sama5d2-xult/include/board_498mhz.h index c0816e9096..08530306c4 100644 --- a/boards/arm/sama5/sama5d2-xult/include/board_498mhz.h +++ b/boards/arm/sama5/sama5d2-xult/include/board_498mhz.h @@ -57,7 +57,7 @@ /* PLLA configuration. * - * Multipler = 43+1: PLLACK = 44 * 12MHz = 498MHz + * Multiplier = 43+1: PLLACK = 44 * 12MHz = 498MHz */ #define BOARD_CKGR_PLLAR_COUNT (63 << PMC_CKGR_PLLAR_COUNT_SHIFT) diff --git a/boards/arm/sama5/sama5d2-xult/include/board_528mhz.h b/boards/arm/sama5/sama5d2-xult/include/board_528mhz.h index 0f721f1570..6a8b22014b 100644 --- a/boards/arm/sama5/sama5d2-xult/include/board_528mhz.h +++ b/boards/arm/sama5/sama5d2-xult/include/board_528mhz.h @@ -57,7 +57,7 @@ /* PLLA configuration. * - * Multipler = 43+1: PLLACK = 44 * 12MHz = 528MHz + * Multiplier = 43+1: PLLACK = 44 * 12MHz = 528MHz */ #define BOARD_CKGR_PLLAR_COUNT (63 << PMC_CKGR_PLLAR_COUNT_SHIFT) diff --git a/boards/arm/sama5/sama5d2-xult/src/sam_boot.c b/boards/arm/sama5/sama5d2-xult/src/sam_boot.c index f8679c4206..6287968a78 100644 --- a/boards/arm/sama5/sama5d2-xult/src/sam_boot.c +++ b/boards/arm/sama5/sama5d2-xult/src/sam_boot.c @@ -60,7 +60,7 @@ void sam_boardinitialize(void) /* Initialize USB if the 1) the HS host or device controller is in the * configuration and 2) the weak function sam_usbinitialize() has been * brought into the build. - * Presumeably either CONFIG_USBDEV or CONFIG_USBHOST is also selected. + * Presumably either CONFIG_USBDEV or CONFIG_USBHOST is also selected. */ #if defined(CONFIG_SAMA5_UHPHS) || defined(CONFIG_SAMA5_UDPHS) diff --git a/boards/arm/sama5/sama5d2-xult/src/sam_sdram.c b/boards/arm/sama5/sama5d2-xult/src/sam_sdram.c index 7d0c4f81f1..8ad5521a99 100644 --- a/boards/arm/sama5/sama5d2-xult/src/sam_sdram.c +++ b/boards/arm/sama5/sama5d2-xult/src/sam_sdram.c @@ -259,7 +259,7 @@ void sam_sdram_config(void) MPDDRC_CR_OCD_EXIT | /* Off-chip Driver */ MPDDRC_CR_8BANKS | /* Number of Banks */ MPDDRC_CR_NDQS | /* Not DQS */ - MPDDRC_CR_UNAL; /* upport Unaligned Access */ + MPDDRC_CR_UNAL; /* support Unaligned Access */ #elif defined(CONFIG_SAMA5D3XPLAINED_MT47H64M16HR) /* For MT47H64M16HR @@ -286,7 +286,7 @@ void sam_sdram_config(void) MPDDRC_CR_OCD_EXIT | /* Off-chip Driver */ MPDDRC_CR_8BANKS | /* Number of Banks */ MPDDRC_CR_NDQS | /* Not DQS */ - MPDDRC_CR_UNAL; /* upport Unaligned Access */ + MPDDRC_CR_UNAL; /* support Unaligned Access */ #else # error Unknown SDRAM type diff --git a/boards/arm/sama5/sama5d2-xult/src/sam_usb.c b/boards/arm/sama5/sama5d2-xult/src/sam_usb.c index 40b177d7f0..fe0b87d973 100644 --- a/boards/arm/sama5/sama5d2-xult/src/sam_usb.c +++ b/boards/arm/sama5/sama5d2-xult/src/sam_usb.c @@ -175,7 +175,7 @@ static int ehci_waiter(int argc, char *argv[]) * Name: sam_usbinitialize * * Description: - * Called from sam_usbinitialize very early in inialization to setup + * Called from sam_usbinitialize very early in initialization to setup * USB-related GPIO pins for the SAMA5D3-Xplained board. * * USB Ports diff --git a/boards/arm/sama5/sama5d3-xplained/include/board_384mhz.h b/boards/arm/sama5/sama5d3-xplained/include/board_384mhz.h index 6a4a064d58..1f3ea5dbbf 100644 --- a/boards/arm/sama5/sama5d3-xplained/include/board_384mhz.h +++ b/boards/arm/sama5/sama5d3-xplained/include/board_384mhz.h @@ -61,7 +61,7 @@ /* PLLA configuration. * * Divider = 1 - * Multipler = 64 + * Multiplier = 64 */ #define BOARD_CKGR_PLLAR_COUNT (63 << PMC_CKGR_PLLAR_COUNT_SHIFT) diff --git a/boards/arm/sama5/sama5d3-xplained/include/board_396mhz.h b/boards/arm/sama5/sama5d3-xplained/include/board_396mhz.h index 37acf44211..396f75bf0a 100644 --- a/boards/arm/sama5/sama5d3-xplained/include/board_396mhz.h +++ b/boards/arm/sama5/sama5d3-xplained/include/board_396mhz.h @@ -59,7 +59,7 @@ /* PLLA configuration. * * Divider = 1 - * Multipler = 66 + * Multiplier = 66 */ #define BOARD_CKGR_PLLAR_COUNT (63 << PMC_CKGR_PLLAR_COUNT_SHIFT) diff --git a/boards/arm/sama5/sama5d3-xplained/include/board_528mhz.h b/boards/arm/sama5/sama5d3-xplained/include/board_528mhz.h index be473c3844..535a61816b 100644 --- a/boards/arm/sama5/sama5d3-xplained/include/board_528mhz.h +++ b/boards/arm/sama5/sama5d3-xplained/include/board_528mhz.h @@ -58,7 +58,7 @@ /* PLLA configuration. * * Divider = 1 - * Multipler = 43+1 + * Multiplier = 43+1 */ #define BOARD_CKGR_PLLAR_COUNT (63 << PMC_CKGR_PLLAR_COUNT_SHIFT) diff --git a/boards/arm/sama5/sama5d3-xplained/src/sam_hsmci.c b/boards/arm/sama5/sama5d3-xplained/src/sam_hsmci.c index bb2dc13ef1..47a628e5d1 100644 --- a/boards/arm/sama5/sama5d3-xplained/src/sam_hsmci.c +++ b/boards/arm/sama5/sama5d3-xplained/src/sam_hsmci.c @@ -25,7 +25,7 @@ * (2) a microSD memory card slot (J11). * * The full size SD card slot connects via HSMCI0. The card detect discrete - * is available on PB17 (pulled high). The write protect descrete is tied to + * is available on PB17 (pulled high). The write protect discrete is tied to * ground (via PP6) and not available to software. The slot supports 8-bit * wide transfer mode, but the NuttX driver currently uses only the 4-bit * wide transfer mode diff --git a/boards/arm/sama5/sama5d3-xplained/src/sam_sdram.c b/boards/arm/sama5/sama5d3-xplained/src/sam_sdram.c index d6482f0145..3423312672 100644 --- a/boards/arm/sama5/sama5d3-xplained/src/sam_sdram.c +++ b/boards/arm/sama5/sama5d3-xplained/src/sam_sdram.c @@ -259,7 +259,7 @@ void sam_sdram_config(void) MPDDRC_CR_OCD_EXIT | /* Off-chip Driver */ MPDDRC_CR_8BANKS | /* Number of Banks */ MPDDRC_CR_NDQS | /* Not DQS */ - MPDDRC_CR_UNAL; /* upport Unaligned Access */ + MPDDRC_CR_UNAL; /* support Unaligned Access */ #elif defined(CONFIG_SAMA5D3XPLAINED_MT47H64M16HR) /* For MT47H64M16HR @@ -286,7 +286,7 @@ void sam_sdram_config(void) MPDDRC_CR_OCD_EXIT | /* Off-chip Driver */ MPDDRC_CR_8BANKS | /* Number of Banks */ MPDDRC_CR_NDQS | /* Not DQS */ - MPDDRC_CR_UNAL; /* upport Unaligned Access */ + MPDDRC_CR_UNAL; /* support Unaligned Access */ #else # error Unknown SDRAM type diff --git a/boards/arm/sama5/sama5d3x-ek/include/board_384mhz.h b/boards/arm/sama5/sama5d3x-ek/include/board_384mhz.h index 8c895ad56d..34d2f72fa6 100644 --- a/boards/arm/sama5/sama5d3x-ek/include/board_384mhz.h +++ b/boards/arm/sama5/sama5d3x-ek/include/board_384mhz.h @@ -62,7 +62,7 @@ /* PLLA configuration. * * Divider = 1 - * Multipler = 64 + * Multiplier = 64 */ #define BOARD_CKGR_PLLAR_COUNT (63 << PMC_CKGR_PLLAR_COUNT_SHIFT) diff --git a/boards/arm/sama5/sama5d3x-ek/include/board_396mhz.h b/boards/arm/sama5/sama5d3x-ek/include/board_396mhz.h index 4b6359ba40..dfdd7d743a 100644 --- a/boards/arm/sama5/sama5d3x-ek/include/board_396mhz.h +++ b/boards/arm/sama5/sama5d3x-ek/include/board_396mhz.h @@ -59,7 +59,7 @@ /* PLLA configuration. * * Divider = 1 - * Multipler = 66 + * Multiplier = 66 */ #define BOARD_CKGR_PLLAR_COUNT (63 << PMC_CKGR_PLLAR_COUNT_SHIFT) diff --git a/boards/arm/sama5/sama5d3x-ek/include/board_528mhz.h b/boards/arm/sama5/sama5d3x-ek/include/board_528mhz.h index f298edd6b7..20d7621e9d 100644 --- a/boards/arm/sama5/sama5d3x-ek/include/board_528mhz.h +++ b/boards/arm/sama5/sama5d3x-ek/include/board_528mhz.h @@ -58,7 +58,7 @@ /* PLLA configuration. * * Divider = 1 - * Multipler = 43+1 + * Multiplier = 43+1 */ #define BOARD_CKGR_PLLAR_COUNT (63 << PMC_CKGR_PLLAR_COUNT_SHIFT) diff --git a/boards/arm/sama5/sama5d3x-ek/src/sam_boot.c b/boards/arm/sama5/sama5d3x-ek/src/sam_boot.c index b86294dc13..3ab0271a26 100644 --- a/boards/arm/sama5/sama5d3x-ek/src/sam_boot.c +++ b/boards/arm/sama5/sama5d3x-ek/src/sam_boot.c @@ -92,7 +92,7 @@ void sam_boardinitialize(void) * 1) the HS host or device controller is in the configuration and * 2) the weak function sam_usbinitialize() has been brought * into the build. - * Presumeably either CONFIG_USBDEV or CONFIG_USBHOST is also selected. + * Presumably either CONFIG_USBDEV or CONFIG_USBHOST is also selected. */ #if defined(CONFIG_SAMA5_UHPHS) || defined(CONFIG_SAMA5_UDPHS) diff --git a/boards/arm/sama5/sama5d3x-ek/src/sam_hsmci.c b/boards/arm/sama5/sama5d3x-ek/src/sam_hsmci.c index fc0a7ee666..357a3ae14e 100644 --- a/boards/arm/sama5/sama5d3x-ek/src/sam_hsmci.c +++ b/boards/arm/sama5/sama5d3x-ek/src/sam_hsmci.c @@ -26,7 +26,7 @@ * * The full size SD card slot connects via HSMCI0. * The card detect discrete is available on PB17 (pulled high). - * The write protect descrete is tied to ground (via PP6) and not available + * The write protect discrete is tied to ground (via PP6) and not available * to software. * The slot supports 8-bit wide transfer mode, but the NuttX driver * currently uses only the 4-bit wide transfer mode diff --git a/boards/arm/sama5/sama5d3x-ek/src/sam_sdram.c b/boards/arm/sama5/sama5d3x-ek/src/sam_sdram.c index 96e4accbed..e2912a11b5 100644 --- a/boards/arm/sama5/sama5d3x-ek/src/sam_sdram.c +++ b/boards/arm/sama5/sama5d3x-ek/src/sam_sdram.c @@ -257,7 +257,7 @@ void sam_sdram_config(void) MPDDRC_CR_OCD_EXIT | /* Off-chip Driver */ MPDDRC_CR_8BANKS | /* Number of Banks */ MPDDRC_CR_NDQS | /* Not DQS */ - MPDDRC_CR_UNAL; /* upport Unaligned Access */ + MPDDRC_CR_UNAL; /* support Unaligned Access */ #elif defined(CONFIG_SAMA5D3XEK_MT47H64M16HR) /* For MT47H64M16HR @@ -284,7 +284,7 @@ void sam_sdram_config(void) MPDDRC_CR_OCD_EXIT | /* Off-chip Driver */ MPDDRC_CR_8BANKS | /* Number of Banks */ MPDDRC_CR_NDQS | /* Not DQS */ - MPDDRC_CR_UNAL; /* upport Unaligned Access */ + MPDDRC_CR_UNAL; /* support Unaligned Access */ #else # error Unknown SDRAM type diff --git a/boards/arm/sama5/sama5d3x-ek/src/sam_usb.c b/boards/arm/sama5/sama5d3x-ek/src/sam_usb.c index e7d0d485a2..497c35aadb 100644 --- a/boards/arm/sama5/sama5d3x-ek/src/sam_usb.c +++ b/boards/arm/sama5/sama5d3x-ek/src/sam_usb.c @@ -175,7 +175,7 @@ static int ehci_waiter(int argc, char *argv[]) * Name: sam_usbinitialize * * Description: - * Called from sam_usbinitialize very early in inialization to setup + * Called from sam_usbinitialize very early in initialization to setup * USB-related GPIO pins for the SAMA5D3x-EK board. * * USB Ports diff --git a/boards/arm/sama5/sama5d3x-ek/src/sama5d3x-ek.h b/boards/arm/sama5/sama5d3x-ek/src/sama5d3x-ek.h index 36793562ab..60df047f86 100644 --- a/boards/arm/sama5/sama5d3x-ek/src/sama5d3x-ek.h +++ b/boards/arm/sama5/sama5d3x-ek/src/sama5d3x-ek.h @@ -803,7 +803,7 @@ bool sam_writeprotected(int slotno); * Name: sam_usbinitialize * * Description: - * Called from sam_usbinitialize very early in inialization to setup + * Called from sam_usbinitialize very early in initialization to setup * USB-related PIO pins for the SAMA5D3x-EK board. * ****************************************************************************/ diff --git a/boards/arm/sama5/sama5d4-ek/include/board_384mhz.h b/boards/arm/sama5/sama5d4-ek/include/board_384mhz.h index 6a130c015e..86ec01f87a 100644 --- a/boards/arm/sama5/sama5d4-ek/include/board_384mhz.h +++ b/boards/arm/sama5/sama5d4-ek/include/board_384mhz.h @@ -61,7 +61,7 @@ /* PLLA configuration. * - * Multipler = 64: PLLACK = 64 * 12MHz = 768MHz + * Multiplier = 64: PLLACK = 64 * 12MHz = 768MHz */ #define BOARD_CKGR_PLLAR_COUNT (63 << PMC_CKGR_PLLAR_COUNT_SHIFT) diff --git a/boards/arm/sama5/sama5d4-ek/include/board_396mhz.h b/boards/arm/sama5/sama5d4-ek/include/board_396mhz.h index b6dba8a0ef..9d1bdd9979 100644 --- a/boards/arm/sama5/sama5d4-ek/include/board_396mhz.h +++ b/boards/arm/sama5/sama5d4-ek/include/board_396mhz.h @@ -58,7 +58,7 @@ /* PLLA configuration. * - * Multipler = 66: PLLACK = 66 * 12MHz = 792MHz + * Multiplier = 66: PLLACK = 66 * 12MHz = 792MHz */ #define BOARD_CKGR_PLLAR_COUNT (63 << PMC_CKGR_PLLAR_COUNT_SHIFT) diff --git a/boards/arm/sama5/sama5d4-ek/include/board_528mhz.h b/boards/arm/sama5/sama5d4-ek/include/board_528mhz.h index 59435384be..d6fa2d4f52 100644 --- a/boards/arm/sama5/sama5d4-ek/include/board_528mhz.h +++ b/boards/arm/sama5/sama5d4-ek/include/board_528mhz.h @@ -57,7 +57,7 @@ /* PLLA configuration. * - * Multipler = 43+1: PLLACK = 44 * 12MHz = 528MHz + * Multiplier = 43+1: PLLACK = 44 * 12MHz = 528MHz */ #define BOARD_CKGR_PLLAR_COUNT (63 << PMC_CKGR_PLLAR_COUNT_SHIFT) diff --git a/boards/arm/sama5/sama5d4-ek/src/sam_boot.c b/boards/arm/sama5/sama5d4-ek/src/sam_boot.c index cc4456621a..036a37e496 100644 --- a/boards/arm/sama5/sama5d4-ek/src/sam_boot.c +++ b/boards/arm/sama5/sama5d4-ek/src/sam_boot.c @@ -92,7 +92,7 @@ void sam_boardinitialize(void) /* Initialize USB if the * 1) the HS host or device controller is in the configuration and * 2) the weak function sam_usbinitialize() has been brought - * into the build. Presumeably either CONFIG_USBDEV or CONFIG_USBHOST is + * into the build. Presumably either CONFIG_USBDEV or CONFIG_USBHOST is * also selected. */ diff --git a/boards/arm/sama5/sama5d4-ek/src/sam_sdram.c b/boards/arm/sama5/sama5d4-ek/src/sam_sdram.c index 95c3aed392..ba03d1ad8d 100644 --- a/boards/arm/sama5/sama5d4-ek/src/sam_sdram.c +++ b/boards/arm/sama5/sama5d4-ek/src/sam_sdram.c @@ -419,7 +419,7 @@ void sam_sdram_config(void) MPDDRC_CR_ZQ_INIT | MPDDRC_CR_8BANKS | /* Number of Banks */ MPDDRC_CR_NDQS | /* Not DQS */ - MPDDRC_CR_UNAL; /* upport Unaligned Access */ + MPDDRC_CR_UNAL; /* support Unaligned Access */ #else # error Unknown SDRAM type diff --git a/boards/arm/sama5/sama5d4-ek/src/sama5d4-ek.h b/boards/arm/sama5/sama5d4-ek/src/sama5d4-ek.h index 01e8b723d0..591451da25 100644 --- a/boards/arm/sama5/sama5d4-ek/src/sama5d4-ek.h +++ b/boards/arm/sama5/sama5d4-ek/src/sama5d4-ek.h @@ -1058,7 +1058,7 @@ bool sam_writeprotected(int slotno); * Name: sam_usbinitialize * * Description: - * Called from sam_usbinitialize very early in inialization to setup + * Called from sam_usbinitialize very early in initialization to setup * USB-related PIO pins for the SAMA5D4-EK board. * ****************************************************************************/ diff --git a/boards/arm/samd5e5/metro-m4/src/sam_composite.c b/boards/arm/samd5e5/metro-m4/src/sam_composite.c index b91a6547fb..d71b0b9a88 100644 --- a/boards/arm/samd5e5/metro-m4/src/sam_composite.c +++ b/boards/arm/samd5e5/metro-m4/src/sam_composite.c @@ -131,7 +131,7 @@ static int board_mscclassobject(int minor, * composite device logic. * * Input Parameters: - * classdev - The class driver instrance previously give to the composite + * classdev - The class driver instance previously given to the composite * driver by board_mscclassobject(). * * Returned Value: diff --git a/boards/arm/samv7/common/include/board_uart_rxdma_poll.h b/boards/arm/samv7/common/include/board_uart_rxdma_poll.h index 94ce371020..14d18f9728 100644 --- a/boards/arm/samv7/common/include/board_uart_rxdma_poll.h +++ b/boards/arm/samv7/common/include/board_uart_rxdma_poll.h @@ -70,7 +70,7 @@ void board_uart_rxdma_poll_start(void); * Name: board_uart_rxdma_poll_stop * * Description: - * This function stops the timer polling UART. No resourses are freed, + * This function stops the timer polling UART. No resources are freed, * time is just stopped and can be started again. * * Input Parameters: diff --git a/boards/arm/samv7/common/scripts/memory.ld.template b/boards/arm/samv7/common/scripts/memory.ld.template index 45b8a4a07a..8cf5e2729f 100644 --- a/boards/arm/samv7/common/scripts/memory.ld.template +++ b/boards/arm/samv7/common/scripts/memory.ld.template @@ -50,7 +50,7 @@ #define XSRAM_SIZE (CONFIG_ARCH_CHIP_SAMV7_MEM_RAM - KSRAM_SIZE - USRAM_SIZE) /* The SAMV7 can have up to 2048Kb of FLASH beginning at address 0x0040:0000 - * and up to 384Kb of SRAM beginining at 0x2040:0000 or 0x2000:0000 + * and up to 384Kb of SRAM beginning at 0x2040:0000 or 0x2000:0000 * * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 * where the code expects to begin execution by jumping to the entry point in diff --git a/boards/arm/samv7/common/src/sam_gpio_enc.c b/boards/arm/samv7/common/src/sam_gpio_enc.c index 8aa1440b37..422dd99d25 100644 --- a/boards/arm/samv7/common/src/sam_gpio_enc.c +++ b/boards/arm/samv7/common/src/sam_gpio_enc.c @@ -243,7 +243,7 @@ static int sam_gpio_enc_setup(struct qe_lowerhalf_s *lower) new = (state_b << 1 | (state_a ^ state_b)); config->position_base = config->position = new; - /* Setup interrups for ENC_A and ENC_B pins. */ + /* Setup interrupts for ENC_A and ENC_B pins. */ ret = board_gpio_enc_irqx(config->enca, config->enca_irq, sam_gpio_enc_interrupt, priv); diff --git a/boards/arm/samv7/common/src/sam_reset.c b/boards/arm/samv7/common/src/sam_reset.c index 3f4359f7d2..269b21e30b 100644 --- a/boards/arm/samv7/common/src/sam_reset.c +++ b/boards/arm/samv7/common/src/sam_reset.c @@ -47,7 +47,7 @@ * reason (and potentially subreason) is saved. * * Returned Value: - * This functions should always return succesfully with 0. We save + * This functions should always return successfully with 0. We save * BOARDIOC_RESETCAUSE_UNKOWN in cause structure if we are * not able to get last reset cause from HW (which is unlikely). * diff --git a/boards/arm/samv7/common/src/sam_uart_rxdma_poll.c b/boards/arm/samv7/common/src/sam_uart_rxdma_poll.c index ded2950086..c326b026c4 100644 --- a/boards/arm/samv7/common/src/sam_uart_rxdma_poll.c +++ b/boards/arm/samv7/common/src/sam_uart_rxdma_poll.c @@ -92,7 +92,7 @@ void board_uart_rxdma_poll_start(void) * Name: board_uart_rxdma_poll_stop * * Description: - * This function stops the timer polling UART. No resourses are freed, + * This function stops the timer polling UART. No resources are freed, * time is just stopped and can be started again. * * Input Parameters: diff --git a/boards/arm/samv7/same70-xplained/src/same70-xplained.h b/boards/arm/samv7/same70-xplained/src/same70-xplained.h index f568752420..4cb6931da0 100644 --- a/boards/arm/samv7/same70-xplained/src/same70-xplained.h +++ b/boards/arm/samv7/same70-xplained/src/same70-xplained.h @@ -235,7 +235,7 @@ * * ------ --------- --------- * SAME70 SAME70 Ethernet - * Pin Function Functio + * Pin Function Function * ------ --------- --------- * PD0 GTXCK REF_CLK * PD1 GTXEN TXEN diff --git a/boards/arm/samv7/samv71-xult/src/sam_composite.c b/boards/arm/samv7/samv71-xult/src/sam_composite.c index 715121cfc5..d8c175749a 100644 --- a/boards/arm/samv7/samv71-xult/src/sam_composite.c +++ b/boards/arm/samv7/samv71-xult/src/sam_composite.c @@ -130,7 +130,7 @@ static int board_mscclassobject(int minor, * composite device logic. * * Input Parameters: - * classdev - The class driver instrance previously give to the composite + * classdev - The class driver instance previously given to the composite * driver by board_mscclassobject(). * * Returned Value: diff --git a/boards/arm/stm32/axoloti/src/stm32_usbhost.c b/boards/arm/stm32/axoloti/src/stm32_usbhost.c index ebf7072992..5bbf632635 100644 --- a/boards/arm/stm32/axoloti/src/stm32_usbhost.c +++ b/boards/arm/stm32/axoloti/src/stm32_usbhost.c @@ -122,7 +122,7 @@ static int usbhost_waiter(int argc, char *argv[]) * Name: stm32_usbinitialize * * Description: - * Called from stm32_usbinitialize very early in inialization to setup + * Called from stm32_usbinitialize very early in initialization to setup * USB-related GPIO pins for the Axoloti board. * ****************************************************************************/ diff --git a/boards/arm/stm32/b-g431b-esc1/src/stm32_can.c b/boards/arm/stm32/b-g431b-esc1/src/stm32_can.c index e946d297bc..d240464d9e 100644 --- a/boards/arm/stm32/b-g431b-esc1/src/stm32_can.c +++ b/boards/arm/stm32/b-g431b-esc1/src/stm32_can.c @@ -47,7 +47,7 @@ /* Configuration ************************************************************/ #if !defined(CONFIG_STM32_FDCAN1) -# error "No CAN is enable. Please eneable at least one CAN device" +# error "No CAN is enable. Please enable at least one CAN device" #endif #ifdef CONFIG_BOARD_STM32_BG431BESC1_CANTERM diff --git a/boards/arm/stm32/b-g431b-esc1/src/stm32_cansock.c b/boards/arm/stm32/b-g431b-esc1/src/stm32_cansock.c index 1b7b8f8f4e..4ed50224bf 100644 --- a/boards/arm/stm32/b-g431b-esc1/src/stm32_cansock.c +++ b/boards/arm/stm32/b-g431b-esc1/src/stm32_cansock.c @@ -38,7 +38,7 @@ /* Configuration ************************************************************/ #if !defined(CONFIG_STM32_FDCAN1) -# error "No CAN is enable. Please eneable at least one CAN device" +# error "No CAN is enable. Please enable at least one CAN device" #endif #ifdef CONFIG_BOARD_STM32_BG431BESC1_CANTERM diff --git a/boards/arm/stm32/b-g474e-dpow1/src/stm32_smps.c b/boards/arm/stm32/b-g474e-dpow1/src/stm32_smps.c index da53efcb96..910c1860f9 100644 --- a/boards/arm/stm32/b-g474e-dpow1/src/stm32_smps.c +++ b/boards/arm/stm32/b-g474e-dpow1/src/stm32_smps.c @@ -752,7 +752,7 @@ static int smps_state_get(struct smps_dev_s *dev, { struct smps_s *smps = (struct smps_s *)dev->priv; - /* Copy localy stored feedbacks data to status structure */ + /* Copy locally stored feedbacks data to status structure */ smps->state.fb.v_in = g_smps_priv.v_in; smps->state.fb.v_out = g_smps_priv.v_out; diff --git a/boards/arm/stm32/clicker2-stm32/src/clicker2-stm32.h b/boards/arm/stm32/clicker2-stm32/src/clicker2-stm32.h index 8619ba1943..8ab6111fd6 100644 --- a/boards/arm/stm32/clicker2-stm32/src/clicker2-stm32.h +++ b/boards/arm/stm32/clicker2-stm32/src/clicker2-stm32.h @@ -285,7 +285,7 @@ int stm32_bringup(void); * Name: stm32_usb_configure * * Description: - * Called from stm32_boardinitialize very early in inialization to setup + * Called from stm32_boardinitialize very early in initialization to setup * USB-related GPIO pins for the Mikroe Clicker2 STM32 board. * ****************************************************************************/ diff --git a/boards/arm/stm32/clicker2-stm32/src/stm32_boot.c b/boards/arm/stm32/clicker2-stm32/src/stm32_boot.c index 3e3b02522c..f0d9cb34ee 100644 --- a/boards/arm/stm32/clicker2-stm32/src/stm32_boot.c +++ b/boards/arm/stm32/clicker2-stm32/src/stm32_boot.c @@ -65,7 +65,7 @@ void stm32_boardinitialize(void) #ifdef CONFIG_STM32_OTGFS /* Initialize USB if the 1) OTG FS controller is in the configuration and * 2) disabled, and 3) the weak function stm32_usb_configure() has been - * brought into the build. Presumeably either CONFIG_USBDEV or + * brought into the build. Presumably either CONFIG_USBDEV or * CONFIG_USBHOST is also selected. */ diff --git a/boards/arm/stm32/clicker2-stm32/src/stm32_mrf24j40.c b/boards/arm/stm32/clicker2-stm32/src/stm32_mrf24j40.c index 7cc84e2b9a..95e16ff3f1 100644 --- a/boards/arm/stm32/clicker2-stm32/src/stm32_mrf24j40.c +++ b/boards/arm/stm32/clicker2-stm32/src/stm32_mrf24j40.c @@ -250,7 +250,7 @@ static int stm32_mrf24j40_devsetup(struct stm32_priv_s *priv) #ifdef CONFIG_IEEE802154_NETDEV /* Use the IEEE802.15.4 MAC interface instance to create a 6LoWPAN - * network interface by wrapping the MAC intrface instance in a + * network interface by wrapping the MAC interface instance in a * network device driver via mac802154dev_register(). */ diff --git a/boards/arm/stm32/clicker2-stm32/src/stm32_usb.c b/boards/arm/stm32/clicker2-stm32/src/stm32_usb.c index 639324fb7c..be722919db 100644 --- a/boards/arm/stm32/clicker2-stm32/src/stm32_usb.c +++ b/boards/arm/stm32/clicker2-stm32/src/stm32_usb.c @@ -56,7 +56,7 @@ * Name: stm32_usb_configure * * Description: - * Called from stm32_boardinitialize very early in inialization to setup + * Called from stm32_boardinitialize very early in initialization to setup * USB-related GPIO pins for the Olimex STM32 P407 board. * ****************************************************************************/ diff --git a/boards/arm/stm32/cloudctrl/src/cloudctrl.h b/boards/arm/stm32/cloudctrl/src/cloudctrl.h index c72d635a5a..58d98fabb4 100644 --- a/boards/arm/stm32/cloudctrl/src/cloudctrl.h +++ b/boards/arm/stm32/cloudctrl/src/cloudctrl.h @@ -223,7 +223,7 @@ void weak_function stm32_spidev_initialize(void); * Name: stm32_usbinitialize * * Description: - * Called from stm32_usbinitialize very early in inialization to setup + * Called from stm32_usbinitialize very early in initialization to setup * USB-related GPIO pins for the STM3240G-EVAL board. * ****************************************************************************/ diff --git a/boards/arm/stm32/cloudctrl/src/stm32_usb.c b/boards/arm/stm32/cloudctrl/src/stm32_usb.c index 52d7c79b04..fc6810f834 100644 --- a/boards/arm/stm32/cloudctrl/src/stm32_usb.c +++ b/boards/arm/stm32/cloudctrl/src/stm32_usb.c @@ -126,7 +126,7 @@ static int usbhost_waiter(int argc, char *argv[]) * Name: stm32_usbinitialize * * Description: - * Called from stm32_usbinitialize very early in inialization to setup + * Called from stm32_usbinitialize very early in initialization to setup * USB-related GPIO pins for the STM3240G-EVAL board. * ****************************************************************************/ diff --git a/boards/arm/stm32/common/src/stm32_ihm07m1.c b/boards/arm/stm32/common/src/stm32_ihm07m1.c index 0ea266e7ba..0481dc03b2 100644 --- a/boards/arm/stm32/common/src/stm32_ihm07m1.c +++ b/boards/arm/stm32/common/src/stm32_ihm07m1.c @@ -42,7 +42,7 @@ ****************************************************************************/ #if CONFIG_MOTOR_FOC_SHUNTS != 3 -# error For now ony 3-shunts configuration is supported +# error For now only 3-shunts configuration is supported #endif /* Configuration specific for L6230: diff --git a/boards/arm/stm32/common/src/stm32_ihm08m1.c b/boards/arm/stm32/common/src/stm32_ihm08m1.c index feb9b8c401..b357484799 100644 --- a/boards/arm/stm32/common/src/stm32_ihm08m1.c +++ b/boards/arm/stm32/common/src/stm32_ihm08m1.c @@ -40,7 +40,7 @@ ****************************************************************************/ #if CONFIG_MOTOR_FOC_SHUNTS != 3 -# error For now ony 3-shunts configuration is supported +# error For now only 3-shunts configuration is supported #endif /* Configuration specific for L6398: diff --git a/boards/arm/stm32/common/src/stm32_ihm16m1.c b/boards/arm/stm32/common/src/stm32_ihm16m1.c index 02d7dac0a1..b15e1b8cc2 100644 --- a/boards/arm/stm32/common/src/stm32_ihm16m1.c +++ b/boards/arm/stm32/common/src/stm32_ihm16m1.c @@ -42,7 +42,7 @@ ****************************************************************************/ #if CONFIG_MOTOR_FOC_SHUNTS != 3 -# error For now ony 3-shunts configuration is supported +# error For now only 3-shunts configuration is supported #endif /* Configuration specific for STSPIN830: diff --git a/boards/arm/stm32/et-stm32-stamp/include/board.h b/boards/arm/stm32/et-stm32-stamp/include/board.h index 7211b69114..444d2d8b20 100644 --- a/boards/arm/stm32/et-stm32-stamp/include/board.h +++ b/boards/arm/stm32/et-stm32-stamp/include/board.h @@ -42,7 +42,7 @@ #define STM32_BOARD_XTAL 8000000ul -/* PLL source is HSE/1, PLL multipler is 9: +/* PLL source is HSE/1, PLL multiplier is 9: * PLL frequency is 8MHz (XTAL) x 9 = 72MHz */ diff --git a/boards/arm/stm32/fire-stm32v2/include/board.h b/boards/arm/stm32/fire-stm32v2/include/board.h index 340cb3347f..d8e09d6f07 100644 --- a/boards/arm/stm32/fire-stm32v2/include/board.h +++ b/boards/arm/stm32/fire-stm32v2/include/board.h @@ -52,7 +52,7 @@ #define STM32_LSE_FREQUENCY 32768 /* PLL source is HSE/1, - * PLL multipler is 9: + * PLL multiplier is 9: * PLL frequency is 8MHz (XTAL) x 9 = 72MHz */ diff --git a/boards/arm/stm32/hymini-stm32v/include/board.h b/boards/arm/stm32/hymini-stm32v/include/board.h index 37f4ce2aa6..441980e64b 100644 --- a/boards/arm/stm32/hymini-stm32v/include/board.h +++ b/boards/arm/stm32/hymini-stm32v/include/board.h @@ -39,7 +39,7 @@ #define STM32_BOARD_XTAL 8000000ul -/* PLL source is HSE/1, PLL multipler is 9: +/* PLL source is HSE/1, PLL multiplier is 9: * PLL frequency is 8MHz (XTAL) x 9 = 72MHz */ diff --git a/boards/arm/stm32/hymini-stm32v/src/stm32_r61505u.c b/boards/arm/stm32/hymini-stm32v/src/stm32_r61505u.c index e4d788aaa8..ac992e22c7 100644 --- a/boards/arm/stm32/hymini-stm32v/src/stm32_r61505u.c +++ b/boards/arm/stm32/hymini-stm32v/src/stm32_r61505u.c @@ -181,7 +181,7 @@ static const uint16_t fsmc_gpios[] = GPIO_NPS_D8, GPIO_NPS_D9, GPIO_NPS_D10, GPIO_NPS_D11, GPIO_NPS_D12, GPIO_NPS_D13, GPIO_NPS_D14, GPIO_NPS_D15, - /* NOE, NWE */ + /* NOE, NWE */ GPIO_NPS_NOE, GPIO_NPS_NWE, diff --git a/boards/arm/stm32/maple/include/board.h b/boards/arm/stm32/maple/include/board.h index edce9c0f89..399e9cf93b 100644 --- a/boards/arm/stm32/maple/include/board.h +++ b/boards/arm/stm32/maple/include/board.h @@ -42,7 +42,7 @@ #define STM32_BOARD_XTAL 8000000ul -/* PLL source is HSE/1, PLL multipler is 9: +/* PLL source is HSE/1, PLL multiplier is 9: * PLL frequency is 8MHz (XTAL) x 9 = 72MHz */ diff --git a/boards/arm/stm32/mikroe-stm32f4/src/stm32_boot.c b/boards/arm/stm32/mikroe-stm32f4/src/stm32_boot.c index c993e5e455..6fbfc9d4bf 100644 --- a/boards/arm/stm32/mikroe-stm32f4/src/stm32_boot.c +++ b/boards/arm/stm32/mikroe-stm32f4/src/stm32_boot.c @@ -85,7 +85,7 @@ void stm32_boardinitialize(void) /* Initialize USB if the 1) OTG FS controller is in the configuration and * 2) disabled, and 3) the weak function stm32_usbinitialize() has been - * brought into the build. Presumeably either CONFIG_USBDEV or + * brought into the build. Presumably either CONFIG_USBDEV or * CONFIG_USBHOST is also selected. */ diff --git a/boards/arm/stm32/mikroe-stm32f4/src/stm32_usb.c b/boards/arm/stm32/mikroe-stm32f4/src/stm32_usb.c index da83462793..2e6c8d4b09 100644 --- a/boards/arm/stm32/mikroe-stm32f4/src/stm32_usb.c +++ b/boards/arm/stm32/mikroe-stm32f4/src/stm32_usb.c @@ -126,7 +126,7 @@ static int usbhost_waiter(int argc, char *argv[]) * Name: stm32_usbinitialize * * Description: - * Called from stm32_usbinitialize very early in inialization to setup + * Called from stm32_usbinitialize very early in initialization to setup * USB-related GPIO pins for the STM32F4Discovery board. * ****************************************************************************/ diff --git a/boards/arm/stm32/nucleo-f103rb/include/board.h b/boards/arm/stm32/nucleo-f103rb/include/board.h index 1dc8e1e886..ebdf7dfd85 100644 --- a/boards/arm/stm32/nucleo-f103rb/include/board.h +++ b/boards/arm/stm32/nucleo-f103rb/include/board.h @@ -53,7 +53,7 @@ #define STM32_HSE_FREQUENCY STM32_BOARD_XTAL #define STM32_LSE_FREQUENCY 32768 /* X2 on board */ -/* PLL source is HSE/1, PLL multipler is 9: +/* PLL source is HSE/1, PLL multiplier is 9: * PLL frequency is 8MHz (XTAL) x 9 = 72MHz */ diff --git a/boards/arm/stm32/nucleo-f207zg/src/stm32_usb.c b/boards/arm/stm32/nucleo-f207zg/src/stm32_usb.c index 3c7c439132..89f0bc8401 100644 --- a/boards/arm/stm32/nucleo-f207zg/src/stm32_usb.c +++ b/boards/arm/stm32/nucleo-f207zg/src/stm32_usb.c @@ -123,7 +123,7 @@ static int usbhost_waiter(int argc, char *argv[]) * Name: stm32_usbinitialize * * Description: - * Called from stm32_usbinitialize very early in inialization to setup + * Called from stm32_usbinitialize very early in initialization to setup * USB-related GPIO pins for the nucleo-144 board. * ****************************************************************************/ diff --git a/boards/arm/stm32/nucleo-f302r8/include/board.h b/boards/arm/stm32/nucleo-f302r8/include/board.h index 9c87ed3d0a..0c0aa006a3 100644 --- a/boards/arm/stm32/nucleo-f302r8/include/board.h +++ b/boards/arm/stm32/nucleo-f302r8/include/board.h @@ -53,7 +53,7 @@ #define STM32_HSE_FREQUENCY STM32_BOARD_XTAL #define STM32_LSE_FREQUENCY 32768 /* X2 on board */ -/* PLL source is HSE/1, PLL multipler is 9: PLL frequency is +/* PLL source is HSE/1, PLL multiplier is 9: PLL frequency is * 8MHz (XTAL) x 9 = 72MHz */ diff --git a/boards/arm/stm32/nucleo-f303re/include/board.h b/boards/arm/stm32/nucleo-f303re/include/board.h index 395455e4b3..9f55d1a309 100644 --- a/boards/arm/stm32/nucleo-f303re/include/board.h +++ b/boards/arm/stm32/nucleo-f303re/include/board.h @@ -55,7 +55,7 @@ #define STM32_LSE_FREQUENCY 32768 /* X2 on board */ /* PLL source is HSE/1, - * PLL multipler is 9: + * PLL multiplier is 9: * PLL frequency is 8MHz (XTAL) x 9 = 72MHz */ diff --git a/boards/arm/stm32/nucleo-f303ze/include/board.h b/boards/arm/stm32/nucleo-f303ze/include/board.h index 46953f6c8f..420cc4c326 100644 --- a/boards/arm/stm32/nucleo-f303ze/include/board.h +++ b/boards/arm/stm32/nucleo-f303ze/include/board.h @@ -54,7 +54,7 @@ #define STM32_HSE_FREQUENCY STM32_BOARD_XTAL #define STM32_LSE_FREQUENCY 32768 /* X2 on board */ -/* PLL source is HSE/1, PLL multipler is 9: +/* PLL source is HSE/1, PLL multiplier is 9: * PLL frequency is 8MHz (XTAL) x 9 = 72MHz */ diff --git a/boards/arm/stm32/nucleo-f334r8/include/board.h b/boards/arm/stm32/nucleo-f334r8/include/board.h index 586971d37b..1398196ba5 100644 --- a/boards/arm/stm32/nucleo-f334r8/include/board.h +++ b/boards/arm/stm32/nucleo-f334r8/include/board.h @@ -53,7 +53,7 @@ #define STM32_HSE_FREQUENCY STM32_BOARD_XTAL #define STM32_LSE_FREQUENCY 32768 /* X2 on board */ -/* PLL source is HSE/1, PLL multipler is 9: PLL frequency is +/* PLL source is HSE/1, PLL multiplier is 9: PLL frequency is * 8MHz (XTAL) x 9 = 72MHz */ diff --git a/boards/arm/stm32/nucleo-f334r8/src/stm32_spwm.c b/boards/arm/stm32/nucleo-f334r8/src/stm32_spwm.c index 211befb18f..83ee36087a 100644 --- a/boards/arm/stm32/nucleo-f334r8/src/stm32_spwm.c +++ b/boards/arm/stm32/nucleo-f334r8/src/stm32_spwm.c @@ -54,8 +54,6 @@ * Pre-processor Definitions ****************************************************************************/ -/* Asserions ****************************************************************/ - #ifndef CONFIG_ARCH_CHIP_STM32F334R8 # warning "This only have been verified with CONFIG_ARCH_CHIP_STM32F334R8" #endif @@ -635,7 +633,7 @@ static int spwm_hrtim_start(struct spwm_s *spwm) outputs |= (1 << (i * 2)); } - /* Enable HRTIM outpus */ + /* Enable HRTIM outputs */ HRTIM_OUTPUTS_ENABLE(hrtim, outputs, true); @@ -675,7 +673,7 @@ static int spwm_hrtim_stop(struct spwm_s *spwm) outputs |= (1 << (i * 2)); } - /* Disable HRTIM outpus */ + /* Disable HRTIM outputs */ HRTIM_OUTPUTS_ENABLE(hrtim, outputs, false); diff --git a/boards/arm/stm32/nucleo-f412zg/src/stm32_usb.c b/boards/arm/stm32/nucleo-f412zg/src/stm32_usb.c index 09e2125f47..db3f494c7d 100644 --- a/boards/arm/stm32/nucleo-f412zg/src/stm32_usb.c +++ b/boards/arm/stm32/nucleo-f412zg/src/stm32_usb.c @@ -135,7 +135,7 @@ static int usbhost_waiter(int argc, char *argv[]) * Name: stm32_usbinitialize * * Description: - * Called from stm32_usbinitialize very early in inialization to setup + * Called from stm32_usbinitialize very early in initialization to setup * USB-related GPIO pins for the STM32F411 Discovery board. * ****************************************************************************/ diff --git a/boards/arm/stm32/nucleo-f429zi/src/nucleo-144.h b/boards/arm/stm32/nucleo-f429zi/src/nucleo-144.h index 3cef78bf08..c66f463faa 100644 --- a/boards/arm/stm32/nucleo-f429zi/src/nucleo-144.h +++ b/boards/arm/stm32/nucleo-f429zi/src/nucleo-144.h @@ -226,7 +226,7 @@ int stm32_sdio_initialize(void); * Name: stm32_usbinitialize * * Description: - * Called from stm32_usbinitialize very early in inialization to + * Called from stm32_usbinitialize very early in initialization to * setup USB-related GPIO pins for the nucleo-144 board. * ****************************************************************************/ diff --git a/boards/arm/stm32/nucleo-f429zi/src/stm32_usb.c b/boards/arm/stm32/nucleo-f429zi/src/stm32_usb.c index b1627d12cc..a65fa99034 100644 --- a/boards/arm/stm32/nucleo-f429zi/src/stm32_usb.c +++ b/boards/arm/stm32/nucleo-f429zi/src/stm32_usb.c @@ -123,7 +123,7 @@ static int usbhost_waiter(int argc, char *argv[]) * Name: stm32_usbinitialize * * Description: - * Called from stm32_usbinitialize very early in inialization + * Called from stm32_usbinitialize very early in initialization * to setup USB-related GPIO pins for the nucleo-144 board. * ****************************************************************************/ diff --git a/boards/arm/stm32/nucleo-f446re/src/stm32_can.c b/boards/arm/stm32/nucleo-f446re/src/stm32_can.c index 1af64e9d29..ccf4aa9e3b 100644 --- a/boards/arm/stm32/nucleo-f446re/src/stm32_can.c +++ b/boards/arm/stm32/nucleo-f446re/src/stm32_can.c @@ -47,7 +47,7 @@ /* Configuration ************************************************************/ #if !defined(CONFIG_STM32_CAN1) && !defined(CONFIG_STM32_CAN2) -# error "No CAN is enable. Please eneable at least one CAN device" +# error "No CAN is enable. Please enable at least one CAN device" #endif /**************************************************************************** diff --git a/boards/arm/stm32/nucleo-f446re/src/stm32_cansock.c b/boards/arm/stm32/nucleo-f446re/src/stm32_cansock.c index 18e1f2a46f..06a5e15e98 100644 --- a/boards/arm/stm32/nucleo-f446re/src/stm32_cansock.c +++ b/boards/arm/stm32/nucleo-f446re/src/stm32_cansock.c @@ -37,7 +37,7 @@ /* Configuration ************************************************************/ #if !defined(CONFIG_STM32_CAN1) && !defined(CONFIG_STM32_CAN2) -# error "No CAN is enable. Please eneable at least one CAN device" +# error "No CAN is enable. Please enable at least one CAN device" #endif /**************************************************************************** diff --git a/boards/arm/stm32/nucleo-g431rb/src/stm32_can.c b/boards/arm/stm32/nucleo-g431rb/src/stm32_can.c index 1e940bfe40..69c8bab311 100644 --- a/boards/arm/stm32/nucleo-g431rb/src/stm32_can.c +++ b/boards/arm/stm32/nucleo-g431rb/src/stm32_can.c @@ -47,7 +47,7 @@ /* Configuration ************************************************************/ #if !defined(CONFIG_STM32_FDCAN1) -# error "No CAN is enable. Please eneable at least one CAN device" +# error "No CAN is enable. Please enable at least one CAN device" #endif /**************************************************************************** diff --git a/boards/arm/stm32/nucleo-l152re/include/board.h b/boards/arm/stm32/nucleo-l152re/include/board.h index ba8056cc8f..cfe5dd41ba 100644 --- a/boards/arm/stm32/nucleo-l152re/include/board.h +++ b/boards/arm/stm32/nucleo-l152re/include/board.h @@ -71,7 +71,7 @@ /* PLL Configuration * * - PLL source is HSE -> 8MHz - * - PLL multipler is 12 -> 96MHz PLL VCO clock output + * - PLL multiplier is 12 -> 96MHz PLL VCO clock output * - PLL output divider 3 -> 32MHz divided down PLL VCO clock output * * Resulting SYSCLK frequency is 8MHz x 12 / 3 = 32MHz diff --git a/boards/arm/stm32/odrive36/src/stm32_foc.c b/boards/arm/stm32/odrive36/src/stm32_foc.c index 50373b50cf..fe3f6158cf 100644 --- a/boards/arm/stm32/odrive36/src/stm32_foc.c +++ b/boards/arm/stm32/odrive36/src/stm32_foc.c @@ -90,7 +90,7 @@ /* Only 2-shunt configuration supported by board */ #if CONFIG_MOTOR_FOC_SHUNTS != 2 -# error For now ony 2-shunts configuration is supported +# error For now only 2-shunts configuration is supported #endif /* Configuration specific for DRV8301: @@ -931,7 +931,7 @@ int stm32_adc_setup(void) goto errout; } - /* Regsiter ADC */ + /* Register ADC */ ret = adc_register(ODRIVE_ADC_AUX_DEVPATH, adc); if (ret < 0) diff --git a/boards/arm/stm32/odrive36/src/stm32_usb.c b/boards/arm/stm32/odrive36/src/stm32_usb.c index de2f3ec169..ca4b506918 100644 --- a/boards/arm/stm32/odrive36/src/stm32_usb.c +++ b/boards/arm/stm32/odrive36/src/stm32_usb.c @@ -72,7 +72,7 @@ * Name: stm32_usbinitialize * * Description: - * Called from stm32_usbinitialize very early in inialization to setup + * Called from stm32_usbinitialize very early in initialization to setup * USB-related GPIO pins for the STM32F4Discovery board. * ****************************************************************************/ diff --git a/boards/arm/stm32/olimex-stm32-e407/src/stm32_boot.c b/boards/arm/stm32/olimex-stm32-e407/src/stm32_boot.c index 1987ab68b7..96e99584a5 100644 --- a/boards/arm/stm32/olimex-stm32-e407/src/stm32_boot.c +++ b/boards/arm/stm32/olimex-stm32-e407/src/stm32_boot.c @@ -59,7 +59,7 @@ void stm32_boardinitialize(void) #if defined(CONFIG_STM32_OTGFS) || defined(CONFIG_STM32_OTGHS) /* Initialize USB if the 1) OTG FS controller is in the configuration and * 2) disabled, and 3) the weak function stm32_usbinitialize() has been - * brought into the build. Presumeably either CONFIG_USBDEV is also + * brought into the build. Presumably either CONFIG_USBDEV is also * selected. */ diff --git a/boards/arm/stm32/olimex-stm32-e407/src/stm32_mrf24j40.c b/boards/arm/stm32/olimex-stm32-e407/src/stm32_mrf24j40.c index 8540c9a423..f61e42c08c 100644 --- a/boards/arm/stm32/olimex-stm32-e407/src/stm32_mrf24j40.c +++ b/boards/arm/stm32/olimex-stm32-e407/src/stm32_mrf24j40.c @@ -213,7 +213,7 @@ static int stm32_mrf24j40_devsetup(struct stm32_priv_s *priv) #ifdef CONFIG_IEEE802154_NETDEV /* Use the IEEE802.15.4 MAC interface instance to create a 6LoWPAN - * network interface by wrapping the MAC intrface instance in a + * network interface by wrapping the MAC interface instance in a * network device driver via mac802154dev_register(). */ diff --git a/boards/arm/stm32/olimex-stm32-e407/src/stm32_usb.c b/boards/arm/stm32/olimex-stm32-e407/src/stm32_usb.c index ffe8b0b6b4..5a832b384a 100644 --- a/boards/arm/stm32/olimex-stm32-e407/src/stm32_usb.c +++ b/boards/arm/stm32/olimex-stm32-e407/src/stm32_usb.c @@ -122,7 +122,7 @@ static int usbhost_waiter(int argc, char *argv[]) * Name: stm32_usbinitialize * * Description: - * Called from stm32_usbinitialize very early in inialization to setup + * Called from stm32_usbinitialize very early in initialization to setup * USB-related GPIO pins for the STM32F4Discovery board. * ****************************************************************************/ diff --git a/boards/arm/stm32/olimex-stm32-h405/src/stm32_boot.c b/boards/arm/stm32/olimex-stm32-h405/src/stm32_boot.c index e60cbb588a..d3c9a7bd4b 100644 --- a/boards/arm/stm32/olimex-stm32-h405/src/stm32_boot.c +++ b/boards/arm/stm32/olimex-stm32-h405/src/stm32_boot.c @@ -53,7 +53,7 @@ void stm32_boardinitialize(void) { /* Initialize USB if the 1) OTG FS controller is in the configuration and * 2) disabled, and 3) the weak function stm32_usbinitialize() has been - * brought into the build. Presumeably either CONFIG_USBDEV is also + * brought into the build. Presumably either CONFIG_USBDEV is also * selected. */ diff --git a/boards/arm/stm32/olimex-stm32-h405/src/stm32_usb.c b/boards/arm/stm32/olimex-stm32-h405/src/stm32_usb.c index 5b56b78f3a..48f5d92275 100644 --- a/boards/arm/stm32/olimex-stm32-h405/src/stm32_usb.c +++ b/boards/arm/stm32/olimex-stm32-h405/src/stm32_usb.c @@ -67,7 +67,7 @@ * Name: stm32_usbinitialize * * Description: - * Called from stm32_usbinitialize very early in inialization to setup + * Called from stm32_usbinitialize very early in initialization to setup * USB-related GPIO pins for the STM32F4Discovery board. * ****************************************************************************/ diff --git a/boards/arm/stm32/olimex-stm32-h407/src/stm32_boot.c b/boards/arm/stm32/olimex-stm32-h407/src/stm32_boot.c index 77da62b5ec..c21e03a8a4 100644 --- a/boards/arm/stm32/olimex-stm32-h407/src/stm32_boot.c +++ b/boards/arm/stm32/olimex-stm32-h407/src/stm32_boot.c @@ -57,7 +57,7 @@ void stm32_boardinitialize(void) /* Initialize USB if the 1) OTG FS controller is in the configuration and * 2) disabled, and 3) the weak function stm32_usbinitialize() has been * brought into the build. - * Presumeably either CONFIG_USBDEV is also selected. + * Presumably either CONFIG_USBDEV is also selected. */ if (stm32_usbinitialize) diff --git a/boards/arm/stm32/olimex-stm32-h407/src/stm32_usb.c b/boards/arm/stm32/olimex-stm32-h407/src/stm32_usb.c index 91d0c1a013..2790953bda 100644 --- a/boards/arm/stm32/olimex-stm32-h407/src/stm32_usb.c +++ b/boards/arm/stm32/olimex-stm32-h407/src/stm32_usb.c @@ -123,7 +123,7 @@ static int usbhost_waiter(int argc, char *argv[]) * Name: stm32_usbinitialize * * Description: - * Called from stm32_usbinitialize very early in inialization to setup + * Called from stm32_usbinitialize very early in initialization to setup * USB-related GPIO pins for the STM32F4Discovery board. * ****************************************************************************/ diff --git a/boards/arm/stm32/olimex-stm32-p207/src/olimex-stm32-p207.h b/boards/arm/stm32/olimex-stm32-p207/src/olimex-stm32-p207.h index a346aed8d3..5f69d7f493 100644 --- a/boards/arm/stm32/olimex-stm32-p207/src/olimex-stm32-p207.h +++ b/boards/arm/stm32/olimex-stm32-p207/src/olimex-stm32-p207.h @@ -91,7 +91,7 @@ * Name: stm32_usbinitialize * * Description: - * Called from stm32_usbinitialize very early in inialization to setup + * Called from stm32_usbinitialize very early in initialization to setup * USB-related GPIO pins for the STM32F4Discovery board. * ****************************************************************************/ diff --git a/boards/arm/stm32/olimex-stm32-p207/src/stm32_usb.c b/boards/arm/stm32/olimex-stm32-p207/src/stm32_usb.c index 18de4231fa..d9f59795f5 100644 --- a/boards/arm/stm32/olimex-stm32-p207/src/stm32_usb.c +++ b/boards/arm/stm32/olimex-stm32-p207/src/stm32_usb.c @@ -125,7 +125,7 @@ static int usbhost_waiter(int argc, char *argv[]) * Name: stm32_usbinitialize * * Description: - * Called from stm32_usbinitialize very early in inialization to setup + * Called from stm32_usbinitialize very early in initialization to setup * USB-related GPIO pins for the STM32F4Discovery board. * ****************************************************************************/ diff --git a/boards/arm/stm32/olimex-stm32-p407/src/olimex-stm32-p407.h b/boards/arm/stm32/olimex-stm32-p407/src/olimex-stm32-p407.h index 8b089d0e63..ef3133a85a 100644 --- a/boards/arm/stm32/olimex-stm32-p407/src/olimex-stm32-p407.h +++ b/boards/arm/stm32/olimex-stm32-p407/src/olimex-stm32-p407.h @@ -276,7 +276,7 @@ void stm32_stram_configure(void); * Name: stm32_usb_configure * * Description: - * Called from stm32_boardinitialize very early in inialization to setup + * Called from stm32_boardinitialize very early in initialization to setup * USB-related GPIO pins for the Olimex STM32 P407 board. * ****************************************************************************/ diff --git a/boards/arm/stm32/olimex-stm32-p407/src/stm32_usb.c b/boards/arm/stm32/olimex-stm32-p407/src/stm32_usb.c index c21de8ecaf..c5dacb1b6e 100644 --- a/boards/arm/stm32/olimex-stm32-p407/src/stm32_usb.c +++ b/boards/arm/stm32/olimex-stm32-p407/src/stm32_usb.c @@ -122,7 +122,7 @@ static int usbhost_waiter(int argc, char *argv[]) * Name: stm32_usb_configure * * Description: - * Called from stm32_usb_configure very early in inialization to setup + * Called from stm32_usb_configure very early in initialization to setup * USB-related GPIO pins for the Olimex STM32 P407 board. * ****************************************************************************/ diff --git a/boards/arm/stm32/olimexino-stm32/include/board.h b/boards/arm/stm32/olimexino-stm32/include/board.h index 2a127be2d8..ea13e6ab4a 100644 --- a/boards/arm/stm32/olimexino-stm32/include/board.h +++ b/boards/arm/stm32/olimexino-stm32/include/board.h @@ -53,7 +53,7 @@ #define STM32_LSE_FREQUENCY 32768 /* PLL source is HSE/1, - * PLL multipler is 9: + * PLL multiplier is 9: * PLL frequency is 8MHz (XTAL) x 9 = 72MHz */ diff --git a/boards/arm/stm32/olimexino-stm32/src/stm32_composite.c b/boards/arm/stm32/olimexino-stm32/src/stm32_composite.c index 4d096e4d65..343289871e 100644 --- a/boards/arm/stm32/olimexino-stm32/src/stm32_composite.c +++ b/boards/arm/stm32/olimexino-stm32/src/stm32_composite.c @@ -161,7 +161,7 @@ static int board_mscclassobject(int minor, * form the composite device logic. * * Input Parameters: - * classdev - The class driver instrance previously give to the composite + * classdev - The class driver instance previously given to the composite * driver by board_mscclassobject(). * * Returned Value: diff --git a/boards/arm/stm32/omnibusf4/src/stm32_usb.c b/boards/arm/stm32/omnibusf4/src/stm32_usb.c index 841c3eed7c..8c47891649 100644 --- a/boards/arm/stm32/omnibusf4/src/stm32_usb.c +++ b/boards/arm/stm32/omnibusf4/src/stm32_usb.c @@ -122,7 +122,7 @@ static int usbhost_waiter(int argc, char *argv[]) * Name: stm32_usbinitialize * * Description: - * Called from stm32_usbinitialize very early in inialization to setup + * Called from stm32_usbinitialize very early in initialization to setup * USB-related GPIO pins for the Omnibusf4 board. * ****************************************************************************/ diff --git a/boards/arm/stm32/photon/src/stm32_usb.c b/boards/arm/stm32/photon/src/stm32_usb.c index 9468fed49c..9d87f81ac0 100644 --- a/boards/arm/stm32/photon/src/stm32_usb.c +++ b/boards/arm/stm32/photon/src/stm32_usb.c @@ -39,7 +39,7 @@ * Name: stm32_usbinitialize * * Description: - * Called from stm32_usbinitialize very early in inialization to setup + * Called from stm32_usbinitialize very early in initialization to setup * USB-related GPIO pins for the Photon board. * ****************************************************************************/ diff --git a/boards/arm/stm32/shenzhou/src/stm32_ili93xx.c b/boards/arm/stm32/shenzhou/src/stm32_ili93xx.c index c7c72f3c4f..ead1d900f7 100644 --- a/boards/arm/stm32/shenzhou/src/stm32_ili93xx.c +++ b/boards/arm/stm32/shenzhou/src/stm32_ili93xx.c @@ -1400,7 +1400,7 @@ static void stm32_lcd9300init(struct stm32_dev_s *priv, stm32_writereg(priv, LCD_REG_96, 0x2700); /* Driver Output Control */ stm32_writereg(priv, LCD_REG_97, 0x0001); /* Driver Output Control */ - stm32_writereg(priv, LCD_REG_106, 0x0000); /* Vertical Srcoll Control */ + stm32_writereg(priv, LCD_REG_106, 0x0000); /* Vertical Scroll Control */ stm32_writereg(priv, LCD_REG_128, 0x0000); /* Display Position? Partial Display 1 */ stm32_writereg(priv, LCD_REG_129, 0x0000); /* RAM Address Start? Partial Display 1 */ diff --git a/boards/arm/stm32/shenzhou/src/stm32_usb.c b/boards/arm/stm32/shenzhou/src/stm32_usb.c index 3f9b7efffb..03d3dab470 100644 --- a/boards/arm/stm32/shenzhou/src/stm32_usb.c +++ b/boards/arm/stm32/shenzhou/src/stm32_usb.c @@ -126,7 +126,7 @@ static int usbhost_waiter(int argc, char *argv[]) * Name: stm32_usbinitialize * * Description: - * Called from stm32_usbinitialize very early in inialization to setup + * Called from stm32_usbinitialize very early in initialization to setup * USB-related GPIO pins for the STM3240G-EVAL board. * ****************************************************************************/ diff --git a/boards/arm/stm32/stm3210e-eval/Kconfig b/boards/arm/stm32/stm3210e-eval/Kconfig index b5666cd757..25fc9b765d 100644 --- a/boards/arm/stm32/stm3210e-eval/Kconfig +++ b/boards/arm/stm32/stm3210e-eval/Kconfig @@ -28,7 +28,7 @@ config STM3210E_LCD_PWM depends on STM3210E_LCD_BACKLIGHT && STM32_TIM1 ---help--- If STM32_TIM1 is also defined, then an adjustable backlight will be - provided using timer 1 to generate various pulse widthes. The + provided using timer 1 to generate various pulse widths. The granularity of the settings is determined by LCD_MAXPOWER. If STM3210E_LCD_PWM (or STM32_TIM1) is not defined, then a simple on/off backlight is provided. diff --git a/boards/arm/stm32/stm3210e-eval/include/board.h b/boards/arm/stm32/stm3210e-eval/include/board.h index bbbfb73d8d..49ffd9d730 100644 --- a/boards/arm/stm32/stm3210e-eval/include/board.h +++ b/boards/arm/stm32/stm3210e-eval/include/board.h @@ -48,7 +48,7 @@ #define STM32_BOARD_XTAL 8000000ul -/* PLL source is HSE/1, PLL multipler is 9: +/* PLL source is HSE/1, PLL multiplier is 9: * PLL frequency is 8MHz (XTAL) x 9 = 72MHz */ diff --git a/boards/arm/stm32/stm3210e-eval/src/stm32_composite.c b/boards/arm/stm32/stm3210e-eval/src/stm32_composite.c index 2aee0f4261..ea8a8c1577 100644 --- a/boards/arm/stm32/stm3210e-eval/src/stm32_composite.c +++ b/boards/arm/stm32/stm3210e-eval/src/stm32_composite.c @@ -156,7 +156,7 @@ static int board_mscclassobject(int minor, * that is called form the composite device logic. * * Input Parameters: - * classdev - The class driver instrance previously give to the composite + * classdev - The class driver instance previously given to the composite * driver by board_mscclassobject(). * * Returned Value: diff --git a/boards/arm/stm32/stm3210e-eval/src/stm32_extmem.c b/boards/arm/stm32/stm3210e-eval/src/stm32_extmem.c index 76579875a6..61e185f5c7 100644 --- a/boards/arm/stm32/stm3210e-eval/src/stm32_extmem.c +++ b/boards/arm/stm32/stm3210e-eval/src/stm32_extmem.c @@ -99,7 +99,7 @@ const uint16_t g_commonconfig[NCOMMON_CONFIG] = GPIO_NPS_D8, GPIO_NPS_D9, GPIO_NPS_D10, GPIO_NPS_D11, GPIO_NPS_D12, GPIO_NPS_D13, GPIO_NPS_D14, GPIO_NPS_D15, - /* NOE, NWE */ + /* NOE, NWE */ GPIO_NPS_NOE, GPIO_NPS_NWE }; diff --git a/boards/arm/stm32/stm3210e-eval/src/stm32_lcd.c b/boards/arm/stm32/stm3210e-eval/src/stm32_lcd.c index 2a919d7ae3..5b657569fa 100644 --- a/boards/arm/stm32/stm3210e-eval/src/stm32_lcd.c +++ b/boards/arm/stm32/stm3210e-eval/src/stm32_lcd.c @@ -1031,7 +1031,7 @@ static int stm3210e_setpower(struct lcd_dev_s *dev, int power) power = CONFIG_LCD_MAXPOWER; } - /* Caclulate the new backlight duty. It is a faction of the timer1 + /* Calculate the new backlight duty. It is a faction of the timer1 * period based on the ration of the current power setting to the * maximum power setting. */ @@ -1112,7 +1112,7 @@ static int stm3210e_setcontrast(struct lcd_dev_s *dev, unsigned int contrast) * Input Parameters: * * cb - Returned to the driver. The driver version of the callback - * strucure may include additional, driver-specific state data at + * structure may include additional, driver-specific state data at * the end of the structure. * * pmstate - Identifies the new PM state @@ -1240,7 +1240,7 @@ static void stm3210e_pm_notify(struct pm_callback_s *cb, int domain, * Input Parameters: * * cb - Returned to the driver. The driver version of the callback - * strucure may include additional, driver-specific state data at + * structure may include additional, driver-specific state data at * the end of the structure. * * pmstate - Identifies the new PM state diff --git a/boards/arm/stm32/stm3220g-eval/src/stm3220g-eval.h b/boards/arm/stm32/stm3220g-eval/src/stm3220g-eval.h index 2ca9823ee2..7908e0a422 100644 --- a/boards/arm/stm32/stm3220g-eval/src/stm3220g-eval.h +++ b/boards/arm/stm32/stm3220g-eval/src/stm3220g-eval.h @@ -230,7 +230,7 @@ void weak_function stm32_spidev_initialize(void); * Name: stm32_usbinitialize * * Description: - * Called from stm32_usbinitialize very early in inialization to setup + * Called from stm32_usbinitialize very early in initialization to setup * USB-related GPIO pins for the STM3220G-EVAL board. * ****************************************************************************/ diff --git a/boards/arm/stm32/stm3220g-eval/src/stm32_boot.c b/boards/arm/stm32/stm3220g-eval/src/stm32_boot.c index 1893ee04d7..b95862e74f 100644 --- a/boards/arm/stm32/stm3220g-eval/src/stm32_boot.c +++ b/boards/arm/stm32/stm3220g-eval/src/stm32_boot.c @@ -79,7 +79,7 @@ void stm32_boardinitialize(void) /* Initialize USB if the 1) OTG FS controller is in the configuration and * 2) the weak function stm32_usbinitialize() has been brought into the * build. - * Presumeably either CONFIG_USBDEV or CONFIG_USBHOST is also selected. + * Presumably either CONFIG_USBDEV or CONFIG_USBHOST is also selected. */ #ifdef CONFIG_STM32_OTGFS diff --git a/boards/arm/stm32/stm3220g-eval/src/stm32_usb.c b/boards/arm/stm32/stm3220g-eval/src/stm32_usb.c index ebb7617bf9..a37272237b 100644 --- a/boards/arm/stm32/stm3220g-eval/src/stm32_usb.c +++ b/boards/arm/stm32/stm3220g-eval/src/stm32_usb.c @@ -126,7 +126,7 @@ static int usbhost_waiter(int argc, char *argv[]) * Name: stm32_usbinitialize * * Description: - * Called from stm32_usbinitialize very early in inialization to setup + * Called from stm32_usbinitialize very early in initialization to setup * USB-related GPIO pins for the STM3220G-EVAL board. * ****************************************************************************/ diff --git a/boards/arm/stm32/stm3240g-eval/src/stm3240g-eval.h b/boards/arm/stm32/stm3240g-eval/src/stm3240g-eval.h index e622004797..8b7b7bc96a 100644 --- a/boards/arm/stm32/stm3240g-eval/src/stm3240g-eval.h +++ b/boards/arm/stm32/stm3240g-eval/src/stm3240g-eval.h @@ -247,7 +247,7 @@ void weak_function stm32_spidev_initialize(void); * Name: stm32_usbinitialize * * Description: - * Called from stm32_usbinitialize very early in inialization to setup + * Called from stm32_usbinitialize very early in initialization to setup * USB-related GPIO pins for the STM3240G-EVAL board. * ****************************************************************************/ diff --git a/boards/arm/stm32/stm3240g-eval/src/stm32_usb.c b/boards/arm/stm32/stm3240g-eval/src/stm32_usb.c index cfc981be73..b475990542 100644 --- a/boards/arm/stm32/stm3240g-eval/src/stm32_usb.c +++ b/boards/arm/stm32/stm3240g-eval/src/stm32_usb.c @@ -126,7 +126,7 @@ static int usbhost_waiter(int argc, char *argv[]) * Name: stm32_usbinitialize * * Description: - * Called from stm32_usbinitialize very early in inialization to setup + * Called from stm32_usbinitialize very early in initialization to setup * USB-related GPIO pins for the STM3240G-EVAL board. * ****************************************************************************/ diff --git a/boards/arm/stm32/stm32_tiny/include/board.h b/boards/arm/stm32/stm32_tiny/include/board.h index 0deb9542d0..c6cbb86049 100644 --- a/boards/arm/stm32/stm32_tiny/include/board.h +++ b/boards/arm/stm32/stm32_tiny/include/board.h @@ -42,7 +42,7 @@ #define STM32_BOARD_XTAL 8000000ul -/* PLL source is HSE/1, PLL multipler is 9: PLL frequency is +/* PLL source is HSE/1, PLL multiplier is 9: PLL frequency is * 8MHz (XTAL) x 9 = 72MHz */ diff --git a/boards/arm/stm32/stm32f334-disco/include/board.h b/boards/arm/stm32/stm32f334-disco/include/board.h index 27aefa27d0..fabc9f6385 100644 --- a/boards/arm/stm32/stm32f334-disco/include/board.h +++ b/boards/arm/stm32/stm32f334-disco/include/board.h @@ -53,7 +53,7 @@ #define STM32_HSE_FREQUENCY STM32_BOARD_XTAL #define STM32_LSE_FREQUENCY 32768 /* X2 on board */ -/* PLL source is HSE/1, PLL multipler is 9: +/* PLL source is HSE/1, PLL multiplier is 9: * PLL frequency is 8MHz (XTAL) x 9 = 72MHz */ @@ -202,8 +202,8 @@ * - Reset HRTIM TIMC output 1 on HRTIM EEV2. * - HRTIM EEV2 is connected to COMP4 output which works as current limit. * - COMP4 inverting input is connected to DAC1CH1 output. - * - COMP4 non-inverting input (PB1) is connceted to current sense - * resitor (1 Ohm). + * - COMP4 non-inverting input (PB1) is connected to current sense + * resistor (1 Ohm). * - DAC1CH1 DMA transfer is triggered by HRTIM TIMC events, which is used * to provide slope compensation. */ diff --git a/boards/arm/stm32/stm32f334-disco/src/stm32_smps.c b/boards/arm/stm32/stm32f334-disco/src/stm32_smps.c index afe5716cd2..d5cc74fb3d 100644 --- a/boards/arm/stm32/stm32f334-disco/src/stm32_smps.c +++ b/boards/arm/stm32/stm32f334-disco/src/stm32_smps.c @@ -683,7 +683,7 @@ static int smps_state_get(struct smps_dev_s *dev, { struct smps_s *smps = (struct smps_s *)dev->priv; - /* Copy localy stored feedbacks data to status structure */ + /* Copy locally stored feedbacks data to status structure */ smps->state.fb.v_in = g_smps_priv.v_in; smps->state.fb.v_out = g_smps_priv.v_out; diff --git a/boards/arm/stm32/stm32f3discovery/include/board.h b/boards/arm/stm32/stm32f3discovery/include/board.h index 1bd85cb90a..099801796f 100644 --- a/boards/arm/stm32/stm32f3discovery/include/board.h +++ b/boards/arm/stm32/stm32f3discovery/include/board.h @@ -53,7 +53,7 @@ #define STM32_LSE_FREQUENCY 32768 /* X2 on board */ /* PLL source is HSE/1, - * PLL multipler is 9: + * PLL multiplier is 9: * PLL frequency is 8MHz (XTAL) x 9 = 72MHz */ diff --git a/boards/arm/stm32/stm32f3discovery/src/stm32_boot.c b/boards/arm/stm32/stm32f3discovery/src/stm32_boot.c index 9529e7d501..64983a56f8 100644 --- a/boards/arm/stm32/stm32f3discovery/src/stm32_boot.c +++ b/boards/arm/stm32/stm32f3discovery/src/stm32_boot.c @@ -64,7 +64,7 @@ void stm32_boardinitialize(void) /* Initialize USB if the 1) USB device controller is in the configuration * and 2) disabled, and 3) the weak function stm32_usbinitialize() has - * been brought into the build. Presumeably either CONFIG_USBDEV is also + * been brought into the build. Presumably either CONFIG_USBDEV is also * selected. */ diff --git a/boards/arm/stm32/stm32f3discovery/src/stm32_usb.c b/boards/arm/stm32/stm32f3discovery/src/stm32_usb.c index 116eaeec79..0301cdd42a 100644 --- a/boards/arm/stm32/stm32f3discovery/src/stm32_usb.c +++ b/boards/arm/stm32/stm32f3discovery/src/stm32_usb.c @@ -69,7 +69,7 @@ * Name: stm32_usbinitialize * * Description: - * Called from stm32_usbinitialize very early in inialization to setup + * Called from stm32_usbinitialize very early in initialization to setup * USB-related GPIO pins for the STM32F3Discovery board. * ****************************************************************************/ diff --git a/boards/arm/stm32/stm32f3discovery/src/stm32f3discovery.h b/boards/arm/stm32/stm32f3discovery/src/stm32f3discovery.h index a045d52e39..99de0fa2dc 100644 --- a/boards/arm/stm32/stm32f3discovery/src/stm32f3discovery.h +++ b/boards/arm/stm32/stm32f3discovery/src/stm32f3discovery.h @@ -168,7 +168,7 @@ void weak_function stm32_spidev_initialize(void); * Name: stm32_usbinitialize * * Description: - * Called from stm32_usbinitialize very early in inialization to setup + * Called from stm32_usbinitialize very early in initialization to setup * USB-related GPIO pins for the STM32F3Discovery board. * ****************************************************************************/ diff --git a/boards/arm/stm32/stm32f401rc-rs485/include/board.h b/boards/arm/stm32/stm32f401rc-rs485/include/board.h index 40ecbf58b0..a51f7f1bc2 100644 --- a/boards/arm/stm32/stm32f401rc-rs485/include/board.h +++ b/boards/arm/stm32/stm32f401rc-rs485/include/board.h @@ -38,7 +38,7 @@ /* Clocking *****************************************************************/ -/* The STM32F401RC-RS485 uses an external 32kHz cristal (X2) to enable HSE +/* The STM32F401RC-RS485 uses an external 32kHz crystal (X2) to enable HSE * clock. * * System Clock source : PLL (HSI) diff --git a/boards/arm/stm32/stm32f401rc-rs485/src/stm32_usb.c b/boards/arm/stm32/stm32f401rc-rs485/src/stm32_usb.c index c1b7d28088..76c92033d0 100644 --- a/boards/arm/stm32/stm32f401rc-rs485/src/stm32_usb.c +++ b/boards/arm/stm32/stm32f401rc-rs485/src/stm32_usb.c @@ -56,7 +56,7 @@ * Name: stm32_usb_configure * * Description: - * Called from stm32_boardinitialize very early in inialization to setup + * Called from stm32_boardinitialize very early in initialization to setup * USB-related GPIO pins for the Olimex STM32 P407 board. * ****************************************************************************/ diff --git a/boards/arm/stm32/stm32f411-minimum/src/stm32_composite.c b/boards/arm/stm32/stm32f411-minimum/src/stm32_composite.c index 4e9e7ad840..82ca957b20 100644 --- a/boards/arm/stm32/stm32f411-minimum/src/stm32_composite.c +++ b/boards/arm/stm32/stm32f411-minimum/src/stm32_composite.c @@ -128,7 +128,7 @@ static int board_mscclassobject(int minor, * that is called form the composite device logic. * * Input Parameters: - * classdev - The class driver instrance previously give to the composite + * classdev - The class driver instance previously given to the composite * driver by board_mscclassobject(). * * Returned Value: diff --git a/boards/arm/stm32/stm32f411-minimum/src/stm32_usb.c b/boards/arm/stm32/stm32f411-minimum/src/stm32_usb.c index f3c83d76eb..9fe02431e9 100644 --- a/boards/arm/stm32/stm32f411-minimum/src/stm32_usb.c +++ b/boards/arm/stm32/stm32f411-minimum/src/stm32_usb.c @@ -119,7 +119,7 @@ static int usbhost_waiter(int argc, char *argv[]) * Name: stm32_usbinitialize * * Description: - * Called from stm32_boardinitialize very early in inialization to setup + * Called from stm32_boardinitialize very early in initialization to setup * USB-related GPIO pins for the WeAct Studio MiniF4 board. * ****************************************************************************/ diff --git a/boards/arm/stm32/stm32f411e-disco/src/stm32_usb.c b/boards/arm/stm32/stm32f411e-disco/src/stm32_usb.c index 6a4b43fea8..ae8450bc00 100644 --- a/boards/arm/stm32/stm32f411e-disco/src/stm32_usb.c +++ b/boards/arm/stm32/stm32f411e-disco/src/stm32_usb.c @@ -135,7 +135,7 @@ static int usbhost_waiter(int argc, char *argv[]) * Name: stm32_usbinitialize * * Description: - * Called from stm32_usbinitialize very early in inialization to setup + * Called from stm32_usbinitialize very early in initialization to setup * USB-related GPIO pins for the STM32F411 board. * ****************************************************************************/ diff --git a/boards/arm/stm32/stm32f429i-disco/src/stm32_usb.c b/boards/arm/stm32/stm32f429i-disco/src/stm32_usb.c index 215e3e83fc..a923bc0fe8 100644 --- a/boards/arm/stm32/stm32f429i-disco/src/stm32_usb.c +++ b/boards/arm/stm32/stm32f429i-disco/src/stm32_usb.c @@ -122,7 +122,7 @@ static int usbhost_waiter(int argc, char *argv[]) * Name: stm32_usbinitialize * * Description: - * Called from stm32_usbinitialize very early in inialization to setup + * Called from stm32_usbinitialize very early in initialization to setup * USB-related GPIO pins for the STM32F4Discovery board. * ****************************************************************************/ diff --git a/boards/arm/stm32/stm32f429i-disco/src/stm32f429i-disco.h b/boards/arm/stm32/stm32f429i-disco/src/stm32f429i-disco.h index f1310e543b..06d6c155a3 100644 --- a/boards/arm/stm32/stm32f429i-disco/src/stm32f429i-disco.h +++ b/boards/arm/stm32/stm32f429i-disco/src/stm32f429i-disco.h @@ -220,8 +220,8 @@ void weak_function stm32_spidev_initialize(void); * Name: stm32_usbinitialize * * Description: - * Called from stm32_usbinitialize very early in inialization to setup USB- - * related GPIO pins for the STM32F429Discovery board. + * Called from stm32_usbinitialize very early in initialization to setup + * USB-related GPIO pins for the STM32F429Discovery board. * ****************************************************************************/ diff --git a/boards/arm/stm32/stm32f4discovery/src/CMakeLists.txt b/boards/arm/stm32/stm32f4discovery/src/CMakeLists.txt index da35accdab..abb7ef0ecf 100644 --- a/boards/arm/stm32/stm32f4discovery/src/CMakeLists.txt +++ b/boards/arm/stm32/stm32f4discovery/src/CMakeLists.txt @@ -176,7 +176,7 @@ target_sources(board PRIVATE ${SRCS}) # TODO: make this the default and then allow boards to redefine set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") -# TODO:move this to apropriate arch/toolchain level +# TODO:move this to appropriate arch/toolchain level set_property( GLOBAL APPEND PROPERTY COMPILE_OPTIONS $<$:-fno-strict-aliasing diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32_composite.c b/boards/arm/stm32/stm32f4discovery/src/stm32_composite.c index a42aae5c2d..2662126d09 100644 --- a/boards/arm/stm32/stm32f4discovery/src/stm32_composite.c +++ b/boards/arm/stm32/stm32f4discovery/src/stm32_composite.c @@ -139,7 +139,7 @@ static int board_mscclassobject(int minor, * that is called form the composite device logic. * * Input Parameters: - * classdev - The class driver instrance previously give to the composite + * classdev - The class driver instance previously given to the composite * driver by board_mscclassobject(). * * Returned Value: diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32_usb.c b/boards/arm/stm32/stm32f4discovery/src/stm32_usb.c index fc8179be95..a2405898e8 100644 --- a/boards/arm/stm32/stm32f4discovery/src/stm32_usb.c +++ b/boards/arm/stm32/stm32f4discovery/src/stm32_usb.c @@ -122,7 +122,7 @@ static int usbhost_waiter(int argc, char *argv[]) * Name: stm32_usbinitialize * * Description: - * Called from stm32_usbinitialize very early in inialization to setup + * Called from stm32_usbinitialize very early in initialization to setup * USB-related GPIO pins for the STM32F4Discovery board. * ****************************************************************************/ diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32f4discovery.h b/boards/arm/stm32/stm32f4discovery/src/stm32f4discovery.h index 6a8ff65a67..035d87a14e 100644 --- a/boards/arm/stm32/stm32f4discovery/src/stm32f4discovery.h +++ b/boards/arm/stm32/stm32f4discovery/src/stm32f4discovery.h @@ -203,7 +203,7 @@ #elif defined(CONFIG_STM32_UART8_HCIUART) # define HCIUART_SERDEV HCIUART8 #else -# error No HCI UART specifified +# error No HCI UART specified #endif /* STM32F4 Discovery GPIOs **************************************************/ diff --git a/boards/arm/stm32/stm32ldiscovery/include/board.h b/boards/arm/stm32/stm32ldiscovery/include/board.h index 6a29b90109..1545f8bead 100644 --- a/boards/arm/stm32/stm32ldiscovery/include/board.h +++ b/boards/arm/stm32/stm32ldiscovery/include/board.h @@ -74,7 +74,7 @@ /* PLL Configuration * * - PLL source is HSI -> 16MHz input (nominal) - * - PLL multipler is 6 -> 96MHz PLL VCO clock output (for USB) + * - PLL multiplier is 6 -> 96MHz PLL VCO clock output (for USB) * - PLL output divider 3 -> 32MHz divided down PLL VCO clock output * * Resulting SYSCLK frequency is 16MHz x 6 / 3 = 32MHz @@ -114,9 +114,9 @@ #define STM32_SYSCLK_SW RCC_CFGR_SW_PLL /* Use the PLL as the SYSCLK */ #define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL #ifdef CONFIG_STM32_USB -# define STM32_SYSCLK_FREQUENCY (STM32_PLL_FREQUENCY/3) /* SYSCLK frequence is 96MHz/PLLDIV = 32MHz */ +# define STM32_SYSCLK_FREQUENCY (STM32_PLL_FREQUENCY/3) /* SYSCLK frequency is 96MHz/PLLDIV = 32MHz */ #else -# define STM32_SYSCLK_FREQUENCY (STM32_PLL_FREQUENCY/2) /* SYSCLK frequence is 64MHz/PLLDIV = 32MHz */ +# define STM32_SYSCLK_FREQUENCY (STM32_PLL_FREQUENCY/2) /* SYSCLK frequency is 64MHz/PLLDIV = 32MHz */ #endif /* AHB clock (HCLK) is SYSCLK (32MHz) */ @@ -256,7 +256,7 @@ # define GPIO_USART2_RX GPIO_USART2_RX_1 /* PA3 */ # define GPIO_USART2_TX GPIO_USART2_TX_1 /* PA2 */ -/* Arbirtrarily select PB10 and PB11 */ +/* Arbitrarily select PB10 and PB11 */ # define GPIO_USART3_RX GPIO_USART3_RX_1 /* PB11 */ # define GPIO_USART3_TX GPIO_USART3_TX_1 /* PB10 */ diff --git a/boards/arm/stm32/stm32ldiscovery/src/stm32_lcd.c b/boards/arm/stm32/stm32ldiscovery/src/stm32_lcd.c index ce238aae98..4247f3d051 100644 --- a/boards/arm/stm32/stm32ldiscovery/src/stm32_lcd.c +++ b/boards/arm/stm32/stm32ldiscovery/src/stm32_lcd.c @@ -605,7 +605,7 @@ static inline uint16_t slcd_mapch(uint8_t ch) return 0x0000; } - /* Handle space and the first block of puncutation */ + /* Handle space and the first block of punctuation */ if (ch < ASCII_0) { @@ -619,7 +619,7 @@ static inline uint16_t slcd_mapch(uint8_t ch) return g_slcdnummap[(int)ch - ASCII_0]; } - /* Handle the next block of puncutation */ + /* Handle the next block of punctuation */ else if (ch < ASCII_A) { @@ -633,7 +633,7 @@ static inline uint16_t slcd_mapch(uint8_t ch) return g_slcdalphamap[(int)ch - ASCII_A]; } - /* Handle the next block of puncutation */ + /* Handle the next block of punctuation */ else if (ch < ASCII_a) { @@ -647,7 +647,7 @@ static inline uint16_t slcd_mapch(uint8_t ch) return g_slcdalphamap[(int)ch - ASCII_a]; } - /* Handle the final block of puncutation */ + /* Handle the final block of punctuation */ else if (ch < ASCII_DEL) { diff --git a/boards/arm/stm32/viewtool-stm32f107/include/board-stm32f103vct6.h b/boards/arm/stm32/viewtool-stm32f107/include/board-stm32f103vct6.h index 31048d0a5d..3fa04fc724 100644 --- a/boards/arm/stm32/viewtool-stm32f107/include/board-stm32f103vct6.h +++ b/boards/arm/stm32/viewtool-stm32f107/include/board-stm32f103vct6.h @@ -44,7 +44,7 @@ #define STM32_BOARD_XTAL 8000000ul /* PLL source is HSE/1, - * PLL multipler is 9: + * PLL multiplier is 9: * PLL frequency is 8MHz (XTAL) x 9 = 72MHz */ diff --git a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/include/board.h b/boards/arm/stm32f0l0g0/b-l072z-lrwan1/include/board.h index 6a6b21bc33..3f7beb3cee 100644 --- a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/include/board.h +++ b/boards/arm/stm32f0l0g0/b-l072z-lrwan1/include/board.h @@ -53,7 +53,7 @@ #define STM32_HSE_FREQUENCY STM32_BOARD_XTAL #define STM32_LSE_FREQUENCY 32768 /* X2 on board */ -/* PLL source is HSI/1, PLL multipler is 4: +/* PLL source is HSI/1, PLL multiplier is 4: * PLL frequency is 16MHz (XTAL) x 4 = 64MHz */ diff --git a/boards/arm/stm32f0l0g0/nucleo-f072rb/include/board.h b/boards/arm/stm32f0l0g0/nucleo-f072rb/include/board.h index c53a7943dd..86fdd79d1c 100644 --- a/boards/arm/stm32f0l0g0/nucleo-f072rb/include/board.h +++ b/boards/arm/stm32f0l0g0/nucleo-f072rb/include/board.h @@ -73,7 +73,7 @@ * * - PLL source is HSI -> 8MHz input (nominal) * - PLL source predivider 2 -> 4MHz divided down PLL VCO clock output - * - PLL multipler is 12 -> 48MHz PLL VCO clock output (for USB) + * - PLL multiplier is 12 -> 48MHz PLL VCO clock output (for USB) * * Resulting SYSCLK frequency is 8MHz x 12 / 2 = 48MHz * diff --git a/boards/arm/stm32f0l0g0/nucleo-f072rb/src/stm32_bringup.c b/boards/arm/stm32f0l0g0/nucleo-f072rb/src/stm32_bringup.c index adcf51aff5..27b6b57587 100644 --- a/boards/arm/stm32f0l0g0/nucleo-f072rb/src/stm32_bringup.c +++ b/boards/arm/stm32f0l0g0/nucleo-f072rb/src/stm32_bringup.c @@ -85,7 +85,7 @@ int stm32_bringup(void) i2c = stm32_i2cbus_initialize(1); if (i2c == NULL) { - i2cerr("ERROR: Inialize I2C1: %d\n", ret); + i2cerr("ERROR: Initialize I2C1: %d\n", ret); } else { diff --git a/boards/arm/stm32f0l0g0/nucleo-f091rc/include/board.h b/boards/arm/stm32f0l0g0/nucleo-f091rc/include/board.h index c59896d54c..5fa08b552e 100644 --- a/boards/arm/stm32f0l0g0/nucleo-f091rc/include/board.h +++ b/boards/arm/stm32f0l0g0/nucleo-f091rc/include/board.h @@ -73,7 +73,7 @@ * * - PLL source is HSI -> 8MHz input (nominal) * - PLL source predivider 2 -> 4MHz divided down PLL VCO clock output - * - PLL multipler is 12 -> 48MHz PLL VCO clock output (for USB) + * - PLL multiplier is 12 -> 48MHz PLL VCO clock output (for USB) * * Resulting SYSCLK frequency is 8MHz x 12 / 2 = 48MHz * diff --git a/boards/arm/stm32f0l0g0/nucleo-l073rz/include/board.h b/boards/arm/stm32f0l0g0/nucleo-l073rz/include/board.h index 308561f5ec..8a6064572a 100644 --- a/boards/arm/stm32f0l0g0/nucleo-l073rz/include/board.h +++ b/boards/arm/stm32f0l0g0/nucleo-l073rz/include/board.h @@ -54,7 +54,7 @@ #define STM32_HSE_FREQUENCY STM32_BOARD_XTAL #define STM32_LSE_FREQUENCY 32768 /* X2 on board */ -/* PLL source is HSE/1, PLL multipler is 8: +/* PLL source is HSE/1, PLL multiplier is 8: * PLL frequency is 8MHz (XTAL) x 8 = 64MHz */ diff --git a/boards/arm/stm32f0l0g0/stm32f051-discovery/include/board.h b/boards/arm/stm32f0l0g0/stm32f051-discovery/include/board.h index c6f36db846..0eb3c07c02 100644 --- a/boards/arm/stm32f0l0g0/stm32f051-discovery/include/board.h +++ b/boards/arm/stm32f0l0g0/stm32f051-discovery/include/board.h @@ -73,7 +73,7 @@ * * - PLL source is HSI -> 8MHz input (nominal) * - PLL source predivider 2 -> 4MHz divided down PLL VCO clock output - * - PLL multipler is 12 -> 48MHz PLL VCO clock output (for USB) + * - PLL multiplier is 12 -> 48MHz PLL VCO clock output (for USB) * * Resulting SYSCLK frequency is 8MHz x 12 / 2 = 48MHz * diff --git a/boards/arm/stm32f0l0g0/stm32f072-discovery/include/board.h b/boards/arm/stm32f0l0g0/stm32f072-discovery/include/board.h index 00c651a1c3..fbd2d98fa8 100644 --- a/boards/arm/stm32f0l0g0/stm32f072-discovery/include/board.h +++ b/boards/arm/stm32f0l0g0/stm32f072-discovery/include/board.h @@ -73,7 +73,7 @@ * * - PLL source is HSI -> 8MHz input (nominal) * - PLL source predivider 2 -> 4MHz divided down PLL VCO clock output - * - PLL multipler is 12 -> 48MHz PLL VCO clock output (for USB) + * - PLL multiplier is 12 -> 48MHz PLL VCO clock output (for USB) * * Resulting SYSCLK frequency is 8MHz x 12 / 2 = 48MHz * diff --git a/boards/arm/stm32f0l0g0/stm32l0538-disco/include/board.h b/boards/arm/stm32f0l0g0/stm32l0538-disco/include/board.h index 0247a6252d..d892396c5c 100644 --- a/boards/arm/stm32f0l0g0/stm32l0538-disco/include/board.h +++ b/boards/arm/stm32f0l0g0/stm32l0538-disco/include/board.h @@ -49,7 +49,7 @@ #define STM32_HSE_FREQUENCY STM32_BOARD_XTAL #define STM32_LSE_FREQUENCY 32768 /* X2 on board */ -/* PLL source is HSE/1, PLL multipler is 8: +/* PLL source is HSE/1, PLL multiplier is 8: * PLL frequency is 8MHz (XTAL) x 8 = 64MHz */ diff --git a/boards/arm/stm32f7/common/src/stm32_cansock_setup.c b/boards/arm/stm32f7/common/src/stm32_cansock_setup.c index 0958e09b59..81715c3462 100644 --- a/boards/arm/stm32f7/common/src/stm32_cansock_setup.c +++ b/boards/arm/stm32f7/common/src/stm32_cansock_setup.c @@ -37,7 +37,7 @@ /* Configuration ************************************************************/ #if !defined(CONFIG_STM32F7_CAN1) && !defined(CONFIG_STM32F7_CAN2) -# error "No CAN is enable. Please eneable at least one CAN device" +# error "No CAN is enable. Please enable at least one CAN device" #endif /**************************************************************************** diff --git a/boards/arm/stm32f7/nucleo-f722ze/src/nucleo-f722ze.h b/boards/arm/stm32f7/nucleo-f722ze/src/nucleo-f722ze.h index 2102d8e5be..af3cb8e902 100644 --- a/boards/arm/stm32f7/nucleo-f722ze/src/nucleo-f722ze.h +++ b/boards/arm/stm32f7/nucleo-f722ze/src/nucleo-f722ze.h @@ -265,7 +265,7 @@ int stm32_sdio_initialize(void); * Name: stm32_usbinitialize * * Description: - * Called from stm32_usbinitialize very early in inialization to setup + * Called from stm32_usbinitialize very early in initialization to setup * USB-related GPIO pins for the nucleo-f722ze board. * ****************************************************************************/ diff --git a/boards/arm/stm32f7/nucleo-f722ze/src/stm32_composite.c b/boards/arm/stm32f7/nucleo-f722ze/src/stm32_composite.c index 218aec5c64..78a9e6fd98 100644 --- a/boards/arm/stm32f7/nucleo-f722ze/src/stm32_composite.c +++ b/boards/arm/stm32f7/nucleo-f722ze/src/stm32_composite.c @@ -139,7 +139,7 @@ static int board_mscclassobject(int minor, * that is called form the composite device logic. * * Input Parameters: - * classdev - The class driver instrance previously give to the composite + * classdev - The class driver instance previously given to the composite * driver by board_mscclassobject(). * * Returned Value: diff --git a/boards/arm/stm32f7/nucleo-f722ze/src/stm32_usb.c b/boards/arm/stm32f7/nucleo-f722ze/src/stm32_usb.c index cb6766206c..aba8793c07 100644 --- a/boards/arm/stm32f7/nucleo-f722ze/src/stm32_usb.c +++ b/boards/arm/stm32f7/nucleo-f722ze/src/stm32_usb.c @@ -123,7 +123,7 @@ static int usbhost_waiter(int argc, char *argv[]) * Name: stm32_usbinitialize * * Description: - * Called from stm32_usbinitialize very early in inialization to setup + * Called from stm32_usbinitialize very early in initialization to setup * USB-related GPIO pins for the nucleo-f722ze board. * ****************************************************************************/ diff --git a/boards/arm/stm32f7/nucleo-f746zg/src/nucleo-f746zg.h b/boards/arm/stm32f7/nucleo-f746zg/src/nucleo-f746zg.h index 9d949b7be2..753ec9a2c3 100644 --- a/boards/arm/stm32f7/nucleo-f746zg/src/nucleo-f746zg.h +++ b/boards/arm/stm32f7/nucleo-f746zg/src/nucleo-f746zg.h @@ -278,7 +278,7 @@ int stm32_sdio_initialize(void); * Name: stm32_usbinitialize * * Description: - * Called from stm32_usbinitialize very early in inialization to setup + * Called from stm32_usbinitialize very early in initialization to setup * USB-related GPIO pins for the nucleo-f746zg board. * ****************************************************************************/ diff --git a/boards/arm/stm32f7/nucleo-f746zg/src/stm32_composite.c b/boards/arm/stm32f7/nucleo-f746zg/src/stm32_composite.c index 113996f35d..30affdb3dd 100644 --- a/boards/arm/stm32f7/nucleo-f746zg/src/stm32_composite.c +++ b/boards/arm/stm32f7/nucleo-f746zg/src/stm32_composite.c @@ -139,7 +139,7 @@ static int board_mscclassobject(int minor, * that is called form the composite device logic. * * Input Parameters: - * classdev - The class driver instrance previously give to the composite + * classdev - The class driver instance previously given to the composite * driver by board_mscclassobject(). * * Returned Value: diff --git a/boards/arm/stm32f7/nucleo-f746zg/src/stm32_usb.c b/boards/arm/stm32f7/nucleo-f746zg/src/stm32_usb.c index e95997f008..1af9a179d9 100644 --- a/boards/arm/stm32f7/nucleo-f746zg/src/stm32_usb.c +++ b/boards/arm/stm32f7/nucleo-f746zg/src/stm32_usb.c @@ -123,7 +123,7 @@ static int usbhost_waiter(int argc, char *argv[]) * Name: stm32_usbinitialize * * Description: - * Called from stm32_usbinitialize very early in inialization to setup + * Called from stm32_usbinitialize very early in initialization to setup * USB-related GPIO pins for the nucleo-f746zg board. * ****************************************************************************/ diff --git a/boards/arm/stm32f7/nucleo-f767zi/src/stm32_composite.c b/boards/arm/stm32f7/nucleo-f767zi/src/stm32_composite.c index 579045b80f..f6aae2d954 100644 --- a/boards/arm/stm32f7/nucleo-f767zi/src/stm32_composite.c +++ b/boards/arm/stm32f7/nucleo-f767zi/src/stm32_composite.c @@ -139,7 +139,7 @@ static int board_mscclassobject(int minor, * that is called form the composite device logic. * * Input Parameters: - * classdev - The class driver instrance previously give to the composite + * classdev - The class driver instance previously given to the composite * driver by board_mscclassobject(). * * Returned Value: diff --git a/boards/arm/stm32f7/nucleo-f767zi/src/stm32_usb.c b/boards/arm/stm32f7/nucleo-f767zi/src/stm32_usb.c index f49a7abd78..d08bdda592 100644 --- a/boards/arm/stm32f7/nucleo-f767zi/src/stm32_usb.c +++ b/boards/arm/stm32f7/nucleo-f767zi/src/stm32_usb.c @@ -123,7 +123,7 @@ static int usbhost_waiter(int argc, char *argv[]) * Name: stm32_usbinitialize * * Description: - * Called from stm32_usbinitialize very early in inialization to setup + * Called from stm32_usbinitialize very early in initialization to setup * USB-related GPIO pins for the nucleo-f767zi board. * ****************************************************************************/ diff --git a/boards/arm/stm32f7/stm32f746-ws/src/stm32_usb.c b/boards/arm/stm32f7/stm32f746-ws/src/stm32_usb.c index 2a04ec432d..31a2daf8cd 100644 --- a/boards/arm/stm32f7/stm32f746-ws/src/stm32_usb.c +++ b/boards/arm/stm32f7/stm32f746-ws/src/stm32_usb.c @@ -122,7 +122,7 @@ static int usbhost_waiter(int argc, char *argv[]) * Name: stm32_usbinitialize * * Description: - * Called from stm32_usbinitialize very early in inialization to setup + * Called from stm32_usbinitialize very early in initialization to setup * USB-related GPIO pins for the STM32F4Discovery board. * ****************************************************************************/ diff --git a/boards/arm/stm32f7/stm32f746g-disco/src/stm32_usb.c b/boards/arm/stm32f7/stm32f746g-disco/src/stm32_usb.c index fee23014ea..f309aa9d23 100644 --- a/boards/arm/stm32f7/stm32f746g-disco/src/stm32_usb.c +++ b/boards/arm/stm32f7/stm32f746g-disco/src/stm32_usb.c @@ -124,7 +124,7 @@ static int usbhost_waiter(int argc, char *argv[]) * Name: stm32_usbinitialize * * Description: - * Called from stm32_usbinitialize very early in inialization to setup + * Called from stm32_usbinitialize very early in initialization to setup * USB-related GPIO pins for the STM32F4Discovery board. * ****************************************************************************/ diff --git a/boards/arm/stm32f7/stm32f777zit6-meadow/src/stm32_composite.c b/boards/arm/stm32f7/stm32f777zit6-meadow/src/stm32_composite.c index cc0cf1db65..1c0056d7d9 100644 --- a/boards/arm/stm32f7/stm32f777zit6-meadow/src/stm32_composite.c +++ b/boards/arm/stm32f7/stm32f777zit6-meadow/src/stm32_composite.c @@ -139,7 +139,7 @@ static int board_mscclassobject(int minor, * that is called form the composite device logic. * * Input Parameters: - * classdev - The class driver instrance previously give to the composite + * classdev - The class driver instance previously given to the composite * driver by board_mscclassobject(). * * Returned Value: diff --git a/boards/arm/stm32f7/stm32f777zit6-meadow/src/stm32_usb.c b/boards/arm/stm32f7/stm32f777zit6-meadow/src/stm32_usb.c index b3448d41c2..db51d9a130 100644 --- a/boards/arm/stm32f7/stm32f777zit6-meadow/src/stm32_usb.c +++ b/boards/arm/stm32f7/stm32f777zit6-meadow/src/stm32_usb.c @@ -124,7 +124,7 @@ static int usbhost_waiter(int argc, char *argv[]) * Name: stm32_usbinitialize * * Description: - * Called from stm32_usbinitialize very early in inialization to setup + * Called from stm32_usbinitialize very early in initialization to setup * USB-related GPIO pins for the STM32F4Discovery board. * ****************************************************************************/ diff --git a/boards/arm/stm32h7/linum-stm32h753bi/include/board.h b/boards/arm/stm32h7/linum-stm32h753bi/include/board.h index 1f83359732..364659dfbe 100644 --- a/boards/arm/stm32h7/linum-stm32h753bi/include/board.h +++ b/boards/arm/stm32h7/linum-stm32h753bi/include/board.h @@ -530,7 +530,7 @@ * FMC_SDTR_TRCD - SDRAM common row cycle delay * FMC_SDTR_TWR - Write recovery time * FMC_SDTR_TRP - SDRAM common row percharge delay - * FMC_SDTR_TRC - Row to collumn delay + * FMC_SDTR_TRC - Row to column delay */ #define BOARD_FMC_SDTR1 (FMC_SDTR_TMRD(2)| /* tMRD = 2CLK */ \ diff --git a/boards/arm/stm32h7/linum-stm32h753bi/src/linum-stm32h753bi.h b/boards/arm/stm32h7/linum-stm32h753bi/src/linum-stm32h753bi.h index 0a77493a73..885910ba38 100644 --- a/boards/arm/stm32h7/linum-stm32h753bi/src/linum-stm32h753bi.h +++ b/boards/arm/stm32h7/linum-stm32h753bi/src/linum-stm32h753bi.h @@ -160,7 +160,7 @@ int stm32_bringup(void); * Name: stm32_usbinitialize * * Description: - * Called from stm32_usbinitialize very early in inialization to setup + * Called from stm32_usbinitialize very early in initialization to setup * USB-related GPIO pins for the LINUM-STM32H753BI board. * ****************************************************************************/ diff --git a/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_usb.c b/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_usb.c index 3b82375e1a..b675e52281 100644 --- a/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_usb.c +++ b/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_usb.c @@ -123,7 +123,7 @@ static int usbhost_waiter(int argc, char *argv[]) * Name: stm32_usbinitialize * * Description: - * Called from stm32_usbinitialize very early in inialization to setup + * Called from stm32_usbinitialize very early in initialization to setup * USB-related GPIO pins for the linum-stm32h753bi board. * ****************************************************************************/ diff --git a/boards/arm/stm32h7/nucleo-h743zi/src/nucleo-h743zi.h b/boards/arm/stm32h7/nucleo-h743zi/src/nucleo-h743zi.h index 4787d6d8a2..b9d0156998 100644 --- a/boards/arm/stm32h7/nucleo-h743zi/src/nucleo-h743zi.h +++ b/boards/arm/stm32h7/nucleo-h743zi/src/nucleo-h743zi.h @@ -287,7 +287,7 @@ int stm32_gpio_initialize(void); * Name: stm32_usbinitialize * * Description: - * Called from stm32_usbinitialize very early in inialization to setup + * Called from stm32_usbinitialize very early in initialization to setup * USB-related GPIO pins for the NUCLEO-H743ZI board. * ****************************************************************************/ diff --git a/boards/arm/stm32h7/nucleo-h743zi/src/stm32_composite.c b/boards/arm/stm32h7/nucleo-h743zi/src/stm32_composite.c index f4012951d9..b9bbad8833 100644 --- a/boards/arm/stm32h7/nucleo-h743zi/src/stm32_composite.c +++ b/boards/arm/stm32h7/nucleo-h743zi/src/stm32_composite.c @@ -139,7 +139,7 @@ static int board_mscclassobject(int minor, * that is called form the composite device logic. * * Input Parameters: - * classdev - The class driver instrance previously give to the composite + * classdev - The class driver instance previously given to the composite * driver by board_mscclassobject(). * * Returned Value: diff --git a/boards/arm/stm32h7/nucleo-h743zi/src/stm32_usb.c b/boards/arm/stm32h7/nucleo-h743zi/src/stm32_usb.c index 61761af590..57863e86a9 100644 --- a/boards/arm/stm32h7/nucleo-h743zi/src/stm32_usb.c +++ b/boards/arm/stm32h7/nucleo-h743zi/src/stm32_usb.c @@ -123,7 +123,7 @@ static int usbhost_waiter(int argc, char *argv[]) * Name: stm32_usbinitialize * * Description: - * Called from stm32_usbinitialize very early in inialization to setup + * Called from stm32_usbinitialize very early in initialization to setup * USB-related GPIO pins for the nucleo-144 board. * ****************************************************************************/ diff --git a/boards/arm/stm32h7/nucleo-h743zi2/src/nucleo-h743zi2.h b/boards/arm/stm32h7/nucleo-h743zi2/src/nucleo-h743zi2.h index 350947c5e2..db4af07cdc 100644 --- a/boards/arm/stm32h7/nucleo-h743zi2/src/nucleo-h743zi2.h +++ b/boards/arm/stm32h7/nucleo-h743zi2/src/nucleo-h743zi2.h @@ -157,7 +157,7 @@ int stm32_bringup(void); * Name: stm32_usbinitialize * * Description: - * Called from stm32_usbinitialize very early in inialization to setup + * Called from stm32_usbinitialize very early in initialization to setup * USB-related GPIO pins for the NUCLEO-H743ZI board. * ****************************************************************************/ diff --git a/boards/arm/stm32h7/nucleo-h743zi2/src/stm32_usb.c b/boards/arm/stm32h7/nucleo-h743zi2/src/stm32_usb.c index d081cd9b96..b0f5074658 100644 --- a/boards/arm/stm32h7/nucleo-h743zi2/src/stm32_usb.c +++ b/boards/arm/stm32h7/nucleo-h743zi2/src/stm32_usb.c @@ -123,7 +123,7 @@ static int usbhost_waiter(int argc, char *argv[]) * Name: stm32_usbinitialize * * Description: - * Called from stm32_usbinitialize very early in inialization to setup + * Called from stm32_usbinitialize very early in initialization to setup * USB-related GPIO pins for the nucleo-144 board. * ****************************************************************************/ diff --git a/boards/arm/stm32h7/nucleo-h745zi/src/stm32_usb.c b/boards/arm/stm32h7/nucleo-h745zi/src/stm32_usb.c index a0e52dfdbb..f729f7b4b4 100644 --- a/boards/arm/stm32h7/nucleo-h745zi/src/stm32_usb.c +++ b/boards/arm/stm32h7/nucleo-h745zi/src/stm32_usb.c @@ -123,7 +123,7 @@ static int usbhost_waiter(int argc, char *argv[]) * Name: stm32_usbinitialize * * Description: - * Called from stm32_usbinitialize very early in inialization to setup + * Called from stm32_usbinitialize very early in initialization to setup * USB-related GPIO pins for the nucleo-144 board. * ****************************************************************************/ diff --git a/boards/arm/stm32h7/openh743i/src/openh743i.h b/boards/arm/stm32h7/openh743i/src/openh743i.h index 6073dd9046..815d5454b1 100644 --- a/boards/arm/stm32h7/openh743i/src/openh743i.h +++ b/boards/arm/stm32h7/openh743i/src/openh743i.h @@ -116,7 +116,7 @@ int stm32_sdio_initialize(void); * Name: stm32_usbinitialize * * Description: - * Called from stm32_usbinitialize very early in inialization to setup + * Called from stm32_usbinitialize very early in initialization to setup * USB-related GPIO pins for the board. * ****************************************************************************/ diff --git a/boards/arm/stm32h7/openh743i/src/stm32_composite.c b/boards/arm/stm32h7/openh743i/src/stm32_composite.c index 2ba24e8584..8067047bc0 100644 --- a/boards/arm/stm32h7/openh743i/src/stm32_composite.c +++ b/boards/arm/stm32h7/openh743i/src/stm32_composite.c @@ -141,7 +141,7 @@ static int board_mscclassobject(int minor, * that is called form the composite device logic. * * Input Parameters: - * classdev - The class driver instrance previously give to the composite + * classdev - The class driver instance previously given to the composite * driver by board_mscclassobject(). * * Returned Value: diff --git a/boards/arm/stm32h7/openh743i/src/stm32_sdmmc.c b/boards/arm/stm32h7/openh743i/src/stm32_sdmmc.c index eff839c26b..7b7b447950 100644 --- a/boards/arm/stm32h7/openh743i/src/stm32_sdmmc.c +++ b/boards/arm/stm32h7/openh743i/src/stm32_sdmmc.c @@ -52,7 +52,7 @@ /* If IDMA is enabled, internal SRAM must be excluded from heap */ #if CONFIG_MM_REGIONS > 1 && defined(CONFIG_STM32H7_SDMMC_IDMA) -# error SDMMC1 with IDMA doesnt work CONFIG_MM_REGIONS > 1 +# error SDMMC1 with IDMA does not work CONFIG_MM_REGIONS > 1 #endif /**************************************************************************** diff --git a/boards/arm/stm32h7/openh743i/src/stm32_usb.c b/boards/arm/stm32h7/openh743i/src/stm32_usb.c index f8f2093a81..c9535522e2 100644 --- a/boards/arm/stm32h7/openh743i/src/stm32_usb.c +++ b/boards/arm/stm32h7/openh743i/src/stm32_usb.c @@ -110,7 +110,7 @@ static int usbhost_waiter(int argc, char *argv[]) * Name: stm32_usbinitialize * * Description: - * Called from stm32_usbinitialize very early in inialization to setup + * Called from stm32_usbinitialize very early in initialization to setup * USB-related GPIO pins for the board. * ****************************************************************************/ diff --git a/boards/arm/stm32h7/openh743i/src/stm32_usbmsc.c b/boards/arm/stm32h7/openh743i/src/stm32_usbmsc.c index 9a63339c27..3cf9f66248 100644 --- a/boards/arm/stm32h7/openh743i/src/stm32_usbmsc.c +++ b/boards/arm/stm32h7/openh743i/src/stm32_usbmsc.c @@ -40,7 +40,7 @@ #if !defined(CONFIG_USBDEV_CUSTOM_TXFIFO_SIZE) && \ defined(CONFIG_USBDEV_DUALSPEED) -# error USBMSC high-speed require custom TXFIFO configuratin that set EPIN FIFO to >=512 +# error USBMSC high-speed require custom TXFIFO configuration that set EPIN FIFO to >=512 #endif /**************************************************************************** diff --git a/boards/arm/stm32h7/stm32h745i-disco/src/stm32_usb.c b/boards/arm/stm32h7/stm32h745i-disco/src/stm32_usb.c index b83713e7ce..310f6d56cf 100644 --- a/boards/arm/stm32h7/stm32h745i-disco/src/stm32_usb.c +++ b/boards/arm/stm32h7/stm32h745i-disco/src/stm32_usb.c @@ -123,7 +123,7 @@ static int usbhost_waiter(int argc, char *argv[]) * Name: stm32_usbinitialize * * Description: - * Called from stm32_usbinitialize very early in inialization to setup + * Called from stm32_usbinitialize very early in initialization to setup * USB-related GPIO pins for the nucleo-144 board. * ****************************************************************************/ diff --git a/boards/arm/stm32h7/stm32h745i-disco/src/stm32h745i_disco.h b/boards/arm/stm32h7/stm32h745i-disco/src/stm32h745i_disco.h index dda3f10c7f..57ef2b05e6 100644 --- a/boards/arm/stm32h7/stm32h745i-disco/src/stm32h745i_disco.h +++ b/boards/arm/stm32h7/stm32h745i-disco/src/stm32h745i_disco.h @@ -179,7 +179,7 @@ int stm32_bringup(void); * Name: stm32_usbinitialize * * Description: - * Called from stm32_usbinitialize very early in inialization to setup + * Called from stm32_usbinitialize very early in initialization to setup * USB-related GPIO pins for the STM32H745I-DISCO board. * ****************************************************************************/ diff --git a/boards/arm/stm32h7/stm32h747i-disco/src/stm32_usb.c b/boards/arm/stm32h7/stm32h747i-disco/src/stm32_usb.c index d681182c08..d072c9cfe6 100644 --- a/boards/arm/stm32h7/stm32h747i-disco/src/stm32_usb.c +++ b/boards/arm/stm32h7/stm32h747i-disco/src/stm32_usb.c @@ -123,7 +123,7 @@ static int usbhost_waiter(int argc, char *argv[]) * Name: stm32_usbinitialize * * Description: - * Called from stm32_usbinitialize very early in inialization to setup + * Called from stm32_usbinitialize very early in initialization to setup * USB-related GPIO pins for the STM32H747I DISCO board. * ****************************************************************************/ diff --git a/boards/arm/stm32h7/stm32h750b-dk/src/stm32_usb.c b/boards/arm/stm32h7/stm32h750b-dk/src/stm32_usb.c index a10b0c4e43..c84a8cbadd 100644 --- a/boards/arm/stm32h7/stm32h750b-dk/src/stm32_usb.c +++ b/boards/arm/stm32h7/stm32h750b-dk/src/stm32_usb.c @@ -121,7 +121,7 @@ static int usbhost_waiter(int argc, char *argv[]) * Name: stm32_usbinitialize * * Description: - * Called from stm32_usbinitialize very early in inialization to setup + * Called from stm32_usbinitialize very early in initialization to setup * USB-related GPIO pins for the nucleo-144 board. * ****************************************************************************/ diff --git a/boards/arm/stm32h7/stm32h750b-dk/src/stm32h750b-dk.h b/boards/arm/stm32h7/stm32h750b-dk/src/stm32h750b-dk.h index 0e7f4e14ca..5e0e6b7f2d 100644 --- a/boards/arm/stm32h7/stm32h750b-dk/src/stm32h750b-dk.h +++ b/boards/arm/stm32h7/stm32h750b-dk/src/stm32h750b-dk.h @@ -177,7 +177,7 @@ int stm32_bringup(void); * Name: stm32_usbinitialize * * Description: - * Called from stm32_usbinitialize very early in inialization to setup + * Called from stm32_usbinitialize very early in initialization to setup * USB-related GPIO pins for the stm32h750b-dk board. * ****************************************************************************/ diff --git a/boards/arm/stm32l4/b-l475e-iot01a/src/stm32_spirit.c b/boards/arm/stm32l4/b-l475e-iot01a/src/stm32_spirit.c index d319d6b958..0dfcaf7233 100644 --- a/boards/arm/stm32l4/b-l475e-iot01a/src/stm32_spirit.c +++ b/boards/arm/stm32l4/b-l475e-iot01a/src/stm32_spirit.c @@ -212,7 +212,7 @@ static int stm32l4_spirit_devsetup(struct stm32l4_priv_s *priv) struct spi_dev_s *spi; int ret; - /* Configure the interrupt pin and SDN pins. Innitializing the SDN to '1' + /* Configure the interrupt pin and SDN pins. Initializing the SDN to '1' * powers down the Spirit. */ diff --git a/boards/arm/stm32l4/nucleo-l496zg/src/nucleo-144.h b/boards/arm/stm32l4/nucleo-l496zg/src/nucleo-144.h index 2b43b7e121..be76478a03 100644 --- a/boards/arm/stm32l4/nucleo-l496zg/src/nucleo-144.h +++ b/boards/arm/stm32l4/nucleo-l496zg/src/nucleo-144.h @@ -238,7 +238,7 @@ int stm32_sdio_initialize(void); * Name: stm32_usbinitialize * * Description: - * Called from stm32_usbinitialize very early in inialization to setup + * Called from stm32_usbinitialize very early in initialization to setup * USB-related GPIO pins for the nucleo-144 board. * ****************************************************************************/ diff --git a/boards/arm/stm32l4/nucleo-l496zg/src/stm32_usb.c b/boards/arm/stm32l4/nucleo-l496zg/src/stm32_usb.c index f76e8329a1..31bb8f623f 100644 --- a/boards/arm/stm32l4/nucleo-l496zg/src/stm32_usb.c +++ b/boards/arm/stm32l4/nucleo-l496zg/src/stm32_usb.c @@ -123,7 +123,7 @@ static int usbhost_waiter(int argc, char *argv[]) * Name: stm32_usbinitialize * * Description: - * Called from stm32_usbinitialize very early in inialization to setup + * Called from stm32_usbinitialize very early in initialization to setup * USB-related GPIO pins for the nucleo-144 board. * ****************************************************************************/ diff --git a/boards/arm/stm32l4/steval-stlcs01v1/src/stm32_boot.c b/boards/arm/stm32l4/steval-stlcs01v1/src/stm32_boot.c index 3e7dc66100..251ce18d59 100644 --- a/boards/arm/stm32l4/steval-stlcs01v1/src/stm32_boot.c +++ b/boards/arm/stm32l4/steval-stlcs01v1/src/stm32_boot.c @@ -56,7 +56,7 @@ void stm32l4_board_initialize(void) { /* Initialize USB if the 1) OTG FS controller is in the configuration and * 2) disabled, and 3) the weak function stm32l4_usbinitialize() has been - * brought into the build. Presumeably either CONFIG_USBDEV is also + * brought into the build. Presumably either CONFIG_USBDEV is also * selected. */ diff --git a/boards/arm/stm32l4/steval-stlcs01v1/src/stm32_usb.c b/boards/arm/stm32l4/steval-stlcs01v1/src/stm32_usb.c index 50614d49f5..6891d5c090 100644 --- a/boards/arm/stm32l4/steval-stlcs01v1/src/stm32_usb.c +++ b/boards/arm/stm32l4/steval-stlcs01v1/src/stm32_usb.c @@ -67,7 +67,7 @@ * Name: stm32l4_usbinitialize * * Description: - * Called from stm32l4_usbinitialize very early in inialization to setup + * Called from stm32l4_usbinitialize very early in initialization to setup * USB-related GPIO pins for the board. * ****************************************************************************/ diff --git a/boards/arm/stm32l4/stm32l4r9ai-disco/include/stm32l4r9ai-disco-clocking.h b/boards/arm/stm32l4/stm32l4r9ai-disco/include/stm32l4r9ai-disco-clocking.h index d40022ff1c..ddc8d01fb1 100644 --- a/boards/arm/stm32l4/stm32l4r9ai-disco/include/stm32l4r9ai-disco-clocking.h +++ b/boards/arm/stm32l4/stm32l4r9ai-disco/include/stm32l4r9ai-disco-clocking.h @@ -61,7 +61,7 @@ #define STM32L4_SYSCLK_FREQUENCY 120000000ul #define BOARD_AHB_FREQUENCY STM32L4_SYSCLK_FREQUENCY -/* Higher SYSCLK reguires more flash wait states. */ +/* Higher SYSCLK requires more flash wait states. */ #define BOARD_FLASH_WAITSTATES 5 diff --git a/boards/arm/stm32wb/flipperzero/include/flipperzero-clocking.h b/boards/arm/stm32wb/flipperzero/include/flipperzero-clocking.h index ffc52e6608..ce6734fd5a 100644 --- a/boards/arm/stm32wb/flipperzero/include/flipperzero-clocking.h +++ b/boards/arm/stm32wb/flipperzero/include/flipperzero-clocking.h @@ -231,7 +231,7 @@ #define BOARD_TIM16_FREQUENCY STM32WB_APB2_TIM16_CLKIN #define BOARD_TIM17_FREQUENCY STM32WB_APB2_TIM17_CLKIN -/* Higher SYSCLK reguires more flash wait states. */ +/* Higher SYSCLK requires more flash wait states. */ #define BOARD_FLASH_WAITSTATES 3 diff --git a/boards/arm/stm32wb/nucleo-wb55rg/include/nucleo-wb55rg.h b/boards/arm/stm32wb/nucleo-wb55rg/include/nucleo-wb55rg.h index 65f9f42701..d48843b273 100644 --- a/boards/arm/stm32wb/nucleo-wb55rg/include/nucleo-wb55rg.h +++ b/boards/arm/stm32wb/nucleo-wb55rg/include/nucleo-wb55rg.h @@ -232,7 +232,7 @@ #define BOARD_TIM16_FREQUENCY STM32WB_APB2_TIM16_CLKIN #define BOARD_TIM17_FREQUENCY STM32WB_APB2_TIM17_CLKIN -/* Higher SYSCLK reguires more flash wait states. */ +/* Higher SYSCLK requires more flash wait states. */ #define BOARD_FLASH_WAITSTATES 3 diff --git a/boards/arm/stm32wl5/nucleo-wl55jc/Kconfig b/boards/arm/stm32wl5/nucleo-wl55jc/Kconfig index a3d291d8fe..bc565d72d9 100644 --- a/boards/arm/stm32wl5/nucleo-wl55jc/Kconfig +++ b/boards/arm/stm32wl5/nucleo-wl55jc/Kconfig @@ -266,7 +266,7 @@ config ARCH_BOARD_FLASH_PART1_FS_SMARTFS when flashing new software, unless you exceeded reserved memory for program code. - Smartfs uses quite substential amount of FLASH data to + Smartfs uses quite substantial amount of FLASH data to get to workable state and mount. Looks like 8 page sizes is absolute minimum (so a 16KiB!). diff --git a/boards/arm/tiva/tm4c1294-launchpad/src/tm4c1294-launchpad.h b/boards/arm/tiva/tm4c1294-launchpad/src/tm4c1294-launchpad.h index 50917198b6..f0798c7e08 100644 --- a/boards/arm/tiva/tm4c1294-launchpad/src/tm4c1294-launchpad.h +++ b/boards/arm/tiva/tm4c1294-launchpad/src/tm4c1294-launchpad.h @@ -60,7 +60,7 @@ #elif defined(CONFIG_TIVA_UART7_HCIUART) # define HCIUART_SERDEV HCIUART7 #else -# error No HCI UART specifified +# error No HCI UART specified #endif /* How many SSI modules does this chip support? */ diff --git a/boards/arm/tiva/tm4c129e-launchpad/src/tm4c129e-launchpad.h b/boards/arm/tiva/tm4c129e-launchpad/src/tm4c129e-launchpad.h index b9ac8e06e5..fde7d18192 100644 --- a/boards/arm/tiva/tm4c129e-launchpad/src/tm4c129e-launchpad.h +++ b/boards/arm/tiva/tm4c129e-launchpad/src/tm4c129e-launchpad.h @@ -60,7 +60,7 @@ #elif defined(CONFIG_TIVA_UART7_HCIUART) # define HCIUART_SERDEV HCIUART7 #else -# error No HCI UART specifified +# error No HCI UART specified #endif /* How many SSI modules does this chip support? */ diff --git a/boards/arm/tlsr82/tlsr8278adk80d/scripts/flash_boot_ble.ld b/boards/arm/tlsr82/tlsr8278adk80d/scripts/flash_boot_ble.ld index bd30d1dae6..7d031d927c 100644 --- a/boards/arm/tlsr82/tlsr8278adk80d/scripts/flash_boot_ble.ld +++ b/boards/arm/tlsr82/tlsr8278adk80d/scripts/flash_boot_ble.ld @@ -48,7 +48,7 @@ SECTIONS /* RF and system timer interrupt handler may call the libgcc * functions, to make sure the RF and system timer interrupt - * handler do not execute falsh code, copy all the libgcc code + * handler do not execute flash code, copy all the libgcc code * to ram (exclude _divdi3, _udivdi3 and _umoddi3). */ @@ -56,7 +56,7 @@ SECTIONS /* Copy some scheduler related functions and read only data to ram * to improve the performance and make sure the RF and system timer - * interrupt handler do not execute falsh code. + * interrupt handler do not execute flash code. */ *libarch.a:arm_interruptcontext.o(.text .text.*) diff --git a/boards/arm/tms570/launchxl-tms57004/include/board.h b/boards/arm/tms570/launchxl-tms57004/include/board.h index 3af9d01c71..5727e610a1 100644 --- a/boards/arm/tms570/launchxl-tms57004/include/board.h +++ b/boards/arm/tms570/launchxl-tms57004/include/board.h @@ -51,7 +51,7 @@ * NR = REFCLKDIV+1 * Fintclk = Fclkin / NR * - * PLLMUL controls multipler on divided input clock (Fintclk): + * PLLMUL controls multiplier on divided input clock (Fintclk): * * Non-modulated: * NF = (PLLMUL + 256) / 256 diff --git a/boards/arm/tms570/launchxl-tms57004/scripts/flash-sram.ld b/boards/arm/tms570/launchxl-tms57004/scripts/flash-sram.ld index 11ef17ccdf..a251ce2979 100644 --- a/boards/arm/tms570/launchxl-tms57004/scripts/flash-sram.ld +++ b/boards/arm/tms570/launchxl-tms57004/scripts/flash-sram.ld @@ -21,7 +21,7 @@ ****************************************************************************/ /* The TMS570LS0432PZ has 384KB of FLASH beginning at address 0x0000:0000 and - * 32Kb of SRAM beginining at 0x0800:0000 + * 32Kb of SRAM beginning at 0x0800:0000 */ MEMORY diff --git a/boards/arm/tms570/tms570ls31x-usb-kit/include/board.h b/boards/arm/tms570/tms570ls31x-usb-kit/include/board.h index c54f539c90..47fbc63dda 100644 --- a/boards/arm/tms570/tms570ls31x-usb-kit/include/board.h +++ b/boards/arm/tms570/tms570ls31x-usb-kit/include/board.h @@ -51,7 +51,7 @@ * NR = REFCLKDIV+1 * Fintclk = Fclkin / NR * - * PLLMUL controls multipler on divided input clock (Fintclk): + * PLLMUL controls multiplier on divided input clock (Fintclk): * * Non-modulated: * NF = (PLLMUL + 256) / 256 diff --git a/boards/arm64/zynq-mpsoc/zcu111/include/board.h b/boards/arm64/zynq-mpsoc/zcu111/include/board.h index b72cbc7709..edfec30d6b 100644 --- a/boards/arm64/zynq-mpsoc/zcu111/include/board.h +++ b/boards/arm64/zynq-mpsoc/zcu111/include/board.h @@ -91,7 +91,7 @@ ****************************************************************************/ /**************************************************************************** - * Clock frequence defnition + * Clock frequency definition ****************************************************************************/ #define CLK_CCF_VIDEO_CLK 27000000 diff --git a/boards/avr/at32uc3/avr32dev1/include/board.h b/boards/avr/at32uc3/avr32dev1/include/board.h index 727753c41a..0671772cc5 100644 --- a/boards/avr/at32uc3/avr32dev1/include/board.h +++ b/boards/avr/at32uc3/avr32dev1/include/board.h @@ -123,7 +123,7 @@ #define AVR32_CPU_CLOCK AVR32_FOSC0 #define AVR32_PBA_CLOCK AVR32_FOSC0 -/* Pin muliplexing selecion *************************************************/ +/* Pin muliplexing selection ************************************************/ #define PINMUX_USART1_RXD PINMUX_USART1_RXD_2 #define PINMUX_USART1_TXD PINMUX_USART1_TXD_2 diff --git a/boards/avr/at32uc3/mizar32a/include/board.h b/boards/avr/at32uc3/mizar32a/include/board.h index 8a9c27920b..002b9e15ad 100644 --- a/boards/avr/at32uc3/mizar32a/include/board.h +++ b/boards/avr/at32uc3/mizar32a/include/board.h @@ -123,7 +123,7 @@ #define AVR32_CPU_CLOCK 66000000 #define AVR32_PBA_CLOCK 16500000 -/* Pin muliplexing selecion *************************************************/ +/* Pin muliplexing selection ************************************************/ #define PINMUX_USART1_RXD PINMUX_USART1_RXD_0 #define PINMUX_USART1_TXD PINMUX_USART1_TXD_0 diff --git a/boards/mips/pic32mx/sure-pic32mx/include/board.h b/boards/mips/pic32mx/sure-pic32mx/include/board.h index af6314d11d..4d6f65c142 100644 --- a/boards/mips/pic32mx/sure-pic32mx/include/board.h +++ b/boards/mips/pic32mx/sure-pic32mx/include/board.h @@ -87,7 +87,7 @@ /* LED definitions **********************************************************/ /* The Sure DB_DP11215 PIC32 Storage Demo Board board has five LEDs. One - * (D4, lablel "Power") is not controllable by software. Four are + * (D4, labeled "Power") is not controllable by software. Four are * controllable by software: * * D7 "USB" Yellow RD7 Low illuminates diff --git a/boards/mips/pic32mx/sure-pic32mx/src/pic32mx_autoleds.c b/boards/mips/pic32mx/sure-pic32mx/src/pic32mx_autoleds.c index b2919a5127..5157328bf2 100644 --- a/boards/mips/pic32mx/sure-pic32mx/src/pic32mx_autoleds.c +++ b/boards/mips/pic32mx/sure-pic32mx/src/pic32mx_autoleds.c @@ -47,7 +47,7 @@ /* LED Configuration ********************************************************/ -/* The Sure PIC32MX board has five LEDs. One (D4, lablel "Power") is not +/* The Sure PIC32MX board has five LEDs. One (D4, labeled "Power") is not * controllable by software. Four are controllable by software: * * D7 "USB" Yellow RD7 Low illuminates diff --git a/boards/mips/pic32mx/sure-pic32mx/src/sure-pic32mx.h b/boards/mips/pic32mx/sure-pic32mx/src/sure-pic32mx.h index 1ad04ea51c..67daa3c844 100644 --- a/boards/mips/pic32mx/sure-pic32mx/src/sure-pic32mx.h +++ b/boards/mips/pic32mx/sure-pic32mx/src/sure-pic32mx.h @@ -37,7 +37,7 @@ /* GPIO Pin Configurations **************************************************/ -/* The Sure PIC32MX board has five LEDs. One (D4, lablel "Power") is not +/* The Sure PIC32MX board has five LEDs. One (D4, labeled "Power") is not * controllable by software. Four are controllable by software: * * D7 "USB" Yellow RD7 Low illuminates diff --git a/boards/renesas/m16c/skp16c26/include/board.h b/boards/renesas/m16c/skp16c26/include/board.h index 8e6581dd39..b4f101b905 100644 --- a/boards/renesas/m16c/skp16c26/include/board.h +++ b/boards/renesas/m16c/skp16c26/include/board.h @@ -49,7 +49,7 @@ # error "UART1/2 should not be used on SKP16C26" #endif -/* Hardware defintitions ****************************************************/ +/* Hardware definitions *****************************************************/ /* Xin Freq */ diff --git a/boards/renesas/m16c/skp16c26/src/m16c_lcdconsole.c b/boards/renesas/m16c/skp16c26/src/m16c_lcdconsole.c index 6beab3c534..cab8d67ccf 100644 --- a/boards/renesas/m16c/skp16c26/src/m16c_lcdconsole.c +++ b/boards/renesas/m16c/skp16c26/src/m16c_lcdconsole.c @@ -67,7 +67,7 @@ * * Description: * Performs the low level UART initialization early in debug so that the - * serial console will be available during bootup. + * serial console will be available during boot up. * This must be called before up_consoleinit. * ****************************************************************************/ diff --git a/boards/renesas/sh1/us7032evb1/shterm/shterm.c b/boards/renesas/sh1/us7032evb1/shterm/shterm.c index 23f8f331d0..1eac04cf83 100644 --- a/boards/renesas/sh1/us7032evb1/shterm/shterm.c +++ b/boards/renesas/sh1/us7032evb1/shterm/shterm.c @@ -741,7 +741,7 @@ int main(int argc, char **argv, char **envp) ret = readbyte(0, &ch); if (ret == 0) { - printconsole("End-of-file: exitting\n"); + printconsole("End-of-file: exiting\n"); close_tty(); return 0; } diff --git a/boards/risc-v/k230/canmv230/src/Makefile b/boards/risc-v/k230/canmv230/src/Makefile index 4673ef50ff..061f9df853 100644 --- a/boards/risc-v/k230/canmv230/src/Makefile +++ b/boards/risc-v/k230/canmv230/src/Makefile @@ -32,7 +32,7 @@ endif include $(TOPDIR)/boards/Board.mk -# don't use single-colon targets as they may coflict with those included ones. +# don't use single-colon targets as they may conflict with those included ones. # use double-colon targets to avoid collisions below. ifeq ($(CONFIG_BUILD_KERNEL),y) diff --git a/boards/risc-v/litex/arty_a7/src/litex_sdio.c b/boards/risc-v/litex/arty_a7/src/litex_sdio.c index 232d719eca..0c0217bea6 100644 --- a/boards/risc-v/litex/arty_a7/src/litex_sdio.c +++ b/boards/risc-v/litex/arty_a7/src/litex_sdio.c @@ -122,7 +122,7 @@ int litex_sdio_initialize(void) finfo("Successfully bound SDIO to the MMC/SD driver\n"); /* Assume that the SD card is inserted. - * The Arty A7 board doesnt have the CD pin wired. + * The Arty A7 board does not have the CD pin wired. */ sdio_mediachange(sdio_dev, litex_sdio_get_card_detect()); diff --git a/boards/risc-v/mpfs/common/src/mpfs_composite.c b/boards/risc-v/mpfs/common/src/mpfs_composite.c index 33e1b15b19..14a55f14e4 100644 --- a/boards/risc-v/mpfs/common/src/mpfs_composite.c +++ b/boards/risc-v/mpfs/common/src/mpfs_composite.c @@ -132,7 +132,7 @@ static int board_mscclassobject(int minor, * composite device logic. * * Input Parameters: - * classdev - The class driver instrance previously give to the composite + * classdev - The class driver instance previously given to the composite * driver by board_mscclassobject(). * * Returned Value: diff --git a/boards/risc-v/mpfs/common/src/mpfs_ihc.c b/boards/risc-v/mpfs/common/src/mpfs_ihc.c index 58b1035aa8..bc06e2da52 100644 --- a/boards/risc-v/mpfs/common/src/mpfs_ihc.c +++ b/boards/risc-v/mpfs/common/src/mpfs_ihc.c @@ -52,7 +52,7 @@ int mpfs_board_ihc_init(void) { int ret = 0; - /* With OpenSBI, initilization comes via mpfs_opensbi.c, not here */ + /* With OpenSBI, initialization comes via mpfs_opensbi.c, not here */ #ifndef CONFIG_MPFS_OPENSBI diff --git a/boards/risc-v/qemu-rv/rv-virt/src/Makefile b/boards/risc-v/qemu-rv/rv-virt/src/Makefile index 36278de7e4..7b35075933 100644 --- a/boards/risc-v/qemu-rv/rv-virt/src/Makefile +++ b/boards/risc-v/qemu-rv/rv-virt/src/Makefile @@ -42,7 +42,7 @@ endif include $(TOPDIR)/boards/Board.mk -# don't use single-colon targets as they may coflict with those included ones. +# don't use single-colon targets as they may conflict with those included ones. # use double-colon targets to avoid collisions below. ifeq ($(CONFIG_BUILD_KERNEL),y) diff --git a/boards/sparc/s698pm/s698pm-dkit/Kconfig b/boards/sparc/s698pm/s698pm-dkit/Kconfig index 042d28a89d..5f62401734 100644 --- a/boards/sparc/s698pm/s698pm-dkit/Kconfig +++ b/boards/sparc/s698pm/s698pm-dkit/Kconfig @@ -18,7 +18,7 @@ config S698PM_DKIT_WDG_TIMEOUT if S698PM_DKIT_WDG config S698PM_DKIT_WDG_THREAD - bool "Watchdog Deamon Thread" + bool "Watchdog Daemon Thread" if S698PM_DKIT_WDG_THREAD config S698PM_DKIT_WDG_THREAD_NAME diff --git a/boards/tricore/tc3xx/tc397/scripts/Lcf_Gnuc_Tricore_Tc.lsl b/boards/tricore/tc3xx/tc397/scripts/Lcf_Gnuc_Tricore_Tc.lsl index 2c2369fc8a..ddd5688fd1 100644 --- a/boards/tricore/tc3xx/tc397/scripts/Lcf_Gnuc_Tricore_Tc.lsl +++ b/boards/tricore/tc3xx/tc397/scripts/Lcf_Gnuc_Tricore_Tc.lsl @@ -2917,7 +2917,7 @@ SECTIONS __DTOR_LIST__ = . ; LONG((__DTOR_END__ - __DTOR_LIST__) / 4 - 2); /* - * Code executed before calling main extra section for C++ distructor init + * Code executed before calling main extra section for C++ destructor init * -------------------------Start----------------------------------------- */ KEEP (*crtbegin.o(.dtors)) @@ -2925,7 +2925,7 @@ SECTIONS KEEP (*(SORT(.dtors.*))) KEEP (*(.dtors)) /* - * Code executed before calling main extra section for C++ distructor init + * Code executed before calling main extra section for C++ destructor init * -------------------------End----------------------------------------- */ LONG(0) ; diff --git a/boards/xtensa/esp32/common/include/esp32_board_adc.h b/boards/xtensa/esp32/common/include/esp32_board_adc.h index aa8df1204d..eb3d5ec192 100644 --- a/boards/xtensa/esp32/common/include/esp32_board_adc.h +++ b/boards/xtensa/esp32/common/include/esp32_board_adc.h @@ -52,7 +52,7 @@ extern "C" * Name: board_adc_init * * Description: - * Initialize and configuree the ADC driver for the board. + * Initialize and configure the ADC driver for the board. * It registers the ADC channels specified in the configuration and ensures * that the ADC hardware is properly set up for use. * diff --git a/boards/xtensa/esp32/common/include/esp32_board_dac.h b/boards/xtensa/esp32/common/include/esp32_board_dac.h index a8198574df..ee59dd5fa0 100644 --- a/boards/xtensa/esp32/common/include/esp32_board_dac.h +++ b/boards/xtensa/esp32/common/include/esp32_board_dac.h @@ -65,7 +65,7 @@ extern "C" * Name: board_dac_initialize * * Description: - * Initialize and register the Digital to Analog Convertor (DAC) driver. + * Initialize and register the Digital to Analog Converter (DAC) driver. * * Input Parameters: * path - The device number, used to build the device path as diff --git a/boards/xtensa/esp32/common/src/esp32_board_adc.c b/boards/xtensa/esp32/common/src/esp32_board_adc.c index a570bd27ea..07c41e542a 100644 --- a/boards/xtensa/esp32/common/src/esp32_board_adc.c +++ b/boards/xtensa/esp32/common/src/esp32_board_adc.c @@ -210,7 +210,7 @@ static int board_adc_register(int adc_num) * Name: board_adc_init * * Description: - * Initialize and configuree the ADC driver for the board. + * Initialize and configure the ADC driver for the board. * It registers the ADC channels specified in the configuration and ensures * that the ADC hardware is properly set up for use. * diff --git a/boards/xtensa/esp32/common/src/esp32_cs4344.c b/boards/xtensa/esp32/common/src/esp32_cs4344.c index dd669f75ca..669406d9fb 100644 --- a/boards/xtensa/esp32/common/src/esp32_cs4344.c +++ b/boards/xtensa/esp32/common/src/esp32_cs4344.c @@ -95,7 +95,7 @@ int esp32_cs4344_initialize(int port) goto errout; } - /* Check wheter to enable a simple character driver that supports I2S + /* Check whether to enable a simple character driver that supports I2S * transfers via a read() and write(). The intent of this driver is to * support I2S testing. It is not an audio driver but does conform to * some of the buffer management heuristics of an audio driver. It is diff --git a/boards/xtensa/esp32/common/src/esp32_es8388.c b/boards/xtensa/esp32/common/src/esp32_es8388.c index 7cfdfe8312..9e4d1a8ec1 100644 --- a/boards/xtensa/esp32/common/src/esp32_es8388.c +++ b/boards/xtensa/esp32/common/src/esp32_es8388.c @@ -120,7 +120,7 @@ int esp32_es8388_initialize(int i2c_port, uint8_t i2c_addr, int i2c_freq, goto errout; } - /* Check wheter to enable a simple character driver that supports I2S + /* Check whether to enable a simple character driver that supports I2S * transfers via a read() and write(). The intent of this driver is to * support I2S testing. It is not an audio driver but does conform to * some of the buffer management heuristics of an audio driver. It is diff --git a/boards/xtensa/esp32s2/common/include/esp32s2_board_adc.h b/boards/xtensa/esp32s2/common/include/esp32s2_board_adc.h index 988b21e49e..a4ed1b40af 100644 --- a/boards/xtensa/esp32s2/common/include/esp32s2_board_adc.h +++ b/boards/xtensa/esp32s2/common/include/esp32s2_board_adc.h @@ -52,7 +52,7 @@ extern "C" * Name: board_adc_init * * Description: - * Initialize and configuree the ADC driver for the board. + * Initialize and configure the ADC driver for the board. * It registers the ADC channels specified in the configuration and ensures * that the ADC hardware is properly set up for use. * diff --git a/boards/xtensa/esp32s2/common/src/esp32s2_board_adc.c b/boards/xtensa/esp32s2/common/src/esp32s2_board_adc.c index bc7255a1f9..0990315a5a 100644 --- a/boards/xtensa/esp32s2/common/src/esp32s2_board_adc.c +++ b/boards/xtensa/esp32s2/common/src/esp32s2_board_adc.c @@ -215,7 +215,7 @@ static int board_adc_register(int adc_num) * Name: board_adc_init * * Description: - * Initialize and configuree the ADC driver for the board. + * Initialize and configure the ADC driver for the board. * It registers the ADC channels specified in the configuration and ensures * that the ADC hardware is properly set up for use. * diff --git a/boards/xtensa/esp32s2/common/src/esp32s2_cs4344.c b/boards/xtensa/esp32s2/common/src/esp32s2_cs4344.c index 3c300e2388..b1729b3b06 100644 --- a/boards/xtensa/esp32s2/common/src/esp32s2_cs4344.c +++ b/boards/xtensa/esp32s2/common/src/esp32s2_cs4344.c @@ -89,7 +89,7 @@ int esp32s2_cs4344_initialize(void) goto errout; } - /* Check wheter to enable a simple character driver that supports I2S + /* Check whether to enable a simple character driver that supports I2S * transfers via a read() and write(). The intent of this driver is to * support I2S testing. It is not an audio driver but does conform to * some of the buffer management heuristics of an audio driver. It is diff --git a/boards/xtensa/esp32s2/common/src/esp32s2_es8311.c b/boards/xtensa/esp32s2/common/src/esp32s2_es8311.c index 557e6b1acf..967e4ef309 100644 --- a/boards/xtensa/esp32s2/common/src/esp32s2_es8311.c +++ b/boards/xtensa/esp32s2/common/src/esp32s2_es8311.c @@ -113,7 +113,7 @@ int esp32s2_es8311_initialize(int i2c_port, uint8_t i2c_addr, int i2c_freq) goto errout; } - /* Check wheter to enable a simple character driver that supports I2S + /* Check whether to enable a simple character driver that supports I2S * transfers via a read() and write(). The intent of this driver is to * support I2S testing. It is not an audio driver but does conform to * some of the buffer management heuristics of an audio driver. It is diff --git a/boards/xtensa/esp32s3/common/include/esp32s3_board_adc.h b/boards/xtensa/esp32s3/common/include/esp32s3_board_adc.h index 1db3f63fc7..2ae778a085 100644 --- a/boards/xtensa/esp32s3/common/include/esp32s3_board_adc.h +++ b/boards/xtensa/esp32s3/common/include/esp32s3_board_adc.h @@ -52,7 +52,7 @@ extern "C" * Name: board_adc_init * * Description: - * Initialize and configuree the ADC driver for the board. + * Initialize and configure the ADC driver for the board. * It registers the ADC channels specified in the configuration and ensures * that the ADC hardware is properly set up for use. * diff --git a/boards/xtensa/esp32s3/common/src/esp32s3_board_adc.c b/boards/xtensa/esp32s3/common/src/esp32s3_board_adc.c index 97c3b6d49c..1c8322e7cd 100644 --- a/boards/xtensa/esp32s3/common/src/esp32s3_board_adc.c +++ b/boards/xtensa/esp32s3/common/src/esp32s3_board_adc.c @@ -215,7 +215,7 @@ static int board_adc_register(int adc_num) * Name: board_adc_init * * Description: - * Initialize and configuree the ADC driver for the board. + * Initialize and configure the ADC driver for the board. * It registers the ADC channels specified in the configuration and ensures * that the ADC hardware is properly set up for use. * diff --git a/boards/xtensa/esp32s3/common/src/esp32s3_cs4344.c b/boards/xtensa/esp32s3/common/src/esp32s3_cs4344.c index 08f5f38f87..fbd96aa9a8 100644 --- a/boards/xtensa/esp32s3/common/src/esp32s3_cs4344.c +++ b/boards/xtensa/esp32s3/common/src/esp32s3_cs4344.c @@ -88,7 +88,7 @@ int esp32s3_cs4344_initialize(int port) goto errout; } - /* Check wheter to enable a simple character driver that supports I2S + /* Check whether to enable a simple character driver that supports I2S * transfers via a read() and write(). The intent of this driver is to * support I2S testing. It is not an audio driver but does conform to * some of the buffer management heuristics of an audio driver. It is diff --git a/boards/xtensa/esp32s3/common/src/esp32s3_es8311.c b/boards/xtensa/esp32s3/common/src/esp32s3_es8311.c index 7fa65e2cb8..532f9de390 100644 --- a/boards/xtensa/esp32s3/common/src/esp32s3_es8311.c +++ b/boards/xtensa/esp32s3/common/src/esp32s3_es8311.c @@ -115,7 +115,7 @@ int esp32s3_es8311_initialize(int i2c_port, uint8_t i2c_addr, int i2c_freq, goto errout; } - /* Check wheter to enable a simple character driver that supports I2S + /* Check whether to enable a simple character driver that supports I2S * transfers via a read() and write(). The intent of this driver is to * support I2S testing. It is not an audio driver but does conform to * some of the buffer management heuristics of an audio driver. It is diff --git a/boards/xtensa/esp32s3/esp32s3-box/src/esp32s3_board_lcd_ili9342c.c b/boards/xtensa/esp32s3/esp32s3-box/src/esp32s3_board_lcd_ili9342c.c index 445155f26c..8508527bfa 100644 --- a/boards/xtensa/esp32s3/esp32s3-box/src/esp32s3_board_lcd_ili9342c.c +++ b/boards/xtensa/esp32s3/esp32s3-box/src/esp32s3_board_lcd_ili9342c.c @@ -93,7 +93,7 @@ static const struct ili9342c_config_data g_lcd_config[] = } }, { - /* Power contorl B, power control = 0, DC_ENA = 1 */ + /* Power control B, power control = 0, DC_ENA = 1 */ ILI9341_POWER_CONTROL_B, 3, { @@ -173,7 +173,7 @@ static const struct ili9342c_config_data g_lcd_config[] = } }, { - /* Memory access contorl, MX=MY=0, MV=1, ML=0, BGR=1, MH=0 */ + /* Memory access control, MX=MY=0, MV=1, ML=0, BGR=1, MH=0 */ ILI9341_MEMORY_ACCESS_CONTROL, 1, { @@ -604,7 +604,7 @@ int board_lcd_initialize(void) * allows support for multiple LCD devices. * * Input Parameters: - * devno - LCD device nmber + * devno - LCD device number * * Returned Value: * LCD device pointer if success or NULL if failed. diff --git a/boards/xtensa/esp32s3/esp32s3-box/src/esp32s3_board_lcd_st7789.c b/boards/xtensa/esp32s3/esp32s3-box/src/esp32s3_board_lcd_st7789.c index af741f789f..26d13278a1 100644 --- a/boards/xtensa/esp32s3/esp32s3-box/src/esp32s3_board_lcd_st7789.c +++ b/boards/xtensa/esp32s3/esp32s3-box/src/esp32s3_board_lcd_st7789.c @@ -118,7 +118,7 @@ int board_lcd_initialize(void) * allows support for multiple LCD devices. * * Input Parameters: - * devno - LCD device nmber + * devno - LCD device number * * Returned Value: * LCD device pointer if success or NULL if failed. diff --git a/boards/xtensa/esp32s3/esp32s3-eye/src/esp32s3_board_lcd.c b/boards/xtensa/esp32s3/esp32s3-eye/src/esp32s3_board_lcd.c index cb622d0b98..62e75356a1 100644 --- a/boards/xtensa/esp32s3/esp32s3-eye/src/esp32s3_board_lcd.c +++ b/boards/xtensa/esp32s3/esp32s3-eye/src/esp32s3_board_lcd.c @@ -111,7 +111,7 @@ int board_lcd_initialize(void) * allows support for multiple LCD devices. * * Input Parameters: - * devno - LCD device nmber + * devno - LCD device number * * Returned Value: * LCD device pointer if success or NULL if failed. diff --git a/boards/xtensa/esp32s3/esp32s3-lcd-ev/src/esp32s3_lcd.c b/boards/xtensa/esp32s3/esp32s3-lcd-ev/src/esp32s3_lcd.c index 135255f313..b6bb5d09de 100644 --- a/boards/xtensa/esp32s3/esp32s3-lcd-ev/src/esp32s3_lcd.c +++ b/boards/xtensa/esp32s3/esp32s3-lcd-ev/src/esp32s3_lcd.c @@ -614,7 +614,7 @@ static void lcd_initialize_spi(void) static void lcd_configure_display(void) { - /* Pull-up V-SYNC pin to start configurating LCD */ + /* Pull-up V-SYNC pin to start configuring LCD */ esp32s3_configgpio(CONFIG_ESP32S3_LCD_VSYNC_PIN, OUTPUT | PULLUP); esp32s3_gpiowrite(CONFIG_ESP32S3_LCD_VSYNC_PIN, 1); diff --git a/boards/xtensa/esp32s3/lckfb-szpi-esp32s3/src/esp32s3_board_lcd.c b/boards/xtensa/esp32s3/lckfb-szpi-esp32s3/src/esp32s3_board_lcd.c index e7cca55a8f..1c29788c68 100644 --- a/boards/xtensa/esp32s3/lckfb-szpi-esp32s3/src/esp32s3_board_lcd.c +++ b/boards/xtensa/esp32s3/lckfb-szpi-esp32s3/src/esp32s3_board_lcd.c @@ -157,7 +157,7 @@ int board_lcd_initialize(void) * allows support for multiple LCD devices. * * Input Parameters: - * devno - LCD device nmber + * devno - LCD device number * * Returned Value: * LCD device pointer if success or NULL if failed. diff --git a/cmake/nuttx_add_dependencies.cmake b/cmake/nuttx_add_dependencies.cmake index c1291729c2..3032c521cd 100644 --- a/cmake/nuttx_add_dependencies.cmake +++ b/cmake/nuttx_add_dependencies.cmake @@ -37,7 +37,7 @@ include(nuttx_parse_function_args) # nuttx_add_dependencies( TARGET DEPENDS ) # # Parameters: -# TARGET : target needs to add dependencie +# TARGET : target needs to add dependency # DEPENDS : targets which depends on # ~~~ diff --git a/cmake/nuttx_add_romfs.cmake b/cmake/nuttx_add_romfs.cmake index 8a05e6952a..43d4b8bfdf 100644 --- a/cmake/nuttx_add_romfs.cmake +++ b/cmake/nuttx_add_romfs.cmake @@ -40,7 +40,7 @@ endfunction() # ~~~ # add_dynamic_rcsrcs & add_dynamic_rcraws # provide a way to add dynamic ROMFS data -# which genrate during the build process +# which generate during the build process # to the final romfs_holder target # ~~~ function(add_dynamic_rcsrcs) @@ -244,7 +244,7 @@ endfunction() # ~~~ # The files of romfs may be added in -# ANY PROCESS IN ANY DIRECORY, +# ANY PROCESS IN ANY DIRECTORY, # so we process all the targets at the end. # ~~~ function(process_all_directory_romfs) diff --git a/cmake/nuttx_add_symtab.cmake b/cmake/nuttx_add_symtab.cmake index b61139cc7b..b3f3b79e40 100644 --- a/cmake/nuttx_add_symtab.cmake +++ b/cmake/nuttx_add_symtab.cmake @@ -93,7 +93,7 @@ function(nuttx_add_symtab) add_library(symtab_${NAME} OBJECT ${CMAKE_CURRENT_BINARY_DIR}/symtab_${NAME}.c) - # Make the dependance between .c and .h explicit. This is necessary since + # Make the dependence between .c and .h explicit. This is necessary since # using configure_file() does not seem to allow this to be automatically # guessed by CMake set_property( diff --git a/cmake/nuttx_remove_compile_options.cmake b/cmake/nuttx_remove_compile_options.cmake index 37cf54260a..b70a4744cc 100644 --- a/cmake/nuttx_remove_compile_options.cmake +++ b/cmake/nuttx_remove_compile_options.cmake @@ -38,7 +38,7 @@ # Example: # nuttx_remove_compile_options(-march -mabi) # -# befor: CFLAGS = -O2 -g -march=rv32if -mabi=ilp32f -mcpu=e907fp +# before: CFLAGS = -O2 -g -march=rv32if -mabi=ilp32f -mcpu=e907fp # after: CFLAGS = -O2 -g -mcpu=e907fp # # ~~~ diff --git a/crypto/cryptosoft.c b/crypto/cryptosoft.c index 8e1fb6af5e..cd34e5c207 100644 --- a/crypto/cryptosoft.c +++ b/crypto/cryptosoft.c @@ -1192,7 +1192,7 @@ static int swcr_dh_make_public(FAR struct cryptkop *krp) * g: the base point of the curve; * x: the private key produced by random; * gx: the public key generated by the private key, - * which could be caculated by gx = g ^ x mod p; + * which could be calculated by gx = g ^ x mod p; * In curve25519, p and g are fixed. */ diff --git a/drivers/analog/ads1115.c b/drivers/analog/ads1115.c index c19c27b3a1..7d672f6e33 100644 --- a/drivers/analog/ads1115.c +++ b/drivers/analog/ads1115.c @@ -352,10 +352,10 @@ static int cmdbyte_init(FAR struct ads1115_dev_s *priv) * reading is stored. * * NOTE: - * When switching between channels in continous mode, old data may be read. - * Using the ALERT/RDY pin can avoid this. + * When switching between channels in continuous mode, old data may be + * read. Using the ALERT/RDY pin can avoid this. * - * Each channel corrseponds to a differing mux configuration as defined in + * Each channel corresponds to a differing mux configuration as defined in * the datasheet. * * msg->am_channel MUX Configuration diff --git a/drivers/analog/ads1255.c b/drivers/analog/ads1255.c index a7332a03e4..1293609ff0 100644 --- a/drivers/analog/ads1255.c +++ b/drivers/analog/ads1255.c @@ -481,7 +481,7 @@ static int adc_interrupt(int irq, FAR void *context, FAR void *arg) up_disable_irq(priv->irq); - /* Schedule the ADC work for the worker thread. Whent he sample has been + /* Schedule the ADC work for the worker thread. When the sample has been * processed, the ADC interrupt will be re-enabled. */ diff --git a/drivers/analog/hx711.c b/drivers/analog/hx711.c index 14ce63e11c..8e549a1730 100644 --- a/drivers/analog/hx711.c +++ b/drivers/analog/hx711.c @@ -866,7 +866,7 @@ static int hx711_close(FAR struct file *filep) * * Description: * Action to take upon file unlinking. Function will free resources if - * noone is using the driver when unlinking occured. If driver is still + * no one is using the driver when unlinking occurred. If driver is still * in use, it will be marked as unlinked and resource freeing will take * place in hx711_close() function instead, once last reference is closed. * @@ -874,7 +874,7 @@ static int hx711_close(FAR struct file *filep) * inode - driver inode that is being unlinked. * * Returned Value: - * OK on successfull close, or negated errno on failure. + * OK on successful close, or negated errno on failure. * ****************************************************************************/ @@ -929,7 +929,7 @@ static int hx711_unlink(FAR struct inode *inode) * Input Parameters: * minor - unique number identifying hx711 chip. * lower - provided by platform code to manipulate hx711 with platform - * dependant functions> + * dependent functions> * * Returned Value: * OK on success, or negated errno on failure diff --git a/drivers/analog/pga11x.c b/drivers/analog/pga11x.c index 0353c38ed8..83943203e4 100644 --- a/drivers/analog/pga11x.c +++ b/drivers/analog/pga11x.c @@ -137,8 +137,8 @@ static void pga11x_lock(FAR struct spi_dev_s *spi) { spiinfo("Locking\n"); - /* On SPI busses where there are multiple devices, it will be necessary to - * lock SPI to have exclusive access to the busses for a sequence of + /* On SPI buses where there are multiple devices, it will be necessary to + * lock SPI to have exclusive access to the buses for a sequence of * transfers. The bus should be locked before the chip is selected. * * This is a blocking call and will not return until we have exclusive @@ -150,7 +150,7 @@ static void pga11x_lock(FAR struct spi_dev_s *spi) /* After locking the SPI bus, the we also need call the setfrequency, * setbits, and setmode methods to make sure that the SPI is properly - * configured for the device. If the SPI buss is being shared, then it may + * configured for the device. If the SPI bus is being shared, then it may * have been left in an incompatible state. */ diff --git a/drivers/audio/cs4344.c b/drivers/audio/cs4344.c index dd956fcd0f..bb16fd96cc 100644 --- a/drivers/audio/cs4344.c +++ b/drivers/audio/cs4344.c @@ -995,7 +995,7 @@ static int cs4344_pause(FAR struct audio_lowerhalf_s *dev) if (priv->running && !priv->paused) { - /* Disable interrupts to prevent us from suppling any more data */ + /* Disable interrupts to prevent us from supplying any more data */ priv->paused = true; } diff --git a/drivers/audio/cs43l22.c b/drivers/audio/cs43l22.c index f5b3ef385b..4d9da4c7cf 100644 --- a/drivers/audio/cs43l22.c +++ b/drivers/audio/cs43l22.c @@ -1238,7 +1238,7 @@ static int cs43l22_pause(FAR struct audio_lowerhalf_s *dev) if (priv->running && !priv->paused) { - /* Disable interrupts to prevent us from suppling any more data */ + /* Disable interrupts to prevent us from supplying any more data */ priv->paused = true; cs43l22_setvolume(priv, priv->volume, true); diff --git a/drivers/audio/vs1053.c b/drivers/audio/vs1053.c index 33957cc693..e9f2d31d05 100644 --- a/drivers/audio/vs1053.c +++ b/drivers/audio/vs1053.c @@ -1637,7 +1637,7 @@ static int vs1053_resume(FAR struct audio_lowerhalf_s *lower) return OK; } - /* Enable interrupts to allow suppling data */ + /* Enable interrupts to allow supplying data */ dev->paused = false; vs1053_feeddata(dev); diff --git a/drivers/audio/wm8904.c b/drivers/audio/wm8904.c index ff3e3b6496..51d43977c4 100644 --- a/drivers/audio/wm8904.c +++ b/drivers/audio/wm8904.c @@ -1675,7 +1675,7 @@ static int wm8904_pause(FAR struct audio_lowerhalf_s *dev) if (priv->running && !priv->paused) { - /* Disable interrupts to prevent us from suppling any more data */ + /* Disable interrupts to prevent us from supplying any more data */ priv->paused = true; wm8904_setvolume(priv, priv->volume, true); diff --git a/drivers/audio/wm8994.c b/drivers/audio/wm8994.c index 51422d8651..86fc2db97b 100644 --- a/drivers/audio/wm8994.c +++ b/drivers/audio/wm8994.c @@ -1364,7 +1364,7 @@ static int wm8994_pause(FAR struct audio_lowerhalf_s *dev) if (priv->running && !priv->paused) { - /* Disable interrupts to prevent us from suppling any more data */ + /* Disable interrupts to prevent us from supplying any more data */ priv->paused = true; WM8994_DISABLE(priv->lower); diff --git a/drivers/audio/wm8994.h b/drivers/audio/wm8994.h index 3d5f85b5cf..7f4918aa4e 100644 --- a/drivers/audio/wm8994.h +++ b/drivers/audio/wm8994.h @@ -866,7 +866,7 @@ /* R76 (0x4C) - Charge Pump (1) */ #define WM8994_CP_ENA (1 << 15) /* Bit 15: Enable charge-pump digits */ -#define WM8994_CP_ENA_DISABLE (0) /* Diable */ +#define WM8994_CP_ENA_DISABLE (0) /* Disable */ #define WM8994_CP_ENA_ENABLE (WM8994_CP_ENA) /* Enable */ /* R77 (0x4D) - Charge Pump (2) */ @@ -877,7 +877,7 @@ /* R81 (0x51) - Class W (1) */ -#define WM8994_CP_DYN_SRC_SEL_SHIFT 8 /* Bits 8-9: Selects the digitial audio source for +#define WM8994_CP_DYN_SRC_SEL_SHIFT 8 /* Bits 8-9: Selects the digital audio source for * envelope tracking */ #define WM8994_CP_DYN_SRC_SEL_MASK (3 << WM8994_CP_DYN_SRC_SEL_SHIFT) #define WM8994_CP_DYN_SRC_SEL_AIF1_TS0 (0 << WM8994_CP_DYN_SRC_SEL_SHIFT) /* AIF1, DAC Timeslot 0 */ @@ -931,10 +931,10 @@ * in progress */ #define WM8994_DCS_ENA_CHAN_1 (1 << 1) /* Bit 1: DC Servo enable for HPOUT1R */ -#define WM8994_DCS_ENA_CHAN_1_DISABLE (0) /* Diable */ +#define WM8994_DCS_ENA_CHAN_1_DISABLE (0) /* Disable */ #define WM8994_DCS_ENA_CHAN_1_ENABLE (WM8994_DCS_ENA_CHAN_1) /* Enable */ #define WM8994_DCS_ENA_CHAN_0 (1 << 0) /* Bit 0: DC Servo enable for HPOUT1L */ -#define WM8994_DCS_ENA_CHAN_0_DISABLE (0) /* Diable */ +#define WM8994_DCS_ENA_CHAN_0_DISABLE (0) /* Disable */ #define WM8994_DCS_ENA_CHAN_0_ENABLE (WM8994_DCS_ENA_CHAN_0) /* Enable */ /* R85 (0x55) - DC Servo (2) */ @@ -946,22 +946,22 @@ /* R96 (0x60) - Analogue HP (1) */ #define WM8994_HPOUT1L_RMV_SHORT (1 << 7) /* Bit 7: Removes HPOUT1L short */ -#define WM8994_HPOUT1L_RMV_SHORT_DISABLE (0) /* HPOUT1L short diabled */ +#define WM8994_HPOUT1L_RMV_SHORT_DISABLE (0) /* HPOUT1L short disabled */ #define WM8994_HPOUT1L_RMV_SHORT_ENABLE (WM8994_HPOUT1L_RMV_SHORT) /* HPOUT1L short enabled */ #define WM8994_HPOUT1L_OUTP (1 << 6) /* Bit 6: Enables HPOUT1L output stage */ -#define WM8994_HPOUT1L_OUTP_DISABLE (0) /* Diable */ +#define WM8994_HPOUT1L_OUTP_DISABLE (0) /* Disable */ #define WM8994_HPOUT1L_OUTP_ENABLE (WM8994_HPOUT1L_OUTP) /* Enable */ #define WM8994_HPOUT1L_DLY (1 << 5) /* Bit 5: Enables HPOUT1L intermediate stage */ -#define WM8994_HPOUT1L_DLY_DISABLE (0) /* Diable */ +#define WM8994_HPOUT1L_DLY_DISABLE (0) /* Disable */ #define WM8994_HPOUT1L_DLY_ENABLE (WM8994_HPOUT1L_DLY) /* Enable */ #define WM8994_HPOUT1R_RMV_SHORT (1 << 3) /* Bit 3: Removes HPOUT1R short */ -#define WM8994_HPOUT1R_RMV_SHORT_DISABLE (0) /* HPOUT1R short diabled */ +#define WM8994_HPOUT1R_RMV_SHORT_DISABLE (0) /* HPOUT1R short disabled */ #define WM8994_HPOUT1R_RMV_SHORT_ENABLE (WM8994_HPOUT1R_RMV_SHORT) /* HPOUT1R short enabled */ #define WM8994_HPOUT1R_OUTP (1 << 2) /* Bit 2: Enables HPOUT1R output stage */ -#define WM8994_HPOUT1R_OUTP_DISABLE (0) /* Diable */ +#define WM8994_HPOUT1R_OUTP_DISABLE (0) /* Disable */ #define WM8994_HPOUT1R_OUTP_ENABLE (WM8994_HPOUT1R_OUTP) /* Enable */ #define WM8994_HPOUT1R_DLY (1 << 1) /* Bit 1: Enables HPOUT1R intermediate stage */ -#define WM8994_HPOUT1R_DLY_DISABLE (0) /* Diable */ +#define WM8994_HPOUT1R_DLY_DISABLE (0) /* Disable */ #define WM8994_HPOUT1R_DLY_ENABLE (WM8994_HPOUT1R_DLY) /* Enable */ /* R208 (0xD0) - Mic Detect 1 */ @@ -977,7 +977,7 @@ /* R272 (0x110) - Write Sequencer Ctrl (1) */ #define WM8994_WSEQ_ENA (1 << 15) /* Bit 15: Write Sequencer Enable */ -#define WM8994_WSEQ_ENA_DISABLE (0) /* Diable */ +#define WM8994_WSEQ_ENA_DISABLE (0) /* Disable */ #define WM8994_WSEQ_ENA_ENABLE (WM8994_WSEQ_ENA) /* Enable */ #define WM8994_WSEQ_ABORT (1 << 9) /* Bit 9: Writing 1 to this bit aborts the current seq. */ #define WM8994_WSEQ_START (1 << 8) /* Bit 8: Writing 1 to this bit starts the seq. */ diff --git a/drivers/can/can_sender.c b/drivers/can/can_sender.c index ccbed8272e..a2ddc397cd 100644 --- a/drivers/can/can_sender.c +++ b/drivers/can/can_sender.c @@ -191,7 +191,7 @@ FAR struct can_msg_s *can_get_msg(FAR struct can_txcache_s *cd_sender) * Name: can_revert_msg * * Description: - * Rever msg in sender, because sending failed. + * Revert msg in sender, because sending failed. * ****************************************************************************/ diff --git a/drivers/can/ctucanfd.h b/drivers/can/ctucanfd.h index 3f7ada9fb5..79873ff1fd 100644 --- a/drivers/can/ctucanfd.h +++ b/drivers/can/ctucanfd.h @@ -156,7 +156,7 @@ CTUCANFD_TXSTAT_MASK) #define CTUCANFD_TXSTAT_NOTEXIST (0) /* TXT buffer doesn't exist */ #define CTUCANFD_TXSTAT_RDY (1) /* "Ready" state */ -#define CTUCANFD_TXSTAT_TRAN (2) /* "TX in porgress" state */ +#define CTUCANFD_TXSTAT_TRAN (2) /* "TX in progress" state */ #define CTUCANFD_TXSTAT_ABTP (3) /* "Abort in progress" state */ #define CTUCANFD_TXSTAT_TOK (4) /* "TX OK" state */ #define CTUCANFD_TXSTAT_ERR (6) /* "Failed" state */ @@ -210,7 +210,7 @@ begin_packed_struct struct ctucanfd_frame_fmt_s uint32_t esi_rsv:1; /* Error state indicator */ uint32_t rwcnt:4; /* Size without FRAME_FORMAT WORD */ uint32_t erf_pos:4; /* Error frame position */ - uint32_t erf_erp:1; /* Error pasive state */ + uint32_t erf_erp:1; /* Error passive state */ uint32_t erf_type:3; /* Error frame type */ uint32_t ivld:1; /* Valid identifier */ uint32_t lbtbi:3; /* Loop-back TXT index */ diff --git a/drivers/can/ctucanfd_pci.c b/drivers/can/ctucanfd_pci.c index 66802d8c5f..d5fc1fabb0 100644 --- a/drivers/can/ctucanfd_pci.c +++ b/drivers/can/ctucanfd_pci.c @@ -1779,7 +1779,7 @@ static void ctucanfd_init(FAR struct ctucanfd_driver_s *priv) * Name: ctucanfd_ctucanfd_probe * * Description: - * Probe CTUCANFD devices on board and return the number of vailalbe chips. + * Probe CTUCANFD devices on board and return the number of available chips. * *****************************************************************************/ diff --git a/drivers/can/kvaser_pci.c b/drivers/can/kvaser_pci.c index c10d108b50..3e71bd33f5 100644 --- a/drivers/can/kvaser_pci.c +++ b/drivers/can/kvaser_pci.c @@ -1593,7 +1593,7 @@ static void kvaser_init(FAR struct kvaser_driver_s *priv) * Name: kvaser_count_sja * * Description: - * Probe SJA1000 devices on board and return the number of vailalbe chips. + * Probe SJA1000 devices on board and return the number of available chips. * *****************************************************************************/ diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c index 0cce75e95e..7c5cc1568d 100644 --- a/drivers/clk/clk.c +++ b/drivers/clk/clk.c @@ -44,7 +44,7 @@ #define CLK_PROCFS_LINELEN 80 /**************************************************************************** - * Private Datas + * Private Data ****************************************************************************/ static rmutex_t g_clk_list_lock = NXRMUTEX_INITIALIZER; diff --git a/drivers/clk/clk_rpmsg.c b/drivers/clk/clk_rpmsg.c index 3a581602c7..3710e6678f 100644 --- a/drivers/clk/clk_rpmsg.c +++ b/drivers/clk/clk_rpmsg.c @@ -192,7 +192,7 @@ static int clk_rpmsg_get_phase(FAR struct clk_s *clk); static int clk_rpmsg_set_phase(FAR struct clk_s *clk, int degrees); /**************************************************************************** - * Private Datas + * Private Data ****************************************************************************/ static mutex_t g_clk_rpmsg_lock = NXMUTEX_INITIALIZER; diff --git a/drivers/coresight/coresight_common.c b/drivers/coresight/coresight_common.c index 21a6f9bf58..21cecdd254 100644 --- a/drivers/coresight/coresight_common.c +++ b/drivers/coresight/coresight_common.c @@ -158,7 +158,7 @@ void coresight_disclaim_device(uintptr_t addr) } else { - cserr("current device is not claimed or something wrong happend\n"); + cserr("current device is not claimed or something wrong happened\n"); } coresight_lock(addr); diff --git a/drivers/coresight/coresight_core.c b/drivers/coresight/coresight_core.c index 28e96480de..1869b00571 100644 --- a/drivers/coresight/coresight_core.c +++ b/drivers/coresight/coresight_core.c @@ -619,7 +619,7 @@ static int coresight_enable_path(FAR struct list_node *path) ret = coresight_enable_sink(node->csdev); if (ret < 0) { - cserr("enalbe sink: %s failed ret: %d\n", + cserr("enable sink: %s failed ret: %d\n", node->csdev->name, ret); return ret; } @@ -635,7 +635,7 @@ static int coresight_enable_path(FAR struct list_node *path) next->csdev); if (ret < 0) { - cserr("enalbe link: %s failed ret: %d\n", + cserr("enable link: %s failed ret: %d\n", node->csdev->name, ret); goto err; } diff --git a/drivers/coresight/coresight_etb.c b/drivers/coresight/coresight_etb.c index 70c889229f..ac3073b629 100644 --- a/drivers/coresight/coresight_etb.c +++ b/drivers/coresight/coresight_etb.c @@ -182,7 +182,7 @@ static void etb_hw_read(FAR struct coresight_etb_dev_s *etbdev) /* ARM recommends that addresses are 128-bit aligned. Read from 0 when ETB * buffer is not full, otherwise, read from writepointer and there are some - * trace data has been overwriten and lost. + * trace data has been overwritten and lost. */ readptr = coresight_get32(etbdev->csdev.addr + ETB_RAM_READ_POINTER); diff --git a/drivers/coresight/coresight_etm4.c b/drivers/coresight/coresight_etm4.c index a1b93185b8..88042bf0f0 100644 --- a/drivers/coresight/coresight_etm4.c +++ b/drivers/coresight/coresight_etm4.c @@ -792,7 +792,7 @@ void etm4_disclaim_device(FAR struct coresight_etm4_dev_s *etmdev) } else { - cserr("current device is not claimed or something wrong happend\n"); + cserr("current device is not claimed or something wrong happened\n"); } } diff --git a/drivers/coresight/coresight_tmc_core.c b/drivers/coresight/coresight_tmc_core.c index e79abeb68f..2d28a4f770 100644 --- a/drivers/coresight/coresight_tmc_core.c +++ b/drivers/coresight/coresight_tmc_core.c @@ -44,7 +44,7 @@ static enum tmc_mem_intf_width_e tmc_etf_get_memwidth(uint32_t devid) { - /* Indicate the minimum alignemnt for RRR/RURP/RWP/DBA etc registers. */ + /* Indicate the minimum alignment for RRR/RURP/RWP/DBA etc registers. */ switch (BMVAL(devid, 8, 10)) { @@ -69,7 +69,7 @@ static enum tmc_mem_intf_width_e tmc_etr_get_memwidth(uint32_t devid) { uint32_t val = (BMVAL(devid, 14, 15) << 3) | BMVAL(devid, 8, 10); - /* Indicate the minimum alignemnt for RRR/RURP/RWP/DBA etc registers. */ + /* Indicate the minimum alignment for RRR/RURP/RWP/DBA etc registers. */ switch (val) { diff --git a/drivers/coresight/coresight_tmc_etf.c b/drivers/coresight/coresight_tmc_etf.c index 05587febcb..4079bea3c0 100644 --- a/drivers/coresight/coresight_tmc_etf.c +++ b/drivers/coresight/coresight_tmc_etf.c @@ -115,7 +115,7 @@ static int tmc_etf_sink_hw_enable(FAR struct coresight_tmc_dev_s *tmcdev) return -EAGAIN; } - /* TMC-ETB and TMC-ETF sink device use cirular buffer mode. */ + /* TMC-ETB and TMC-ETF sink device use circular buffer mode. */ coresight_put32(TMC_MODE_CIRCULAR_BUFFER, tmcdev->csdev.addr + TMC_MODE); coresight_put32(TMC_FFCR_EN_FMT | TMC_FFCR_EN_TI | TMC_FFCR_FON_FLIN | @@ -193,7 +193,7 @@ static void tmc_flush_and_stop(FAR struct coresight_tmc_dev_s *tmcdev) * Description: * Dump ETB RAM buffer to device's buffer for usrspace's read. It just need * to performing successive reads to the RRD Register, until the value - * 0xFFFFFFFF is returned whick is kind different from coresight ETB + * 0xFFFFFFFF is returned which is kind different from coresight ETB * device's reading process. refers to TRM. * ****************************************************************************/ @@ -230,7 +230,7 @@ static void tmc_etf_hw_read(FAR struct coresight_tmc_dev_s *tmcdev) * Description: * Used for ETF sink devices to dump trace buffer. Do not dump trace buffer * in tmc_etf_hw_disable to avoid trace buffer's data confusion when a - * process is reading trace buffer and anther process calles tmc_disable. + * process is reading trace buffer and another process calls tmc_disable. * ****************************************************************************/ diff --git a/drivers/devicetree/fdt_cfi.c b/drivers/devicetree/fdt_cfi.c index e544ef18c0..299209674c 100644 --- a/drivers/devicetree/fdt_cfi.c +++ b/drivers/devicetree/fdt_cfi.c @@ -89,7 +89,7 @@ int fdt_cfi_register(FAR const void *fdt) } else { - ferr("cfi flash%d has beed used to store text:" + ferr("cfi flash%d has been used to store text:" "[%x,%x], flash:[%x,%x]\n", i, flash_base, flash_end, CONFIG_FLASH_START, CONFIG_FLASH_START + CONFIG_FLASH_SIZE); diff --git a/drivers/i3c/device.c b/drivers/i3c/device.c index 71e17bb812..3afe7b4fb4 100644 --- a/drivers/i3c/device.c +++ b/drivers/i3c/device.c @@ -257,7 +257,7 @@ void i3c_device_free_ibi(FAR const struct i3c_device *dev) * cmd - The buf of ccc commands to transfer, only one frame at a time * * Returned Value: - * 0 or positive if Success, nagative otherwise. + * 0 or positive if Success, negative otherwise. ****************************************************************************/ int i3c_device_send_ccc_cmd(FAR const struct i3c_device *dev, diff --git a/drivers/i3c/master.c b/drivers/i3c/master.c index 40ab0a763b..fe26126f25 100644 --- a/drivers/i3c/master.c +++ b/drivers/i3c/master.c @@ -2161,8 +2161,8 @@ void i3c_master_detach_i2c_dev(FAR struct i3c_master_controller *master, * * This function takes care of everything for you: * - creates and initializes the I3C bus. - * - registers all I3C charactor driver that supports I3C transfer. - * - registers the I2C charactor driver that supports I2C transfer. + * - registers all I3C character driver that supports I3C transfer. + * - registers the I2C character driver that supports I2C transfer. * * Input Parameters: * master - Master used to send frames on the bus. diff --git a/drivers/input/aw86225.c b/drivers/input/aw86225.c index c93d2f48a7..da46216ee1 100644 --- a/drivers/input/aw86225.c +++ b/drivers/input/aw86225.c @@ -888,7 +888,7 @@ static int aw86225_haptic_cont_get_f0(FAR struct aw86225 *aw86225) else { cnt--; - iinfo("%s waitting for standby, glb_state=0x%02X\n", + iinfo("%s waiting for standby, glb_state=0x%02X\n", __func__, reg_val); } @@ -1133,7 +1133,7 @@ static void aw86225_rtp_work_routine(FAR void *arg) atomic_set(&aw86225->exit_in_rtp_loop, 0); nxsem_post(&aw86225->stop_wait_q); nxmutex_unlock(&aw86225->lock); - ierr("%s: wake up by signal return erro\n", __func__); + ierr("%s: wake up by signal return error\n", __func__); return; } } @@ -2163,7 +2163,7 @@ static int aw86225_haptics_upload_effect(FAR struct ff_lowerhalf_s *lower, iinfo("%s: wakeup \n", __func__); if (ret == -ERESTART) { - ierr("%s: wake up by signal return erro\n", __func__); + ierr("%s: wake up by signal return error\n", __func__); return ret; } diff --git a/drivers/input/ff_dummy.c b/drivers/input/ff_dummy.c index b73ba11d4e..468a3d6ffe 100644 --- a/drivers/input/ff_dummy.c +++ b/drivers/input/ff_dummy.c @@ -93,7 +93,7 @@ static void ff_dummy_haptics_set_gain(FAR struct ff_lowerhalf_s *lower, * * Input Parameters: * devno - The user specifies device number, from 0. If the - * devno alerady exists, -EEXIST will be returned. + * devno already exists, -EEXIST will be returned. * * Returned Value: * Zero (OK) on success; a negated errno value on failure. diff --git a/drivers/input/ff_upper.c b/drivers/input/ff_upper.c index b8024b1987..43eee8e809 100644 --- a/drivers/input/ff_upper.c +++ b/drivers/input/ff_upper.c @@ -550,7 +550,7 @@ int ff_register(FAR struct ff_lowerhalf_s *lower, FAR const char *path, * release the occupied resources. * * Arguments: - * lower - A pointer to an insatnce of force feedback lower half driver. + * lower - A pointer to an instance of force feedback lower half driver. * path - The path of force feedback device. such as "/dev/input0" * ****************************************************************************/ diff --git a/drivers/input/spq10kbd.c b/drivers/input/spq10kbd.c index 0f11208e3a..6975ba60d3 100644 --- a/drivers/input/spq10kbd.c +++ b/drivers/input/spq10kbd.c @@ -425,7 +425,7 @@ static int spq10kbd_interrupt(int irq, FAR void *context, FAR void *arg) int ret; /* Let the event worker know that it has an interrupt event to handle - * It is possbile that we will already have work scheduled from a + * It is possible that we will already have work scheduled from a * previous interrupt event. That is OK we will service all the events * in the same work job. */ diff --git a/drivers/input/stmpe811_tsc.c b/drivers/input/stmpe811_tsc.c index 7fd2d83e1c..986ac2cb7a 100644 --- a/drivers/input/stmpe811_tsc.c +++ b/drivers/input/stmpe811_tsc.c @@ -916,7 +916,7 @@ int stmpe811_register(STMPE811_HANDLE handle, int minor) stmpe811_tscinitialize(priv); - /* Inidicate that the touchscreen controller was successfully initialized */ + /* Indicate that the touchscreen controller was successfully initialized */ priv->inuse |= TSC_PIN_SET; /* Pins 4-7 are now in-use */ priv->flags |= STMPE811_FLAGS_TSC_INITIALIZED; /* TSC function is initialized */ diff --git a/drivers/ioexpander/sx1509.c b/drivers/ioexpander/sx1509.c index 09baeeced3..8c86f312f2 100644 --- a/drivers/ioexpander/sx1509.c +++ b/drivers/ioexpander/sx1509.c @@ -877,7 +877,7 @@ static int sx1509_interrupt(int irq, FAR void *context, FAR void *arg) * Name: sx1509_osc_config * * Description: - * Configure oscilator required for LED driver and keypad engine. + * Configure oscillator required for LED driver and keypad engine. * ****************************************************************************/ @@ -893,7 +893,7 @@ static int sx1509_osc_config(FAR struct sx1509_dev_s *priv) return ret; } - /* Configure oscilator source */ + /* Configure oscillator source */ buf[0] = SX1509_REGCLOCK; buf[1] = SX1509_OSC_INT; @@ -1332,7 +1332,7 @@ int sx1509_leds_initialize(FAR struct ioexpander_dev_s *ioe, FAR struct sx1509_dev_s *priv = (FAR struct sx1509_dev_s *)ioe; int ret; - /* Configure oscilator */ + /* Configure oscillator */ ret = sx1509_osc_config(priv); if (ret < 0) diff --git a/drivers/ipcc/ipcc_close.c b/drivers/ipcc/ipcc_close.c index a12ef6bba7..64aa85fe2a 100644 --- a/drivers/ipcc/ipcc_close.c +++ b/drivers/ipcc/ipcc_close.c @@ -52,7 +52,7 @@ * filep - pointer to a file structure to close. * * Returned Value: - * OK on successfull close, or negated errno on failure. + * OK on successful close, or negated errno on failure. * * Assumptions/Limitations: * diff --git a/drivers/ipcc/ipcc_open.c b/drivers/ipcc/ipcc_open.c index 6f160cf69a..bf62e266c9 100644 --- a/drivers/ipcc/ipcc_open.c +++ b/drivers/ipcc/ipcc_open.c @@ -49,7 +49,7 @@ * filep - pointer to a file structure to open. * * Returned Value: - * OK on successfull open, or negated errno on failure. + * OK on successful open, or negated errno on failure. * * Assumptions/Limitations: * diff --git a/drivers/ipcc/ipcc_unlink.c b/drivers/ipcc/ipcc_unlink.c index a6630b2f55..1153da1cca 100644 --- a/drivers/ipcc/ipcc_unlink.c +++ b/drivers/ipcc/ipcc_unlink.c @@ -46,7 +46,7 @@ * * Description: * Action to take upon file unlinking. Function will free resources if - * noone is using the driver when unlinking occured. If driver is still + * no one is using the driver when unlinking occurred. If driver is still * in use, it will be marked as unlinked and resource freeing will take * place in ipcc_close() function instead, once last reference is closed. * @@ -54,7 +54,7 @@ * inode - driver inode that is being unlinked * * Returned Value: - * OK on successfull close, or negated errno on failure. + * OK on successful close, or negated errno on failure. * * Assumptions/Limitations: * diff --git a/drivers/ipcc/ipcc_write.c b/drivers/ipcc/ipcc_write.c index aee5eedc51..723a9f6808 100644 --- a/drivers/ipcc/ipcc_write.c +++ b/drivers/ipcc/ipcc_write.c @@ -106,7 +106,7 @@ void ipcc_txfree_notify(FAR struct ipcc_driver_s *priv) * * Description: * Writes data to IPCC memory so that another CPU can read the contents. - * Will block untill whole buffer is copied unless signal is received + * Will block until whole buffer is copied unless signal is received * or O_NONBLOCK flag is set. * * Input Parameters: diff --git a/drivers/lcd/apa102.c b/drivers/lcd/apa102.c index 1e28a63113..b77caf3666 100644 --- a/drivers/lcd/apa102.c +++ b/drivers/lcd/apa102.c @@ -475,7 +475,7 @@ static int apa102_putrun(FAR struct lcd_dev_s *dev, fb_coord_t row, * buffer - The buffer containing the area to be written to the LCD * stride - Length of a line in bytes. This parameter may be necessary * to allow the LCD driver to calculate the offset for partial - * writes when the buffer needs to be splited for row-by-row + * writes when the buffer needs to be split for row-by-row * writing. * ****************************************************************************/ diff --git a/drivers/lcd/gc9a01.c b/drivers/lcd/gc9a01.c index 679c4feeb1..e0056c00cf 100644 --- a/drivers/lcd/gc9a01.c +++ b/drivers/lcd/gc9a01.c @@ -651,7 +651,7 @@ static int gc9a01_putrun(FAR struct lcd_dev_s *dev, * buffer - The buffer containing the area to be written to the LCD * stride - Length of a line in bytes. This parameter may be necessary * to allow the LCD driver to calculate the offset for partial - * writes when the buffer needs to be splited for row-by-row + * writes when the buffer needs to be split for row-by-row * writing. * ****************************************************************************/ diff --git a/drivers/lcd/jd9851.c b/drivers/lcd/jd9851.c index 61d5afdec1..e3d0914cb6 100644 --- a/drivers/lcd/jd9851.c +++ b/drivers/lcd/jd9851.c @@ -663,7 +663,7 @@ static int jd9851_putrun(FAR struct lcd_dev_s *dev, * buffer - The buffer containing the area to be written to the LCD * stride - Length of a line in bytes. This parameter may be necessary * to allow the LCD driver to calculate the offset for partial - * writes when the buffer needs to be splited for row-by-row + * writes when the buffer needs to be split for row-by-row * writing. * ****************************************************************************/ diff --git a/drivers/lcd/mio283qt2.c b/drivers/lcd/mio283qt2.c index 0b10e6fbd4..03927efdfb 100644 --- a/drivers/lcd/mio283qt2.c +++ b/drivers/lcd/mio283qt2.c @@ -568,7 +568,7 @@ static int mio283qt2_getrun(FAR struct lcd_dev_s *dev, lcd->select(lcd); - /* Red the run fram GRAM. */ + /* Read the run from GRAM. */ mio283qt2_setarea(lcd, col, row, col + npixels - 1, row); mio283qt2_gramselect(lcd); diff --git a/drivers/lcd/mio283qt9a.c b/drivers/lcd/mio283qt9a.c index 5e8356b633..0f015e2e99 100644 --- a/drivers/lcd/mio283qt9a.c +++ b/drivers/lcd/mio283qt9a.c @@ -468,7 +468,7 @@ static int mio283qt9a_getrun(FAR struct lcd_dev_s *dev, lcd->select(lcd); - /* Red the run fram GRAM. */ + /* Read the run from GRAM. */ mio283qt9a_setarea(lcd, col, row, col + npixels - 1, row); mio283qt9a_gramselect_read(lcd); diff --git a/drivers/lcd/pcd8544.h b/drivers/lcd/pcd8544.h index 40908a34a9..223d482b81 100644 --- a/drivers/lcd/pcd8544.h +++ b/drivers/lcd/pcd8544.h @@ -44,7 +44,7 @@ #define PCD8544_MODEV (1 << 1) /* Enable Vertical Addressing */ #define PCD8544_MODEH (1 << 0) /* Enable extended instruction set */ -/* Command with Instructon Set H = 0 */ +/* Command with Instruction Set H = 0 */ #define PCD8544_DISP_CTRL (1 << 3) /* sets display configuration */ #define PCD8544_DISP_BLANK 0x00 /* display blank */ @@ -55,7 +55,7 @@ #define PCD8544_SET_Y_ADDR (1 << 6) /* Set the Y bank 0-5 */ #define PCD8544_SET_X_ADDR (1 << 7) /* Set the X bank 0-83 */ -/* Command with Instructon Set H = 1 */ +/* Command with Instruction Set H = 1 */ #define PCD8544_TEMP_COEF (1 << 2) /* set Temperature Coefficient */ #define PCD8544_BIAS_SYSTEM (1 << 4) /* set Bias System */ diff --git a/drivers/lcd/pcf8833.h b/drivers/lcd/pcf8833.h index 2209a79d05..561e0ea4ee 100644 --- a/drivers/lcd/pcf8833.h +++ b/drivers/lcd/pcf8833.h @@ -67,7 +67,7 @@ #define PCF8833_RAMWR 0x2c /* Memory write; Data: (1) write data */ #define PCF8833_RGBSET 0x2d /* Colour set; Data: (1-8) red tones, (9-16) green tones, (17-20) blue tones */ #define PCF8833_PTLAR 0x30 /* Partial area; Data: (1) start address (2) end address */ -#define PCF8833_VSCRDEF 0x33 /* Vertical scroll definition; Data: (1) top fixed, (2) scrol area, (3) bottom fixed */ +#define PCF8833_VSCRDEF 0x33 /* Vertical scroll definition; Data: (1) top fixed, (2) scroll area, (3) bottom fixed */ #define PCF8833_TEOFF 0x34 /* Tearing line off; Data: none */ #define PCF8833_TEON 0x35 /* Tearing line on; Data: (1) don't care */ #define PCF8833_MADCTL 0x36 /* Memory data access control; Data: (1) access control settings */ diff --git a/drivers/lcd/ssd1680.c b/drivers/lcd/ssd1680.c index 5b9742aa50..73a7748230 100644 --- a/drivers/lcd/ssd1680.c +++ b/drivers/lcd/ssd1680.c @@ -279,7 +279,7 @@ static const struct lcd_dev_s g_lcd_epaper_dev = .setpower = ssd1680_setpower, /* setcontrast could be implemented in future by changing - * dispalys voltage and LUT table + * displays voltage and LUT table */ }; diff --git a/drivers/lcd/st7789.c b/drivers/lcd/st7789.c index 8e4fd02d32..82037adbde 100644 --- a/drivers/lcd/st7789.c +++ b/drivers/lcd/st7789.c @@ -359,7 +359,7 @@ static inline void st7789_sendcmd(FAR struct st7789_dev_s *dev, uint8_t cmd) #ifdef CONFIG_LCD_ST7789_3WIRE uint16_t txbuf; - /* Add command prefix (9th bit shoudl be 0 ) */ + /* Add command prefix (9th bit should be 0 ) */ txbuf = LCD_ST7789_CMD_PREFIX | cmd; @@ -777,7 +777,7 @@ static int st7789_putrun(FAR struct lcd_dev_s *dev, * buffer - The buffer containing the area to be written to the LCD * stride - Length of a line in bytes. This parameter may be necessary * to allow the LCD driver to calculate the offset for partial - * writes when the buffer needs to be splited for row-by-row + * writes when the buffer needs to be split for row-by-row * writing. * ****************************************************************************/ diff --git a/drivers/leds/lp503x.c b/drivers/leds/lp503x.c index 3521cd0eeb..4d6c384931 100644 --- a/drivers/leds/lp503x.c +++ b/drivers/leds/lp503x.c @@ -419,7 +419,7 @@ static int lp503x_open(struct file *filep) /* reset and enable the device */ - /* means the device was possibly never regsitered? */ + /* means the device was possibly never registered? */ if (priv->state == LP503X_STATE_UNINIT) { diff --git a/drivers/misc/rpmsgblk.c b/drivers/misc/rpmsgblk.c index 114d7de5a4..f95b127397 100644 --- a/drivers/misc/rpmsgblk.c +++ b/drivers/misc/rpmsgblk.c @@ -56,19 +56,19 @@ struct rpmsgblk_s FAR const char *remotecpu; /* The server cpu name */ FAR const char *remotepath; /* The device path in the server cpu */ sem_t wait; /* Wait sem, used for preventing any - * opreation until the connection + * operation until the connection * between two cpu established. */ mutex_t lock; /* Lock for thread-safe */ - struct geometry geo; /* block geomerty */ - int refs; /* refence count */ + struct geometry geo; /* block geometry */ + int refs; /* reference count */ }; /* Rpmsg device cookie used to handle the response from the remote cpu */ struct rpmsgblk_cookie_s { - sem_t sem; /* Semaphore used fo rpmsg */ + sem_t sem; /* Semaphore used for rpmsg */ int result; /* The return value of the remote call */ FAR void *data; /* The return data buffer of the remote call */ }; @@ -423,7 +423,7 @@ out: * * Parameters: * inode - the blk device inode - * geometry - pointer to the application geomoetry struct + * geometry - pointer to the application geometry struct * * Returned Values: * On success, the number of bytes written are returned (zero indicates @@ -450,7 +450,7 @@ static int rpmsgblk_geometry(FAR struct inode *inode, return ret; } - /* Return the perviously got geometry */ + /* Return the previously got geometry */ if (priv->geo.geo_sectorsize != 0) { @@ -893,8 +893,8 @@ fail: * ept - The rpmsg endpoint * data - The return message * len - The return message length - * src - unknow - * priv - unknow + * src - unknown + * priv - unknown * * Returned Values: * Always OK @@ -929,8 +929,8 @@ static int rpmsgblk_default_handler(FAR struct rpmsg_endpoint *ept, * ept - The rpmsg endpoint * data - The return message * len - The return message length - * src - unknow - * priv - unknow + * src - unknown + * priv - unknown * * Returned Values: * Always OK @@ -976,8 +976,8 @@ static int rpmsgblk_read_handler(FAR struct rpmsg_endpoint *ept, * ept - The rpmsg endpoint * data - The return message * len - The return message length - * src - unknow - * priv - unknow + * src - unknown + * priv - unknown * * Returned Values: * Always OK @@ -1063,8 +1063,8 @@ rpmsgblk_mmc_multi_cmd_handler(FAR struct rpmsgblk_cookie_s *cookie, * ept - The rpmsg endpoint * data - The return message * len - The return message length - * src - unknow - * priv - unknow + * src - unknown + * priv - unknown * * Returned Values: * Always OK @@ -1196,8 +1196,8 @@ static void rpmsgblk_device_destroy(FAR struct rpmsg_device *rdev, * ept - The rpmsg-blk end point * data - The received data * len - The received data length - * src - unknow - * priv - unknow + * src - unknown + * priv - unknown * * Returned Values: * OK on success; A negated errno value is returned on any failure. @@ -1234,7 +1234,7 @@ static int rpmsgblk_ept_cb(FAR struct rpmsg_endpoint *ept, * remotecpu - the server cpu name * remotepath - the device you want to access in the remote cpu * localpath - the device path in local cpu, if NULL, the localpath is - * same as the remotepath, provide this argument to supoort + * same as the remotepath, provide this argument to support * custom device path * * Returned Values: diff --git a/drivers/misc/rpmsgdev.c b/drivers/misc/rpmsgdev.c index 15c270aaae..b25c1b09f9 100644 --- a/drivers/misc/rpmsgdev.c +++ b/drivers/misc/rpmsgdev.c @@ -73,7 +73,7 @@ struct rpmsgdev_s FAR const char *remotecpu; /* The server cpu name */ FAR const char *remotepath; /* The device path in the server cpu */ sem_t wait; /* Wait sem, used for preventing any - * opreation until the connection + * operation until the connection * between two cpu established. */ uint32_t flags; /* Read and write special handle flags */ @@ -83,7 +83,7 @@ struct rpmsgdev_s struct rpmsgdev_cookie_s { - sem_t sem; /* Semaphore used fo rpmsg */ + sem_t sem; /* Semaphore used for rpmsg */ int result; /* The return value of the remote call */ FAR void *data; /* The return data buffer of the remote call */ }; @@ -321,7 +321,7 @@ static void rpmsgdev_wait_cb(FAR struct pollfd *fds) * not NONBLOCKED to avoid the server rptun thread blocked in file_read() * or file_write(). By calling this function before sending the READ or * WRITE command to server, a simulated blocked read/write operation is - * achived. + * achieved. * * Parameters: * filep - the file instance @@ -863,8 +863,8 @@ fail: * ept - The rpmsg endpoint * data - The return message * len - The return message length - * src - unknow - * priv - unknow + * src - unknown + * priv - unknown * * Returned Values: * Always OK @@ -900,8 +900,8 @@ static int rpmsgdev_default_handler(FAR struct rpmsg_endpoint *ept, * ept - The rpmsg endpoint * data - The return message * len - The return message length - * src - unknow - * priv - unknow + * src - unknown + * priv - unknown * * Returned Values: * Always OK @@ -945,8 +945,8 @@ static int rpmsgdev_read_handler(FAR struct rpmsg_endpoint *ept, * ept - The rpmsg endpoint * data - The return message * len - The return message length - * src - unknow - * priv - unknow + * src - unknown + * priv - unknown * * Returned Values: * Always OK @@ -982,8 +982,8 @@ static int rpmsgdev_ioctl_handler(FAR struct rpmsg_endpoint *ept, * ept - The rpmsg endpoint * data - The return message * len - The return message length - * src - unknow - * priv - unknow + * src - unknown + * priv - unknown * * Returned Values: * Always OK @@ -1097,8 +1097,8 @@ static void rpmsgdev_device_destroy(FAR struct rpmsg_device *rdev, * ept - The rpmsg-device end point * data - The received data * len - The received data length - * src - unknow - * priv - unknow + * src - unknown + * priv - unknown * * Returned Values: * OK on success; A negated errno value is returned on any failure. @@ -1135,7 +1135,7 @@ static int rpmsgdev_ept_cb(FAR struct rpmsg_endpoint *ept, * remotecpu - the server cpu name * remotepath - the device you want to access in the remote cpu * localpath - the device path in local cpu, if NULL, the localpath is - * same as the remotepath, provide this argument to supoort + * same as the remotepath, provide this argument to support * custom device path * flags - RPMSGDEV_NOFRAG_READ and RPMSGDEV_NOFRAG_WRITE can be set * to indicates that the read and write data of the device diff --git a/drivers/mmcsd/Kconfig b/drivers/mmcsd/Kconfig index 7ace74ea7e..e550fdcbe6 100644 --- a/drivers/mmcsd/Kconfig +++ b/drivers/mmcsd/Kconfig @@ -60,7 +60,7 @@ config MMCSD_MULTIBLOCK_LIMIT ---help--- The max block can be handled in single transfer. Default to 0, means no limitation. Block count larger than this - limit will be splited to multiple multi-block transfer. Set it to 1 will + limit will be split to multiple multi-block transfer. Set it to 1 will only use single-block transfer mode, and can be used to work around buggy SDIO drivers that cannot handle multiple block transfers. diff --git a/drivers/mmcsd/sdio.c b/drivers/mmcsd/sdio.c index a259fa8e0a..cb6a5f9b38 100644 --- a/drivers/mmcsd/sdio.c +++ b/drivers/mmcsd/sdio.c @@ -415,7 +415,7 @@ int sdio_probe(FAR struct sdio_dev_s *dev) goto err; } - /* Get the maximun and minimum values for VDD */ + /* Get the maximum and minimum values for VDD */ bit = ffs(data); if (bit) diff --git a/drivers/modem/alt1250/alt1250.c b/drivers/modem/alt1250/alt1250.c index da2a7f5730..87480b5a09 100644 --- a/drivers/modem/alt1250/alt1250.c +++ b/drivers/modem/alt1250/alt1250.c @@ -1019,7 +1019,7 @@ static int altcom_recvthread(int argc, FAR char *argv[]) } else if (ret == ALTMDM_RETURN_RESET_PKT) { - m_info("recieve ALTMDM_RETURN_RESET_PKT\n"); + m_info("receive ALTMDM_RETURN_RESET_PKT\n"); set_senddisable(dev, true); } else if (ret == ALTMDM_RETURN_RESET_V1 || @@ -1027,7 +1027,7 @@ static int altcom_recvthread(int argc, FAR char *argv[]) { reason = altmdm_get_reset_reason(); - m_info("recieve ALTMDM_RETURN_RESET_V%s reason: %d\n", + m_info("receive ALTMDM_RETURN_RESET_V%s reason: %d\n", (ret == ALTMDM_RETURN_RESET_V1) ? "1" : "4", reason); @@ -1064,7 +1064,7 @@ static int altcom_recvthread(int argc, FAR char *argv[]) } else if (ret == ALTMDM_RETURN_SUSPENDED) { - m_info("recieve ALTMDM_RETURN_SUSPENDED\n"); + m_info("receive ALTMDM_RETURN_SUSPENDED\n"); nxsem_post(&dev->rxthread_sem); while (1) { @@ -1077,7 +1077,7 @@ static int altcom_recvthread(int argc, FAR char *argv[]) } else if (ret == ALTMDM_RETURN_EXIT) { - m_info("recieve ALTMDM_RETURN_EXIT\n"); + m_info("receive ALTMDM_RETURN_EXIT\n"); is_running = false; } else diff --git a/drivers/modem/alt1250/altcom_hdlr_firmware.c b/drivers/modem/alt1250/altcom_hdlr_firmware.c index 02082ea501..f6840ca6f9 100644 --- a/drivers/modem/alt1250/altcom_hdlr_firmware.c +++ b/drivers/modem/alt1250/altcom_hdlr_firmware.c @@ -248,8 +248,8 @@ int32_t altcom_fwcommon_pkt_parse(FAR struct alt1250_dev_s *dev, FAR struct apicmd_cmddat_fw_deltaupcommres_s *in = (FAR struct apicmd_cmddat_fw_deltaupcommres_s *)pktbuf; - /* Negative value in result_cmd means an error is occured. - * Zero indicates command successed or size of injected data + /* Negative value in result_cmd means an error is occurred. + * Zero indicates command succeeded or size of injected data */ result_cmd = altcom_geterrcode(in->api_result); diff --git a/drivers/modem/alt1250/altcom_hdlr_net.c b/drivers/modem/alt1250/altcom_hdlr_net.c index 815deb33e9..aae035f78d 100644 --- a/drivers/modem/alt1250/altcom_hdlr_net.c +++ b/drivers/modem/alt1250/altcom_hdlr_net.c @@ -349,7 +349,7 @@ static int parse_simd(FAR struct apicmd_cmddat_repevt_simd_s *simd, default: { - m_err("Unsupport SIMD status. status:%d\n", simd->status); + m_err("Unsupported SIMD status. status:%d\n", simd->status); return -EILSEQ; } break; @@ -392,7 +392,7 @@ static int parse_simstate( default: { - m_err("Unsupport SIM state. status:%d\n", simstate->state); + m_err("Unsupported SIM state. status:%d\n", simstate->state); ret = -EILSEQ; } break; @@ -1197,7 +1197,7 @@ int32_t altcom_repevt_pkt_parse(FAR struct alt1250_dev_s *dev, default: { - m_err("Unsupport event type. type:%d\n", in->type); + m_err("Unsupported event type. type:%d\n", in->type); ret = -EILSEQ; } break; @@ -1247,7 +1247,7 @@ int32_t altcom_repevt_pkt_parse(FAR struct alt1250_dev_s *dev, default: { - m_err("Unsupport event type. type:%d\n", + m_err("Unsupported event type. type:%d\n", ntohs(in->type)); ret = -EILSEQ; } diff --git a/drivers/modem/alt1250/altcom_hdlr_sms.c b/drivers/modem/alt1250/altcom_hdlr_sms.c index aac06eb6c5..0e80a58578 100644 --- a/drivers/modem/alt1250/altcom_hdlr_sms.c +++ b/drivers/modem/alt1250/altcom_hdlr_sms.c @@ -301,7 +301,7 @@ int32_t altcom_smsreportrecv_pkt_parse(FAR struct alt1250_dev_s *dev, &in->msg.u.delivery_report.discharge_time, sizeof(report->status_report.discharge_time)); - m_info("[staus report] msg size: %u\n", *msg_sz); + m_info("[status report] msg size: %u\n", *msg_sz); m_info(" msgtype: %u\n", msgheader->msgtype); m_info(" datalen: %u\n", msgheader->datalen); m_info(" refid: %u\n", report->status_report.refid); diff --git a/drivers/modem/alt1250/altcom_hdlr_socket.c b/drivers/modem/alt1250/altcom_hdlr_socket.c index 01d9a65de9..c140af6029 100644 --- a/drivers/modem/alt1250/altcom_hdlr_socket.c +++ b/drivers/modem/alt1250/altcom_hdlr_socket.c @@ -121,7 +121,7 @@ static void altstorage2sockaddr( memcpy(&in6addr_to->sin6_addr, &in6addr_from->sin6_addr, sizeof(struct in6_addr)); - /* LwIP does not use thease members, so it should be set to 0 */ + /* LwIP does not use these members, so it should be set to 0 */ in6addr_to->sin6_flowinfo = 0; in6addr_to->sin6_scope_id = 0; diff --git a/drivers/modem/alt1250/altmdm.c b/drivers/modem/alt1250/altmdm.c index d097d403cf..563304b2a8 100644 --- a/drivers/modem/alt1250/altmdm.c +++ b/drivers/modem/alt1250/altmdm.c @@ -83,7 +83,7 @@ typedef enum altmdm_state_e * state */ ALTMDM_STATE_BODYTRX, /* SPI body transaction state */ ALTMDM_STATE_GOTRX, /* Received normal body state */ - ALTMDM_STATE_GOTRST, /* Received reset pakcet body state */ + ALTMDM_STATE_GOTRST, /* Received reset packet body state */ ALTMDM_STATE_GOTSLEEP, /* Received sleep packet body state */ ALTMDM_STATE_BACKTOIDLE, /* Back to Idle state */ ALTMDM_STATE_RETRECV, /* Return state */ diff --git a/drivers/motor/Make.defs b/drivers/motor/Make.defs index 6baee176b4..f5a4035f12 100644 --- a/drivers/motor/Make.defs +++ b/drivers/motor/Make.defs @@ -32,7 +32,7 @@ ifeq ($(CONFIG_MOTOR_UPPER),y) CSRCS += motor.c endif -# Stepper upper half and lower halfs +# Stepper upper half and lower halves ifeq ($(CONFIG_STEPPER_UPPER),y) CSRCS += stepper.c diff --git a/drivers/motor/foc/drv8301.c b/drivers/motor/foc/drv8301.c index 9e8712e30a..5818849c60 100644 --- a/drivers/motor/foc/drv8301.c +++ b/drivers/motor/foc/drv8301.c @@ -145,7 +145,7 @@ static void drv8301_read(FAR struct drv8301_priv_s *priv, uint8_t addr, regval = 0; SPI_RECVBLOCK(priv->spi, ®val, 1); - /* Retrun data */ + /* Return data */ *data = (regval & 0x7ff); diff --git a/drivers/motor/foc/foc_pwr.c b/drivers/motor/foc/foc_pwr.c index fc0ef44a36..fb60031814 100644 --- a/drivers/motor/foc/foc_pwr.c +++ b/drivers/motor/foc/foc_pwr.c @@ -62,7 +62,7 @@ int focpwr_initialize(FAR struct focpwr_dev_s *pwr, pwr->devno = devno; pwr->ops = ops; - /* Connet to FOC device */ + /* Connect to FOC device */ dev->pwr = pwr; diff --git a/drivers/mtd/gd55.c b/drivers/mtd/gd55.c index 772ffa8842..87cb1e8e45 100644 --- a/drivers/mtd/gd55.c +++ b/drivers/mtd/gd55.c @@ -911,7 +911,7 @@ static int gd55_erase_chip(FAR struct gd55_dev_s *priv) * Name: gd55_write_enable * * Description: - * Enable the device for writing by setting the wriet enable latch bit + * Enable the device for writing by setting the write enable latch bit * * Input Parameters: * priv - a reference to the device structure diff --git a/drivers/mtd/mtd_config_fs.c b/drivers/mtd/mtd_config_fs.c index d846361e64..4e4805a784 100644 --- a/drivers/mtd/mtd_config_fs.c +++ b/drivers/mtd/mtd_config_fs.c @@ -126,7 +126,7 @@ begin_packed_struct struct nvs_ate * Private Function Prototypes ****************************************************************************/ -/* MTD NVS opeation api */ +/* MTD NVS operation api */ static int mtdconfig_open(FAR struct file *filep); static int mtdconfig_close(FAR struct file *filep); @@ -670,7 +670,7 @@ static int nvs_flash_wrt_entry(FAR struct nvs_fs *fs, uint32_t id, if (rc) { - /* Write align block which inlcude part key + part data */ + /* Write align block which include part key + part data */ left = rc; memset(buf, fs->erasestate, NVS_ALIGN_SIZE); @@ -1346,7 +1346,7 @@ static int nvs_startup(FAR struct nvs_fs *fs) /* Check if there exists an old entry with the same id and key * as the newest entry. - * If so, power loss occured before writing the old entry id as expired. + * If so, power loss occurred before writing the old entry id as expired. * We need to set old entry expired. */ diff --git a/drivers/mtd/mtd_onfi.c b/drivers/mtd/mtd_onfi.c index cc3e217baf..3e07c1e45c 100644 --- a/drivers/mtd/mtd_onfi.c +++ b/drivers/mtd/mtd_onfi.c @@ -479,7 +479,7 @@ bool onfi_ebidetect(uintptr_t cmdaddr, uintptr_t addraddr, if (onfi_compatible(cmdaddr, addraddr, dataaddr)) { /* Report true if it is an ONFI device that is not in device - * list (perhaps it is a new device that is ONFI campatible + * list (perhaps it is a new device that is ONFI compatible). */ found = true; diff --git a/drivers/mtd/rpmsgmtd.c b/drivers/mtd/rpmsgmtd.c index 42525d0abd..a6b4afa737 100644 --- a/drivers/mtd/rpmsgmtd.c +++ b/drivers/mtd/rpmsgmtd.c @@ -52,18 +52,18 @@ struct rpmsgmtd_s FAR const char *remotecpu; /* The server cpu name */ FAR const char *remotepath; /* The device path in the server cpu */ sem_t wait; /* Wait sem, used for preventing any - * opreation until the connection + * operation until the connection * between two cpu established. */ mutex_t geolock; /* Get mtd geometry operation mutex */ - struct mtd_geometry_s geo; /* MTD geomerty */ + struct mtd_geometry_s geo; /* MTD geometry */ }; /* Rpmsg device cookie used to handle the response from the remote cpu */ struct rpmsgmtd_cookie_s { - sem_t sem; /* Semaphore used fo rpmsg */ + sem_t sem; /* Semaphore used for rpmsg */ int result; /* The return value of the remote call */ FAR void *data; /* The return data buffer of the remote call */ }; @@ -215,7 +215,7 @@ static int rpmsgmtd_get_geometry(FAR struct rpmsgmtd_s *dev, return ret; } - /* Return the perviously got geometry */ + /* Return the previously got geometry */ if (priv->geo.blocksize != 0) { @@ -775,8 +775,8 @@ fail: * ept - The rpmsg endpoint * data - The return message * len - The return message length - * src - unknow - * priv - unknow + * src - unknown + * priv - unknown * * Returned Values: * Always OK @@ -812,8 +812,8 @@ static int rpmsgmtd_default_handler(FAR struct rpmsg_endpoint *ept, * ept - The rpmsg endpoint * data - The return message * len - The return message length - * src - unknow - * priv - unknow + * src - unknown + * priv - unknown * * Returned Values: * Always OK @@ -859,8 +859,8 @@ static int rpmsgmtd_bread_handler(FAR struct rpmsg_endpoint *ept, * ept - The rpmsg endpoint * data - The return message * len - The return message length - * src - unknow - * priv - unknow + * src - unknown + * priv - unknown * * Returned Values: * Always OK @@ -903,8 +903,8 @@ static int rpmsgmtd_read_handler(FAR struct rpmsg_endpoint *ept, * ept - The rpmsg endpoint * data - The return message * len - The return message length - * src - unknow - * priv - unknow + * src - unknown + * priv - unknown * * Returned Values: * Always OK @@ -939,8 +939,8 @@ static int rpmsgmtd_geometry_handler(FAR struct rpmsg_endpoint *ept, * ept - The rpmsg endpoint * data - The return message * len - The return message length - * src - unknow - * priv - unknow + * src - unknown + * priv - unknown * * Returned Values: * Always OK @@ -1059,8 +1059,8 @@ static void rpmsgmtd_device_destroy(FAR struct rpmsg_device *rdev, * ept - The rpmsg-mtd end point * data - The received data * len - The received data length - * src - unknow - * priv - unknow + * src - unknown + * priv - unknown * * Returned Values: * OK on success; A negated errno value is returned on any failure. @@ -1097,7 +1097,7 @@ static int rpmsgmtd_ept_cb(FAR struct rpmsg_endpoint *ept, * remotecpu - the server cpu name * remotepath - the device you want to access in the remote cpu * localpath - the device path in local cpu, if NULL, the localpath is - * same as the remotepath, provide this argument to supoort + * same as the remotepath, provide this argument to support * custom device path * * Returned Values: diff --git a/drivers/mtd/smart.c b/drivers/mtd/smart.c index ff0f0cb582..701caa5a2d 100644 --- a/drivers/mtd/smart.c +++ b/drivers/mtd/smart.c @@ -2884,7 +2884,7 @@ static int smart_relocate_static_data(FAR struct smart_struct_s *dev, x = minblock; - /* We are resuing nextsector and newsector variables here simply as + /* We are reusing nextsector and newsector variables here simply as * variables for displaying debug data. I have learned through my * years of programming that this is a really good way to create * spaghetti code, but I didn't want to add stack variables just @@ -5312,7 +5312,7 @@ static inline int smart_allocsector(FAR struct smart_struct_s *dev, if (allocsect == NULL) { - ferr("ERROR: Out of memory allocting sector\n"); + ferr("ERROR: Out of memory allocating sector\n"); return -ENOMEM; } diff --git a/drivers/mtd/w25.c b/drivers/mtd/w25.c index 07f585bc51..e6344405cb 100644 --- a/drivers/mtd/w25.c +++ b/drivers/mtd/w25.c @@ -543,7 +543,7 @@ static uint8_t w25_waitwritecomplete(struct w25_dev_s *priv) uint8_t status; /* Loop as long as the memory is busy with a write cycle. Device sets BUSY - * flag to a 1 state whhen previous write or erase command is still + * flag to a 1 state when previous write or erase command is still * executing and during this time, device will ignore further instructions * except for "Read Status Register" and "Erase/Program Suspend" * instructions. diff --git a/drivers/net/e1000.c b/drivers/net/e1000.c index 41761a5825..419263b400 100644 --- a/drivers/net/e1000.c +++ b/drivers/net/e1000.c @@ -69,7 +69,7 @@ /* After RX packet is done, we provide free netpkt to the RX descriptor ring. * The upper-half network logic is responsible for freeing the RX packets * so we need some additional spare netpkt buffers to assure that it's - * allways possible to allocate the new RX packet in the recevier logic. + * always possible to allocate the new RX packet in the receiver logic. * It's hard to tell how many spare buffers is needed, for now it's set to 8. */ @@ -480,7 +480,7 @@ static void e1000_dump_mem(FAR struct e1000_driver_s *priv, * Name: e1000_txclean * * Description: - * Clean transmition ring + * Clean transmission ring * * Input Parameters: * priv - Reference to the driver state structure @@ -673,7 +673,7 @@ static FAR netpkt_t *e1000_receive(FAR struct netdev_lowerhalf_s *dev) e1000_putreg_mem(priv, E1000_RDT, desc); - /* Handle errros */ + /* Handle errors */ if (rx->errors) { @@ -1181,7 +1181,7 @@ static void e1000_disable(FAR struct e1000_driver_s *priv) e1000_putreg_mem(priv, E1000_IMC, priv->irqs); up_disable_irq(priv->irq); - /* Disable Transmiter */ + /* Disable Transmitter */ e1000_putreg_mem(priv, E1000_TCTL, 0); @@ -1289,7 +1289,7 @@ static void e1000_enable(FAR struct e1000_driver_s *priv) e1000_rxclean(priv); - /* All RX descriptors availalbe */ + /* All RX descriptors available */ e1000_putreg_mem(priv, E1000_RDT, E1000_RX_DESC); @@ -1303,7 +1303,7 @@ static void e1000_enable(FAR struct e1000_driver_s *priv) regval = E1000_CTRL_SLU | E1000_CTRL_ASDE; e1000_putreg_mem(priv, E1000_CTRL, regval); - /* Setup and enable Transmiter */ + /* Setup and enable Transmitter */ regval = e1000_getreg_mem(priv, E1000_TCTL); regval |= E1000_TCTL_EN | E1000_TCTL_PSP; @@ -1319,7 +1319,7 @@ static void e1000_enable(FAR struct e1000_driver_s *priv) #endif e1000_putreg_mem(priv, E1000_RCTL, regval); - /* REVISIT: Set granuality to Descriptors */ + /* REVISIT: Set granularity to Descriptors */ regval = e1000_getreg_mem(priv, E1000_RXDCTL); regval |= E1000_RXDCTL_GRAN; @@ -1372,7 +1372,7 @@ static int e1000_initialize(FAR struct e1000_driver_s *priv) priv->irq = pci_get_irq(priv->pcidev); } - /* Attach interupts */ + /* Attach interrupts */ irq_attach(priv->irq, e1000_interrupt, priv); @@ -1401,7 +1401,7 @@ static int e1000_initialize(FAR struct e1000_driver_s *priv) } else { - nwarn("Receive Address not vaild!\n"); + nwarn("Receive Address not valid!\n"); } return OK; diff --git a/drivers/net/e1000.h b/drivers/net/e1000.h index c2f92c7340..06a341a212 100644 --- a/drivers/net/e1000.h +++ b/drivers/net/e1000.h @@ -351,8 +351,8 @@ #define E1000_IVAR_TXQ0_EN (1 << 11) /* Bit 11: Enable bit for TxQ0 */ #define E1000_IVAR_TXQ1_SHIFT (12) /* Bits 12-14: MSI-X vector assigned to TxQ1 */ #define E1000_IVAR_TXQ1_EN (1 << 15) /* Bit 15: Enable bit for TxQ1 */ -#define E1000_IVAR_OTHER_SHIFT (16) /* Bits 16-18: MSI-X vector assigned to Ohter Cause */ -#define E1000_IVAR_OTHER_EN (1 << 19) /* Bit 19: Enable bit for Ohter Cause */ +#define E1000_IVAR_OTHER_SHIFT (16) /* Bits 16-18: MSI-X vector assigned to Other Cause */ +#define E1000_IVAR_OTHER_EN (1 << 19) /* Bit 19: Enable bit for Other Cause */ /* Bits 20-30: Reserved */ #define E1000_IVAR_ONALLWB (1 << 31) /* Bit 31: Tx interrupts occur on every write back */ diff --git a/drivers/net/encx24j600.c b/drivers/net/encx24j600.c index c26efa8cb1..6904ae6d79 100644 --- a/drivers/net/encx24j600.c +++ b/drivers/net/encx24j600.c @@ -238,7 +238,7 @@ struct enc_driver_s struct enc_descr_s txdescralloc[ENC_NTXDESCR]; struct enc_descr_s rxdescralloc[CONFIG_ENCX24J600_NRXDESCR]; - sq_queue_t txfreedescr; /* Free inititialized TX descriptors */ + sq_queue_t txfreedescr; /* Free initialized TX descriptors */ sq_queue_t rxfreedescr; /* Free RX descriptors */ sq_queue_t txqueue; /* Enqueued descriptors waiting for transmission */ sq_queue_t rxqueue; /* Unhandled incoming packets waiting for reception */ diff --git a/drivers/net/igc.c b/drivers/net/igc.c index 98f0b1253b..83979ed2ab 100644 --- a/drivers/net/igc.c +++ b/drivers/net/igc.c @@ -69,7 +69,7 @@ /* After RX packet is done, we provide free netpkt to the RX descriptor ring. * The upper-half network logic is responsible for freeing the RX packets * so we need some additional spare netpkt buffers to assure that it's - * allways possible to allocate the new RX packet in the recevier logic. + * always possible to allocate the new RX packet in the receiver logic. * It's hard to tell how many spare buffers is needed, for now it's set to 8. */ @@ -434,7 +434,7 @@ static void igc_dump_mem(FAR struct igc_driver_s *priv, FAR const char *msg) * Name: igc_txclean * * Description: - * Clean transmition ring + * Clean transmission ring * * Input Parameters: * priv - Reference to the driver state structure @@ -629,7 +629,7 @@ static FAR netpkt_t * igc_receive(FAR struct netdev_lowerhalf_s *dev) igc_putreg_mem(priv, IGC_RDT0, desc); - /* Handle errros */ + /* Handle errors */ if (rx->errors) { @@ -1062,7 +1062,7 @@ static void igc_disable(FAR struct igc_driver_s *priv) igc_putreg_mem(priv, IGC_IMC, IGC_MSIX_IMS); up_disable_irq(priv->irq); - /* Disable Transmiter */ + /* Disable Transmitter */ igc_putreg_mem(priv, IGC_TCTL, 0); @@ -1184,7 +1184,7 @@ static void igc_enable(FAR struct igc_driver_s *priv) igc_putreg_mem(priv, IGC_CTRL, IGC_CTRL_SLU); - /* Setup and enable Transmiter */ + /* Setup and enable Transmitter */ regval = igc_getreg_mem(priv, IGC_TCTL); regval |= IGC_TCTL_EN | IGC_TCTL_PSP; @@ -1215,7 +1215,7 @@ static void igc_enable(FAR struct igc_driver_s *priv) igc_rxclean(priv); - /* All RX descriptors availalbe */ + /* All RX descriptors available */ igc_putreg_mem(priv, IGC_RDT0, IGC_RX_DESC); @@ -1298,7 +1298,7 @@ static int igc_initialize(FAR struct igc_driver_s *priv) } else { - nwarn("Receive Address not vaild!\n"); + nwarn("Receive Address not valid!\n"); } return OK; diff --git a/drivers/net/igc.h b/drivers/net/igc.h index 95586d17d3..0b56aa3c9a 100644 --- a/drivers/net/igc.h +++ b/drivers/net/igc.h @@ -430,9 +430,9 @@ #define IGC_IVARMSC_TCPTIM (0) /* Bits 0-5: MSI-X vectorassigned to TCP timer interrupt */ /* Bits 5-6: Reserved */ #define IGC_IVARMSC_TCPTIM_VAL (1 << 7) /* Bit 7: Enable bit for TCP timer interrupt */ -#define IGC_IVARMSC_OTHER_SHIFT (8) /* Bits 8-12: MSI-X vector assigned to Ohter Cause */ +#define IGC_IVARMSC_OTHER_SHIFT (8) /* Bits 8-12: MSI-X vector assigned to Other Cause */ /* Bits 13-14: Reserved */ -#define IGC_IVARMSC_OTHER_VAL (1 << 15) /* Bit 15: Enable bit for Ohter Cause */ +#define IGC_IVARMSC_OTHER_VAL (1 << 15) /* Bit 15: Enable bit for Other Cause */ /* Bits 20-30: Reserved */ /* General Purpose Interrupt Enable */ diff --git a/drivers/net/ksz9477.c b/drivers/net/ksz9477.c index 0cbd404c65..d2b3aadda5 100644 --- a/drivers/net/ksz9477.c +++ b/drivers/net/ksz9477.c @@ -135,8 +135,8 @@ static int ksz9477_reg_write16(uint16_t reg, uint16_t data) uint32_t data32; /* Errata: 16-bit writes to registers 0xN120-0xN13f will corrupt the - * adjacent regsters. Workaround: perform only 32-bit writes to this - * area + * adjacent registers. Workaround: perform only 32-bit writes to this + * area. */ if ((reg & 0xfff) >= 0x120 && (reg & 0xfff) <= 0x13f) diff --git a/drivers/net/lan9250.c b/drivers/net/lan9250.c index a13a1c1caf..c3f55078f4 100644 --- a/drivers/net/lan9250.c +++ b/drivers/net/lan9250.c @@ -1337,7 +1337,7 @@ static int lan9250_reset(FAR struct lan9250_driver_s *priv) /* Configure HMAC control: * - * - Automaticaly strip the pad field on incoming packets + * - Automatically strip the pad field on incoming packets * - TX enable * - RX enable * - Full duplex mode if !CONFIG_LAN9250_HALFDUPPLEX @@ -1417,7 +1417,7 @@ static int lan9250_transmit(FAR struct lan9250_driver_s *priv) status_size = (regval & TXFIR_TXSFUS_M) >> TXFIR_TXSFUS_S; free_size = regval & TXFIR_TXDFFS_M; - ninfo("availabe status size:%d, free space size:%d\n", + ninfo("available status size:%d, free space size:%d\n", status_size, free_size); /* Clear TX status FIFO if it is no empty by reading data */ diff --git a/drivers/net/netdev_upperhalf.c b/drivers/net/netdev_upperhalf.c index ec51c71b10..afcdc600df 100644 --- a/drivers/net/netdev_upperhalf.c +++ b/drivers/net/netdev_upperhalf.c @@ -157,7 +157,7 @@ static FAR netpkt_t *netpkt_get(FAR struct net_driver_s *dev, if (atomic_fetch_sub(&upper->lower->quota[type], 1) <= 0) { - nwarn("WARNING: Allowing temperarily exceeding quota of %s.\n", + nwarn("WARNING: Allowing temporarily exceeding quota of %s.\n", dev->d_ifname); } @@ -1510,7 +1510,7 @@ FAR uint8_t *netpkt_getbase(FAR netpkt_t *pkt) * Description: * Set the length of data in netpkt, used when data is written into * netpkt by data/base pointer, no need to set this length after - * copyin. + * copying. * * Input Parameters: * dev - The lower half device driver structure diff --git a/drivers/net/tun.c b/drivers/net/tun.c index 0301734cfd..0afcf54220 100644 --- a/drivers/net/tun.c +++ b/drivers/net/tun.c @@ -883,7 +883,7 @@ static int tun_dev_init(FAR struct tun_device_s *priv, #endif priv->dev.d_private = priv; /* Used to recover private state from dev */ - /* Initialize the mutual exlcusion and wait semaphore */ + /* Initialize the mutual exclusion and wait semaphore */ nxmutex_init(&priv->lock); nxsem_init(&priv->read_wait_sem, 0, 0); diff --git a/drivers/net/wifi_sim.c b/drivers/net/wifi_sim.c index bb47bd2eab..06c86be8cc 100644 --- a/drivers/net/wifi_sim.c +++ b/drivers/net/wifi_sim.c @@ -778,7 +778,7 @@ redo: p = realloc(*rbuf, size); if (p == NULL) { - nerr("read bss faied in realloc!\n"); + nerr("read bss failed in realloc!\n"); free(*rbuf); *rbuf = NULL; return -ENOMEM; @@ -813,7 +813,7 @@ static int wifidriver_start_connect(FAR struct wifi_sim_s *wifidev) { case IW_MODE_INFRA: { - /* If wlan is connected, should be disconnect before connectting. */ + /* If wlan is connected, should be disconnect before connecting. */ /* 1. check and disconnect */ diff --git a/drivers/note/note_driver.c b/drivers/note/note_driver.c index e4f702cf3d..c775690887 100644 --- a/drivers/note/note_driver.c +++ b/drivers/note/note_driver.c @@ -2095,7 +2095,7 @@ void sched_note_filter_tag(FAR struct note_filter_named_tag_s *oldf, * PID - Task ID * * Returned Value: - * Retrun name if task name can be retrieved, otherwise NULL + * Return name if task name can be retrieved, otherwise NULL ****************************************************************************/ FAR const char *note_get_taskname(pid_t pid) diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 3d6b7e7049..42860eb325 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -396,7 +396,7 @@ static int pci_ioctl(FAR struct file *filep, int cmd, unsigned long arg) * Name: pci_change_master * * Description: - * Enables/Disbale bus-mastering for device dev + * Enable/Disable bus-mastering for device dev * * Input Parameters: * dev - The PCI device to cchange @@ -602,7 +602,7 @@ static FAR struct pci_device_s *pci_alloc_device(void) * Name: pci_register_bus_devices * * Description: - * Register all devices scanned and all buses scanned to responsing list. + * Register all devices scanned and all buses scanned to responding list. * * Input Parameters: * bus - The boot bus @@ -1191,7 +1191,7 @@ static int pci_enable_msi(FAR struct pci_device_s *dev, FAR int *irq, uint32_t mmc = 0; int ret = OK; - /* Suppoted messages */ + /* Supported messages */ for (mme = 0; (1 << mme) < num; mme++); @@ -1214,7 +1214,7 @@ static int pci_enable_msi(FAR struct pci_device_s *dev, FAR int *irq, return ret; } - /* Write Message Address Regsiter */ + /* Write Message Address Register */ pci_write_config_dword(dev, msi + PCI_MSI_ADDRESS_LO, mar); @@ -1265,7 +1265,7 @@ static void pci_disable_msi(FAR struct pci_device_s *dev, uint8_t msi) pci_read_config_word(dev, msi + PCI_MSI_FLAGS, &flags); - /* Write Message Address Regsiter */ + /* Write Message Address Register */ pci_write_config_dword(dev, msi + PCI_MSI_ADDRESS_LO, 0); @@ -1496,7 +1496,7 @@ pci_find_device_from_bus(FAR struct pci_bus_s *bus, uint8_t busno, * val - The data buffer * * Returned Value: - * Zero if success, otherwise nagative + * Zero if success, otherwise negative * ****************************************************************************/ @@ -1526,7 +1526,7 @@ int pci_bus_read_config(FAR struct pci_bus_s *bus, * val - The data * * Returned Value: - * Zero if success, otherwise nagative + * Zero if success, otherwise negative * ****************************************************************************/ @@ -1555,7 +1555,7 @@ int pci_bus_write_config(FAR struct pci_bus_s *bus, * val - The data buffer * * Returned Value: - * Zero if success, otherwise nagative + * Zero if success, otherwise negative * ****************************************************************************/ @@ -1583,7 +1583,7 @@ int pci_bus_read_io(FAR struct pci_bus_s *bus, uintptr_t addr, * val - The data * * Returned Value: - * Zero if success, otherwise nagative + * Zero if success, otherwise negative * ****************************************************************************/ @@ -1641,7 +1641,7 @@ void pci_clear_master(FAR struct pci_device_s *dev) * dev - PCI device to be enabled * * Returned Value: - * Zero if success, otherwise nagative + * Zero if success, otherwise negative * ****************************************************************************/ @@ -1665,7 +1665,7 @@ int pci_enable_device(FAR struct pci_device_s *dev) * dev - PCI device to be disable * * Returned Value: - * Zero if success, otherwise nagative + * Zero if success, otherwise negative * ****************************************************************************/ @@ -1918,7 +1918,7 @@ int pci_get_irq(FAR struct pci_device_s *dev) * num - number of vectors * * Return value: - * Return the number of allocated vectors on succes or negative errno + * Return the number of allocated vectors on success or negative errno * on failure. * ****************************************************************************/ @@ -2014,7 +2014,7 @@ int pci_connect_irq(FAR struct pci_device_s *dev, FAR int *irq, int num) #ifdef CONFIG_PCI_MSIX if (msix != 0) { - /* Disalbe MSI */ + /* Disable MSI */ if (msi != 0) { @@ -2323,7 +2323,7 @@ int pci_dev_register(void) * val - The data buf * * Returned Value: - * Zero if success, otherwise nagative + * Zero if success, otherwise negative * ****************************************************************************/ @@ -2344,7 +2344,7 @@ PCI_BUS_READ_CONFIG(dword, uint32_t, 4) * val - The data * * Returned Value: - * Zero if success, otherwise nagative + * Zero if success, otherwise negative * ****************************************************************************/ @@ -2364,7 +2364,7 @@ PCI_BUS_WRITE_CONFIG(dword, uint32_t, 4) * val - The data buffer * * Returned Value: - * Zero if success, otherwise nagative + * Zero if success, otherwise negative * ****************************************************************************/ @@ -2384,7 +2384,7 @@ PCI_BUS_READ_IO(dword, uint32_t, 4) * val - The data * * Returned Value: - * Zero if success, otherwise nagative + * Zero if success, otherwise negative * ****************************************************************************/ diff --git a/drivers/pci/pci_ecam.c b/drivers/pci/pci_ecam.c index 3a31d065ab..2a8a128409 100644 --- a/drivers/pci/pci_ecam.c +++ b/drivers/pci/pci_ecam.c @@ -189,7 +189,7 @@ static bool pci_ecam_addr_valid(FAR const struct pci_bus_s *bus, * Name: pci_ecam_read_config * * Description: - * Read data from the speicfy register. + * Read data from the specified register. * * Input Parameters: * bus - The bus on this to read reg data @@ -247,7 +247,7 @@ static int pci_ecam_read_config(FAR struct pci_bus_s *bus, * Name: pci_ecam_write_config * * Description: - * Write data into speicfy register. + * Write data into specified register. * * Input Parameters: * bus - The specify bus private data diff --git a/drivers/pci/pci_ep_test.c b/drivers/pci/pci_ep_test.c index a6dc9682d8..7cff95e433 100644 --- a/drivers/pci/pci_ep_test.c +++ b/drivers/pci/pci_ep_test.c @@ -656,7 +656,7 @@ pci_ep_test_set_irq(struct pci_ep_test_s *test, int req_irq_type) if (req_irq_type < PCI_EP_TEST_IRQ_TYPE_LEGACY || req_irq_type > PCI_EP_TEST_COMMAND_MSIX_IRQ) { - pcierr("invaild irq option\n"); + pcierr("invalid irq option\n"); return false; } @@ -702,7 +702,7 @@ static int pci_ep_test_ioctl(FAR struct file *filep, bar = arg; if (bar > PCI_STD_NUM_BARS || bar < 0) { - pcierr("bar num %d is invaild\n", bar); + pcierr("bar num %d is invalid\n", bar); break; } @@ -775,7 +775,7 @@ static int pci_ep_test_probe(FAR struct pci_device_s *dev) test = kmm_zalloc(sizeof(*test)); if (NULL == test) { - pcierr("malloc ptest memory faild\n"); + pcierr("malloc ptest memory failed\n"); return -ENOMEM; } diff --git a/drivers/pci/pci_qemu_edu.c b/drivers/pci/pci_qemu_edu.c index 4f6dc7512e..b0c58bab98 100644 --- a/drivers/pci/pci_qemu_edu.c +++ b/drivers/pci/pci_qemu_edu.c @@ -48,13 +48,13 @@ #define PCI_QEMU_EDU_REG_LIVE 0x04 /* Liveness Check */ #define PCI_QEMU_EDU_REG_FAC 0x08 /* Factorial Computation */ #define PCI_QEMU_EDU_REG_STATUS 0x20 /* Status */ -#define PCI_QEMU_EDU_REG_INT_STATUS 0x24 /* Interupt Status */ +#define PCI_QEMU_EDU_REG_INT_STATUS 0x24 /* Interrupt Status */ #define PCI_QEMU_EDU_REG_INT_RAISE 0x60 /* Raise an interrupt */ #define PCI_QEMU_EDU_REG_INT_ACK 0x64 /* Acknowledge interrupt */ #define PCI_QEMU_EDU_REG_DMA_SOURCE 0x80 /* Source address for DMA transfer */ #define PCI_QEMU_EDU_REG_DMA_DEST 0x88 /* Destination address for DMA transfer */ #define PCI_QEMU_EDU_REG_DMA_COUNT 0x90 /* Size of area to transfer with DMA */ -#define PCI_QEMU_EDU_REG_DMA_CMD 0x98 /* Control DMA tranfer */ +#define PCI_QEMU_EDU_REG_DMA_CMD 0x98 /* Control DMA transfer */ /* One 4096 bytes long buffer at offset 0x40000 is available in the * EDU device diff --git a/drivers/power/battery/axp202.c b/drivers/power/battery/axp202.c index 1c4bb2f2d4..d717686ea4 100644 --- a/drivers/power/battery/axp202.c +++ b/drivers/power/battery/axp202.c @@ -245,7 +245,7 @@ static int axp202_health(FAR struct battery_charger_dev_s *dev, /* Only a few of the possible states are supported by this driver: * BATTERY_HEALTH_UNKNOWN - health state is not known - * BATTERY_HEALTH_GOOD - is in good condiction + * BATTERY_HEALTH_GOOD - is in good condition * BATTERY_HEALTH_DEAD - is dead, nothing we can do * BATTERY_HEALTH_OVERHEAT - is over recommended temperature * BATTERY_HEALTH_OVERVOLTAGE - voltage is over recommended level diff --git a/drivers/power/battery/goldfish_battery.c b/drivers/power/battery/goldfish_battery.c index 958e96c428..1a8246b54e 100644 --- a/drivers/power/battery/goldfish_battery.c +++ b/drivers/power/battery/goldfish_battery.c @@ -233,11 +233,11 @@ static int goldfish_battery_temp(FAR struct battery_gauge_dev_s *dev, int32_t regval; float temp; - /* BATTERY_TEMP units is 0.1 celsuis */ + /* BATTERY_TEMP units is 0.1 celsius */ regval = GOLDFISH_BATTERY_READ(data, BATTERY_TEMP); - /* convert to unit celsuis and fill b16_t */ + /* convert to unit celsius and fill b16_t */ temp = regval / 10.0f; *value = ftob8(temp); diff --git a/drivers/power/pm/Kconfig b/drivers/power/pm/Kconfig index 598230cc6c..c475070d0e 100644 --- a/drivers/power/pm/Kconfig +++ b/drivers/power/pm/Kconfig @@ -38,7 +38,7 @@ config PM_RUNTIME ---help--- Enable PM runtime that can suspend/resume device by driver when system is running. If the device is not used, you can use - PM rutime interface to suspend the device. When the device is + PM runtime interface to suspend the device. When the device is needed again, the driver can call the framework to wake up the device. diff --git a/drivers/power/pm/pm_activity.c b/drivers/power/pm/pm_activity.c index 6fd3c78ab1..8788e28790 100644 --- a/drivers/power/pm/pm_activity.c +++ b/drivers/power/pm/pm_activity.c @@ -197,7 +197,7 @@ void pm_relax(int domain, enum pm_state_e state) * This function is called by a device driver to indicate that it is * performing meaningful activities (non-idle), needs the power kept at * the last the specified level. - * And this will timeout after time (ms), menas auto pm_relax + * And this will timeout after time (ms), means auto pm_relax * * Input Parameters: * domain - The domain of the PM activity @@ -423,7 +423,7 @@ void pm_wakelock_relax(FAR struct pm_wakelock_s *wakelock) * This function is called by a device driver to indicate that it is * performing meaningful activities (non-idle), needs the power at kept * last the specified level. - * And this will be timeout after time (ms), menas auto pm_wakelock_relax + * And this will be timeout after time (ms), means auto pm_wakelock_relax * * Input Parameters: * wakelock - wakelock ID diff --git a/drivers/power/supply/Kconfig b/drivers/power/supply/Kconfig index aadf309552..91876e23b3 100644 --- a/drivers/power/supply/Kconfig +++ b/drivers/power/supply/Kconfig @@ -84,7 +84,7 @@ menuconfig REGULATOR_ACT8945A TAKE GREAT CARE - BOARD DAMAGE MAY RESULT FROM INNAPPROPIATE CHANGES ----------------------------------------------------------------------- - The ACT8945A regulator driver implements the lower regulator ops thats + The ACT8945A regulator driver implements the lower regulator ops that use I2C to control the regulator functions. if REGULATOR_ACT8945A diff --git a/drivers/power/supply/smps.c b/drivers/power/supply/smps.c index 9a8dd42ea0..58b61cce3c 100644 --- a/drivers/power/supply/smps.c +++ b/drivers/power/supply/smps.c @@ -243,8 +243,8 @@ static int smps_ioctl(FAR struct file *filep, int cmd, unsigned long arg) goto errout; } - /* When constan current mode, then output current must be - * provided + /* When constant current mode, then output current must be + * provided. */ if (smps->opmode == SMPS_OPMODE_CC && smps->param.i_out <= 0) @@ -255,8 +255,8 @@ static int smps_ioctl(FAR struct file *filep, int cmd, unsigned long arg) goto errout; } - /* When constan voltage mode, then output voltage must be - * provided + /* When constant voltage mode, then output voltage must be + * provided. */ if (smps->opmode == SMPS_OPMODE_CV && smps->param.v_out <= 0) @@ -267,7 +267,7 @@ static int smps_ioctl(FAR struct file *filep, int cmd, unsigned long arg) goto errout; } - /* When constan power mode, then output power must be provided */ + /* When constant power mode, then output power must be provided */ if (smps->opmode == SMPS_OPMODE_CP && smps->param.p_out <= 0) { diff --git a/drivers/rc/lirc_dev.c b/drivers/rc/lirc_dev.c index 57b2f67256..a50d792fc2 100644 --- a/drivers/rc/lirc_dev.c +++ b/drivers/rc/lirc_dev.c @@ -763,7 +763,7 @@ static ssize_t lirc_read(FAR struct file *filep, FAR char *buffer, * Input Parameters: * lower - A pointer to an instance of lower half lirc driver. * devno - The user specifies device number, from 0. If the - * devno alerady exists, -EEXIST will be returned. + * devno already exists, -EEXIST will be returned. * * Returned Value: * OK if the driver was successfully register; A negated errno value is diff --git a/drivers/regmap/regmap_spi.c b/drivers/regmap/regmap_spi.c index f90f3b0060..7483318949 100644 --- a/drivers/regmap/regmap_spi.c +++ b/drivers/regmap/regmap_spi.c @@ -191,7 +191,7 @@ regmap_init_spi(FAR struct spi_dev_s *spi, uint32_t freq, dev->base.read = regmap_spi_read; dev->trans.deselect = true; /* De-select after transfer. */ - dev->seq.dev = devid; /* SPI controler hard cs index. */ + dev->seq.dev = devid; /* SPI controller hard cs index. */ dev->seq.mode = mode; /* See enum spi_mode_e. */ dev->seq.nbits = 8; /* Number of bits, Only supports 8bit. */ dev->seq.ntrans = 1; /* Number of transactions. */ diff --git a/drivers/reset/core.c b/drivers/reset/core.c index f67eedf503..dff6ba398b 100644 --- a/drivers/reset/core.c +++ b/drivers/reset/core.c @@ -437,7 +437,7 @@ reset_controller_get_by_name(FAR const char *name) * name - The reset controller name * index - The reset controller in reset controller device * shared - Is this a shared (1), or an exclusive (0) reset_control - * acquired - Flags that used to get a exculsive reset control + * acquired - Flags that used to get a exclusive reset control * * Returned Value: * Return reset_control if success, others return NULL if failed @@ -827,7 +827,7 @@ int reset_control_acquire(FAR struct reset_control *rstc) /**************************************************************************** * Name: reset_control_release() * - * Discription: + * Description: * Releases exclusive access to a reset control. * * Releases exclusive access right to a reset control previously obtained @@ -982,7 +982,7 @@ int reset_control_device_reset(FAR const char *name) } /**************************************************************************** - * Nmae: reset_controller_register + * Name: reset_controller_register * * Description: * Register a reset controller device diff --git a/drivers/rpmsg/rpmsg_port_uart.c b/drivers/rpmsg/rpmsg_port_uart.c index 545214668a..0e8650dde7 100644 --- a/drivers/rpmsg/rpmsg_port_uart.c +++ b/drivers/rpmsg/rpmsg_port_uart.c @@ -430,7 +430,7 @@ static int rpmsg_port_uart_tx_thread(int argc, FAR char *argv[]) * Name: rpmsg_port_uart_initialize * * Description: - * Initialze a rpmsg_port_uart device to communicate between two chips. + * Initialize a rpmsg_port_uart device to communicate between two chips. * * Input Parameters: * cfg - Configuration of buffers needed for communication. diff --git a/drivers/rpmsg/rpmsg_virtio_ivshmem.c b/drivers/rpmsg/rpmsg_virtio_ivshmem.c index dadc009f8f..e339dd5eb7 100644 --- a/drivers/rpmsg/rpmsg_virtio_ivshmem.c +++ b/drivers/rpmsg/rpmsg_virtio_ivshmem.c @@ -156,7 +156,7 @@ rpmsg_virtio_ivshmem_get_resource(FAR struct rpmsg_virtio_lite_s *dev) } else { - /* Wait untils master is ready, salve need use master base to + /* Wait until master is ready, slave needs to use master base to * initialize addrenv. */ diff --git a/drivers/rptun/rptun_ivshmem.c b/drivers/rptun/rptun_ivshmem.c index 6b836c2b0d..57f4617747 100644 --- a/drivers/rptun/rptun_ivshmem.c +++ b/drivers/rptun/rptun_ivshmem.c @@ -155,7 +155,7 @@ rptun_ivshmem_get_resource(FAR struct rptun_dev_s *dev) { priv->raddrenv[0].pa = (uintptr_t)priv->shmem; - /* Wait untils salve is ready */ + /* Wait until slave is ready */ while (RPTUN_GET_CMD(cmd->cmd_slave) != RPTUN_CMD_READY) { @@ -197,7 +197,7 @@ rptun_ivshmem_get_resource(FAR struct rptun_dev_s *dev) cmd->cmd_master = 0; cmd->cmd_slave = RPTUN_CMD(RPTUN_CMD_READY, 0); - /* Wait untils master is ready, salve need use master base to + /* Wait until master is ready, slave needs to use master base to * initialize addrenv. */ diff --git a/drivers/sensors/amg88xx.c b/drivers/sensors/amg88xx.c index 9a9bf903ce..e2c78246bb 100644 --- a/drivers/sensors/amg88xx.c +++ b/drivers/sensors/amg88xx.c @@ -497,7 +497,7 @@ static int amg88xx_ioctl(FAR struct file *filep, int cmd, break; /* Enabling and disabling the moving average requires following - * a precedure described in the i2c communication interface manual + * a procedure described in the i2c communication interface manual. */ case SNIOC_SET_MOVING_AVG: diff --git a/drivers/sensors/apds9922.c b/drivers/sensors/apds9922.c index d7a26e7df0..7a023c7ffa 100644 --- a/drivers/sensors/apds9922.c +++ b/drivers/sensors/apds9922.c @@ -120,7 +120,7 @@ #define APDS9922_PS_DATA0 (0x08) /* LSB of measured PS data */ #define APDS9922_ALS_DATA0 (0x0d) /* LSB of measured ALS data */ #define APDS9922_INT_CFG (0x19) /* Interrupt configuration */ -#define APDS9922_INT_PERSIST (0x1a) /* Interrupt persistance */ +#define APDS9922_INT_PERSIST (0x1a) /* Interrupt persistence */ #define APDS9922_PS_THRESHU (0x1b) /* PS threshold, upper limit */ #define APDS9922_PS_THRESHL (0x1d) /* PS threshold, lower limit */ #define APDS9922_CANCEL_LVLL (0x1f) /* Intelligent Cancellation level */ @@ -1000,7 +1000,7 @@ static int apds9922_als_variance(FAR struct apds9922_dev_s *priv, * * Input Parameters: * priv - pointer to device structure - * persistance - number of values to be out of range before int asserted + * persistence - number of values to be out of range before int asserted * * Returned Value: * Success or failure diff --git a/drivers/sensors/bmi088.c b/drivers/sensors/bmi088.c index 0247290658..70da73ade0 100644 --- a/drivers/sensors/bmi088.c +++ b/drivers/sensors/bmi088.c @@ -130,7 +130,7 @@ static int bmi088_gyro_open(FAR struct file *filep) FAR struct inode *inode = filep->f_inode; FAR struct bmi088_dev_s *priv = inode->i_private; - /* emable and config acc */ + /* enable and config acc */ bmi088_put_gyro_reg8(priv, BMI088_GYRO_LPM1 , BMI088_GYRO_PM_NORMAL); bmi088_put_gyro_reg8(priv, BMI088_GYRO_RANGE , gyro_range); @@ -212,7 +212,7 @@ static ssize_t bmi088_acc_read(FAR struct file *filep, FAR char *buffer, return 0; } - /* read and caculate acc */ + /* read and calculate acc */ bmi088_get_acc_regs(priv, BMI088_ACC_X_LSB, (uint8_t *)&p->acc_source, 6); p->accel.x = p->acc_source.x / 32768.0 * ((1 << (acc_range)) * 3.0); diff --git a/drivers/sensors/bmi088_uorb.c b/drivers/sensors/bmi088_uorb.c index b349756832..f9ea6d4933 100644 --- a/drivers/sensors/bmi088_uorb.c +++ b/drivers/sensors/bmi088_uorb.c @@ -683,7 +683,7 @@ static void bmi088_gyro_worker(FAR void *arg) * * Input Parameters: * devno - Sensor device number. - * config - Interrupt fuctions. + * config - Interrupt functions. * * Returned Value: * Description of the value returned by this function (if any), @@ -771,7 +771,7 @@ static int bmi088_register_accel(int devno, * * Input Parameters: * devno - Sensor device number. - * config - Interrupt fuctions. + * config - Interrupt functions. * * Returned Value: * Description of the value returned by this function (if any), diff --git a/drivers/sensors/bmi160_uorb.c b/drivers/sensors/bmi160_uorb.c index 0de92f12c6..1c9877313d 100644 --- a/drivers/sensors/bmi160_uorb.c +++ b/drivers/sensors/bmi160_uorb.c @@ -549,7 +549,7 @@ static void bmi160_gyro_worker(FAR void *arg) * * Input Parameters: * devno - Sensor device number. - * config - Interrupt fuctions. + * config - Interrupt functions. * * Returned Value: * Description of the value returned by this function (if any), @@ -640,7 +640,7 @@ static int bmi160_register_accel(int devno, * * Input Parameters: * devno - Sensor device number. - * config - Interrupt fuctions. + * config - Interrupt functions. * * Returned Value: * Description of the value returned by this function (if any), diff --git a/drivers/sensors/bmm150_uorb.c b/drivers/sensors/bmm150_uorb.c index 7d4749f78e..527621dd70 100644 --- a/drivers/sensors/bmm150_uorb.c +++ b/drivers/sensors/bmm150_uorb.c @@ -735,7 +735,7 @@ int bmm150_register_uorb(int devno, FAR struct bmm150_config_s *config) return ret; } - /* Regsiter driver */ + /* Register driver */ ret = sensor_register(&dev->lower, devno); if (ret < 0) diff --git a/drivers/sensors/bmp280_uorb.c b/drivers/sensors/bmp280_uorb.c index a7502cf4fe..9eb38e6bdc 100644 --- a/drivers/sensors/bmp280_uorb.c +++ b/drivers/sensors/bmp280_uorb.c @@ -427,13 +427,13 @@ static int bmp280_initialize(FAR struct bmp280_dev_s *priv) * Name: bmp280_compensate * * Description: - * calculate compensate tempreture + * calculate compensate temperature * * Input Parameters: - * temp - uncompensate value of tempreture. + * temp - uncompensate value of temperature. * * Returned Value: - * calculate result of compensate tempreture. + * calculate result of compensate temperature. * ****************************************************************************/ diff --git a/drivers/sensors/ds18b20_uorb.c b/drivers/sensors/ds18b20_uorb.c index 8430343726..0b97ee53e4 100644 --- a/drivers/sensors/ds18b20_uorb.c +++ b/drivers/sensors/ds18b20_uorb.c @@ -81,7 +81,7 @@ #define DS18B20_RES_VAL(x) (((x) >> 5) & 0x3) #define DS18B20_RES_CONV(x) (((x) & 0x3) << 5) -/* Measurement timneout offset */ +/* Measurement timeout offset */ #define DS18B20_TIMEOUT_OFFSET(x) (DS18B20_RESMAX - (x)) @@ -631,7 +631,7 @@ static int ds18b20_measure_read(FAR struct ds18b20_dev_s *dev, /**************************************************************************** * Name: ds18b20_fetch * - * Description: Performs a measuremnt cylce and data read with data + * Description: Performs a measuremnt cycle and data read with data * conversion. * * Parameter: @@ -876,7 +876,7 @@ static int ds18b20_thread(int argc, char** argv) } else { - /* Default nofitication when temperature has been changed */ + /* Default notification when temperature has been changed */ ret = ds18b20_measure_read(priv, &data); if (!ret) diff --git a/drivers/sensors/gnss_uorb.c b/drivers/sensors/gnss_uorb.c index 1567fb00e0..0c38e98a0b 100644 --- a/drivers/sensors/gnss_uorb.c +++ b/drivers/sensors/gnss_uorb.c @@ -704,7 +704,7 @@ static void gnss_push_event(FAR void *priv, FAR const void *data, * instance is bound to the GNSS driver and must persist as long * as the driver persists. * devno - The user specifies which device of this type, from 0. If the - * devno alerady exists, -EEXIST will be returned. + * devno already exists, -EEXIST will be returned. * nbuffer - The number of events that the circular buffer can hold. * count - The array size of nbuffer. * diff --git a/drivers/sensors/lis2mdl_uorb.c b/drivers/sensors/lis2mdl_uorb.c index 4c8cbbe5b9..efc84c1fe2 100644 --- a/drivers/sensors/lis2mdl_uorb.c +++ b/drivers/sensors/lis2mdl_uorb.c @@ -1251,7 +1251,7 @@ static int lis2mdl_thread(int argc, char **argv) * devno - The device number to use for the topic (i.e. /dev/mag0) * attach - A function which is called by this driver to attach the * LIS2MDL interrupt handler to an IRQ. Pass NULL to operate - * in polling mode. This function should return 0 on succes + * in polling mode. This function should return 0 on success * and a negated error code otherwise. * * Returned Value: diff --git a/drivers/sensors/lis3dsh.c b/drivers/sensors/lis3dsh.c index e5962cb5fe..6f9b098049 100644 --- a/drivers/sensors/lis3dsh.c +++ b/drivers/sensors/lis3dsh.c @@ -212,7 +212,7 @@ static void lis3dsh_read_measurement_data(FAR struct lis3dsh_dev_s *dev) uint16_t z_acc = 0; int ret; - /* Read acclerometer data */ + /* Read accelerometer data */ lis3dsh_read_acclerometer_data(dev, &x_acc, &y_acc, &z_acc); diff --git a/drivers/sensors/mcp9844.c b/drivers/sensors/mcp9844.c index 4cdc012fc9..136f6e0274 100644 --- a/drivers/sensors/mcp9844.c +++ b/drivers/sensors/mcp9844.c @@ -99,7 +99,7 @@ static const struct file_operations g_mcp9844_fops = * Name: mcp9844_read_u16 * * Description: - * Read a 16 bit valie from the MCP9844 at the address regaddr. + * Read a 16 bit value from the MCP9844 at the address regaddr. * ****************************************************************************/ diff --git a/drivers/sensors/mpu9250_uorb.c b/drivers/sensors/mpu9250_uorb.c index e64dc0ccf0..ca8e42cd21 100644 --- a/drivers/sensors/mpu9250_uorb.c +++ b/drivers/sensors/mpu9250_uorb.c @@ -1675,7 +1675,7 @@ static int write_ak8963_reg(FAR struct mpu9250_dev_s *dev, return ret; } - /* Continuously check I2C_MST_STATUS regsiter value for the completion + /* Continuously check I2C_MST_STATUS register value for the completion * of I2C transfer until timeout. */ diff --git a/drivers/sensors/sensor.c b/drivers/sensors/sensor.c index 89bd6bbbf2..1e8aa6e127 100644 --- a/drivers/sensors/sensor.c +++ b/drivers/sensors/sensor.c @@ -1235,7 +1235,7 @@ void sensor_remap_vector_raw16(FAR const int16_t *in, FAR int16_t *out, * instance is bound to the sensor driver and must persists as long * as the driver persists. * devno - The user specifies which device of this type, from 0. If the - * devno alerady exists, -EEXIST will be returned. + * devno already exists, -EEXIST will be returned. * * Returned Value: * OK if the driver was successfully register; A negated errno value is diff --git a/drivers/sensors/sensor_rpmsg.c b/drivers/sensors/sensor_rpmsg.c index 58860760eb..6ed7577121 100644 --- a/drivers/sensors/sensor_rpmsg.c +++ b/drivers/sensors/sensor_rpmsg.c @@ -1357,7 +1357,7 @@ static void sensor_rpmsg_ept_release(FAR struct rpmsg_endpoint *ept) sre = container_of(ept, struct sensor_rpmsg_ept_s, ept); /* Remove all proxy and stub info in sensor device with the ept - * destoryed. + * destroyed. */ nxrmutex_lock(&g_dev_lock); @@ -1537,7 +1537,7 @@ void sensor_rpmsg_unregister(FAR struct sensor_lowerhalf_s *lower) * * Description: * This function initializes the context of sensor rpmsg, registers - * rpmsg callback and prepares enviroment to intercat with remote sensor. + * rpmsg callback and prepares environment to interact with remote sensor. * * Returned Value: * OK on success; A negated errno value is returned on any failure. diff --git a/drivers/sensors/zerocross.c b/drivers/sensors/zerocross.c index c72b065f3b..ab05b351c7 100644 --- a/drivers/sensors/zerocross.c +++ b/drivers/sensors/zerocross.c @@ -343,7 +343,7 @@ errout_with_lock: * Name: zc_read * * Description: - * A dummy read method. This is provided only to satsify the VFS layer. + * A dummy read method. This is provided only to satisfy the VFS layer. * ****************************************************************************/ @@ -359,7 +359,7 @@ static ssize_t zc_read(FAR struct file *filep, FAR char *buffer, * Name: zc_write * * Description: - * A dummy write method. This is provided only to satsify the VFS layer. + * A dummy write method. This is provided only to satisfy the VFS layer. * ****************************************************************************/ diff --git a/drivers/serial/serial_cmsdk.c b/drivers/serial/serial_cmsdk.c index 2aea93a172..3d4bc3fc6a 100644 --- a/drivers/serial/serial_cmsdk.c +++ b/drivers/serial/serial_cmsdk.c @@ -703,7 +703,7 @@ static void uart_cmsdk_putc(FAR struct uart_cmsdk_s *priv, int ch) #endif /**************************************************************************** - * Public Funtions + * Public Functions ****************************************************************************/ /**************************************************************************** @@ -711,7 +711,7 @@ static void uart_cmsdk_putc(FAR struct uart_cmsdk_s *priv, int ch) * * Description: * Performs the low level UART initialization early in debug so that the - * serial console will be available during bootup. This must be called + * serial console will be available during boot up. This must be called * before uart_serialinit. * * NOTE: Configuration of the CONSOLE UART was performed by uart_lowsetup() diff --git a/drivers/serial/serial_gdbstub.c b/drivers/serial/serial_gdbstub.c index ca0981cade..6f5c33e656 100644 --- a/drivers/serial/serial_gdbstub.c +++ b/drivers/serial/serial_gdbstub.c @@ -181,7 +181,7 @@ static int uart_gdbstub_panic_callback(FAR struct notifier_block *nb, uart_gdbstub_attach(uart_gdbstub, true); #endif - _alert("Enter panic gdbstub mode, plase use gdb connect to debug\n"); + _alert("Enter panic gdbstub mode, please use gdb connect to debug\n"); _alert("Please use gdb of the corresponding architecture to " "connect to nuttx"); _alert("such as: arm-none-eabi-gdb nuttx -ex \"set " diff --git a/drivers/serial/uart_16550.c b/drivers/serial/uart_16550.c index 190e39b61f..c7ad45f3f6 100644 --- a/drivers/serial/uart_16550.c +++ b/drivers/serial/uart_16550.c @@ -1646,7 +1646,7 @@ static bool u16550_txempty(struct uart_dev_s *dev) * * Description: * Performs the low level UART initialization early in debug so that the - * serial console will be available during bootup. This must be called + * serial console will be available during boot up. This must be called * before uart_serialinit. * * NOTE: Configuration of the CONSOLE UART was performed by uart_lowsetup() diff --git a/drivers/serial/uart_pci_16550.c b/drivers/serial/uart_pci_16550.c index e8c3b70b13..0a404932fa 100644 --- a/drivers/serial/uart_pci_16550.c +++ b/drivers/serial/uart_pci_16550.c @@ -75,7 +75,7 @@ struct pci_u16550_type_s uint8_t portincr; /* Port address increment */ }; -/* Extend default UART 16550 strucutre */ +/* Extend default UART 16550 structure */ struct pci_u16550_priv_s { diff --git a/drivers/spi/spi_slave_driver.c b/drivers/spi/spi_slave_driver.c index 427a59a694..48b4533fb8 100644 --- a/drivers/spi/spi_slave_driver.c +++ b/drivers/spi/spi_slave_driver.c @@ -72,7 +72,7 @@ struct spi_slave_driver_s FAR struct pollfd *fds; - /* The semphore reader */ + /* The semaphore reader */ sem_t wait; @@ -639,7 +639,7 @@ static void spi_slave_cmddata(FAR struct spi_slave_dev_s *dev, bool data) * * Input Parameters: * dev - SPI Slave device interface instance - * data - Pointer to the data buffer pointer to be shifed out. + * data - Pointer to the data buffer pointer to be shifted out. * The device will set the data buffer pointer to the actual data * * Returned Value: diff --git a/drivers/syslog/Kconfig b/drivers/syslog/Kconfig index 85748d103c..4fb02bd2fd 100644 --- a/drivers/syslog/Kconfig +++ b/drivers/syslog/Kconfig @@ -63,7 +63,7 @@ config SYSLOG_CRLF bool "Syslog convert LF to CRLF" default y ---help--- - Pre-pend a carriage return before every linefeed that goes into the + Prepend a carriage return before every linefeed that goes into the syslog. config SYSLOG_MAX_CHANNELS diff --git a/drivers/syslog/ramlog.c b/drivers/syslog/ramlog.c index 404ce17965..d8cf0cbd1a 100644 --- a/drivers/syslog/ramlog.c +++ b/drivers/syslog/ramlog.c @@ -76,7 +76,7 @@ struct ramlog_user_s { struct list_node rl_node; /* The list_node of reader */ volatile uint32_t rl_tail; /* The tail index (where data is removed) */ - uint32_t rl_threashold; /* The threashold of the reader to read log */ + uint32_t rl_threashold; /* The threshold of the reader to read log */ #ifndef CONFIG_RAMLOG_NONBLOCKING sem_t rl_waitsem; /* Used to wait for data */ #endif @@ -417,7 +417,7 @@ static ssize_t ramlog_file_read(FAR struct file *filep, FAR char *buffer, break; } - /* We may now be pre-empted! But that should be okay because we + /* We may now be preempted! But that should be okay because we * have already incremented nwaiters. Pre-emptions is disabled * but will be re-enabled while we are waiting. */ diff --git a/drivers/syslog/syslog_device.c b/drivers/syslog/syslog_device.c index bd08fac6e2..f3678aee2d 100644 --- a/drivers/syslog/syslog_device.c +++ b/drivers/syslog/syslog_device.c @@ -566,7 +566,7 @@ static int syslog_dev_putc(FAR syslog_channel_t *channel, int ch) return ret; } - /* Pre-pend a newline with a carriage return. */ + /* Prepend a newline with a carriage return. */ if (ch == '\n') { diff --git a/drivers/thermal/thermal_core.c b/drivers/thermal/thermal_core.c index f0c9196292..8f068daab3 100644 --- a/drivers/thermal/thermal_core.c +++ b/drivers/thermal/thermal_core.c @@ -663,7 +663,7 @@ void thermal_cooling_device_update(FAR struct thermal_cooling_device_s *cdev) * Input Parameters: * name - Name of zone. * devdata - Device driver data. - * ops - Operations of zone deivce. + * ops - Operations of zone device. * params - Parameter of zone device. * * Returned Value: diff --git a/drivers/thermal/thermal_cpufreq_cooling.c b/drivers/thermal/thermal_cpufreq_cooling.c index d8782920ea..7758decd6b 100644 --- a/drivers/thermal/thermal_cpufreq_cooling.c +++ b/drivers/thermal/thermal_cpufreq_cooling.c @@ -207,7 +207,7 @@ FAR struct thermal_cooling_device_s *thermal_cpufreq_cooling_register(void) * Unregister cpufreq cooling device * * Input Parameters: - * cdev - Addr of cpufre cooling devcie entry + * cdev - Addr of cpufre cooling device entry * * Returned Value: * None diff --git a/drivers/timers/Kconfig b/drivers/timers/Kconfig index aaab1a4b55..a44a7cda9f 100644 --- a/drivers/timers/Kconfig +++ b/drivers/timers/Kconfig @@ -57,7 +57,7 @@ config PWM_DEADTIME ---help--- Some hardware will support deadtime generators that automatically insert output activation delay for complementary PWM outputs. This - is usefull for H-bridge motor control for example. The deadtime + is useful for H-bridge motor control for example. The deadtime values are set from application level via the same IOCTL that sets up duty cycle and frequency. @@ -424,7 +424,7 @@ config WATCHDOG_PANIC_NOTIFIER bool "Enable watchdog panic notifier" default n ---help--- - When system PANIC, wdog_notifier() will be callled to disable the watchdog, + When system PANIC, wdog_notifier() will be called to disable the watchdog, this is an useful option for debug if you want to keep crash scene. menuconfig WATCHDOG_AUTOMONITOR diff --git a/drivers/timers/arch_alarm.c b/drivers/timers/arch_alarm.c index bb1db50a64..d2a3b0b8db 100644 --- a/drivers/timers/arch_alarm.c +++ b/drivers/timers/arch_alarm.c @@ -110,7 +110,7 @@ static void oneshot_callback(FAR struct oneshot_lowerhalf_s *lower, #else /* Start the next tick first, in order to minimize latency. Ideally * the ONESHOT_TICK_START would also return the current tick so that - * the retriving the current tick and starting the new one could be done + * the retrieving the current tick and starting the new one could be done * atomically w. respect to a HW timer */ diff --git a/drivers/timers/capture.c b/drivers/timers/capture.c index e58fda840a..3f90b60921 100644 --- a/drivers/timers/capture.c +++ b/drivers/timers/capture.c @@ -311,8 +311,8 @@ static int cap_ioctl(FAR struct file *filep, int cmd, unsigned long arg) } break; - /* CAPIOC_FREQUENCE - Get the pulse frequence from the capture. - * Argument: int32_t pointer to the location to return the frequence. + /* CAPIOC_FREQUENCE - Get the pulse frequency from the capture. + * Argument: int32_t pointer to the location to return the frequency. */ case CAPIOC_FREQUENCE: @@ -351,7 +351,7 @@ static int cap_ioctl(FAR struct file *filep, int cmd, unsigned long arg) } break; - /* CAPIOC_ALL - Get the pwm duty, pulse frequence, pwm edges, from + /* CAPIOC_ALL - Get the pwm duty, pulse frequency, pwm edges, from * the capture. * Argument: A reference to struct cap_all_s. */ diff --git a/drivers/timers/oneshot.c b/drivers/timers/oneshot.c index dc8c6e4657..bfc2e26dcc 100644 --- a/drivers/timers/oneshot.c +++ b/drivers/timers/oneshot.c @@ -112,7 +112,7 @@ static void oneshot_callback(FAR struct oneshot_lowerhalf_s *lower, * Name: oneshot_read * * Description: - * A dummy read method. This is provided only to satsify the VFS layer. + * A dummy read method. This is provided only to satisfy the VFS layer. * ****************************************************************************/ @@ -129,7 +129,7 @@ static ssize_t oneshot_read(FAR struct file *filep, FAR char *buffer, * Name: oneshot_write * * Description: - * A dummy write method. This is provided only to satsify the VFS layer. + * A dummy write method. This is provided only to satisfy the VFS layer. * ****************************************************************************/ diff --git a/drivers/usbdev/cdcncm.c b/drivers/usbdev/cdcncm.c index 86daf73c5f..7c2aa36455 100644 --- a/drivers/usbdev/cdcncm.c +++ b/drivers/usbdev/cdcncm.c @@ -719,7 +719,7 @@ static ssize_t cdcmbim_write(FAR struct file *filep, FAR const char *buffer, if (ret < 0) { iob_free_chain(iob); - uerr("CDCMBIM copyin failed: %d\n", ret); + uerr("CDCMBIM copying failed: %d\n", ret); goto errout; } @@ -1786,7 +1786,7 @@ static int cdcncm_setinterface(FAR struct cdcncm_driver_s *self, } else { - uerr("invailid interface %d\n", interface); + uerr("invalid interface %d\n", interface); return -EINVAL; } @@ -2791,7 +2791,7 @@ static int cdcncm_setup(FAR struct usbdevclass_driver_s *driver, if (ret < 0) { iob_free_chain(iob); - uerr("CDCMBIM copyin failed: %d\n", ret); + uerr("CDCMBIM copying failed: %d\n", ret); return ret; } diff --git a/drivers/usbdev/usbmsc.c b/drivers/usbdev/usbmsc.c index 28ff61eff3..64478f8686 100644 --- a/drivers/usbdev/usbmsc.c +++ b/drivers/usbdev/usbmsc.c @@ -1785,7 +1785,7 @@ void usbmsc_uninitialize(FAR void *handle) priv = &alloc->dev; - /* If the thread hasn't already exitted, tell it to exit now */ + /* If the thread hasn't already exited, tell it to exit now */ if (priv->thstate != USBMSC_STATE_NOTSTARTED) { diff --git a/drivers/usbdev/usbmsc.h b/drivers/usbdev/usbmsc.h index cb3800eeb8..81afd81a50 100644 --- a/drivers/usbdev/usbmsc.h +++ b/drivers/usbdev/usbmsc.h @@ -227,7 +227,7 @@ #define USBMSC_STATE_CMDWRITE (5) /* Processing a SCSI write command */ #define USBMSC_STATE_CMDFINISH (6) /* Finish command processing */ #define USBMSC_STATE_CMDSTATUS (7) /* Processing the final status of the command */ -#define USBMSC_STATE_TERMINATED (8) /* Thread has exitted */ +#define USBMSC_STATE_TERMINATED (8) /* Thread has exited */ /* Event communicated to worker thread */ diff --git a/drivers/usbdev/usbmsc_scsi.c b/drivers/usbdev/usbmsc_scsi.c index 03eb5cf169..4e98c1b2ac 100644 --- a/drivers/usbdev/usbmsc_scsi.c +++ b/drivers/usbdev/usbmsc_scsi.c @@ -372,7 +372,7 @@ static int usbmsc_scsi_wait(FAR struct usbmsc_dev_s *priv) /* A flag is used to prevent driving up the semaphore count. This function * is called (primarily) from the SCSI work thread so we must disable - * interrupts momentarily to assure that test of the flag and the wait fo + * interrupts momentarily to assure that test of the flag and the wait for * the semaphore count are atomic. Interrupts will, of course, be re- * enabled while we wait for the event. */ @@ -2037,7 +2037,7 @@ static int usbmsc_cmdparsestate(FAR struct usbmsc_dev_s *priv) * case SCSI_CMD_WRITEANDVERIFY: 0x2e Optional */ - case SCSI_CMD_VERIFY10: /* 0x2f Opt, excpt Windows */ + case SCSI_CMD_VERIFY10: /* 0x2f Opt, except Windows */ ret = usbmsc_cmdverify10(priv); break; diff --git a/drivers/usbhost/usbhost_bthci.c b/drivers/usbhost/usbhost_bthci.c index 9901587b2a..66fe292244 100644 --- a/drivers/usbhost/usbhost_bthci.c +++ b/drivers/usbhost/usbhost_bthci.c @@ -463,7 +463,7 @@ static inline int usbhci_cfgdesc(FAR struct usbhost_state_s *priv, configdesc += cfgdesc->len; remaining -= cfgdesc->len; - /* Loop where there are more dscriptors to examine */ + /* Loop where there are more descriptors to examine */ while (remaining >= sizeof(struct usb_desc_s)) { diff --git a/drivers/usbhost/usbhost_hidkbd.c b/drivers/usbhost/usbhost_hidkbd.c index 0d12730c2e..f7269522b3 100644 --- a/drivers/usbhost/usbhost_hidkbd.c +++ b/drivers/usbhost/usbhost_hidkbd.c @@ -1932,7 +1932,7 @@ static inline int usbhost_devinit(FAR struct usbhost_state_s *priv) if (priv->epin) { - /* Use interrupt tranfers to get reports. */ + /* Use interrupt transfers to get reports. */ uinfo("Start waiting for key reports\n"); ret = DRVR_ASYNCH(hport->drvr, priv->epin, @@ -1964,7 +1964,7 @@ static inline int usbhost_devinit(FAR struct usbhost_state_s *priv) uinfo("Start poll task\n"); - /* The inputs to a task started by kthread_create() are very awkard for + /* The inputs to a task started by kthread_create() are very awkward for * this purpose. They are really designed for command line tasks * (argc/argv). So the following is kludge pass binary data when the * keyboard poll task is started. diff --git a/drivers/usbhost/usbhost_max3421e.c b/drivers/usbhost/usbhost_max3421e.c index 6956fe55e8..5b42abd587 100644 --- a/drivers/usbhost/usbhost_max3421e.c +++ b/drivers/usbhost/usbhost_max3421e.c @@ -1083,7 +1083,7 @@ static void max3421e_sndblock(FAR struct max3421e_usbhost_s *priv, SPI_SELECT(spi, SPIDEV_USBHOST(lower->devid), true); - /* Send the wrte command byte */ + /* Send the write command byte */ cmd = max3421e_fmtcmd(priv, addr, MAX3421E_DIR_WRITE); SPI_SEND(spi, cmd); diff --git a/drivers/usbhost/usbhost_skeleton.c b/drivers/usbhost/usbhost_skeleton.c index a11340752f..e093cf542c 100644 --- a/drivers/usbhost/usbhost_skeleton.c +++ b/drivers/usbhost/usbhost_skeleton.c @@ -412,7 +412,7 @@ static inline int usbhost_cfgdesc(FAR struct usbhost_state_s *priv, configdesc += cfgdesc->len; remaining -= cfgdesc->len; - /* Loop where there are more dscriptors to examine */ + /* Loop where there are more descriptors to examine */ while (remaining >= sizeof(struct usb_desc_s)) { diff --git a/drivers/usbhost/usbhost_storage.c b/drivers/usbhost/usbhost_storage.c index 7f60769815..45cae2de11 100644 --- a/drivers/usbhost/usbhost_storage.c +++ b/drivers/usbhost/usbhost_storage.c @@ -687,7 +687,7 @@ static inline int usbhost_testunitready(FAR struct usbhost_state_s *priv) DEBUGASSERT(priv->usbclass.hport); hport = priv->usbclass.hport; - /* Initialize a CBW (re-using the allocated transfer buffer) */ + /* Initialize a CBW (reusing the allocated transfer buffer) */ cbw = usbhost_cbwalloc(priv); if (!cbw) @@ -725,7 +725,7 @@ static inline int usbhost_requestsense(FAR struct usbhost_state_s *priv) DEBUGASSERT(priv->usbclass.hport); hport = priv->usbclass.hport; - /* Initialize a CBW (re-using the allocated transfer buffer) */ + /* Initialize a CBW (reusing the allocated transfer buffer) */ cbw = usbhost_cbwalloc(priv); if (!cbw) @@ -771,7 +771,7 @@ static inline int usbhost_readcapacity(FAR struct usbhost_state_s *priv) DEBUGASSERT(priv->usbclass.hport); hport = priv->usbclass.hport; - /* Initialize a CBW (re-using the allocated transfer buffer) */ + /* Initialize a CBW (reusing the allocated transfer buffer) */ cbw = usbhost_cbwalloc(priv); if (!cbw) @@ -823,7 +823,7 @@ static inline int usbhost_inquiry(FAR struct usbhost_state_s *priv) DEBUGASSERT(priv->usbclass.hport); hport = priv->usbclass.hport; - /* Initialize a CBW (re-using the allocated transfer buffer) */ + /* Initialize a CBW (reusing the allocated transfer buffer) */ cbw = usbhost_cbwalloc(priv); if (!cbw) @@ -1000,7 +1000,7 @@ static inline int usbhost_cfgdesc(FAR struct usbhost_state_s *priv, configdesc += cfgdesc->len; remaining -= cfgdesc->len; - /* Loop where there are more dscriptors to examine */ + /* Loop where there are more descriptors to examine */ while (remaining >= sizeof(struct usb_desc_s)) { @@ -1614,7 +1614,7 @@ static inline int usbhost_tfree(FAR struct usbhost_state_s *priv) * Name: usbhost_cbwalloc * * Description: - * Initialize a CBW (re-using the allocated transfer buffer). Upon + * Initialize a CBW (reusing the allocated transfer buffer). Upon * successful return, the CBW is cleared and has the CBW signature in * place. * @@ -2023,7 +2023,7 @@ static ssize_t usbhost_read(FAR struct inode *inode, unsigned char *buffer, nbytes = -ENOMEM; - /* Initialize a CBW (re-using the allocated transfer buffer) */ + /* Initialize a CBW (reusing the allocated transfer buffer) */ cbw = usbhost_cbwalloc(priv); if (cbw) @@ -2135,7 +2135,7 @@ static ssize_t usbhost_write(FAR struct inode *inode, nbytes = -ENOMEM; - /* Initialize a CBW (re-using the allocated transfer buffer) */ + /* Initialize a CBW (reusing the allocated transfer buffer) */ cbw = usbhost_cbwalloc(priv); if (cbw) diff --git a/drivers/usbhost/usbhost_xboxcontroller.c b/drivers/usbhost/usbhost_xboxcontroller.c index 01acb84f4f..a9689197c8 100644 --- a/drivers/usbhost/usbhost_xboxcontroller.c +++ b/drivers/usbhost/usbhost_xboxcontroller.c @@ -1085,7 +1085,7 @@ static inline int usbhost_cfgdesc(FAR struct usbhost_state_s *priv, configdesc += cfgdesc->len; remaining -= cfgdesc->len; - /* Loop where there are more dscriptors to examine */ + /* Loop where there are more descriptors to examine */ while (remaining >= sizeof(struct usb_desc_s) && !done) { diff --git a/drivers/usbmisc/fusb302.c b/drivers/usbmisc/fusb302.c index 920662894a..f0c27cc59b 100644 --- a/drivers/usbmisc/fusb302.c +++ b/drivers/usbmisc/fusb302.c @@ -632,7 +632,7 @@ void enableccmeas(struct fusb302_dev_s *priv, enum cc_meas_e measure, * * Input Parameters: * priv - pointer to device structure - * threhold - MDAC threshold value + * threshold - MDAC threshold value * * Returned Value: * none diff --git a/drivers/vhost/vhost.c b/drivers/vhost/vhost.c index 6c19cdbdd3..a2c83d2f2e 100644 --- a/drivers/vhost/vhost.c +++ b/drivers/vhost/vhost.c @@ -47,9 +47,9 @@ struct vhost_bus_s { mutex_t lock; /* Lock for the list */ struct list_node device; /* Wait match vhost device list */ - struct list_node defered_device; /* Defered vhost device list */ + struct list_node defered_device; /* Deferred vhost device list */ struct list_node driver; /* Vhost driver list */ - struct work_s defered_work; /* Defered probe work */ + struct work_s defered_work; /* Deferred probe work */ }; struct vhost_device_item_s @@ -275,7 +275,7 @@ int vhost_register_device(FAR struct vhost_device *device) return ret; } - /* 1. Add device to defered device list if virtio driver not OK; + /* 1. Add device to deferred device list if virtio driver not OK; * 2. Add device to the normal device list and try to probe the driver * if virtio driver has been OK. */ diff --git a/drivers/video/isx019.c b/drivers/video/isx019.c index ba91fb8cf9..c3ad2beac3 100644 --- a/drivers/video/isx019.c +++ b/drivers/video/isx019.c @@ -2439,7 +2439,7 @@ static int set_wbmode(FAR isx019_dev_t *priv, static int set_awb(FAR isx019_dev_t *priv, imgsensor_value_t val) { - /* true -> false : Update regster to HOLD + /* true -> false : Update register to HOLD * false -> true : Update register * with IMGSENSOR_ID_AUTO_N_PRESET_WB setting * otherwise : Nothing to do @@ -2616,7 +2616,7 @@ static int set_spot_position(FAR isx019_dev_t *priv, int split; /* Spot position of ISX019 is divided into 9x7 sections. - * - Horizontal direction is devided into 9 sections. + * - Horizontal direction is divided into 9 sections. * - Vertical direction is divided into 7 sections. * The register value 0 means left top. * The register value 62 means right bottom. diff --git a/drivers/video/max7456.c b/drivers/video/max7456.c index 184329a604..fda378410f 100644 --- a/drivers/video/max7456.c +++ b/drivers/video/max7456.c @@ -1286,7 +1286,7 @@ static ssize_t mx7_write_fb(FAR struct file *filep, FAR const char *buf, * We use the approach you see here so that we don't have to have one * distinct function (and a separate file_operations structure) for each of * the many interfaces we're likely to create for interacting with this - * chip in its various useful ways. This schema also lets us re-use the + * chip in its various useful ways. This schema also lets us reuse the * interface code internally (see the test-pattern generator at startup.) * * In general, any function we call from here uses the combination of @@ -1529,7 +1529,7 @@ static ssize_t mx7_debug_write(FAR struct file *filep, FAR const char *buf, * path - The full path to the interface to register. E.g., "/dev/osd0" * name - Entry underneath @path (making the latter a directory) * fops - File operations for the interface - * mode - Access permisisons + * mode - Access permissions * private - Opaque pointer to forward to the file operation handlers * * Returned value: diff --git a/drivers/video/mipidsi/mipi_dsi_device.c b/drivers/video/mipidsi/mipi_dsi_device.c index 13f2a0fde5..6de785e41e 100644 --- a/drivers/video/mipidsi/mipi_dsi_device.c +++ b/drivers/video/mipidsi/mipi_dsi_device.c @@ -68,7 +68,7 @@ * msg - Message to transfer * * Returned Value: - * The number of bytes successfully transfered or a negative error code on + * The number of bytes successfully transferred or a negative error code on * failure. * ****************************************************************************/ diff --git a/drivers/video/vnc/vnc_fbdev.c b/drivers/video/vnc/vnc_fbdev.c index d51fbbd2e6..c15eec289c 100644 --- a/drivers/video/vnc/vnc_fbdev.c +++ b/drivers/video/vnc/vnc_fbdev.c @@ -555,8 +555,8 @@ static inline int vnc_wait_start(int display) * first things that the VNC server will do with the kernel thread is * started. But we might be here before the thread has gotten that far. * - * If it has been allocated, then wait until it is in the INIITIALIZED - * state. The INITIAILIZED states indicates that the session structure + * If it has been allocated, then wait until it is in the INITIALIZED + * state. The INITIALIZED states indicates that the session structure * has been allocated and fully initialized. */ diff --git a/drivers/video/vnc/vnc_keymap.c b/drivers/video/vnc/vnc_keymap.c index 3abec1e133..d578a9aefa 100644 --- a/drivers/video/vnc/vnc_keymap.c +++ b/drivers/video/vnc/vnc_keymap.c @@ -587,7 +587,7 @@ void vnc_key_map(FAR struct vnc_session_s *session, uint16_t keysym, keych = vnc_kbd_lookup(g_modifiers, G_MODIFIERS_NELEM, keysym); if (keych >= 0) { - /* Encode the speical character */ + /* Encode the special character */ if (keydown) { diff --git a/drivers/video/vnc/vnc_server.c b/drivers/video/vnc/vnc_server.c index f0c501ec4d..dc4f67e403 100644 --- a/drivers/video/vnc/vnc_server.c +++ b/drivers/video/vnc/vnc_server.c @@ -78,7 +78,7 @@ FAR struct vnc_session_s *g_vnc_sessions[RFB_MAX_DISPLAYS]; * Description: * Conclude the current VNC session. This function re-initializes the * session structure; it does not free either the session structure nor - * the framebuffer so that they may be re-used. + * the framebuffer so that they may be reused. * * Input Parameters: * session - An instance of the session structure. diff --git a/drivers/video/vnc/vnc_updater.c b/drivers/video/vnc/vnc_updater.c index bed219ebd7..f3a5e0ae86 100644 --- a/drivers/video/vnc/vnc_updater.c +++ b/drivers/video/vnc/vnc_updater.c @@ -152,7 +152,7 @@ static void vnc_sem_debug(FAR struct vnc_session_s *session, syslog(LOG_INFO, " semcount: %d\n", freecount); syslog(LOG_INFO, " queued nodes: %u\n", nfree); syslog(LOG_INFO, " waiting: %u\n", freewaiting); - syslog(LOG_INFO, " Qeued Updates:\n"); + syslog(LOG_INFO, " Queued Updates:\n"); syslog(LOG_INFO, " semcount: %d\n", queuecount); syslog(LOG_INFO, " queued nodes: %u\n", nqueued); syslog(LOG_INFO, " waiting: %u\n", queuewaiting); diff --git a/drivers/virtio/virtio-mmio.c b/drivers/virtio/virtio-mmio.c index 170616b8b7..3fe11edff0 100644 --- a/drivers/virtio/virtio-mmio.c +++ b/drivers/virtio/virtio-mmio.c @@ -331,7 +331,7 @@ static int virtio_mmio_config_virtqueue(FAR struct metal_io_region *io, if (pfn >> 32) { - vrterr("Legacy virtio-mmio used RAM shoud not above 0x%llxGB\n", + vrterr("Legacy virtio-mmio used RAM should not above 0x%llxGB\n", 0x1ull << (2 + VIRITO_PAGE_SHIFT)); } @@ -901,7 +901,7 @@ static int virtio_register_mmio_device_(FAR void *regs, int irq, bool secure) UNUSED(secure); #endif - /* Attach the intterupt before register the device driver */ + /* Attach the interrupt before register the device driver */ ret = irq_attach(irq, virtio_mmio_interrupt, vmdev); if (ret < 0) diff --git a/drivers/virtio/virtio-rng.c b/drivers/virtio/virtio-rng.c index 276975676a..47ae508c30 100644 --- a/drivers/virtio/virtio-rng.c +++ b/drivers/virtio/virtio-rng.c @@ -184,7 +184,7 @@ static ssize_t virtio_rng_read(FAR struct file *filep, FAR char *buffer, virtqueue_kick(vq); spin_unlock_irqrestore(&priv->lock, flags); - /* Wait fot completion */ + /* Wait for completion */ nxsem_wait_uninterruptible(&cookie.sem); memcpy(buffer, vb.buf, cookie.len); diff --git a/drivers/virtio/virtio-rpmb.c b/drivers/virtio/virtio-rpmb.c index eb40dc5058..314ede0bd6 100644 --- a/drivers/virtio/virtio-rpmb.c +++ b/drivers/virtio/virtio-rpmb.c @@ -165,7 +165,7 @@ static int virtio_rpmb_transact(FAR struct virtio_rpmb_priv_s *priv, virtqueue_kick(vq); spin_unlock_irqrestore(&priv->lock, flags); - /* Wait fot completion */ + /* Wait for completion */ nxsem_wait_uninterruptible(&cookie.sem); return cookie.len; diff --git a/drivers/virtio/virtio-serial.c b/drivers/virtio/virtio-serial.c index 2719acc29d..c2230b7d3a 100644 --- a/drivers/virtio/virtio-serial.c +++ b/drivers/virtio/virtio-serial.c @@ -50,11 +50,11 @@ struct virtio_serial_priv_s { - /* Virtio device informations */ + /* Virtio device information */ FAR struct virtio_device *vdev; - /* Nuttx uart device informations */ + /* Nuttx uart device information */ FAR struct uart_dev_s udev; char name[NAME_MAX]; @@ -413,7 +413,7 @@ static void virtio_serial_dmarxfree(FAR struct uart_dev_s *dev) * Name: virtio_serial_rxready * * Description: - * The virt serial receive virtqueue callback funtion + * The virt serial receive virtqueue callback function * ****************************************************************************/ @@ -440,7 +440,7 @@ static void virtio_serial_rxready(FAR struct virtqueue *vq) * Name: virtio_serial_txdone * * Description: - * The virt serial transimit virtqueue callback funtion + * The virt serial transimit virtqueue callback function * ****************************************************************************/ diff --git a/drivers/wireless/Kconfig b/drivers/wireless/Kconfig index a074cdbbb1..08e93a28e4 100644 --- a/drivers/wireless/Kconfig +++ b/drivers/wireless/Kconfig @@ -64,7 +64,7 @@ config WL_GS2200M_SYNC_INTERVAL Time interval to recognize dis-association situation. The value indicate n times of Wi-Fi beacon. If the node lost receiving beacon n times, behave as dis-associtaion. - Time difference between 2 beacons are approximetely 100 msec. + Time difference between 2 beacons are approximately 100 msec. So the unit of the value is 100 ms. config WL_GS2200M_LOGLEVEL diff --git a/drivers/wireless/bluetooth/bt_rpmsghci.c b/drivers/wireless/bluetooth/bt_rpmsghci.c index 4d96621d99..b69bb55a24 100644 --- a/drivers/wireless/bluetooth/bt_rpmsghci.c +++ b/drivers/wireless/bluetooth/bt_rpmsghci.c @@ -49,7 +49,7 @@ struct rpmsghci_s { - /* This must be te first thung in the structure so we can simply cast from + /* This must be the first thing in the structure so we can simply cast from * struct rpmsghci_s to struct bt_driver_s. */ @@ -308,8 +308,8 @@ static int rpmsghci_bt_ioctl(FAR struct bt_driver_s *btdev, int cmd, * ept - The rpmsg endpoint * data - The return message * len - The return message length - * src - unknow - * priv - unknow + * src - unknown + * priv - unknown * * Returned Values: * Always OK @@ -342,8 +342,8 @@ static int rpmsghci_default_handler(FAR struct rpmsg_endpoint *ept, * ept - The rpmsg endpoint * data - The return message * len - The return message length - * src - unknow - * priv - unknow + * src - unknown + * priv - unknown * * Returned Values: * OK on success; A negated errno value is returned on any failure. @@ -381,8 +381,8 @@ static int rpmsghci_recv_handler(FAR struct rpmsg_endpoint *ept, * ept - The rpmsg-HCI end point * data - The received data * len - The received data length - * src - unknow - * priv - unknow + * src - unknown + * priv - unknown * * Returned Values: * OK on success; A negated errno value is returned on any failure. diff --git a/drivers/wireless/bluetooth/bt_rpmsghci_server.c b/drivers/wireless/bluetooth/bt_rpmsghci_server.c index d373c38a6b..dbccc172bb 100644 --- a/drivers/wireless/bluetooth/bt_rpmsghci_server.c +++ b/drivers/wireless/bluetooth/bt_rpmsghci_server.c @@ -159,8 +159,8 @@ errout: * ept - The rpmsg endpoint * data - The return message * len - The return message length - * src - unknow - * priv - unknow + * src - unknown + * priv - unknown * * Returned Values: * OK on success; A negated errno value is returned on any failure. @@ -201,8 +201,8 @@ static int rpmsghci_open_handler(FAR struct rpmsg_endpoint *ept, * ept - The rpmsg endpoint * data - The return message * len - The return message length - * src - unknow - * priv - unknow + * src - unknown + * priv - unknown * * Returned Values: * OK on success; A negated errno value is returned on any failure. @@ -243,8 +243,8 @@ static int rpmsghci_close_handler(FAR struct rpmsg_endpoint *ept, * ept - The rpmsg endpoint * data - The return message * len - The return message length - * src - unknow - * priv - unknow + * src - unknown + * priv - unknown * * Returned Values: * OK on success; A negated errno value is returned on any failure. @@ -285,8 +285,8 @@ static int rpmsghci_send_handler(FAR struct rpmsg_endpoint *ept, * ept - The rpmsg endpoint * data - The return message * len - The return message length - * src - unknow - * priv - unknow + * src - unknown + * priv - unknown * * Returned Values: * OK on success; A negated errno value is returned on any failure. @@ -329,8 +329,8 @@ static int rpmsghci_ioctl_handler(FAR struct rpmsg_endpoint *ept, * ept - The rpmsg endpoint * data - The return message * len - The return message length - * src - unknow - * priv - unknow + * src - unknown + * priv - unknown * * Returned Values: * Always OK @@ -378,8 +378,8 @@ static bool rpmsghci_ns_match(FAR struct rpmsg_device *rdev, FAR void *priv, * ept - The rpmsg-HCI end point * data - The received data * len - The received data length - * src - unknow - * priv - unknow + * src - unknown + * priv - unknown * * Returned Values: * OK on success; A negated errno value is returned on any failure. diff --git a/drivers/wireless/bluetooth/bt_slip.c b/drivers/wireless/bluetooth/bt_slip.c index 9dfef441a7..ac273e4af0 100644 --- a/drivers/wireless/bluetooth/bt_slip.c +++ b/drivers/wireless/bluetooth/bt_slip.c @@ -553,7 +553,7 @@ static void bt_slip_unack_handle(FAR struct sliphci_s *priv) { bt_slip_unack_dtor(priv); - /* When it was blocked by full tx window, we needs to notifiy + /* When it was blocked by full tx window, we need to notify * bt_slip_send. */ @@ -941,7 +941,7 @@ static int bt_slip_receive(FAR struct bt_driver_s *drv, break; } - /* Remove 2 bytes crc payload, then caculate packect + /* Remove 2 bytes crc payload, then calculate packet * checksum with packet header and body. */ diff --git a/drivers/wireless/ieee80211/bcm43xxx/bcmf_driver.c b/drivers/wireless/ieee80211/bcm43xxx/bcmf_driver.c index 064e0bb1ac..65377ab275 100644 --- a/drivers/wireless/ieee80211/bcm43xxx/bcmf_driver.c +++ b/drivers/wireless/ieee80211/bcm43xxx/bcmf_driver.c @@ -888,7 +888,7 @@ void bcmf_wl_scan_event_handler(FAR struct bcmf_dev_s *priv, ie_offset += ie_buffer[ie_offset + 1] + 2; } - /* Check if AP is configured for WEP or unsupport privacy */ + /* Check if AP is configured for WEP or unsupported privacy */ if ((vaild_bss && (bss->capability & DOT11_CAP_PRIVACY)) || !vaild_bss) { @@ -1784,7 +1784,7 @@ int bcmf_wl_get_rate(FAR struct bcmf_dev_s *priv, struct iwreq *iwr) * Name: bcmf_wl_get_txpower * * Description: - * Get the tranmit power for the device + * Get the transmit power for the device ****************************************************************************/ int bcmf_wl_get_txpower(FAR struct bcmf_dev_s *priv, struct iwreq *iwr) diff --git a/drivers/wireless/ieee802154/at86rf23x/at86rf23x.c b/drivers/wireless/ieee802154/at86rf23x/at86rf23x.c index a803384405..459ecdf8fd 100644 --- a/drivers/wireless/ieee802154/at86rf23x/at86rf23x.c +++ b/drivers/wireless/ieee802154/at86rf23x/at86rf23x.c @@ -617,7 +617,7 @@ static int at86rf23x_set_trxstate(FAR struct at86rf23x_dev_s *dev, break; default: - wlerr("ERRPR: %s\n", EINVAL_STR); + wlerr("ERROR: %s\n", EINVAL_STR); init_status = 0; /* Placed this here to keep compiler if no debug */ return -EINVAL; } diff --git a/drivers/wireless/ieee802154/xbee/xbee.c b/drivers/wireless/ieee802154/xbee/xbee.c index 29a65eadbd..12bfd40ef7 100644 --- a/drivers/wireless/ieee802154/xbee/xbee.c +++ b/drivers/wireless/ieee802154/xbee/xbee.c @@ -1664,7 +1664,7 @@ void xbee_set_saddr(FAR struct xbee_priv_s *priv, FAR const uint8_t *saddr) * * Description: * Sends API frame with AT command request in order to set the RF channel - * (Operatin Channel) of the device. + * (Operation Channel) of the device. * ****************************************************************************/ diff --git a/drivers/wireless/ieee802154/xbee/xbee.h b/drivers/wireless/ieee802154/xbee/xbee.h index 1302f6e7dc..b3de8e6f49 100644 --- a/drivers/wireless/ieee802154/xbee/xbee.h +++ b/drivers/wireless/ieee802154/xbee/xbee.h @@ -419,7 +419,7 @@ void xbee_set_saddr(FAR struct xbee_priv_s *priv, FAR const uint8_t *saddr); * * Description: * Sends API frame with AT command request in order to set the RF channel - * (Operatin Channel) of the device. + * (Operation Channel) of the device. * ****************************************************************************/ diff --git a/drivers/wireless/ieee802154/xbee/xbee_mac.c b/drivers/wireless/ieee802154/xbee/xbee_mac.c index 8911993ca2..584c613e37 100644 --- a/drivers/wireless/ieee802154/xbee/xbee_mac.c +++ b/drivers/wireless/ieee802154/xbee/xbee_mac.c @@ -121,7 +121,7 @@ static void xbee_assoctimer(wdparm_t arg) * Name: xbee_assocworker * * Description: - * Poll the device for the assosciation status. This function is indirectly + * Poll the device for the association status. This function is indirectly * scheduled rom xbee_req_associate in order to poll the device for * association progress. * diff --git a/drivers/wireless/lpwan/sx127x/sx127x.h b/drivers/wireless/lpwan/sx127x/sx127x.h index 4db4fb8b83..7e2fb3d2ba 100644 --- a/drivers/wireless/lpwan/sx127x/sx127x.h +++ b/drivers/wireless/lpwan/sx127x/sx127x.h @@ -143,7 +143,7 @@ #define SX127X_LRM_PAYLOADMAX 0x23 /* LORA: LORA maximum payload length */ #define SX127X_LRM_HOPPER 0x24 /* LORA: FHSS Hop period */ #define SX127X_LRM_RXFIFOADDR 0x25 /* LORA: Address of last byte written in FIFO */ -#define SX127X_LRM_MODEMCFG3 0x26 /* LORA: Modem PHY confgi 3*/ +#define SX127X_LRM_MODEMCFG3 0x26 /* LORA: Modem PHY config 3*/ #define SX127X_LRM_FEIMSB 0x28 /* LORA: Estimated frequency error MSB */ #define SX127X_LRM_FEIMID 0x29 /* LORA: Estimated frequency error, MID */ #define SX127X_LRM_FEILSB 0x2a /* LORA: Estimated frequency error, LSB*/ @@ -760,7 +760,7 @@ #define SX127X_LRM_HOPPER_DEFAULT (0x00) -/* LORA: Modem PHY confgi 3 */ +/* LORA: Modem PHY config 3 */ #define SX127X_LRM_MODEMCFG3_AGCAUTOON (1 << 2) /* Bit 2: AGC auto ON */ #define SX127X_LRM_MODEMCFG3_LOWDRATEOPT (1 << 3) /* Bit 3: Low data rate optimize enable */ diff --git a/drivers/wireless/spirit/include/spirit_irq.h b/drivers/wireless/spirit/include/spirit_irq.h index 45bd898224..98996bb85c 100644 --- a/drivers/wireless/spirit/include/spirit_irq.h +++ b/drivers/wireless/spirit/include/spirit_irq.h @@ -55,7 +55,7 @@ * microcontroller EXTI line. Then, the user can check which IRQ has been * raised using two different ways. * - * On the ISR of the EXTI line phisically linked to the Spirit pin + * On the ISR of the EXTI line physically linked to the Spirit pin * configured for IRQ: * * Check only one Spirit IRQ (because the Spirit IRQ status register diff --git a/drivers/wireless/spirit/include/spirit_pktcommon.h b/drivers/wireless/spirit/include/spirit_pktcommon.h index 81e60ea1cc..5849e6cd2c 100644 --- a/drivers/wireless/spirit/include/spirit_pktcommon.h +++ b/drivers/wireless/spirit/include/spirit_pktcommon.h @@ -982,7 +982,7 @@ int spirit_pktcommon_get_rxcrc(FAR struct spirit_library_s *spirit, * Name: spirit_pktcommon_enable_rxautoack * * Description: - * Sets the AUTO ACKNOLEDGEMENT mechanism on the receiver. When the feature + * Sets the AUTO ACKNOWLEDGEMENT mechanism on the receiver. When the feature * is enabled and a data packet has been correctly received, then an * acknowledgement packet is sent back to the originator of the received * packet. If the PIGGYBACKING bit is also set, payload data will be read @@ -1008,7 +1008,7 @@ int spirit_pktcommon_enable_rxautoack(FAR struct spirit_library_s *spirit, * Name: spirit_pktcommon_enable_txautoack * * Description: - * Sets the AUTO ACKNOLEDGEMENT mechanism on the transmitter. On the + * Sets the AUTO ACKNOWLEDGEMENT mechanism on the transmitter. On the * transmitter side, the NACK_TX field can be used to require or not an * acknowledgment for each individual packet: if NACK_TX is set to "1" then * acknowledgment will not be required; if NACK_TX is set to "0" then diff --git a/drivers/wireless/spirit/include/spirit_pktstack.h b/drivers/wireless/spirit/include/spirit_pktstack.h index a15edd1302..7e2fcc12d1 100644 --- a/drivers/wireless/spirit/include/spirit_pktstack.h +++ b/drivers/wireless/spirit/include/spirit_pktstack.h @@ -50,7 +50,7 @@ * configure the link layer protocol features like autoack, * autoretransmission or piggybacking. * - * In addiiton, functions to set the payload length and the destination + * In addition, functions to set the payload length and the destination * address are provided. * * Example: diff --git a/drivers/wireless/spirit/include/spirit_regs.h b/drivers/wireless/spirit/include/spirit_regs.h index 7a1097491b..aa042cc0e3 100644 --- a/drivers/wireless/spirit/include/spirit_regs.h +++ b/drivers/wireless/spirit/include/spirit_regs.h @@ -290,7 +290,7 @@ * Read Write * Default value: 0x00 * 7 Reserved. - * 6:5 CLOCK_TAIL[1:0]: Specifies the number of extra cylces provided + * 6:5 CLOCK_TAIL[1:0]: Specifies the number of extra cycles provided * before entering in STANDBY state. * * CLOCK_TAIL1 | CLOCK_TAIL0 | Number of Extra Cycles @@ -1589,7 +1589,7 @@ #define PROTOCOL0_PERS_TX_MASK ((uint8_t)0x01) /* Enables persistent transmission */ #define PROTOCOL0_PERS_RX_MASK ((uint8_t)0x02) /* Enables persistent reception */ -#define PROTOCOL0_AUTO_ACK_MASK ((uint8_t)0x04) /* Enables auto acknowlegment */ +#define PROTOCOL0_AUTO_ACK_MASK ((uint8_t)0x04) /* Enables auto acknowledgment */ #define PROTOCOL0_NACK_TX_MASK ((uint8_t)0x08) /* Writes field NO_ACK=1 on * transmitted packet */ #define PROTOCOL0_NMAX_RETX_MASK ((uint8_t)0xf0) /* Retransmission mask */ diff --git a/drivers/wireless/spirit/include/spirit_spi.h b/drivers/wireless/spirit/include/spirit_spi.h index 5cf1f0927d..836d05b8e6 100644 --- a/drivers/wireless/spirit/include/spirit_spi.h +++ b/drivers/wireless/spirit/include/spirit_spi.h @@ -30,7 +30,7 @@ #include "spirit_types.h" /**************************************************************************** - * Pre-processor Defintiions + * Pre-processor Definitions ****************************************************************************/ /* SPIRIT1 SPI Headers */ diff --git a/drivers/wireless/spirit/include/spirit_timer.h b/drivers/wireless/spirit/include/spirit_timer.h index 8e8f086dd5..7721bd724a 100644 --- a/drivers/wireless/spirit/include/spirit_timer.h +++ b/drivers/wireless/spirit/include/spirit_timer.h @@ -324,7 +324,7 @@ int spirit_timer_get_rxtimeout_setup(FAR struct spirit_library_s *spirit, * Twu=(PRESCALER +1)*(COUNTER+1)*Tck, * where Tck = 28.818 us. The minimum vale of the wakeup timeout is 28.818us * (PRESCALER and COUNTER equals to 0) and the maximum value is about 1.89 s - * (PRESCALER anc COUNTER equals to 255). + * (PRESCALER and COUNTER equals to 255). * * Input Parameters: * spirit - Reference to a Spirit library state structure instance @@ -347,7 +347,7 @@ int spirit_timer_setup_wakeuptimer(FAR struct spirit_library_s *spirit, * in ms, according to the formula: Twu=(PRESCALER +1)*(COUNTER+1)*Tck, * where Tck = 28.818 us. The minimum vale of the wakeup timeout is * 28.818us (PRESCALER and COUNTER equals to 0) and the maximum value is - * about 1.89 s (PRESCALER anc COUNTER equals to 255). + * about 1.89 s (PRESCALER and COUNTER equals to 255). * * Input Parameters: * spirit - Reference to a Spirit library state structure instance @@ -438,7 +438,7 @@ int spirit_timer_get_wakeuptimer_setup(FAR struct spirit_library_s *spirit, * * where Tck = 28.818 us. The minimum vale of the wakeup timeout is * 28.818us (PRESCALER and COUNTER equals to 0) and the maximum value is - * about 1.89 s (PRESCALER anc COUNTER equals to 255). + * about 1.89 s (PRESCALER and COUNTER equals to 255). * * Input Parameters: * spirit - Reference to a Spirit library state structure instance @@ -464,7 +464,7 @@ int spirit_timer_setup_wakeuptimer_reload(FAR struct spirit_library_s *spirit, * * where Tck = 28.818 us. The minimum vale of the wakeup timeout is 28.818us * (PRESCALER and COUNTER equals to 0) and the maximum value is about 1.89 s - * (PRESCALER anc COUNTER equals to 255). + * (PRESCALER and COUNTER equals to 255). * * Input Parameters: * spirit - Reference to a Spirit library state structure instance diff --git a/drivers/wireless/spirit/lib/spirit_pktcommon.c b/drivers/wireless/spirit/lib/spirit_pktcommon.c index 0be9b4910a..1f38c829ab 100644 --- a/drivers/wireless/spirit/lib/spirit_pktcommon.c +++ b/drivers/wireless/spirit/lib/spirit_pktcommon.c @@ -1595,7 +1595,7 @@ int spirit_pktcommon_get_rxcrc(FAR struct spirit_library_s *spirit, * Name: spirit_pktcommon_enable_rxautoack * * Description: - * Sets the AUTO ACKNOLEDGEMENT mechanism on the receiver. When the feature + * Sets the AUTO ACKNOWLEDGEMENT mechanism on the receiver. When the feature * is enabled and a data packet has been correctly received, then an * acknowledgement packet is sent back to the originator of the received * packet. If the PIGGYBACKING bit is also set, payload data will be read @@ -1670,7 +1670,7 @@ int spirit_pktcommon_enable_rxautoack(FAR struct spirit_library_s *spirit, * Name: spirit_pktcommon_enable_txautoack * * Description: - * Sets the AUTO ACKNOLEDGEMENT mechanism on the transmitter. On the + * Sets the AUTO ACKNOWLEDGEMENT mechanism on the transmitter. On the * transmitter side, the NACK_TX field can be used to require or not an * acknowledgment for each individual packet: if NACK_TX is set to "1" then * acknowledgment will not be required; if NACK_TX is set to "0" then diff --git a/drivers/wireless/spirit/lib/spirit_timer.c b/drivers/wireless/spirit/lib/spirit_timer.c index 5c24103353..cc0cf88484 100644 --- a/drivers/wireless/spirit/lib/spirit_timer.c +++ b/drivers/wireless/spirit/lib/spirit_timer.c @@ -357,7 +357,7 @@ int spirit_timer_get_rxtimeout_setup(FAR struct spirit_library_s *spirit, * * where Tck = 28.818 us. The minimum vale of the wakeup timeout is 28.818us * (PRESCALER and COUNTER equals to 0) and the maximum value is about 1.89 s - * (PRESCALER anc COUNTER equals to 255). + * (PRESCALER and COUNTER equals to 255). * * Input Parameters: * spirit - Reference to a Spirit library state structure instance @@ -392,7 +392,7 @@ int spirit_timer_setup_wakeuptimer(FAR struct spirit_library_s *spirit, * in ms, according to the formula: Twu=(PRESCALER +1)*(COUNTER+1)*Tck, * where Tck = 28.818 us. The minimum vale of the wakeup timeout is * 28.818us (PRESCALER and COUNTER equals to 0) and the maximum value is - * about 1.89 s (PRESCALER anc COUNTER equals to 255). + * about 1.89 s (PRESCALER and COUNTER equals to 255). * * Input Parameters: * spirit - Reference to a Spirit library state structure instance @@ -530,7 +530,7 @@ int spirit_timer_get_wakeuptimer_setup(FAR struct spirit_library_s *spirit, * * where Tck = 28.818 us. The minimum vale of the wakeup timeout is * 28.818us (PRESCALER and COUNTER equals to 0) and the maximum value is - * about 1.89 s (PRESCALER anc COUNTER equals to 255). + * about 1.89 s (PRESCALER and COUNTER equals to 255). * * Input Parameters: * spirit - Reference to a Spirit library state structure instance @@ -569,7 +569,7 @@ int spirit_timer_setup_wakeuptimer_reload(FAR struct spirit_library_s *spirit, * * where Tck = 28.818 us. The minimum vale of the wakeup timeout is 28.818us * (PRESCALER and COUNTER equals to 0) and the maximum value is about 1.89 s - * (PRESCALER anc COUNTER equals to 255). + * (PRESCALER and COUNTER equals to 255). * * Input Parameters: * spirit - Reference to a Spirit library state structure instance diff --git a/fs/aio/Kconfig b/fs/aio/Kconfig index 3e519cdc3a..d3561a5ee0 100644 --- a/fs/aio/Kconfig +++ b/fs/aio/Kconfig @@ -8,7 +8,7 @@ config FS_AIO default n depends on SCHED_WORKQUEUE ---help--- - Enable support for aynchronous I/O. This selection enables the + Enable support for asynchronous I/O. This selection enables the interfaces declared in include/aio.h. if FS_AIO diff --git a/fs/fat/fs_fat32.c b/fs/fat/fs_fat32.c index cc7f4d9696..39eca06e04 100644 --- a/fs/fat/fs_fat32.c +++ b/fs/fat/fs_fat32.c @@ -1585,7 +1585,7 @@ static int fat_dup(FAR const struct file *oldp, FAR struct file *newp) * file structure. Then, instead of dup'ing the whole structure * as is done here, just increment the reference count on the * structure. The would have to be integrated with open logic as - * well, however, so that the same file structure is re-used if the + * well, however, so that the same file structure is reused if the * file is re-opened. */ diff --git a/fs/fat/fs_fat32dirent.c b/fs/fat/fs_fat32dirent.c index 9b311f250a..b5baa6dca9 100644 --- a/fs/fat/fs_fat32dirent.c +++ b/fs/fat/fs_fat32dirent.c @@ -1831,8 +1831,8 @@ static inline int fat_getsfname(FAR uint8_t *direntry, FAR char *buffer, /* In this version, we never write 0xe5 in the directory filenames * (because we do not handle any character sets where 0xe5 is valid - * in a filaname), but we could eencounter this in a filesystem - * written by some other system + * in a filename), but we could eencounter this in a filesystem + * written by some other system. */ if (ndx == 0 && ch == DIR0_E5) diff --git a/fs/hostfs/Kconfig b/fs/hostfs/Kconfig index 6ef25b8dae..0328a9400c 100644 --- a/fs/hostfs/Kconfig +++ b/fs/hostfs/Kconfig @@ -22,7 +22,7 @@ config FS_HOSTFS The backend implementation is arch-dependent. As of writing this, it's implemented for sim, arm and xtensa. - Note: depending on the backend implementions, hostfs might + Note: depending on the backend implementations, hostfs might only provide very restricted subset of filesystem operations. Sim: It's implemented with direct calls to the host OS API. diff --git a/fs/inode/fs_inoderemove.c b/fs/inode/fs_inoderemove.c index 3b8660e71f..ec507adcd4 100644 --- a/fs/inode/fs_inoderemove.c +++ b/fs/inode/fs_inoderemove.c @@ -46,7 +46,7 @@ * path refers to. This is normally done in preparation to removing or * moving an inode. * - * In symbolic links in the pseduo file system are enabled, then this + * In symbolic links in the pseudo file system are enabled, then this * logic will follow the symbolic links up until the terminal node. Then * that link in removed. So if this the terminal node is a symbolic link, * the symbolic link node will be removed, not the target of the link. diff --git a/fs/inode/inode.h b/fs/inode/inode.h index 0eb860a934..59dfc1d2d0 100644 --- a/fs/inode/inode.h +++ b/fs/inode/inode.h @@ -106,7 +106,7 @@ * relpath - INPUT: (not used) * OUTPUT: If the returned inode is a mountpoint, this is the * relative path from the mountpoint. - * OUTPUT: If a symobolic link into a mounted file system is + * OUTPUT: If a symbolic link into a mounted file system is * detected while traversing the path, then the link * will be converted to a mountpoint inode if the * mountpoint link is in an intermediate node of the diff --git a/fs/littlefs/lfs_getsetattr.patch b/fs/littlefs/lfs_getsetattr.patch index 60d77412be..1ac149f5d8 100644 --- a/fs/littlefs/lfs_getsetattr.patch +++ b/fs/littlefs/lfs_getsetattr.patch @@ -59,7 +59,7 @@ +// Returns the size of the attribute, or a negative error code on failure. +// Note, the returned size is the size of the attribute on disk, irrespective +// of the size of the buffer. This can be used to dynamically allocate a buffer -+// or check for existance. ++// or check for existence. +lfs_ssize_t lfs_file_getattr(lfs_t *lfs, lfs_file_t *file, + uint8_t type, void *buffer, lfs_size_t size); + diff --git a/fs/mnemofs/mnemofs.c b/fs/mnemofs/mnemofs.c index 42f9ebf5c8..bf1a432678 100644 --- a/fs/mnemofs/mnemofs.c +++ b/fs/mnemofs/mnemofs.c @@ -806,8 +806,8 @@ errout: * The new offset may be beyond the current file size. If that's the case, * then on any subsequent writes, it will be such that there are bytes with * '\0' in the gap/hole. In mnemofs, the whole hole situation is that the - * LRU doesn't know about the existence of holes, but comitting a file from - * LRU to the journal does write all the holes to the flash. + * LRU doesn't know about the existence of holes, but committing a file + * from LRU to the journal does write all the holes to the flash. * * Input Parameters: * filep - File pointer. @@ -1489,7 +1489,7 @@ static int mnemofs_readdir(FAR struct inode *mountpt, MFS_EXTRA_LOG("READDIR", "Mutex acquired."); } - MFS_EXTRA_LOG("READDIR", "Curretn direntry index is %" PRIu8, + MFS_EXTRA_LOG("READDIR", "Current direntry index is %" PRIu8, fsdirent->idx); if (fsdirent->idx == 0) @@ -2629,7 +2629,7 @@ int mnemofs_flush(FAR struct mfs_sb_s *sb) int ret = OK; bool change; - /* Emtpy the LRU, and maybe the journal as well. */ + /* Empty the LRU, and maybe the journal as well. */ finfo("Flush operation started."); diff --git a/fs/mnemofs/mnemofs.h b/fs/mnemofs/mnemofs.h index 357fabccc8..fa346eabc2 100644 --- a/fs/mnemofs/mnemofs.h +++ b/fs/mnemofs/mnemofs.h @@ -1104,10 +1104,10 @@ FAR char *mfs_ser_str(FAR const char * const str, const mfs_t len, * Name: mfs_deser_str * * Description: - * Deserialize a string from intput. + * Deserialize a string from input. * * Input Parameters: - * in - Intput array from where to deserialize. + * in - Input array from where to deserialize. * str - String to deserialize * len - Length of string * @@ -1360,7 +1360,7 @@ int mfs_ctz_wrtnode(FAR struct mfs_sb_s * const sb, * number of index `idx_dest`. * * The source is preferably the last CTZ block in the CTZ list, but it can - * realistically be any CTZ block in the CTZ list whos position is known. + * realistically be any CTZ block in the CTZ list whose position is known. * However, `idx_dest <= idx_src` has to be followed. Takes O(log(n)) * complexity to travel. * @@ -1571,7 +1571,7 @@ int mfs_mn_fmt(FAR struct mfs_sb_s * const sb, const mfs_t blk1, * Input Parameters: * sb - Superblock instance of the device. * root - New location of the root of the file system. - * root_sz - New size of the CTZ list of the root of the file syste. + * root_sz - New size of the CTZ list of the root of the file system. * * Returned Value: * 0 - OK @@ -1652,8 +1652,8 @@ mfs_t mfs_get_fsz(FAR struct mfs_sb_s * const sb, * * Assumptions/Limitations: * This allocates the `path` array in heap, and transfers the ownership - * of this array to the caller. It's the caller's reponsibility to use this - * with `mfs_free_patharr`. + * of this array to the caller. It's the caller's responsibility to use + * this with `mfs_free_patharr`. * ****************************************************************************/ diff --git a/fs/mnemofs/mnemofs_ctz.c b/fs/mnemofs/mnemofs_ctz.c index ec16bd748f..97f8910e9a 100644 --- a/fs/mnemofs/mnemofs_ctz.c +++ b/fs/mnemofs/mnemofs_ctz.c @@ -176,7 +176,7 @@ static mfs_t ctz_idx_nptrs(const mfs_t idx) * Input Parameters: * sb - Superblock instance of the device. * off - Offset of the data stored in the CTZ list. - * idx - Indes of the CTZ block, to be populated. + * idx - Index of the CTZ block, to be populated. * pgoff - Offset inside the CTZ block, to be populated. * ****************************************************************************/ diff --git a/fs/mnemofs/mnemofs_fsobj.c b/fs/mnemofs/mnemofs_fsobj.c index 71ddd68007..e6c4381412 100644 --- a/fs/mnemofs/mnemofs_fsobj.c +++ b/fs/mnemofs/mnemofs_fsobj.c @@ -57,7 +57,7 @@ * most updated data, which includes data from the flash, the updates from * the journal and the LRU deltas as well. * - * TODO: The above menetioned concept. + * TODO: The above mentioned concept. ****************************************************************************/ /**************************************************************************** @@ -546,7 +546,7 @@ int mfs_pitr_init(FAR const struct mfs_sb_s * const sb, } else { - /* 0 or gabage value is fine for master node, not required. */ + /* 0 or garbage value is fine for master node, not required. */ pitr->p.ctz.idx_e = 0; pitr->p.ctz.pg_e = 0; diff --git a/fs/mnemofs/mnemofs_lru.c b/fs/mnemofs/mnemofs_lru.c index 5199bbf4a2..fbed366c60 100644 --- a/fs/mnemofs/mnemofs_lru.c +++ b/fs/mnemofs/mnemofs_lru.c @@ -442,7 +442,7 @@ static int lru_wrtooff(FAR struct mfs_sb_s * const sb, const mfs_t data_off, } else if (found && lru_isnodefull(sb, node)) { - /* This can be optimized further if needed, but for now, for saftey of + /* This can be optimized further if needed, but for now, for safety of * the data, I think it's better to flush the entire thing. It won't * flush ALL of it, just, whatever's required. */ @@ -725,7 +725,7 @@ int mfs_lru_flush(FAR struct mfs_sb_s * const sb) * However, since passing the mode all the way requires a lot of change, and * is a redundant piece of information in most cases, the quick sort can * simply be done on the basis of depth, and this adventure can be left as a - * TOOD. + * TODO. * * This involves recursion, but given the LRU size is a constant, the depth * of recursion will be log2(n). For an LRU size of even 128 (which is quite diff --git a/fs/mnemofs/mnemofs_master.c b/fs/mnemofs/mnemofs_master.c index 4f90735b5e..54c1b2da0e 100644 --- a/fs/mnemofs/mnemofs_master.c +++ b/fs/mnemofs/mnemofs_master.c @@ -58,7 +58,7 @@ * * Master nodes sit at the very end of the journal. The last two blocks of * the journal are called master blocks, and they are filled with a new - * entry for a master node everytime it is updated. They are filled in a + * entry for a master node every time it is updated. They are filled in a * sequential manner, and thus, the latest master node can be found easily. * The two master blocks contain identical information, and exist to be as a * backup. diff --git a/fs/nfs/nfs_vfsops.c b/fs/nfs/nfs_vfsops.c index 2d0e1af939..3ded083764 100644 --- a/fs/nfs/nfs_vfsops.c +++ b/fs/nfs/nfs_vfsops.c @@ -107,7 +107,7 @@ struct nfs_dir_s { - struct fs_dirent_s nfs_base; /* VFS diretory structure */ + struct fs_dirent_s nfs_base; /* VFS directory structure */ uint8_t nfs_fhsize; /* Length of the file handle */ uint8_t nfs_fhandle[DIRENT_NFS_MAXHANDLE]; /* File handle (max size allocated) */ uint8_t nfs_verifier[DIRENT_NFS_VERFLEN]; /* Cookie verifier */ diff --git a/fs/nfs/rpc_clnt.c b/fs/nfs/rpc_clnt.c index 33b402dcc3..9500afcc34 100644 --- a/fs/nfs/rpc_clnt.c +++ b/fs/nfs/rpc_clnt.c @@ -132,7 +132,9 @@ static uint32_t rpc_vers; static uint32_t rpc_auth_null; static uint32_t rpc_auth_unix; -/* Global statics for all client instances. Cleared by NuttX on boot-up. */ +/* Global statistics for all client instances. + * Cleared by NuttX on boot-up. + */ #ifdef CONFIG_NFS_STATISTICS static struct rpcstats rpcstats; diff --git a/fs/notify/Kconfig b/fs/notify/Kconfig index 1a61711083..9dd9bef234 100644 --- a/fs/notify/Kconfig +++ b/fs/notify/Kconfig @@ -19,7 +19,7 @@ config FS_NOTIFY_MAX_EVENTS default 1024 config FS_NOTIFY_FD_POLLWAITERS - int "Max pollwaiters in one notify devcie" + int "Max pollwaiters in one notify device" default 2 endif # FS_NOTIFY diff --git a/fs/nxffs/Kconfig b/fs/nxffs/Kconfig index f3a6749843..b0c2c2ea69 100644 --- a/fs/nxffs/Kconfig +++ b/fs/nxffs/Kconfig @@ -107,10 +107,10 @@ config NXFFS_TAILTHRESHOLD Clean-up can either mean packing files together toward the end of the file or, if files are deleted at the end of the file, clean up can simply mean erasing the end of FLASH memory so that it can be - re-used again. However, doing this can also harm the life of the + reused again. However, doing this can also harm the life of the FLASH part because it can mean that the tail end of the FLASH is - re-used too often. This threshold determines if/when it is worth - erased the tail end of FLASH and making it available for re-use + reused too often. This threshold determines if/when it is worth + erased the tail end of FLASH and making it available for reuse (and possible over-wear). Default: 8192. endif diff --git a/fs/nxffs/nxffs_inode.c b/fs/nxffs/nxffs_inode.c index 04a6c147e8..9a84360e2a 100644 --- a/fs/nxffs/nxffs_inode.c +++ b/fs/nxffs/nxffs_inode.c @@ -285,7 +285,7 @@ int nxffs_nextentry(FAR struct nxffs_volume_s *volume, off_t offset, nerased = 0; /* Check for the magic sequence indicating the start of an NXFFS - * inode. There is the possibility of this magic sequnce occurring + * inode. There is the possibility of this magic sequence occurring * in FLASH data. However, the header CRC should distinguish * between real NXFFS inode headers and such false alarms. */ diff --git a/fs/nxffs/nxffs_open.c b/fs/nxffs/nxffs_open.c index 833cd7ebe1..d24bc85879 100644 --- a/fs/nxffs/nxffs_open.c +++ b/fs/nxffs/nxffs_open.c @@ -605,7 +605,7 @@ static inline int nxffs_wropen(FAR struct nxffs_volume_s *volume, } /* Then just break out of the loop reporting success. Note - * that the alllocated inode name string is retained; it + * that the allocated inode name string is retained; it * will be needed later to calculate the inode CRC. */ diff --git a/fs/nxffs/nxffs_pack.c b/fs/nxffs/nxffs_pack.c index 1ff34ad73b..03e6f8236a 100644 --- a/fs/nxffs/nxffs_pack.c +++ b/fs/nxffs/nxffs_pack.c @@ -785,7 +785,7 @@ static void nxffs_packtransfer(FAR struct nxffs_volume_s *volume, uint16_t destlen = volume->geo.blocksize - pack->iooffset; - /* Dermined how much data is available in the src data block */ + /* Determined how much data is available in the src data block */ uint16_t srclen = pack->src.blklen - pack->src.blkpos; diff --git a/fs/nxffs/nxffs_read.c b/fs/nxffs/nxffs_read.c index b898aa53a5..edd54fee85 100644 --- a/fs/nxffs/nxffs_read.c +++ b/fs/nxffs/nxffs_read.c @@ -303,7 +303,7 @@ int nxffs_nextblock(FAR struct nxffs_volume_s *volume, off_t offset, /* Check for the magic sequence indicating the start of an NXFFS * data block or start of the next inode. There is the possibility - * of this magic sequnce occurring in FLASH data. However, the + * of this magic sequence occurring in FLASH data. However, the * data block CRC should distinguish between real NXFFS data blocks * headers and such false alarms. */ diff --git a/fs/partition/fs_gpt.c b/fs/partition/fs_gpt.c index 3aaefaa47f..e71ba267cb 100644 --- a/fs/partition/fs_gpt.c +++ b/fs/partition/fs_gpt.c @@ -229,7 +229,7 @@ gpt_alloc_verify_entries(FAR struct partition_state_s *state, crc = crc32part((FAR const uint8_t *)pte, size, ~0l) ^ ~0l; if (crc != le32toh(gpt->partition_entry_array_crc32)) { - ferr("GUID Partitition Entry Array CRC check failed.\n"); + ferr("GUID Partition Entry Array CRC check failed.\n"); fs_heap_free(pte); return NULL; } diff --git a/fs/procfs/fs_procfsutil.c b/fs/procfs/fs_procfsutil.c index f498005d35..72311a952a 100644 --- a/fs/procfs/fs_procfsutil.c +++ b/fs/procfs/fs_procfsutil.c @@ -154,7 +154,7 @@ int procfs_snprintf(FAR char *buf, size_t size, * Name: procfs_sprintf * * Description: - * This function used to continous format string and copy it to buffer. + * This function used to continuous format string and copy it to buffer. * Every single string length must be smaller then LINEBUF_SIZE. * * Input Parameters: diff --git a/fs/romfs/fs_romfs.c b/fs/romfs/fs_romfs.c index 3f070d1569..707cd91155 100644 --- a/fs/romfs/fs_romfs.c +++ b/fs/romfs/fs_romfs.c @@ -1185,7 +1185,7 @@ static int romfs_bind(FAR struct inode *blkdriver, FAR const void *data, } #endif - /* Then complete the mount by getting the ROMFS configuratrion from + /* Then complete the mount by getting the ROMFS configuration from * the ROMF header */ diff --git a/fs/romfs/fs_romfs.h b/fs/romfs/fs_romfs.h index 0e6dc45d18..06347e5ccc 100644 --- a/fs/romfs/fs_romfs.h +++ b/fs/romfs/fs_romfs.h @@ -109,7 +109,7 @@ #define SEC_NSECTORS(r,o) ((o) / (r)->rm_hwsectorsize) #define SEC_ALIGN(r,o) ((o) & ~SEC_NDXMASK(r)) -/* Maximum numbr of links that will be followed before we decide that there +/* Maximum number of links that will be followed before we decide that there * is a problem. */ diff --git a/fs/shm/shmfs.c b/fs/shm/shmfs.c index e1cc39a539..37191f8ae4 100644 --- a/fs/shm/shmfs.c +++ b/fs/shm/shmfs.c @@ -154,7 +154,7 @@ static ssize_t shmfs_write(FAR struct file *filep, FAR const char *buffer, nwritten = buflen; endpos = startpos + buflen; - /* Desn't support shm auto expand, truncate first */ + /* Doesn't support shm auto expand, truncate first */ if (endpos > sho->length) { diff --git a/fs/spiffs/src/spiffs_check.c b/fs/spiffs/src/spiffs_check.c index cf2e9d54d8..cfebfa7733 100644 --- a/fs/spiffs/src/spiffs_check.c +++ b/fs/spiffs/src/spiffs_check.c @@ -1141,7 +1141,7 @@ static int spiffs_lucheck_callback(FAR struct spiffs_s *fs, int16_t objid, * * Returned Value: * The index associated with the objid is returned on success. -ENOENT - * is resutled if the objid was not found. + * is resulted if the objid was not found. * ****************************************************************************/ diff --git a/fs/spiffs/src/spiffs_vfs.c b/fs/spiffs/src/spiffs_vfs.c index 240533ceca..18ece82e58 100644 --- a/fs/spiffs/src/spiffs_vfs.c +++ b/fs/spiffs/src/spiffs_vfs.c @@ -510,7 +510,7 @@ static int spiffs_close(FAR struct file *filep) /* Flush any cached writes for the file object being closed. * This could result in an ENOSPC error being reported if the - * cache could not flushed to FALSH (and the file will appear to + * cache could not flushed to FLASH (and the file will appear to * to have been truncated). */ diff --git a/fs/unionfs/fs_unionfs.c b/fs/unionfs/fs_unionfs.c index c920b83b97..4fc395f6fd 100644 --- a/fs/unionfs/fs_unionfs.c +++ b/fs/unionfs/fs_unionfs.c @@ -84,7 +84,7 @@ struct unionfs_inode_s bool ui_unmounted; /* File system has been unmounted */ }; -/* This structure descries one opened file */ +/* This structure describes one opened file */ struct unionfs_file_s { diff --git a/fs/v9fs/client.c b/fs/v9fs/client.c index fbcfe6be68..e447a9610f 100644 --- a/fs/v9fs/client.c +++ b/fs/v9fs/client.c @@ -1743,7 +1743,7 @@ void v9fs_transport_done(FAR struct v9fs_payload_s *cookie, int ret) { FAR struct v9fs_lerror_s *error = cookie->riov[0].iov_base; - /* Recive message = riov[0] (Header) + iov[1] (Payload) + ... + /* Receive message = riov[0] (Header) + iov[1] (Payload) + ... * So we first check if the type on the rheader is RLERROR. If it is, * it means that payload[1] is ecode. */ diff --git a/fs/vfs/fs_dir.c b/fs/vfs/fs_dir.c index 585df77e14..14c172bdc6 100644 --- a/fs/vfs/fs_dir.c +++ b/fs/vfs/fs_dir.c @@ -209,7 +209,7 @@ static off_t seek_pseudodir(FAR struct file *filep, off_t offset) for (; curr != NULL && pos != offset; pos++, curr = curr->i_peer); - /* Now get the inode to vist next time that readdir() is called */ + /* Now get the inode to visit next time that readdir() is called */ prev = pdir->next; diff --git a/fs/vfs/fs_dup2.c b/fs/vfs/fs_dup2.c index 39b5494f28..bf01133267 100644 --- a/fs/vfs/fs_dup2.c +++ b/fs/vfs/fs_dup2.c @@ -84,7 +84,7 @@ int file_dup3(FAR struct file *filep1, FAR struct file *filep2, int flags) /* If there is already an inode contained in the new file structure, * close the file and release the inode. - * But we need keep the filep2->f_inode, incase of realloced by others. + * But we need keep the filep2->f_inode, in case of realloced by others. */ ret = file_close_without_clear(filep2); diff --git a/fs/vfs/fs_epoll.c b/fs/vfs/fs_epoll.c index 1b24b73f97..dc78f935d2 100644 --- a/fs/vfs/fs_epoll.c +++ b/fs/vfs/fs_epoll.c @@ -322,7 +322,7 @@ static int epoll_setup(FAR epoll_head_t *eph) * Name: epoll_teardown * * Description: - * Teardown all the notifed fd and check the notified fd's event with user + * Teardown all the notified fd and check the notified fd's event with user * expected event. * * Input Parameters: @@ -331,7 +331,7 @@ static int epoll_setup(FAR epoll_head_t *eph) * maxevents - The epoll events array size * * Returned Value: - * Return the number of fd that notifed and the events is also user + * Return the number of fd that notified and the events is also user * expected. * ****************************************************************************/ @@ -347,7 +347,7 @@ static int epoll_teardown(FAR epoll_head_t *eph, FAR struct epoll_event *evs, list_for_every_entry_safe(&eph->setup, epn, tepn, epoll_node_t, node) { - /* Only check the notifed fd */ + /* Only check the notified fd */ if (!epn->notified) { diff --git a/fs/vfs/fs_read.c b/fs/vfs/fs_read.c index 5ae13b57cd..f21107182b 100644 --- a/fs/vfs/fs_read.c +++ b/fs/vfs/fs_read.c @@ -118,7 +118,7 @@ static ssize_t file_readv_compat(FAR struct file *filep, ntotal += nread; - /* Check for a parital success condition, including an end-of-file */ + /* Check for a partial success condition, including an end-of-file */ if (nread < iov[i].iov_len) { diff --git a/fs/vfs/fs_symlink.c b/fs/vfs/fs_symlink.c index d868b17749..cb32bff301 100644 --- a/fs/vfs/fs_symlink.c +++ b/fs/vfs/fs_symlink.c @@ -56,7 +56,7 @@ * * Description: * The symlink() function will create a new link (directory entry) for the - * existing file, path2. This implementation is simplied for use with + * existing file, path2. This implementation is simplified for use with * NuttX in these ways: * * - Links may be created only within the NuttX top-level, pseudo file diff --git a/fs/vfs/fs_write.c b/fs/vfs/fs_write.c index 89b5cddd91..22195de380 100644 --- a/fs/vfs/fs_write.c +++ b/fs/vfs/fs_write.c @@ -100,7 +100,7 @@ static ssize_t file_writev_compat(FAR struct file *filep, ntotal += nwritten; - /* Check for a parital success condition */ + /* Check for a partial success condition */ if (nwritten < iov[i].iov_len) { diff --git a/graphics/nxbe/nxbe_move.c b/graphics/nxbe/nxbe_move.c index cced6f611d..3bddf1f440 100644 --- a/graphics/nxbe/nxbe_move.c +++ b/graphics/nxbe/nxbe_move.c @@ -345,7 +345,7 @@ static inline void nxbe_move_pwfb(FAR struct nxbe_window_s *wnd, /* Construct the destination bounding box in relative window * coordinates. This derives from the source bounding box with - * an offset distination. + * an offset destination. */ nxgl_rectoffset(&destrect, &srcrect, offset->x, offset->y); diff --git a/graphics/nxbe/nxbe_setsize.c b/graphics/nxbe/nxbe_setsize.c index cd7312b3b8..0c17f2b0ba 100644 --- a/graphics/nxbe/nxbe_setsize.c +++ b/graphics/nxbe/nxbe_setsize.c @@ -284,7 +284,7 @@ void nxbe_setsize(FAR struct nxbe_window_s *wnd, nxgl_rectunion(&bounds, &bounds, &wnd->bounds); /* Then redraw this window AND all windows below it. Having resized the - * window, we may have exposed previoulsy obscured portions of windows + * window, we may have exposed previously obscured portions of windows * below this one. */ diff --git a/graphics/nxterm/nxterm_driver.c b/graphics/nxterm/nxterm_driver.c index 24c1bc2f8b..3202e028cd 100644 --- a/graphics/nxterm/nxterm_driver.c +++ b/graphics/nxterm/nxterm_driver.c @@ -233,7 +233,7 @@ static ssize_t nxterm_write(FAR struct file *filep, FAR const char *buffer, do { - /* Is the character part of a VT100 escape sequnce? */ + /* Is the character part of a VT100 escape sequence? */ state = nxterm_vt100(priv, ch); switch (state) @@ -312,7 +312,7 @@ static int nxterm_ioctl(FAR struct file *filep, int cmd, unsigned long arg) { /* NOTE: We don't need driver context here because the NXTERM handle * provided within each of the NXTERM IOCTL command data. Mutual - * exclusion is similar managed by the IOCTL cmmand handler. + * exclusion is similar managed by the IOCTL command handler. * * This permits the IOCTL to be called in abnormal context (such as * from boardctl()) @@ -378,7 +378,7 @@ static int nxterm_unlink(FAR struct inode *inode) * * NOTE: We don't need driver context here because the NXTERM handle * provided within each of the NXTERM IOCTL command data. Mutual - * exclusion is similar managed by the IOCTL cmmand handler. + * exclusion is similar managed by the IOCTL command handler. * * This permits the IOCTL to be called in abnormal context (such as * from boardctl()) diff --git a/graphics/nxterm/nxterm_font.c b/graphics/nxterm/nxterm_font.c index 81200bb214..97eee1b0c9 100644 --- a/graphics/nxterm/nxterm_font.c +++ b/graphics/nxterm/nxterm_font.c @@ -131,7 +131,7 @@ static void nxterm_fillspace(FAR struct nxterm_state_s *priv, * * Description: * This is part of the nxterm_putc logic. It creates and positions a - * the character and renders (or re-uses) a glyph for font. + * the character and renders (or reuses) a glyph for font. * ****************************************************************************/ diff --git a/include/crypto/bn.h b/include/crypto/bn.h index 8d423c757c..a624b88235 100644 --- a/include/crypto/bn.h +++ b/include/crypto/bn.h @@ -63,8 +63,8 @@ * Pre-processor Definitions ****************************************************************************/ -/* This macro defines the word size in bytes of the array that constitues the - * big-number data structure. +/* This macro defines the word size in bytes of the array that constitutes + * the big-number data structure. */ #define WORD_SIZE 1 diff --git a/include/crypto/siphash.h b/include/crypto/siphash.h index 97e2048a2c..e1c6636335 100644 --- a/include/crypto/siphash.h +++ b/include/crypto/siphash.h @@ -37,7 +37,7 @@ * optimized for speed on short messages returning a 64bit hash/digest value. * * The number of rounds is defined during the initialization: - * siphash24_init() for the fast and resonable strong version + * siphash24_init() for the fast and reasonable strong version * siphash48_init() for the strong version (half as fast) * * struct SIPHASH_CTX ctx; diff --git a/include/dsp.h b/include/dsp.h index 436b42ac3b..4dce26ea6c 100644 --- a/include/dsp.h +++ b/include/dsp.h @@ -191,7 +191,7 @@ typedef struct float_sat_f32_s float_sat_f32_t; struct pid_controller_f32_s { bool aw_en; /* Integral part decay if saturated */ - bool ireset_en; /* Intergral part reset if saturated */ + bool ireset_en; /* Integral part reset if saturated */ bool pisat_en; /* PI saturation enabled */ bool pidsat_en; /* PID saturation enabled */ bool _res; /* Reserved */ @@ -237,7 +237,7 @@ typedef struct ab_frame_f32_s ab_frame_f32_t; struct dq_frame_f32_s { - float d; /* Driect component */ + float d; /* Direct component */ float q; /* Quadrature component */ }; @@ -323,7 +323,7 @@ struct motor_aobserver_smo_f32_s float emf_lp_filter1; /* Adaptive first low pass EMF filter */ float emf_lp_filter2; /* Adaptive second low pass EMF filter */ ab_frame_f32_t emf; /* Estimated back-EMF */ - ab_frame_f32_t emf_f; /* Fitlered estimated back-EMF */ + ab_frame_f32_t emf_f; /* Filtered estimated back-EMF */ ab_frame_f32_t z; /* Correction factor */ ab_frame_f32_t i_est; /* Estimated idq current */ ab_frame_f32_t v_err; /* v_err = v_ab - emf */ diff --git a/include/dspb16.h b/include/dspb16.h index 9b095fb6b2..24b63aec54 100644 --- a/include/dspb16.h +++ b/include/dspb16.h @@ -181,7 +181,7 @@ typedef struct float_sat_b16_s float_sat_b16_t; struct pid_controller_b16_s { bool aw_en; /* Integral part decay if saturated */ - bool ireset_en; /* Intergral part reset if saturated */ + bool ireset_en; /* Integral part reset if saturated */ bool pisat_en; /* PI saturation enabled */ bool pidsat_en; /* PID saturation enabled */ bool _res; /* Reserved */ @@ -227,7 +227,7 @@ typedef struct ab_frame_b16_s ab_frame_b16_t; struct dq_frame_b16_s { - b16_t d; /* Driect component */ + b16_t d; /* Direct component */ b16_t q; /* Quadrature component */ }; @@ -313,7 +313,7 @@ struct motor_aobserver_smo_b16_s b16_t emf_lp_filter1; /* Adaptive first low pass EMF filter */ b16_t emf_lp_filter2; /* Adaptive second low pass EMF filter */ ab_frame_b16_t emf; /* Estimated back-EMF */ - ab_frame_b16_t emf_f; /* Fitlered estimated back-EMF */ + ab_frame_b16_t emf_f; /* Filtered estimated back-EMF */ ab_frame_b16_t z; /* Correction factor */ ab_frame_b16_t i_est; /* Estimated idq current */ ab_frame_b16_t v_err; /* v_err = v_ab - emf */ @@ -383,7 +383,7 @@ struct motor_phy_params_b16_s b16_t one_by_p; /* Inverse number of motor pole pairs */ }; -/* PMSM motor physcial parameters */ +/* PMSM motor physical parameters */ struct pmsm_phy_params_b16_s { diff --git a/include/fixedmath.h b/include/fixedmath.h index 3f15ceddf4..585c25cdd7 100644 --- a/include/fixedmath.h +++ b/include/fixedmath.h @@ -126,8 +126,8 @@ #define b8addi(a,i) ((a)+itob8(i)) /* Add integer from b16 */ #define b8subb8(a,b) ((a)-(b)) /* Subtraction */ #define b8subi(a,i) ((a)-itob8(i)) /* Subtract integer from b8 */ -#define b8mulb8(a,b) (b16tob8((b16_t)(a)*(b16_t)(b)) /* Muliplication */ -#define ub8mulub8(a,b) (ub16toub8((ub16_t)(a)*(ub16_t)(b)) /* Muliplication */ +#define b8mulb8(a,b) (b16tob8((b16_t)(a)*(b16_t)(b)) /* Multiplication */ +#define ub8mulub8(a,b) (ub16toub8((ub16_t)(a)*(ub16_t)(b)) /* Multiplication */ #define b8muli(a,i) ((a)*(i)) /* Simple multiplication by integer */ #define b8sqr(a) b8mulb8(a,a) /* Square */ #define ub8sqr(a) ub8mulub8(a,a) /* Square */ diff --git a/include/nuttx/analog/hx711.h b/include/nuttx/analog/hx711.h index b51077bd76..e2c77de678 100644 --- a/include/nuttx/analog/hx711.h +++ b/include/nuttx/analog/hx711.h @@ -55,7 +55,7 @@ #define HX711_SET_GAIN 2 -/* Set what value coresponds to 1 unit. Takes integer. +/* Set what value corresponds to 1 unit. Takes integer. * If set to 0 (default) driver will return raw readings from * hx711 instead of calculated units. */ @@ -180,7 +180,7 @@ struct hx711_lower_s * arg - private data for handler, should be passed to handler * * Returned Value: - * On successfull interrupt initialization 0 should be returned, + * On successful interrupt initialization 0 should be returned, * when there was failure initializing interrupt -1 shall be returned. * **************************************************************************/ @@ -204,7 +204,7 @@ struct hx711_lower_s * Input Parameters: * minor - unique number identifying hx711 chip. * lower - provided by platform code to manipulate hx711 with platform - * dependant functions> + * dependent functions> * * Returned Value: * OK on success, or negated errno on failure diff --git a/include/nuttx/binfmt/ieee695.h b/include/nuttx/binfmt/ieee695.h index 42d7404f3d..ac9d641a5b 100644 --- a/include/nuttx/binfmt/ieee695.h +++ b/include/nuttx/binfmt/ieee695.h @@ -400,7 +400,7 @@ struct ieee695_lheadr_s uint8_t name[1]; /* Name string data begins here */ }; -/* 88H COMENT - Comment Record */ +/* 88H COMMENT - Comment Record */ struct ieee695_coment_s { diff --git a/include/nuttx/board.h b/include/nuttx/board.h index d3430d2b3c..2ca04d1f54 100644 --- a/include/nuttx/board.h +++ b/include/nuttx/board.h @@ -349,7 +349,7 @@ int board_switch_boot(FAR const char *system); * Input Parameters: * path - Path to the new application firmware image to be booted. * hdr_size - Image header size in bytes. This value may be useful for - * skipping metadata information preprended to the application + * skipping metadata information prepended to the application * image. * * Returned Value: diff --git a/include/nuttx/compiler.h b/include/nuttx/compiler.h index 38f4c815c1..2c93231439 100644 --- a/include/nuttx/compiler.h +++ b/include/nuttx/compiler.h @@ -278,7 +278,7 @@ # define nosanitize_address __attribute__((no_sanitize_address)) -/* the Greenhills compiler do not support the following atttributes */ +/* the Greenhills compiler do not support the following attributes */ # if defined(__ghs__) # undef nooptimiziation_function @@ -349,7 +349,7 @@ # define used_code __attribute__((used)) # define used_data __attribute__((used)) -/* The allocation function annonations */ +/* The allocation function annotations */ # if __GNUC__ >= 11 # define fopen_like __attribute__((__malloc__(fclose, 1))) @@ -586,7 +586,7 @@ # define no_builtin(n) # endif -/* CMSE extention */ +/* CMSE extension */ # ifdef CONFIG_ARCH_HAVE_TRUSTZONE # define tz_nonsecure_entry __attribute__((cmse_nonsecure_entry)) diff --git a/include/nuttx/coresight/coresight_funnel.h b/include/nuttx/coresight/coresight_funnel.h index 2a47f773c1..63fef7233d 100644 --- a/include/nuttx/coresight/coresight_funnel.h +++ b/include/nuttx/coresight/coresight_funnel.h @@ -37,7 +37,7 @@ struct coresight_funnel_dev_s { struct coresight_dev_s csdev; uint32_t priority; /* Port selection order. */ - uint8_t port_num; /* Port numbre. */ + uint8_t port_num; /* Port number. */ uint8_t port_refcnt[0]; /* Port refcnt. */ }; diff --git a/include/nuttx/drivers/rpmsgblk.h b/include/nuttx/drivers/rpmsgblk.h index 0765b21f65..302187b10e 100644 --- a/include/nuttx/drivers/rpmsgblk.h +++ b/include/nuttx/drivers/rpmsgblk.h @@ -71,7 +71,7 @@ int rpmsgblk_server_init(void); * remotecpu - the server cpu name * remotepath - the device you want to access in the remote cpu * localpath - the device path in local cpu, if NULL, the localpath is - * same as the remotepath, provide this argument to supoort + * same as the remotepath, provide this argument to support * custom device path * * Returned Values: diff --git a/include/nuttx/drivers/rpmsgdev.h b/include/nuttx/drivers/rpmsgdev.h index 1bef6e694c..eb51d13b79 100644 --- a/include/nuttx/drivers/rpmsgdev.h +++ b/include/nuttx/drivers/rpmsgdev.h @@ -79,7 +79,7 @@ int rpmsgdev_export(FAR const char *remotecpu, FAR const char *localpath); * remotecpu - the server cpu name * remotepath - the device you want to access in the remote cpu * localpath - the device path in local cpu, if NULL, the localpath is - * same as the remotepath, provide this argument to supoort + * same as the remotepath, provide this argument to support * custom device path * flags - RPMSGDEV_NOFRAG_READ and RPMSGDEV_NOFRAG_WRITE can be set * to indicates that the read and write data of the device diff --git a/include/nuttx/fs/nxffs.h b/include/nuttx/fs/nxffs.h index 2dc829e2fb..e9a3f74293 100644 --- a/include/nuttx/fs/nxffs.h +++ b/include/nuttx/fs/nxffs.h @@ -65,12 +65,12 @@ /* Clean-up can either mean packing files together toward the end of the file * or, if file are deleted at the end of the file, clean up can simply mean - * erasing the end of FLASH memory so that it can be re-used again. However, + * erasing the end of FLASH memory so that it can be reused again. However, * doing this can also harm the life of the FLASH part because it can mean - * that the tail end of the FLASH is re-used too often. + * that the tail end of the FLASH is reused too often. * * This threshold determines if/when it is worth erased the tail end of FLASH - * and making it available for re-use (and possible over-wear). + * and making it available for reuse (and possible over-wear). */ #ifndef CONFIG_NXFFS_TAILTHRESHOLD diff --git a/include/nuttx/fs/procfs.h b/include/nuttx/fs/procfs.h index efece595f9..bdffda4bb0 100644 --- a/include/nuttx/fs/procfs.h +++ b/include/nuttx/fs/procfs.h @@ -228,7 +228,7 @@ int procfs_snprintf(FAR char *buf, size_t size, * Name: procfs_sprintf * * Description: - * This function used to continous format string and copy it to buffer. + * This function used to continuous format string and copy it to buffer. * Every single string length must be smaller then LINEBUF_SIZE. * * Input Parameters: diff --git a/include/nuttx/i3c/device.h b/include/nuttx/i3c/device.h index 3b2b4e9215..7b40fc0d3a 100644 --- a/include/nuttx/i3c/device.h +++ b/include/nuttx/i3c/device.h @@ -441,7 +441,7 @@ FAR const struct i3c_device *i3c_master_find_i3c_dev( * cmd - The buf of ccc commands to transfer, only one frame at a time * * Returned Value: - * 0 or positive if Success, nagative otherwise. + * 0 or positive if Success, negative otherwise. ****************************************************************************/ int i3c_device_send_ccc_cmd(FAR const struct i3c_device *dev, diff --git a/include/nuttx/i3c/i3c_driver.h b/include/nuttx/i3c/i3c_driver.h index 716b6de6cb..63c8f96815 100644 --- a/include/nuttx/i3c/i3c_driver.h +++ b/include/nuttx/i3c/i3c_driver.h @@ -91,7 +91,7 @@ #define I3CIOC_FREE_IBI _I3CIOC(0x0005) /* Command: I3CIOC_GET_DEVINFO - * Description: Get an I3C bus dev infomation + * Description: Get an I3C bus dev information * * Argument: None * Dependencies: diff --git a/include/nuttx/i3c/master.h b/include/nuttx/i3c/master.h index cbc40db4a2..cc50e88933 100644 --- a/include/nuttx/i3c/master.h +++ b/include/nuttx/i3c/master.h @@ -490,8 +490,8 @@ struct i3c_bus * This method is mandatory only if ->request_ibi is not NULL. * @recycle_ibi_slot: recycle an IBI slot. Called every time an IBI has been * processed by its handler. The IBI slot should be put back - * in the IBI slot pool so that the controller can re-use it - * for a future IBI + * in the IBI slot pool so that the controller can reuse it + * for a future IBI. * This method is mandatory only if ->request_ibi is not * NULL. */ @@ -584,7 +584,7 @@ struct i3c_generic_ibi_slot /* struct i3c_generic_ibi_pool - I3C master controller object * @lock: used to protect share resource. * @num_slots: the number of struct i3c_generic_ibi_slot. - * @slots: the general slot used to manager payload infomation in pool. + * @slots: the general slot used to manager payload information in pool. * @payload_buf: pending process messages from IBI handler. * @free_slots: a free slot list from a generic IBI pool. * @pending: a pending slots list from a generic IBI pool. @@ -904,8 +904,8 @@ FAR struct i3c_ibi_slot *i3c_master_get_free_ibi_slot( * * This function takes care of everything for you: * - Creates and initializes the I3C bus. - * - Registers all I3C charactor driver that supports I3C transfer. - * - Registers the I2C charactor driver that supports I2C transfer. + * - Registers all I3C character driver that supports I3C transfer. + * - Registers the I2C character driver that supports I2C transfer. * * Input Parameters: * master - Master used to send frames on the bus. diff --git a/include/nuttx/input/aw86225.h b/include/nuttx/input/aw86225.h index 655b8f9f7d..333e712308 100644 --- a/include/nuttx/input/aw86225.h +++ b/include/nuttx/input/aw86225.h @@ -109,7 +109,7 @@ struct aw86225_config unsigned int sine_array[4]; - /* The boundry between ram mode and rtp mode */ + /* The boundary between ram mode and rtp mode */ unsigned int effect_id_boundary; diff --git a/include/nuttx/input/ff.h b/include/nuttx/input/ff.h index 0a0fdefb9d..b4060af122 100644 --- a/include/nuttx/input/ff.h +++ b/include/nuttx/input/ff.h @@ -420,7 +420,7 @@ struct ff_lowerhalf_s * device or dedicated registers. At each power-on, so that the values read * from the device are already corrected. When the device is calibrated, * the absolute accuracy will be better than before. - * Note: the parameters associated with calibration value, maxinum 32-byte. + * Note: the parameters associated with calibration value, maximum 32-byte. */ CODE int (*set_calibvalue)(FAR struct ff_lowerhalf_s *lower, @@ -434,7 +434,7 @@ struct ff_lowerhalf_s * calibration value of the device needs to be obtained and backed up, * so that the last calibration value can be directly obtained after * power-on. - * Note: the parameters associated with calibration value, maxinum 32-byte. + * Note: the parameters associated with calibration value, maximum 32-byte. */ CODE int (*calibrate)(FAR struct ff_lowerhalf_s *lower, @@ -514,7 +514,7 @@ int ff_register(FAR struct ff_lowerhalf_s *lower, FAR const char *path, * release the occupied resources. * * Arguments: - * lower - A pointer to an insatnce of force feedback lower half driver. + * lower - A pointer to an instance of force feedback lower half driver. * path - The path of force feedback device. such as "/dev/input0" * ****************************************************************************/ diff --git a/include/nuttx/input/ff_dummy.h b/include/nuttx/input/ff_dummy.h index 947b2d72b4..a7c185e0f9 100644 --- a/include/nuttx/input/ff_dummy.h +++ b/include/nuttx/input/ff_dummy.h @@ -40,7 +40,7 @@ * * Input Parameters: * devno - The user specifies device number, from 0. If the - * devno alerady exists, -EEXIST will be returned. + * devno already exists, -EEXIST will be returned. * * Returned Value: * Zero (OK) on success; a negated errno value on failure. diff --git a/include/nuttx/input/mouse.h b/include/nuttx/input/mouse.h index 37174f819a..4e4d56c464 100644 --- a/include/nuttx/input/mouse.h +++ b/include/nuttx/input/mouse.h @@ -229,7 +229,7 @@ int mouse_register(FAR struct mouse_lowerhalf_s *lower, * release the occupied resources. * * Arguments: - * lower - A pointer to an insatnce of mouse lower half driver. + * lower - A pointer to an instance of mouse lower half driver. * path - The path of mouse device. such as "/dev/mouse0" ****************************************************************************/ diff --git a/include/nuttx/input/stmpe811.h b/include/nuttx/input/stmpe811.h index cb51418e09..9937acc4b9 100644 --- a/include/nuttx/input/stmpe811.h +++ b/include/nuttx/input/stmpe811.h @@ -478,7 +478,7 @@ struct stmpe811_config_s int irq; /* IRQ number received by interrupt handler. */ #endif - /* These are the timing valuses for ADC CTRL1 and CTRL2. These values + /* These are the timing values for ADC CTRL1 and CTRL2. These values * are only used if either the TSC or the ADC are enabled. These values * determine the characteristics of sampling. */ diff --git a/include/nuttx/input/touchscreen.h b/include/nuttx/input/touchscreen.h index a06043b96c..26a39d68db 100644 --- a/include/nuttx/input/touchscreen.h +++ b/include/nuttx/input/touchscreen.h @@ -334,7 +334,7 @@ int touch_register(FAR struct touch_lowerhalf_s *lower, * release the occupied resources. * * Arguments: - * lower - A pointer to an insatnce of touchscreen lower half driver. + * lower - A pointer to an instance of touchscreen lower half driver. * path - The path of touchscreen device. such as "/dev/input0" ****************************************************************************/ diff --git a/include/nuttx/input/x11_xf86keysym.h b/include/nuttx/input/x11_xf86keysym.h index 215613c414..d0fdbeca3c 100644 --- a/include/nuttx/input/x11_xf86keysym.h +++ b/include/nuttx/input/x11_xf86keysym.h @@ -118,7 +118,7 @@ #define XF86XK_ApplicationRight 0x1008FF51 /* switch to application, right*/ #define XF86XK_Book 0x1008FF52 /* Launch bookreader */ #define XF86XK_CD 0x1008FF53 /* Launch CD/DVD player */ -#define XF86XK_Calculater 0x1008FF54 /* Launch Calculater */ +#define XF86XK_Calculater 0x1008FF54 /* Launch Calculator */ #define XF86XK_Clear 0x1008FF55 /* Clear window, screen */ #define XF86XK_Close 0x1008FF56 /* Close window */ #define XF86XK_Copy 0x1008FF57 /* Copy selection */ @@ -152,7 +152,7 @@ #define XF86XK_RotationKB 0x1008FF76 /* don't use */ #define XF86XK_Save 0x1008FF77 /* Save (file, document, state */ #define XF86XK_ScrollUp 0x1008FF78 /* Scroll window/contents up */ -#define XF86XK_ScrollDown 0x1008FF79 /* Scrool window/contentd down */ +#define XF86XK_ScrollDown 0x1008FF79 /* Scroll window/contentd down */ #define XF86XK_ScrollClick 0x1008FF7A /* Use XKB mousekeys instead */ #define XF86XK_Send 0x1008FF7B /* Send mail, file, object */ #define XF86XK_Spell 0x1008FF7C /* Spell checker */ diff --git a/include/nuttx/instrument.h b/include/nuttx/instrument.h index 3467629b4e..111faf1351 100644 --- a/include/nuttx/instrument.h +++ b/include/nuttx/instrument.h @@ -60,7 +60,7 @@ struct instrument_s * entry - instrument entry structure. * Notice: * use CONFIG_ARCH_INSTRUMENT_ALL must mark _start or entry - * noinstrument_function, becuase bss not set. + * noinstrument_function, because bss not set. * Make sure your callbacks are not instrumented recursively. * ****************************************************************************/ diff --git a/include/nuttx/ioexpander/gpio.h b/include/nuttx/ioexpander/gpio.h index 8e27b6a077..2b8bea7928 100644 --- a/include/nuttx/ioexpander/gpio.h +++ b/include/nuttx/ioexpander/gpio.h @@ -164,7 +164,7 @@ struct gpio_dev_s uint8_t register_count; - /* Number of times interrupt occured */ + /* Number of times interrupt occurred */ uintptr_t int_count; diff --git a/include/nuttx/ioexpander/ioexpander.h b/include/nuttx/ioexpander/ioexpander.h index 06e2c24054..48bbcc666c 100644 --- a/include/nuttx/ioexpander/ioexpander.h +++ b/include/nuttx/ioexpander/ioexpander.h @@ -75,7 +75,7 @@ #define IOEXPANDER_OPTION_NONGENERIC 4 /* Non generic option interface. Some * IO expanders have more advance * options for pins and communication. - * This is used to pass driver dependend + * This is used to pass driver dependent * structure to expander driver. */ diff --git a/include/nuttx/ipcc.h b/include/nuttx/ipcc.h index 68cf724497..25854b1a27 100644 --- a/include/nuttx/ipcc.h +++ b/include/nuttx/ipcc.h @@ -146,7 +146,7 @@ struct ipcc_ops_s * * Description: * Cleans up resources initialized by _ipcc_init(). If arch code - * malloc()ed any memory, this funciton is responsible of freeing it. + * malloc()ed any memory, this function is responsible of freeing it. * After this function is called, ipcc driver will not access lower * half pointer anymore. * diff --git a/include/nuttx/lcd/ht16k33.h b/include/nuttx/lcd/ht16k33.h index 8c465c2afc..b836505b3f 100644 --- a/include/nuttx/lcd/ht16k33.h +++ b/include/nuttx/lcd/ht16k33.h @@ -55,7 +55,7 @@ /* HT16K33 register addresses */ #define HT16K33_DISP_DATA_ADDR 0x00 /* Display Data Address Pointer: 0x00-0x0f */ -#define HT16K33_SYSTEM_SETUP 0x20 /* System Setup: bit 0 = System Oscilator */ +#define HT16K33_SYSTEM_SETUP 0x20 /* System Setup: bit 0 = System Oscillator */ #define HT16K33_KEY_DATA_ADDR 0x40 /* Key Data Address Pointer: 0x00-0x07 */ #define HT16K33_INT_FLAG_ADDR 0x60 /* INT Flag Address */ #define HT16K33_DISPLAY_SETUP 0x80 /* DISPLAY Setup */ diff --git a/include/nuttx/lcd/ili9225.h b/include/nuttx/lcd/ili9225.h index 6508056bfb..b459a085a5 100644 --- a/include/nuttx/lcd/ili9225.h +++ b/include/nuttx/lcd/ili9225.h @@ -128,7 +128,7 @@ #define ILI9225_DISP_CTRL1_D(n) (((uint16_t)(n) << ILI9225_DISP_CTRL1_D_SHIFT) & ILI9225_DISP_CTRL1_D_MASK) #define ILI9225_DISP_CTRL1_REV (1 << 2) /* Invert grayscale levels */ #define ILI9225_DISP_CTRL1_CL (1 << 3) /* Select 8-color display mode */ -#define ILI9225_DISP_CTRL1_GON (1 << 4) /* Set the output leve of gate driver */ +#define ILI9225_DISP_CTRL1_GON (1 << 4) /* Set the output level of gate driver */ #define ILI9225_DISP_CTRL1_TEMON (1 << 12) /* Enable the frame flag output signal */ /* ILI9225_DISP_CTRL2, Display Control 2, Offset: 0x08 */ @@ -160,7 +160,7 @@ #define ILI9225_RGB_DISP_INT_CTRL1_RIM_MASK (3 << ILI9225_RGB_DISP_INT_CTRL1_RIM_SHIFT) #define ILI9225_RGB_DISP_INT_CTRL1_RIM(n) (((uint16_t)(n) << ILI9225_RGB_DISP_INT_CTRL1_RIM_SHIFT) & ILI9225_RGB_DISP_INT_CTRL1_RIM_MASK) #define ILI9225_RGB_DISP_INT_CTRL1_DM (1 << 4) /* Select RGB interface */ -#define ILI9225_RGB_DISP_INT_CTRL1_RM (1 << 8) /* Select RGB interface acces to GRAM */ +#define ILI9225_RGB_DISP_INT_CTRL1_RM (1 << 8) /* Select RGB interface access to GRAM */ /* ILI9225_OSC_CTRL, Frame Maker Position, Offset: 0x0f */ @@ -188,7 +188,7 @@ #define ILI9225_POWER_CTRL2_PON1 (1 << 9) /* Operation starting bit for booster circuit 2 (VGH) */ #define ILI9225_POWER_CTRL2_PON2 (1 << 10) /* Operation starting bit for booster circuit 2 (VGL) */ #define ILI9225_POWER_CTRL2_PON3 (1 << 11) /* Operation starting bit for booster circout 3 (VCL) */ -#define ILI9225_POWER_CTRL2_APON (1 << 12) /* Automatic boosting operatio starting bit */ +#define ILI9225_POWER_CTRL2_APON (1 << 12) /* Automatic boosting operation starting bit */ /* ILI9225_POWER_CTRL3, Power Control 3, Offset: 0x12 */ diff --git a/include/nuttx/lcd/lcd.h b/include/nuttx/lcd/lcd.h index 892472e31e..30b0b47d98 100644 --- a/include/nuttx/lcd/lcd.h +++ b/include/nuttx/lcd/lcd.h @@ -98,7 +98,7 @@ struct lcd_planeinfo_s * buffer - The buffer containing the area to be written to the LCD * stride - Length of a line in bytes. This parameter may be necessary * to allow the LCD driver to calculate the offset for partial - * writes when the buffer needs to be splited for row-by-row + * writes when the buffer needs to be split for row-by-row * writing. * * NOTE: this operation may not be supported by the device, in which case @@ -150,7 +150,7 @@ struct lcd_planeinfo_s * * dev - LCD interface to redraw its memory content * - * NOTE: In case of non e-ink dispalys redrawing is cheap and can be done + * NOTE: In case of non e-ink displays redrawing is cheap and can be done * after each memory modification. Redrawing e-ink display is time and * energy consuming. * In order to avoid such operation (time and energy consumption) we can diff --git a/include/nuttx/leds/pca9635pw.h b/include/nuttx/leds/pca9635pw.h index 16c82d0e0a..b184a7c783 100644 --- a/include/nuttx/leds/pca9635pw.h +++ b/include/nuttx/leds/pca9635pw.h @@ -78,10 +78,10 @@ #define PCA9635PW_MODE_1_AI1 (1<<6) /* auto increment bit 1 */ #define PCA9635PW_MODE_1_AI0 (1<<5) /* auto increment bit 0 */ #define PCA9635PW_MODE_1_SLEEP (1<<4) /* low power mode/sleep enable/disable */ -#define PCA9635PW_MODE_1_SUB1 (1<<3) /* PCA9635PW reponds to I2C subaddress 1 enable/disable */ -#define PCA9635PW_MODE_1_SUB2 (1<<2) /* PCA9635PW reponds to I2C subaddress 2 enable/disable */ -#define PCA9635PW_MODE_1_SUB3 (1<<1) /* PCA9635PW reponds to I2C subaddress 3 enable/disable */ -#define PCA9635PW_MODE_1_ALLCALL (1<<0) /* PCA9635PW reponds to led all call I2C address enable/disable */ +#define PCA9635PW_MODE_1_SUB1 (1<<3) /* PCA9635PW responds to I2C subaddress 1 enable/disable */ +#define PCA9635PW_MODE_1_SUB2 (1<<2) /* PCA9635PW responds to I2C subaddress 2 enable/disable */ +#define PCA9635PW_MODE_1_SUB3 (1<<1) /* PCA9635PW responds to I2C subaddress 3 enable/disable */ +#define PCA9635PW_MODE_1_ALLCALL (1<<0) /* PCA9635PW responds to led all call I2C address enable/disable */ /* PCA9635PW_MODE_2 bit definitions */ diff --git a/include/nuttx/lib/elf.h b/include/nuttx/lib/elf.h index 12f7018803..601609fe25 100644 --- a/include/nuttx/lib/elf.h +++ b/include/nuttx/lib/elf.h @@ -177,7 +177,7 @@ struct module_s #if CONFIG_LIBC_ELF_MAXDEPEND > 0 uint8_t dependents; /* Number of modules that depend on this module */ - /* This is an upacked array of pointers to other modules that this module + /* This is an unpacked array of pointers to other modules that this module * depends upon. */ diff --git a/include/nuttx/lin.h b/include/nuttx/lin.h index 51bd3be173..e6a603edbd 100644 --- a/include/nuttx/lin.h +++ b/include/nuttx/lin.h @@ -40,9 +40,9 @@ #define LIN_ID_MASK ((1 << LIN_ID_BITS) - 1) #define LIN_ID_MAX LIN_ID_MASK -#define LIN_CTRL_FLAG CAN_EFF_FLAG /* Describe control information(such as wirte et.) */ +#define LIN_CTRL_FLAG CAN_EFF_FLAG /* Describe control information (such as write etc.) */ #define LIN_RTR_FLAG CAN_RTR_FLAG /* Describe the direction of sending and receiving */ -#define LIN_ERR_FLAG CAN_ERR_FLAG /* The flag indicate this is LIN err_frame */ +#define LIN_ERR_FLAG CAN_ERR_FLAG /* The flag indicates this is LIN err_frame */ /* Bit flags on can_frame.types * @@ -95,8 +95,8 @@ * define in bit 29 of can_id(CAN_ERR_FLAG) in can_frame. * ERR_CLASS : Indicate at what stage or where the error occurred, * define in data[0] in can_frame. - * ERR_REASON ：Indicate the error reson(timeout,error in the frame, etc.), - * define in data[0] ~ data[4] in can_frame. + * ERR_REASON ：Indicate the error reason (timeout, error in the frame, + * etc.), define in data[0] ~ data[4] in can_frame. */ /* ERR_CLASS in data[0] */ @@ -150,7 +150,7 @@ #define LIN_EVT_UNSPEC 0x00 /* Unspecified state event */ #define LIN_EVT_WAKEUP (1 << 0) /* Already send a wake-up command to lin_bus */ -#define LIN_EVT_WAKEUP_PASSIVE (1 << 1) /* Wake up when detecte low level signal of bus a for a period of time(such as 250us-5ms) */ +#define LIN_EVT_WAKEUP_PASSIVE (1 << 1) /* Wake up when detected low level signal of bus a for a period of time (such as 250us-5ms) */ #define LIN_EVT_SLEEP (1 << 2) /* Send a sleep command(0x3c) to the bus, only Master */ #define LIN_EVT_SLEEP_PASSIVE (1 << 3) /* Receive a sleep command from bus */ #define LIN_EVT_SLEEP_IDLE (1 << 4) /* Go to sleep when bus keep in the inactive for a period of time(such as 4s) */ diff --git a/include/nuttx/math/fft.h b/include/nuttx/math/fft.h index ee53b8bf7d..2d9b61f346 100644 --- a/include/nuttx/math/fft.h +++ b/include/nuttx/math/fft.h @@ -33,7 +33,7 @@ * DCT-II, the normally so called DCT * DCT-III, inverse of DCT-II, so called IDCT * DCT-IV, inverse of DCT-IV is itself - * see all the formula and more mathmatics trueth in wikipedia: + * see all the formula and more mathematics trueth in wikipedia: * https://en.wikipedia.org/wiki/Discrete_cosine_transform */ diff --git a/include/nuttx/mm/kasan.h b/include/nuttx/mm/kasan.h index a349eb9675..5c0e5454be 100644 --- a/include/nuttx/mm/kasan.h +++ b/include/nuttx/mm/kasan.h @@ -110,7 +110,7 @@ FAR void *kasan_unpoison(FAR const void *addr, size_t size); * None. * * Note: - * The size is shrinked for the shadow region + * The size is shrunk for the shadow region * ****************************************************************************/ @@ -166,7 +166,7 @@ void kasan_start(void); * * Description: * Stop kasan check, setup g_region_init variable. - * This used for some platfroms clear bss late, and error use kasan before + * This used for some platforms clear bss late, and error use kasan before * called kasan_register(). * * Input Parameters: diff --git a/include/nuttx/mm/mempool.h b/include/nuttx/mm/mempool.h index 7e64a9ae09..08051470b7 100644 --- a/include/nuttx/mm/mempool.h +++ b/include/nuttx/mm/mempool.h @@ -103,7 +103,7 @@ struct mempool_s /* Private data for memory pool */ - FAR char *ibase; /* The inerrupt mempool base pointer */ + FAR char *ibase; /* The interrupt mempool base pointer */ sq_queue_t queue; /* The free block queue in normal mempool */ sq_queue_t iqueue; /* The free block queue in interrupt mempool */ sq_queue_t equeue; /* The expand block queue for normal mempool */ @@ -323,9 +323,9 @@ void mempool_procfs_unregister(FAR struct mempool_procfs_entry_s *entry); * alloc - The alloc memory function for multiples pool. * alloc_size - Get the address size of the alloc function. * free - The free memory function for multiples pool. - * arg - The alloc & free memory fuctions used arg. + * arg - The alloc & free memory functions used arg. * chunksize - The multiples pool chunk size. - * expandsize - The expend mempry for all pools in multiples pool. + * expandsize - The expend memory for all pools in multiples pool. * dict_expendsize - The expend size for multiple dictnoary. * Returned Value: * Return an initialized multiple pool pointer on success, @@ -388,7 +388,7 @@ FAR void *mempool_multiple_realloc(FAR struct mempool_multiple_s *mpool, * Name: mempool_multiple_free * * Description: - * Release an memory block to the multiple mempry pool. The blk must have + * Release an memory block to the multiple memory pool. The blk must have * been returned by a previous call to mempool_multiple_alloc. * * Input Parameters: diff --git a/include/nuttx/motor/foc/foc.h b/include/nuttx/motor/foc/foc.h index 2efe7fedc6..f41b626e8f 100644 --- a/include/nuttx/motor/foc/foc.h +++ b/include/nuttx/motor/foc/foc.h @@ -104,7 +104,7 @@ struct foc_params_s foc_duty_t duty[CONFIG_MOTOR_FOC_PHASES]; /* PWM duty cycle for phases */ }; -/* Hardware specific informations */ +/* Hardware specific information */ struct foc_info_hw_s { @@ -123,7 +123,7 @@ struct foc_info_hw_s */ int32_t iphase_scale; /* Current phase scale [x100000] */ - int32_t iphase_max; /* Maximum phase curretn [x1000] */ + int32_t iphase_max; /* Maximum phase current [x1000] */ /* ADC configuration for BEMF sampling */ @@ -136,7 +136,7 @@ struct foc_info_hw_s struct foc_info_s { - struct foc_info_hw_s hw_cfg; /* Hardware specific informations */ + struct foc_info_hw_s hw_cfg; /* Hardware specific information */ }; /* FOC board-specific configuration */ diff --git a/include/nuttx/motor/stepper.h b/include/nuttx/motor/stepper.h index f1a5a4082c..c14f771e88 100644 --- a/include/nuttx/motor/stepper.h +++ b/include/nuttx/motor/stepper.h @@ -89,7 +89,7 @@ enum stepper_idle_e { STEPPER_ENABLE_IDLE = 0, /* Enable IDLE mode */ STEPPER_DISABLE_IDLE = 1, /* Disable IDLE mode */ - STEPPER_AUTO_IDLE = 2, /* Set automaticaly IDLE when stepper not in movement */ + STEPPER_AUTO_IDLE = 2, /* Set automatically IDLE when stepper not in movement */ }; /* Stepper driver status */ diff --git a/include/nuttx/mqueue.h b/include/nuttx/mqueue.h index 877bb3f6c6..60f2ee96f2 100644 --- a/include/nuttx/mqueue.h +++ b/include/nuttx/mqueue.h @@ -292,7 +292,7 @@ int nxmq_send(mqd_t mqdes, FAR const char *msg, size_t msglen, * msg - Message to send * msglen - The length of the message in bytes * prio - The priority of the message - * abstime - the absolute time to wait until a timeout is decleared + * abstime - the absolute time to wait until a timeout is declared * * Returned Value: * This is an internal OS interface and should not be used by applications. @@ -568,7 +568,7 @@ int file_mq_send(FAR struct file *mq, FAR const char *msg, size_t msglen, * msg - Message to send * msglen - The length of the message in bytes * prio - The priority of the message - * abstime - the absolute time to wait until a timeout is decleared + * abstime - the absolute time to wait until a timeout is declared * * Returned Value: * This is an internal OS interface and should not be used by applications. diff --git a/include/nuttx/mtd/mtd.h b/include/nuttx/mtd/mtd.h index 736e155290..171f2e583b 100644 --- a/include/nuttx/mtd/mtd.h +++ b/include/nuttx/mtd/mtd.h @@ -740,7 +740,7 @@ FAR struct mtd_dev_s *nullmtd_initialize(size_t mtdlen, int16_t sectsize, * remotecpu - the server cpu name * remotepath - the device you want to access in the remote cpu * localpath - the device path in local cpu, if NULL, the localpath is - * same as the remotepath, provide this argument to supoort + * same as the remotepath, provide this argument to support * custom device path * * Returned Values: diff --git a/include/nuttx/mtd/nand_wrapper.h b/include/nuttx/mtd/nand_wrapper.h index 03c2419865..e17cc6c178 100644 --- a/include/nuttx/mtd/nand_wrapper.h +++ b/include/nuttx/mtd/nand_wrapper.h @@ -43,7 +43,7 @@ struct nand_wrapper_dev_s { struct nand_dev_s wrapper; /* Wrapper device */ - struct nand_dev_s under; /* Underlying actuall upper half device */ + struct nand_dev_s under; /* Underlying the upper half device */ }; /**************************************************************************** diff --git a/include/nuttx/net/gmii.h b/include/nuttx/net/gmii.h index 8f44aa50be..184af40783 100644 --- a/include/nuttx/net/gmii.h +++ b/include/nuttx/net/gmii.h @@ -91,7 +91,7 @@ #define GMII_RTL8211F_PHYSR_A43 26 /* PHY Specific Status Register */ #define GMII_RTL8211F_INSR_A43 29 /* Interrupt Status Register */ #define GMII_RTL8211F_PAGSR 31 /* Page Select Register */ -#define GMII_RTL8211F_PHYSCR_A46 20 /* PHY Special Cofig Register */ +#define GMII_RTL8211F_PHYSCR_A46 20 /* PHY Special Config Register */ #define GMII_RTL8211F_LCR_D04 16 /* LED Control Register */ #define GMII_RTL8211F_EEELCR_D04 17 /* EEE LED Control Register */ #define GMII_RTL8211F_MIICR_D08 21 /* MII Control Register */ diff --git a/include/nuttx/net/icmpv6.h b/include/nuttx/net/icmpv6.h index 74eae20fc1..86513b3c0e 100644 --- a/include/nuttx/net/icmpv6.h +++ b/include/nuttx/net/icmpv6.h @@ -120,7 +120,7 @@ #define ICMPv6_PRFX_FLAG_L (1 << 7) /* On-link flag */ #define ICMPv6_PRFX_FLAG_A (1 << 6) /* Autonomous address-configuration flag */ -/* Return with size of an option (in full octects) using the size of a link +/* Return with size of an option (in full octets) using the size of a link * layer address taking into account a header of the two-bytes. */ diff --git a/include/nuttx/net/ioctl.h b/include/nuttx/net/ioctl.h index 7e1e982778..aedd0ab6af 100644 --- a/include/nuttx/net/ioctl.h +++ b/include/nuttx/net/ioctl.h @@ -94,7 +94,7 @@ /* MDIO/MCD *****************************************************************/ -#define SIOCMIINOTIFY _SIOC(0x0023) /* Receive notificaion via signal on +#define SIOCMIINOTIFY _SIOC(0x0023) /* Receive notification via signal on * PHY state change */ #define SIOCGMIIPHY _SIOC(0x0024) /* Get address of MII PHY in use */ #define SIOCGMIIREG _SIOC(0x0025) /* Get a MII register via MDIO */ @@ -120,8 +120,8 @@ #define SIOCGCANBITRATE _SIOC(0x002C) /* Get bitrate from a CAN controller */ #define SIOCSCANBITRATE _SIOC(0x002D) /* Set bitrate of a CAN controller */ -#define SIOCACANEXTFILTER _SIOC(0x002E) /* Add hardware-level exteneded ID filter */ -#define SIOCDCANEXTFILTER _SIOC(0x002F) /* Delete hardware-level exteneded ID filter */ +#define SIOCACANEXTFILTER _SIOC(0x002E) /* Add hardware-level extended ID filter */ +#define SIOCDCANEXTFILTER _SIOC(0x002F) /* Delete hardware-level extended ID filter */ #define SIOCACANSTDFILTER _SIOC(0x0030) /* Add hardware-level standard ID filter */ #define SIOCDCANSTDFILTER _SIOC(0x0031) /* Delete hardware-level standard ID filter */ #define SIOCCANRECOVERY _SIOC(0x0032) /* Recovery can, work only when bus-off state */ diff --git a/include/nuttx/net/net.h b/include/nuttx/net/net.h index 9a64c76099..28beb66865 100644 --- a/include/nuttx/net/net.h +++ b/include/nuttx/net/net.h @@ -229,7 +229,7 @@ struct socket_conn_s /* Definitions of IPv4 TOS and IPv6 Traffic Class */ uint8_t s_tos; /* IPv4 Type of Service */ -#define s_tclass s_tos /* IPv6 traffic class defination */ +#define s_tclass s_tos /* IPv6 traffic class definition */ #if defined(CONFIG_NET_IPv4) || defined(CONFIG_NET_IPv6) uint8_t s_ttl; /* Default time-to-live */ #endif @@ -339,7 +339,7 @@ ssize_t net_ioctl_arglen(uint8_t domain, int cmd); * * Returned Value: * Zero (OK) is returned on success; a negated errno value is returned on - * failured (probably -ECANCELED). + * failure (probably -ECANCELED). * ****************************************************************************/ @@ -358,7 +358,7 @@ int net_lock(void); * * Returned Value: * Zero (OK) is returned on success; a negated errno value is returned on - * failured (probably -EAGAIN). + * failure (probably -EAGAIN). * ****************************************************************************/ diff --git a/include/nuttx/net/netdev.h b/include/nuttx/net/netdev.h index 67f964e32e..c31ce180d7 100644 --- a/include/nuttx/net/netdev.h +++ b/include/nuttx/net/netdev.h @@ -745,7 +745,7 @@ int devif_poll(FAR struct net_driver_s *dev, devif_poll_callback_t callback); * If the destination IPv6 address is in the local network (determined * by logical ANDing of netmask and our IPv6 address), the function * checks the Neighbor Table to see if an entry for the destination IPv6 - * address is found. If so, an L2 header is pre-pended at the beginning + * address is found. If so, an L2 header is prepended at the beginning * of the packet and the function returns. * * If no Neighbor Table entry is found for the destination IPv6 address, diff --git a/include/nuttx/net/netdev_lowerhalf.h b/include/nuttx/net/netdev_lowerhalf.h index 29a55f3b32..b9421afaa3 100644 --- a/include/nuttx/net/netdev_lowerhalf.h +++ b/include/nuttx/net/netdev_lowerhalf.h @@ -426,7 +426,7 @@ FAR uint8_t *netpkt_getbase(FAR netpkt_t *pkt); * Description: * Set the length of data in netpkt, used when data is written into * netpkt by data/base pointer, no need to set this length after - * copyin. + * copying. * * Input Parameters: * dev - The lower half device driver structure diff --git a/include/nuttx/net/sixlowpan.h b/include/nuttx/net/sixlowpan.h index 6b3cfc5b8a..e4b71f673a 100644 --- a/include/nuttx/net/sixlowpan.h +++ b/include/nuttx/net/sixlowpan.h @@ -505,7 +505,7 @@ struct sixlowpan_reassbuf_s * radio, or (2) struct pktradio_metadata_s for a non-standard * packet radio. * - * If there are multilple frames in the list, this metadata + * If there are multiple frames in the list, this metadata * must apply to all of the frames in the list. * * Returned Value: diff --git a/include/nuttx/note/note_driver.h b/include/nuttx/note/note_driver.h index 88de1d279e..9b8496cf6f 100644 --- a/include/nuttx/note/note_driver.h +++ b/include/nuttx/note/note_driver.h @@ -192,7 +192,7 @@ int note_initialize(void); * PID - Task ID * * Returned Value: - * Retrun name if task name can be retrieved, otherwise NULL + * Return name if task name can be retrieved, otherwise NULL * ****************************************************************************/ diff --git a/include/nuttx/nx/nx.h b/include/nuttx/nx/nx.h index e1108d636b..a75d41d065 100644 --- a/include/nuttx/nx/nx.h +++ b/include/nuttx/nx/nx.h @@ -220,7 +220,7 @@ struct nx_callback_s * NXEVENT_SYNCHED - Synchronization handshake * * This completes the handshake started by nx_synch(). nx_synch() - * sends a syncrhonization messages to the NX server which responds + * sends a synchronization messages to the NX server which responds * with this event. The sleeping client is awakened and continues * graphics processing, completing the handshake. * diff --git a/include/nuttx/nx/nxmu.h b/include/nuttx/nx/nxmu.h index 5f6ab2297a..da708e4cbd 100644 --- a/include/nuttx/nx/nxmu.h +++ b/include/nuttx/nx/nxmu.h @@ -122,7 +122,7 @@ enum nxmsg_e NX_SVRMSG_OPENWINDOW, /* Create a new window */ NX_SVRMSG_CLOSEWINDOW, /* Close an existing window */ NX_SVRMSG_BLOCKED, /* The window is blocked */ - NX_SVRMSG_SYNCH, /* Window syncrhonization request */ + NX_SVRMSG_SYNCH, /* Window synchronization request */ NX_SVRMSG_CURSOR_ENABLE, /* Enable/disablel cursor presentation */ NX_SVRMSG_CURSOR_IMAGE, /* Set cursor image */ NX_SVRMSG_CURSOR_SETPOS, /* Set cursor position */ diff --git a/include/nuttx/nx/nxterm.h b/include/nuttx/nx/nxterm.h index a687dc9520..cdd19f6799 100644 --- a/include/nuttx/nx/nxterm.h +++ b/include/nuttx/nx/nxterm.h @@ -41,7 +41,7 @@ /* Configuration ************************************************************/ -/* Nx Console prerequistes */ +/* Nx Console prerequisites */ #ifndef CONFIG_NX # warning "NX is not enabled (CONFIG_NX) @@ -371,7 +371,7 @@ NXTERM nxtool_register(NXTKWINDOW hfwnd, FAR struct nxterm_window_s *wndo, * * NOTE: We don't need driver context here because the NXTERM handle * provided within each of the NXTERM IOCTL command data. Mutual - * exclusion is similar managed by the IOCTL cmmand handler. + * exclusion is similar managed by the IOCTL command handler. * * This permits the IOCTL to be called in abnormal context (such as * from boardctl()) diff --git a/include/nuttx/pci/pci.h b/include/nuttx/pci/pci.h index 3cc0af14c6..58de9fa813 100644 --- a/include/nuttx/pci/pci.h +++ b/include/nuttx/pci/pci.h @@ -396,7 +396,7 @@ struct pci_driver_s * val - The data buf * * Returned Value: - * Zero if success, otherwise nagative + * Zero if success, otherwise negative * ****************************************************************************/ @@ -417,7 +417,7 @@ int pci_bus_read_config(FAR struct pci_bus_s *bus, * val - The data buf * * Returned Value: - * Zero if success, otherwise nagative + * Zero if success, otherwise negative * ****************************************************************************/ @@ -445,7 +445,7 @@ int pci_bus_read_config_dword(FAR struct pci_bus_s *bus, * val - The data * * Returned Value: - * Zero if success, otherwise nagative + * Zero if success, otherwise negative * ****************************************************************************/ @@ -466,7 +466,7 @@ int pci_bus_write_config(FAR struct pci_bus_s *bus, * val - The data * * Returned Value: - * Zero if success, otherwise nagative + * Zero if success, otherwise negative * ****************************************************************************/ @@ -493,7 +493,7 @@ int pci_bus_write_config_dword(FAR struct pci_bus_s *bus, * val - The data buffer * * Returned Value: - * Zero if success, otherwise nagative + * Zero if success, otherwise negative * ****************************************************************************/ @@ -512,7 +512,7 @@ int pci_bus_read_io(FAR struct pci_bus_s *bus, uintptr_t addr, * val - The data buffer * * Returned Value: - * Zero if success, otherwise nagative + * Zero if success, otherwise negative * ****************************************************************************/ @@ -536,7 +536,7 @@ int pci_bus_read_io_dword(FAR struct pci_bus_s *bus, uintptr_t where, * val - The data * * Returned Value: - * Zero if success, otherwise nagative + * Zero if success, otherwise negative * ****************************************************************************/ @@ -555,7 +555,7 @@ int pci_bus_write_io(FAR struct pci_bus_s *bus, uintptr_t addr, * val - The data * * Returned Value: - * Zero if success, otherwise nagative + * Zero if success, otherwise negative * ****************************************************************************/ @@ -603,7 +603,7 @@ void pci_clear_master(FAR struct pci_device_s *dev); * dev - PCI device to be initialized *pci_bus_ops_s * Returned Value: - * Zero if success, otherwise nagative + * Zero if success, otherwise negative * ****************************************************************************/ @@ -620,7 +620,7 @@ int pci_enable_device(FAR struct pci_device_s *dev); * dev - PCI device to be Disable * * Returned Value: - * Zero if success, otherwise nagative + * Zero if success, otherwise negative * ****************************************************************************/ @@ -791,7 +791,7 @@ int pci_get_irq(FAR struct pci_device_s *dev); * num - number of vectors * * Return value: - * Return the number of allocated vectors on succes or negative errno + * Return the number of allocated vectors on success or negative errno * on failure. * ****************************************************************************/ diff --git a/include/nuttx/pci/pci_regs.h b/include/nuttx/pci/pci_regs.h index 1a84e56159..fcd85ff14d 100644 --- a/include/nuttx/pci/pci_regs.h +++ b/include/nuttx/pci/pci_regs.h @@ -672,7 +672,7 @@ #define PCI_EXP_DEVCAP2_LTR 0x00000800 /* Latency tolerance reporting */ #define PCI_EXP_DEVCAP2_OBFF_MASK 0x000c0000 /* OBFF support mechanism */ #define PCI_EXP_DEVCAP2_OBFF_MSG 0x00040000 /* New message signaling */ -#define PCI_EXP_DEVCAP2_OBFF_WAKE 0x00080000 /* Re-use WAKE# for OBFF */ +#define PCI_EXP_DEVCAP2_OBFF_WAKE 0x00080000 /* Reuse WAKE# for OBFF */ #define PCI_EXP_DEVCTL2 40 /* Device Control 2 */ #define PCI_EXP_DEVCTL2_COMP_TIMEOUT 0x000f /* Completion Timeout Value */ #define PCI_EXP_DEVCTL2_ARI 0x0020 /* Alternative Routing-ID */ diff --git a/include/nuttx/power/battery_gauge.h b/include/nuttx/power/battery_gauge.h index 8e7c89f31c..e4868e3e5b 100644 --- a/include/nuttx/power/battery_gauge.h +++ b/include/nuttx/power/battery_gauge.h @@ -263,7 +263,7 @@ FAR struct battery_gauge_dev_s *max1704x_initialize( * Name: goldfish_battery_register * * Description: - * Register a emulate battery to tyhe upper-half battery driver. + * Register a emulate battery to the upper-half battery driver. * * Input Parameters: * regs - the base address for the goldfish battery. diff --git a/include/nuttx/power/battery_ioctl.h b/include/nuttx/power/battery_ioctl.h index 939f17fdd6..ea75cf832e 100644 --- a/include/nuttx/power/battery_ioctl.h +++ b/include/nuttx/power/battery_ioctl.h @@ -99,7 +99,7 @@ enum battery_status_e enum battery_health_e { BATTERY_HEALTH_UNKNOWN = 0, /* Battery health state is not known */ - BATTERY_HEALTH_GOOD, /* Battery is in good condiction */ + BATTERY_HEALTH_GOOD, /* Battery is in good condition */ BATTERY_HEALTH_DEAD, /* Battery is dead, nothing we can do */ BATTERY_HEALTH_OVERHEAT, /* Battery is over recommended temperature */ BATTERY_HEALTH_OVERVOLTAGE, /* Battery voltage is over recommended level */ diff --git a/include/nuttx/power/pm.h b/include/nuttx/power/pm.h index 483d9276c0..1a6c3fa9bd 100644 --- a/include/nuttx/power/pm.h +++ b/include/nuttx/power/pm.h @@ -115,7 +115,7 @@ enum pm_state_e */ PM_NORMAL = 0, /* Normal full power operating mode. If the driver is in * a reduced power usage mode, it should immediately re- - * initialize for normal operatin. + * initialize for normal operation. * * PM_NORMAL may be followed by PM_IDLE. */ @@ -625,7 +625,7 @@ void pm_relax(int domain, enum pm_state_e state); * This function is called by a device driver to indicate that it is * performing meaningful activities (non-idle), needs the power at kept * last the specified level. - * And this will be timeout after time (ms), menas auto pm_relax + * And this will be timeout after time (ms), means auto pm_relax * * Input Parameters: * domain - The domain of the PM activity @@ -747,7 +747,7 @@ void pm_wakelock_relax(FAR struct pm_wakelock_s *wakelock); * This function is called by a device driver to indicate that it is * performing meaningful activities (non-idle), needs the power at kept * last the specified level. - * And this will be timeout after time (ms), menas auto pm_wakelock_relax + * And this will be timeout after time (ms), means auto pm_wakelock_relax * * Input Parameters: * wakelock - wakelock ID diff --git a/include/nuttx/power/regulator.h b/include/nuttx/power/regulator.h index 6251092d58..84b1b5b64d 100644 --- a/include/nuttx/power/regulator.h +++ b/include/nuttx/power/regulator.h @@ -116,7 +116,7 @@ struct regulator_desc_s unsigned int pulldown; /* Enable pulldown when disabled */ unsigned int pulldown_reg; /* Device register, for pulldown enable */ unsigned int pulldown_mask; /* Register mask, for pulldown enable */ - unsigned int apply_uv; /* If true, the voltage specifed (between) + unsigned int apply_uv; /* If true, the voltage specified (between) * min_uv and max_uv will be applied during * initialisation. */ diff --git a/include/nuttx/rc/lirc_dev.h b/include/nuttx/rc/lirc_dev.h index d6a3f36bba..f225a77d4d 100644 --- a/include/nuttx/rc/lirc_dev.h +++ b/include/nuttx/rc/lirc_dev.h @@ -182,7 +182,7 @@ extern "C" * Input Parameters: * lower - A pointer to an instance of lower half lirc driver. * devno - The user specifies device number, from 0. If the - * devno alerady exists, -EEXIST will be returned. + * devno already exists, -EEXIST will be returned. * * Returned Value: * OK if the driver was successfully register; A negated errno value is diff --git a/include/nuttx/reset/reset.h b/include/nuttx/reset/reset.h index a186e5c39c..cd50deafed 100644 --- a/include/nuttx/reset/reset.h +++ b/include/nuttx/reset/reset.h @@ -143,7 +143,7 @@ int reset_control_status(FAR struct reset_control *rstc); * name - The reset controller name * index - The reset controller in reset controller device * shared - Is this a shared (1), or an exclusive (0) reset_control - * acquired - flags that used to get a exculsive reset control + * acquired - flags that used to get a exclusive reset control * * Returned Value: * Return reset_control if success, others return NULL if failed @@ -310,7 +310,7 @@ reset_control_get_shared(FAR const char *name) * This is to be used to perform a list of resets for a device or power * domain in whatever order. Returns a struct reset_control or NULL errno. * Input Parameters: - * name - The controller name symble + * name - The controller name symbol * index - Index of the reset controller * * Returned Value: diff --git a/include/nuttx/rpmsg/rpmsg_port.h b/include/nuttx/rpmsg/rpmsg_port.h index ae4a16b4b3..83274a290a 100644 --- a/include/nuttx/rpmsg/rpmsg_port.h +++ b/include/nuttx/rpmsg/rpmsg_port.h @@ -160,7 +160,7 @@ rpmsg_port_spi_slave_initialize(FAR const struct rpmsg_port_config_s *cfg, * Name: rpmsg_port_uart_initialize * * Description: - * Initialze a rpmsg_port_uart device to communicate between two chips. + * Initialize a rpmsg_port_uart device to communicate between two chips. * * Input Parameters: * cfg - Configuration of buffers needed for communication. diff --git a/include/nuttx/sched.h b/include/nuttx/sched.h index 018abb6a42..c0f65f316b 100644 --- a/include/nuttx/sched.h +++ b/include/nuttx/sched.h @@ -101,7 +101,7 @@ #define TCB_FLAG_CPU_LOCKED (1 << 4) /* Bit 4: Locked to this CPU */ #define TCB_FLAG_SIGNAL_ACTION (1 << 5) /* Bit 5: In a signal handler */ #define TCB_FLAG_SYSCALL (1 << 6) /* Bit 6: In a system call */ -#define TCB_FLAG_EXIT_PROCESSING (1 << 7) /* Bit 7: Exitting */ +#define TCB_FLAG_EXIT_PROCESSING (1 << 7) /* Bit 7: Exiting */ #define TCB_FLAG_FREE_STACK (1 << 8) /* Bit 8: Free stack after exit */ #define TCB_FLAG_HEAP_CHECK (1 << 9) /* Bit 9: Heap check */ #define TCB_FLAG_HEAP_DUMP (1 << 10) /* Bit 10: Heap dump */ @@ -914,7 +914,7 @@ FAR struct tcb_s *nxsched_get_tcb(pid_t pid); * * Description: * When a task is destroyed, this function must be called to make its - * process ID available for re-use. + * process ID available for reuse. * ****************************************************************************/ diff --git a/include/nuttx/sched_note.h b/include/nuttx/sched_note.h index f1b04b57d7..4795bbfbf6 100644 --- a/include/nuttx/sched_note.h +++ b/include/nuttx/sched_note.h @@ -70,8 +70,8 @@ #define NOTE_FILTER_MODE_FLAG_ENABLE (1 << 0) /* Enable instrumentation */ #define NOTE_FILTER_MODE_FLAG_SWITCH (1 << 1) /* Enable syscall instrumentation */ #define NOTE_FILTER_MODE_FLAG_SYSCALL (1 << 2) /* Enable syscall instrumentation */ -#define NOTE_FILTER_MODE_FLAG_IRQ (1 << 3) /* Enable IRQ instrumentaiton */ -#define NOTE_FILTER_MODE_FLAG_DUMP (1 << 4) /* Enable dump instrumentaiton */ +#define NOTE_FILTER_MODE_FLAG_IRQ (1 << 3) /* Enable IRQ instrumentation */ +#define NOTE_FILTER_MODE_FLAG_DUMP (1 << 4) /* Enable dump instrumentation */ #define NOTE_FILTER_MODE_FLAG_SYSCALL_ARGS (1 << 5) /* Enable collecting syscall arguments */ /* Helper macros for syscall instrumentation filter */ diff --git a/include/nuttx/scsi.h b/include/nuttx/scsi.h index 7d9c656081..69b1920bb3 100644 --- a/include/nuttx/scsi.h +++ b/include/nuttx/scsi.h @@ -337,9 +337,9 @@ #define SCSI_KCQUA_PARAMETERSCHANGED 0x062a00 /* Unit Attention - parameters changed */ #define SCSI_KCQUA_MODEPARAMETERSCHANGED 0x062a01 /* Unit Attention - mode parameters changed */ #define SCSI_KCQUA_LOGSELECTPARMSCHANGED 0x062a02 /* Unit Attention - log select parms changed */ -#define SCSI_KCQUA_RESERVATIONSPREEMPTED 0x062a03 /* Unit Attention - Reservations pre-empted */ +#define SCSI_KCQUA_RESERVATIONSPREEMPTED 0x062a03 /* Unit Attention - Reservations preempted */ #define SCSI_KCQUA_RESERVATIONSRELEASED 0x062a04 /* Unit Attention - Reservations released */ -#define SCSI_KCQUA_REGISTRATIONSPREEMPTED 0x062a05 /* Unit Attention - Registrations pre-empted */ +#define SCSI_KCQUA_REGISTRATIONSPREEMPTED 0x062a05 /* Unit Attention - Registrations preempted */ #define SCSI_KCQUA_COMMANDSCLEARED 0x062f00 /* Unit Attention - commands cleared by another initiator */ #define SCSI_KCQUA_OPERATINGCONDITIONSCHANGED 0x063f00 /* Unit Attention - target operating conditions have changed */ #define SCSI_KCQUA_MICROCODECHANGED 0x063f01 /* Unit Attention - microcode changed */ diff --git a/include/nuttx/sdio.h b/include/nuttx/sdio.h index aff35af838..23a2550ef0 100644 --- a/include/nuttx/sdio.h +++ b/include/nuttx/sdio.h @@ -699,7 +699,7 @@ * * Returned Value: * Number of bytes sent on success; a negated errno on failure. Here a - * failure means only a faiure to obtain the requested response (due to + * failure means only a failure to obtain the requested response (due to * transport problem -- timeout, CRC, etc.). The implementation only * assures that the response is returned intacta and does not check errors * within the response itself. diff --git a/include/nuttx/sdio_slave.h b/include/nuttx/sdio_slave.h index a96440ec75..8c0e8c3771 100644 --- a/include/nuttx/sdio_slave.h +++ b/include/nuttx/sdio_slave.h @@ -41,11 +41,11 @@ * Description: * Set callback to hardware, when the buffer have received or send * completed, hardware should call the callback to tell user transfer - * finshed. + * finished. * * Input Parameters: * dev - An instance of the SDIO Slave device interface - * callback - User defined that recived transfer finshed + * callback - User defined that received transfer finished * arg - The context for setcallback * * Returned Value: @@ -122,7 +122,7 @@ * recvbuffer/sendbuffer again. * * Input Parameters: - * recv - true on recive finshed; false on send finshed. + * recv - true on receive finished; false on send finished. * buf - Address of the transfer buffer. * result - negated errno on failure; the size received. * arg - the context of setcallback. diff --git a/include/nuttx/sensors/gnss.h b/include/nuttx/sensors/gnss.h index 5c1bfe8158..f26f3dd7e4 100644 --- a/include/nuttx/sensors/gnss.h +++ b/include/nuttx/sensors/gnss.h @@ -163,7 +163,7 @@ struct gnss_lowerhalf_s /* Lower half driver pushes raw data by calling this function. * It is provided by upper half driver to lower half driver, - * if paramenter is_nmea is true, the data includes nmea message. + * if parameter is_nmea is true, the data includes nmea message. */ gnss_push_data_t push_data; @@ -207,7 +207,7 @@ extern "C" * instance is bound to the GNSS driver and must persist as long * as the driver persists. * devno - The user specifies which device of this type, from 0. If the - * devno alerady exists, -EEXIST will be returned. + * devno already exists, -EEXIST will be returned. * nbuffer - The number of events that the circular buffer can hold. * count - The array size of nbuffer. * diff --git a/include/nuttx/sensors/lis2mdl.h b/include/nuttx/sensors/lis2mdl.h index 4701b80f0b..ce7bc85bd4 100644 --- a/include/nuttx/sensors/lis2mdl.h +++ b/include/nuttx/sensors/lis2mdl.h @@ -52,7 +52,7 @@ typedef int (*lis2mdl_attach)(xcpt_t, FAR void *arg); * devno - The device number to use for the topic (i.e. /dev/mag0) * attach - A function which is called by this driver to attach the * LIS2MDL interrupt handler to an IRQ. Pass NULL to operate - * in polling mode. This function should return 0 on succes + * in polling mode. This function should return 0 on success * and a negated error code otherwise. * * Returned Value: diff --git a/include/nuttx/sensors/ltc4151.h b/include/nuttx/sensors/ltc4151.h index 25e2716e66..90a79c3422 100644 --- a/include/nuttx/sensors/ltc4151.h +++ b/include/nuttx/sensors/ltc4151.h @@ -59,7 +59,7 @@ #define LTC4151_VALUE_MSB_MASK 0x00ff #define LTC4151_VALUE_LSB_MASK 0x0f00 -/* NOTE: When meassurement values are read, they are return as b16_t, fixed +/* NOTE: When measurement values are read, they are return as b16_t, fixed * precision integer values (see include/fixedmath.h). */ diff --git a/include/nuttx/sensors/qencoder.h b/include/nuttx/sensors/qencoder.h index 9431ccbcaa..6c78d224ee 100644 --- a/include/nuttx/sensors/qencoder.h +++ b/include/nuttx/sensors/qencoder.h @@ -59,7 +59,7 @@ * QEIOC_GETINDEX - Get the index position and count of the encoder. * The structure also contains current position so QEIOC_POSITION * is not required when QEIOC_GETINDEX is used. - * Argment: qe_index_s structure (refer below) + * Argument: qe_index_s structure (refer below) */ #define QEIOC_POSITION _QEIOC(0x0001) /* Arg: int32_t* pointer */ @@ -147,14 +147,14 @@ struct qe_ops_s /* Structure qe_index_s is used for QEIOC_GETINDEX call. This call returns * current encoder position, the last index position and number of index - * occurances. + * occurrences. */ struct qe_index_s { int32_t qenc_pos; /* Qencoder actual position */ int32_t indx_pos; /* Index last position */ - int16_t indx_cnt; /* Number of index occurances */ + int16_t indx_cnt; /* Number of index occurrences */ }; /* This is the interface between the lower half quadrature encoder driver diff --git a/include/nuttx/sensors/sensor.h b/include/nuttx/sensors/sensor.h index 77b7805670..f90dc1181b 100644 --- a/include/nuttx/sensors/sensor.h +++ b/include/nuttx/sensors/sensor.h @@ -654,7 +654,7 @@ void sensor_remap_vector_raw16(FAR const int16_t *in, FAR int16_t *out, * instance is bound to the sensor driver and must persist as long * as the driver persists. * devno - The user specifies which device of this type, from 0. If the - * devno alerady exists, -EEXIST will be returned. + * devno already exists, -EEXIST will be returned. * * Returned Value: * OK if the driver was successfully register; A negated errno value is @@ -732,7 +732,7 @@ void sensor_custom_unregister(FAR struct sensor_lowerhalf_s *dev, * Description: * This function registers usensor character node "/dev/usensor", so that * application can register user sensor by this node. The node will - * manager all user sensor in this character dirver. + * manage all user sensor in this character driver. * ****************************************************************************/ @@ -784,7 +784,7 @@ void sensor_rpmsg_unregister(FAR struct sensor_lowerhalf_s *lower); * * Description: * This function initializes the context of sensor rpmsg, registers - * rpmsg callback and prepares enviroment to intercat with remote sensor. + * rpmsg callback and prepares environment to interact with remote sensor. * * Returned Value: * OK on success; A negated errno value is returned on any failure. diff --git a/include/nuttx/serial/uart_16550.h b/include/nuttx/serial/uart_16550.h index 9acd75a87a..7c4af0ce24 100644 --- a/include/nuttx/serial/uart_16550.h +++ b/include/nuttx/serial/uart_16550.h @@ -389,7 +389,7 @@ struct u16550_s * * Description: * Performs the low level UART initialization early in debug so that the - * serial console will be available during bootup. This must be called + * serial console will be available during boot up. This must be called * before uart_serialinit. * * NOTE: Configuration of the CONSOLE UART was performed by uart_lowsetup() diff --git a/include/nuttx/serial/uart_cmsdk.h b/include/nuttx/serial/uart_cmsdk.h index 4fd7124a1c..827556d395 100644 --- a/include/nuttx/serial/uart_cmsdk.h +++ b/include/nuttx/serial/uart_cmsdk.h @@ -94,7 +94,7 @@ * * Description: * Performs the low level UART initialization early in debug so that the - * serial console will be available during bootup. This must be called + * serial console will be available during boot up. This must be called * before uart_serialinit. * ****************************************************************************/ diff --git a/include/nuttx/spi/slave.h b/include/nuttx/spi/slave.h index 962630f072..bdd5c48d95 100644 --- a/include/nuttx/spi/slave.h +++ b/include/nuttx/spi/slave.h @@ -252,7 +252,7 @@ * * Input Parameters: * dev - SPI Slave device interface instance - * data - Pointer to the data buffer pointer to be shifed out. + * data - Pointer to the data buffer pointer to be shifted out. * The device will set the data buffer pointer to the actual data * * Returned Value: diff --git a/include/nuttx/spinlock.h b/include/nuttx/spinlock.h index a637f2a6ed..583994a7ef 100644 --- a/include/nuttx/spinlock.h +++ b/include/nuttx/spinlock.h @@ -662,8 +662,9 @@ void spin_unlock_irqrestore(FAR volatile spinlock_t *lock, irqstate_t flags) * * This implementation is non-reentrant and set a bit of lock. * - * The priority of reader is higher than writter if a reader hold the - * lock, a new reader can get its lock but writer can't get this lock. + * The reader's priority is higher than the writer's priority. If a reader + * holds the lock, a new reader can get its lock but a writer can't get this + * lock. * * Input Parameters: * lock - A reference to the spinlock object to lock. @@ -706,8 +707,9 @@ static inline_function void read_lock(FAR volatile rwlock_t *lock) * * This implementation is non-reentrant and set a bit of lock. * - * The priority of reader is higher than writter if a reader hold the - * lock, a new reader can get its lock but writer can't get this lock. + * The reader's priority is higher than the writer's priority. If a reader + * holds the lock, a new reader can get its lock but a writer can't get this + * lock. * * Input Parameters: * lock - A reference to the spinlock object to lock. @@ -778,8 +780,9 @@ static inline_function void read_unlock(FAR volatile rwlock_t *lock) * This implementation is non-reentrant and set all bit on lock to avoid * readers and writers. * - * The priority of reader is higher than writter if a reader hold the - * lock, a new reader can get its lock but writer can't get this lock. + * The reader's priority is higher than the writer's priority. If a reader + * holds the lock, a new reader can get its lock but a writer can't get this + * lock. * * Input Parameters: * lock - A reference to the spinlock object to lock. @@ -816,8 +819,9 @@ static inline_function void write_lock(FAR volatile rwlock_t *lock) * This implementation is non-reentrant and set all bit on lock to avoid * readers and writers. * - * The priority of reader is higher than writter if a reader hold the - * lock, a new reader can get its lock but writer can't get this lock. + * The reader's priority is higher than the writer's priority. If a reader + * holds the lock, a new reader can get its lock but a writer can't get this + * lock. * * Input Parameters: * lock - A reference to the spinlock object to lock. diff --git a/include/nuttx/timers/capture.h b/include/nuttx/timers/capture.h index c50c1c325c..2b72b22d26 100644 --- a/include/nuttx/timers/capture.h +++ b/include/nuttx/timers/capture.h @@ -46,8 +46,8 @@ #define CAPIOC_DUTYCYCLE _CAPIOC(1) /* Command: CAPIOC_FREQUENCE - * Description: Get the pulse frequence from the capture. - * Arguments: int32_t pointer to the location to return the frequence. + * Description: Get the pulse frequency from the capture. + * Arguments: int32_t pointer to the location to return the frequency. * Return: Zero (OK) on success. Minus one will be returned on failure * with the errno value set appropriately. */ @@ -64,7 +64,7 @@ #define CAPIOC_EDGES _CAPIOC(3) /* Command: CAPIOC_ALL - * Description: Get the pwm duty, pulse frequence, pwm edges, from + * Description: Get the pwm duty, pulse frequency, pwm edges, from * the capture. * Arguments: A reference to struct cap_all_s. * Return: Zero (OK) on success. Minus one will be returned on failure @@ -148,7 +148,7 @@ struct cap_ops_s CODE int (*getduty)(FAR struct cap_lowerhalf_s *lower, FAR uint8_t *duty); - /* Get the result pwm capture frequence value */ + /* Get the result pwm capture frequency value */ CODE int (*getfreq)(FAR struct cap_lowerhalf_s *lower, FAR uint32_t *freq); diff --git a/include/nuttx/timers/pwm.h b/include/nuttx/timers/pwm.h index bab35ef912..f59df5e3ed 100644 --- a/include/nuttx/timers/pwm.h +++ b/include/nuttx/timers/pwm.h @@ -143,11 +143,11 @@ /* PWM disabled channel polarity ********************************************/ /* The output of the PWM disabled channel may depend on the platform - * dependant peripheral. These helper definitions can be used for setting + * dependent peripheral. These helper definitions can be used for setting * the disabled channel's output state. */ -#define PWM_DCPOL_NDEF 0 /* Not defined, the default output state is arch dependant */ +#define PWM_DCPOL_NDEF 0 /* Not defined, the default output state is arch dependent */ #define PWM_DCPOL_LOW 1 /* Logical zero */ #define PWM_DCPOL_HIGH 2 /* Logical one */ diff --git a/include/nuttx/timers/timer.h b/include/nuttx/timers/timer.h index 5559262d2c..3b055db007 100644 --- a/include/nuttx/timers/timer.h +++ b/include/nuttx/timers/timer.h @@ -412,7 +412,7 @@ FAR void *timer_register(FAR const char *path, void timer_unregister(FAR void *handle); /**************************************************************************** - * Kernel internal interfaces. Thse may not be used by application logic + * Kernel internal interfaces. These may not be used by application logic. ****************************************************************************/ /**************************************************************************** diff --git a/include/nuttx/usb/audio.h b/include/nuttx/usb/audio.h index d3cbddbab0..77cd6b5073 100644 --- a/include/nuttx/usb/audio.h +++ b/include/nuttx/usb/audio.h @@ -852,7 +852,7 @@ struct adc_srconverter_desc_s uint8_t sr_srcid; /* 4: ID of unit/terminal to which unit is connected */ uint8_t sr_csrcinid; /* 5: ID of clock entity to which unit input is connected */ uint8_t sr_csrcoutid; /* 6: ID of clock entity to which unit output is connected */ - uint8_t sr_converter; /* 7: String index to the name fo the SRC unit */ + uint8_t sr_converter; /* 7: String index to the name for the SRC unit */ }; #define USB_SIZEOF_ADC_SRCCONVERTER_DESC (8) diff --git a/include/nuttx/usb/ehci.h b/include/nuttx/usb/ehci.h index 95c80e9cb0..51d5693d58 100644 --- a/include/nuttx/usb/ehci.h +++ b/include/nuttx/usb/ehci.h @@ -439,7 +439,7 @@ /* Bits 3-4: zero */ #define PFL_MASK (0xffffffe0) /* Bits 5-31: Frame List Link Pointer */ -/* Aysnchronous List Queue Head Pointer. +/* Asynchronous List Queue Head Pointer. * Paragraph 3.2. Circular list of queue heads */ @@ -687,7 +687,7 @@ #define QH_EPCHAR_DEVADDR_SHIFT (0) /* Bitx 0-6: Device Address */ #define QH_EPCHAR_DEVADDR_MASK (0x7f << QH_EPCHAR_DEVADDR_SHIFT) -#define QH_EPCHAR_I (1 << 7) /* Bit 7: Inactivate on Next Transaction */ +#define QH_EPCHAR_I (1 << 7) /* Bit 7: Deactivate on Next Transaction */ #define QH_EPCHAR_ENDPT_SHIFT (8) /* Bitx 8-11: Endpoint Number */ #define QH_EPCHAR_ENDPT_MASK (15 << QH_EPCHAR_ENDPT_SHIFT) #define QH_EPCHAR_EPS_SHIFT (12) /* Bitx 12-13: Endpoint Speed */ @@ -881,7 +881,7 @@ struct ehci_hcor_s /* USB2 Debug Port Register Interface. * This register block is normally found via the PCI capabalities. - * In non-PCI implementions, you need apriori information about the + * In non-PCI implementations, you need apriori information about the * location of these registers. */ @@ -901,7 +901,7 @@ struct ehci_debug_s * Paragraph 3.1. An array of pointers. */ -/* Aysnchronous List Queue Head Pointer. +/* Asynchronous List Queue Head Pointer. * Paragraph 3.2. Circular list of queue heads */ diff --git a/include/nuttx/usb/usbdev.h b/include/nuttx/usb/usbdev.h index 132e24c432..47cf9fe44a 100644 --- a/include/nuttx/usb/usbdev.h +++ b/include/nuttx/usb/usbdev.h @@ -45,7 +45,7 @@ /* Endpoint helpers *********************************************************/ /* Configure endpoint, making it usable. - * The class driver may deallocate or re-use the 'desc' structure after + * The class driver may deallocate or reuse the 'desc' structure after * returning: * * ep - the struct usbdev_ep_s instance obtained from allocep() diff --git a/include/nuttx/usb/usbdev_trace.h b/include/nuttx/usb/usbdev_trace.h index 487c1713c0..eb01d78e85 100644 --- a/include/nuttx/usb/usbdev_trace.h +++ b/include/nuttx/usb/usbdev_trace.h @@ -406,7 +406,7 @@ struct usbtrace_s struct trace_msg_t { uint16_t id; /* 8-bit ID value */ - FAR const char *str; /* String assoiciated with the ID */ + FAR const char *str; /* String associated with the ID */ }; #endif diff --git a/include/nuttx/usb/usbhost.h b/include/nuttx/usb/usbhost.h index e60b45c93f..d056299408 100644 --- a/include/nuttx/usb/usbhost.h +++ b/include/nuttx/usb/usbhost.h @@ -919,7 +919,7 @@ struct usbhost_driver_s #endif /* Cancel any pending synchronous or asynchronous transfer on an - * endpoint + * endpoint. */ CODE int (*cancel)(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep); diff --git a/include/nuttx/video/fb.h b/include/nuttx/video/fb.h index 28492db445..d7c3199518 100644 --- a/include/nuttx/video/fb.h +++ b/include/nuttx/video/fb.h @@ -192,7 +192,7 @@ #define FB_NO_OVERLAY -1 #ifdef CONFIG_FB_OVERLAY -# define FB_ACCL_TRANSP 0x01 /* Hardware tranparency support */ +# define FB_ACCL_TRANSP 0x01 /* Hardware transparency support */ # define FB_ACCL_CHROMA 0x02 /* Hardware chromakey support */ # define FB_ACCL_COLOR 0x04 /* Hardware color support */ # define FB_ACCL_AREA 0x08 /* Hardware support area selection */ @@ -332,7 +332,7 @@ #define FB_AUX_TEXT_MDA 0 /* Monochrome text */ #define FB_AUX_TEXT_CGA 1 /* CGA/EGA/VGA Color text */ #define FB_AUX_TEXT_S3_MMIO 2 /* S3 MMIO fasttext */ -#define FB_AUX_TEXT_MGA_STEP16 3 /* MGA Millenium I: text, attr, */ +#define FB_AUX_TEXT_MGA_STEP16 3 /* MGA Millennium I: text, attr, */ /* 14 reserved bytes */ #define FB_AUX_TEXT_MGA_STEP8 4 /* other MGAs: text, attr, */ /* 6 reserved bytes */ @@ -377,10 +377,10 @@ #define FB_ACCEL_SUN_LEO 13 /* Sun leo/zx */ #define FB_ACCEL_IMS_TWINTURBO 14 /* IMS Twin Turbo */ #define FB_ACCEL_3DLABS_PERMEDIA2 15 /* 3Dlabs Permedia 2 */ -#define FB_ACCEL_MATROX_MGA2064W 16 /* Matrox MGA2064W (Millenium) */ +#define FB_ACCEL_MATROX_MGA2064W 16 /* Matrox MGA2064W (Millennium) */ #define FB_ACCEL_MATROX_MGA1064SG 17 /* Matrox MGA1064SG (Mystique) */ -#define FB_ACCEL_MATROX_MGA2164W 18 /* Matrox MGA2164W (Millenium II) */ -#define FB_ACCEL_MATROX_MGA2164W_AGP 19 /* Matrox MGA2164W (Millenium II) */ +#define FB_ACCEL_MATROX_MGA2164W 18 /* Matrox MGA2164W (Millennium II) */ +#define FB_ACCEL_MATROX_MGA2164W_AGP 19 /* Matrox MGA2164W (Millennium II) */ #define FB_ACCEL_MATROX_MGAG100 20 /* Matrox G100 (Productiva G100) */ #define FB_ACCEL_MATROX_MGAG200 21 /* Matrox G200 (Myst, Mill, ...) */ #define FB_ACCEL_SUN_CG14 22 /* Sun cgfourteen */ @@ -901,7 +901,7 @@ struct fb_fix_screeninfo * * For pseudocolor: offset and length should be the same for all color * components. Offset specifies the position of the least significant bit - * of the pallette index in a pixel value. Length indicates the number + * of the palette index in a pixel value. Length indicates the number * of available palette entries (i.e. # of entries = 1 << length). */ diff --git a/include/nuttx/video/mipi_dsi.h b/include/nuttx/video/mipi_dsi.h index 242f623181..7d5f6819ed 100644 --- a/include/nuttx/video/mipi_dsi.h +++ b/include/nuttx/video/mipi_dsi.h @@ -124,7 +124,7 @@ struct mipi_dsi_msg size_t tx_len; /* Length of tx_buf */ FAR const void *tx_buf; /* Data to be written */ - size_t rx_len; /* Lenght of rx_buf */ + size_t rx_len; /* Length of rx_buf */ FAR void *rx_buf; /* Data to be read, or NULL */ }; @@ -152,7 +152,7 @@ struct mipi_dsi_packet * packets. * * Note that typically DSI packet transmission is atomic, so the .transfer() - * function will seldomly return anything other than the number of bytes + * function will seldom return anything other than the number of bytes * contained in the transmit buffer on success. * * Also note that those callbacks can be called no matter the state the @@ -199,10 +199,10 @@ struct mipi_dsi_device uint8_t format; /* Pixel formal */ uint32_t mode_flags; /* Dsi operate mode flag */ uint32_t hs_rate; /* Maximum lane frequency for high speed - * mode in hertz, this shoud be set + * mode in hertz, this should be set * to the real limits of the hardware. */ uint32_t lp_rate; /* Maximum lane frequency for low power - * mode in hertz, this shoud be set + * mode in hertz, this should be set * to the real limits of the hardware. */ }; @@ -388,7 +388,7 @@ int mipi_dsi_detach(FAR struct mipi_dsi_device *device); * msg - Message to transfer * * Returned Value: - * The number of bytes successfully transfered or a negative error code on + * The number of bytes successfully transferred or a negative error code on * failure. * ****************************************************************************/ diff --git a/include/nuttx/wireless/bluetooth/bt_ioctl.h b/include/nuttx/wireless/bluetooth/bt_ioctl.h index f3ccf07914..3fbeb9ce84 100644 --- a/include/nuttx/wireless/bluetooth/bt_ioctl.h +++ b/include/nuttx/wireless/bluetooth/bt_ioctl.h @@ -183,7 +183,7 @@ #define SIOCBTGATTRD _BLUETOOTHIOC(18) #define SIOCBTGATTWR _BLUETOOTHIOC(19) -/* Connect/diconnect from a peer */ +/* Connect/disconnect from a peer */ #define SIOCBTCONNECT _BLUETOOTHIOC(24) #define SIOCBTDISCONNECT _BLUETOOTHIOC(25) diff --git a/include/nuttx/wireless/cellular/cellular.h b/include/nuttx/wireless/cellular/cellular.h index cbbbbe16e9..fa33a334c7 100644 --- a/include/nuttx/wireless/cellular/cellular.h +++ b/include/nuttx/wireless/cellular/cellular.h @@ -41,7 +41,7 @@ /* Sizing parameters */ -#define IFCELLDEVPARAMSIZ 136 /* Big enough to store cellular net paramters */ +#define IFCELLDEVPARAMSIZ 136 /* Big enough to store cellular net parameters */ /* Network Driver IOCTL Commands ********************************************/ diff --git a/include/nuttx/wireless/ieee80211/ieee80211.h b/include/nuttx/wireless/ieee80211/ieee80211.h index 9931c8092d..89f374c422 100644 --- a/include/nuttx/wireless/ieee80211/ieee80211.h +++ b/include/nuttx/wireless/ieee80211/ieee80211.h @@ -968,7 +968,7 @@ struct ieee80211_sec_chan_offs_ie /* struct ieee80211_mesh_chansw_params_ie - mesh channel switch parameters IE * - * This structure represents the "Mesh Channel Switch Paramters element" + * This structure represents the "Mesh Channel Switch Parameters element" */ struct ieee80211_mesh_chansw_params_ie @@ -1932,7 +1932,7 @@ struct ieee80211_ht_operation * If this field is 0 this value should not be used to * consider the highest TX data rate supported. * The top 2 bits of this field are reserved, the - * 3rd bit from the top indiciates VHT Extended NSS BW + * 3rd bit from the top indicates VHT Extended NSS BW * Capability. */ diff --git a/include/nuttx/wireless/ieee802154/ieee802154_mac.h b/include/nuttx/wireless/ieee802154/ieee802154_mac.h index 220ff8e91a..e07210f39f 100644 --- a/include/nuttx/wireless/ieee802154/ieee802154_mac.h +++ b/include/nuttx/wireless/ieee802154/ieee802154_mac.h @@ -1137,7 +1137,7 @@ struct ieee802154_disassoc_conf_s enum ieee802154_status_e status; - /* Address of device either requesting or being intructed to disassociate */ + /* Address of device either requesting or being instructed to disassociate */ struct ieee802154_addr_s dev_addr; }; diff --git a/include/nuttx/wireless/lpwan/sx126x.h b/include/nuttx/wireless/lpwan/sx126x.h index e7c6792004..8abd9faa5d 100644 --- a/include/nuttx/wireless/lpwan/sx126x.h +++ b/include/nuttx/wireless/lpwan/sx126x.h @@ -40,7 +40,7 @@ #include /**************************************************************************** - * Defintions + * Definitions ****************************************************************************/ #define SX126X_RX_PAYLOAD_SIZE 0xff @@ -346,7 +346,7 @@ struct sx126x_lower_s /* This controls which DIO reacts to interrupts * Depended on the pinout of the board / module. * Note that DIO 2 and DIO 3 can be already in use - * by the module and setting them might intefere + * by the module and setting them might interfere * with the operation or even damage them. */ diff --git a/include/nuttx/wireless/lte/lte.h b/include/nuttx/wireless/lte/lte.h index 4cb0be2d5e..3e1c19acf0 100644 --- a/include/nuttx/wireless/lte/lte.h +++ b/include/nuttx/wireless/lte/lte.h @@ -499,25 +499,25 @@ #define LTE_SIMINFO_GID_LEN (128) /* Maximum length of GID */ /* Maximum length of phone number - * that includes a null terminater + * that includes a null terminator */ #define LTE_PHONENO_LEN (41) /* Maximum length of IMEI - * that includes a null terminater + * that includes a null terminator */ #define LTE_IMEI_LEN (16) /* Maximum length of network operator - * that includes a null terminater + * that includes a null terminator */ #define LTE_OPERATOR_LEN (17) /* Maximum length of IMSI - * that includes a null terminater + * that includes a null terminator */ #define LTE_IMSI_LEN (LTE_SIMINFO_IMSI_LEN + 1) @@ -934,7 +934,7 @@ typedef struct lte_edrx_setting bool enable; /* eDRX cycle. - * This variable is not vaild when LTE_EDRX_ACTTYPE_NOTUSE + * This variable is not valid when LTE_EDRX_ACTTYPE_NOTUSE * is set to act_type. * Definitions are below: * - LTE_EDRX_CYC_512 @@ -956,7 +956,7 @@ typedef struct lte_edrx_setting uint32_t edrx_cycle; /* Paging time window. - * This variable is not vaild when LTE_EDRX_ACTTYPE_NOTUSE + * This variable is not valid when LTE_EDRX_ACTTYPE_NOTUSE * is set to act_type. * Definitions are below: * - LTE_EDRX_PTW_128 @@ -1150,7 +1150,7 @@ typedef struct lte_pdn lte_ipaddr_t address[LTE_PDN_IPADDR_MAX_COUNT]; - /* IMS registored status. + /* IMS registered status. * This is valid when LTE_APN_TYPE_IMS is set in apn_type. * Definition is as below. * - LTE_IMS_NOT_REGISTERED @@ -1243,7 +1243,7 @@ typedef struct lte_netinfo lte_nw_err_info_t nw_err; - /* Number of PDN status informations. + /* Number of PDN status information. * The maximum number of PDNs is LTE_SESSION_ID_MAX. */ diff --git a/include/semaphore.h b/include/semaphore.h index 6546e7a61e..75df214577 100644 --- a/include/semaphore.h +++ b/include/semaphore.h @@ -71,8 +71,8 @@ struct semholder_s FAR struct semholder_s *flink; /* List of semaphore's holder */ #endif FAR struct semholder_s *tlink; /* List of task held semaphores */ - FAR struct sem_s *sem; /* This corresponding semaphore */ - FAR struct tcb_s *htcb; /* This corresponding TCB */ + FAR struct sem_s *sem; /* The corresponding semaphore */ + FAR struct tcb_s *htcb; /* The corresponding TCB */ int32_t counts; /* Number of counts owned by this holder */ }; diff --git a/include/sys/poll.h b/include/sys/poll.h index df1c4697fd..23690e8c13 100644 --- a/include/sys/poll.h +++ b/include/sys/poll.h @@ -66,8 +66,8 @@ * * POLLALWAYS * Indicate that should ALWAYS call the poll callback whether the - * drvier notified the user expected event or not, and this value is - * used inside kernal only (events only). + * driver notified the user expected event or not, and this value is + * used inside kernel only (events only). */ #define POLLIN (0x01) /* NuttX does not make priority distinctions */ diff --git a/include/sys/videoio.h b/include/sys/videoio.h index 5e44ae90b2..92823f2d0b 100644 --- a/include/sys/videoio.h +++ b/include/sys/videoio.h @@ -1344,7 +1344,7 @@ struct v4l2_ext_controls struct v4s_ext_controls_scene { - enum v4l2_scene_mode mode; /* Scene mode to be controled */ + enum v4l2_scene_mode mode; /* Scene mode to be controlled */ struct v4l2_ext_controls control; /* Same as VIDIOC_S_EXT_CTRLS */ }; diff --git a/libs/libc/aio/aio_error.c b/libs/libc/aio/aio_error.c index 067bdb7bad..8f3a856b22 100644 --- a/libs/libc/aio/aio_error.c +++ b/libs/libc/aio/aio_error.c @@ -63,7 +63,7 @@ * * Description: * The aio_error() function returns the error status associated with the - * aiocb structure referenced by the aiocbp argument. The error status fo + * aiocb structure referenced by the aiocbp argument. The error status for * an asynchronous I/O operation is the errno value that would be set by * the corresponding read(), write(), fdatasync(), or fsync() operation. If * the operation has not yet completed, then the error status will be equal diff --git a/libs/libc/ctype/lib_ctype.c b/libs/libc/ctype/lib_ctype.c index d369a33f31..29ab6c66bb 100644 --- a/libs/libc/ctype/lib_ctype.c +++ b/libs/libc/ctype/lib_ctype.c @@ -34,7 +34,7 @@ #ifndef CONFIG_LIBCXXTOOLCHAIN -/* MSVC seems to conflict with theses macro if defined in the public area. +/* MSVC seems to conflict with these macros if defined in the public area. * As such, they are defined in the private section to let NuttX build */ diff --git a/libs/libc/elf/elf_depend.c b/libs/libc/elf/elf_depend.c index 128334107e..79c3ebb200 100644 --- a/libs/libc/elf/elf_depend.c +++ b/libs/libc/elf/elf_depend.c @@ -69,7 +69,7 @@ int libelf_depend(FAR struct module_s *importer, * exporting module. In that case, the module would already be in the * list of dependencies. * - * The list dependency list is a a dumb, upacked array of pointers. This + * The list dependency list is a a dumb, unpacked array of pointers. This * should not be too inefficient if the number of CONFIG_LIBC_ELF_MAXDEPEND * is small. Otherwise, a more dynamic data structure would be in order. */ @@ -157,7 +157,7 @@ int libelf_undepend(FAR struct module_s *importer) DEBUGASSERT(importer != NULL && importer->dependents == 0); /* Decrement the dependency count on each of exporters of symbols used by - * this importer module. This is an upacked array of pointers. This + * this importer module. This is an unpacked array of pointers. This * should not be too inefficient if the number of CONFIG_LIBC_ELF_MAXDEPEND * is small. Otherwise, a more dynamic data structure would be in order. */ diff --git a/libs/libc/elf/elf_loadhdrs.c b/libs/libc/elf/elf_loadhdrs.c index a433efddb0..1aea7643a8 100644 --- a/libs/libc/elf/elf_loadhdrs.c +++ b/libs/libc/elf/elf_loadhdrs.c @@ -109,7 +109,7 @@ int libelf_loadhdrs(FAR struct mod_loadinfo_s *loadinfo) (size_t)loadinfo->ehdr.e_phnum; if (loadinfo->ehdr.e_phoff + phdrsize > loadinfo->filelen) { - berr("ERROR: Insufficent space for program header table\n"); + berr("ERROR: Insufficient space for program header table\n"); return -ESPIPE; } diff --git a/libs/libc/gdbstub/lib_gdbstub.c b/libs/libc/gdbstub/lib_gdbstub.c index ca72821c98..362735fe5d 100644 --- a/libs/libc/gdbstub/lib_gdbstub.c +++ b/libs/libc/gdbstub/lib_gdbstub.c @@ -1043,7 +1043,7 @@ static void gdb_get_registers(FAR struct gdb_state_s *state) * Zero on success. * Negative value on error. * - * Note: Comand Format: g. + * Note: Command Format: g. * Response Format: xxxxxxxxyyyyyyyyy... ****************************************************************************/ @@ -1079,7 +1079,7 @@ static int gdb_read_registers(FAR struct gdb_state_s *state) * Negative value on error. * * Note: This function is not really change the register values. - * Comand Format: Gxxxxxxxxyyyyyyyyy + * Command Format: Gxxxxxxxxyyyyyyyyy * Response Format: OK ****************************************************************************/ @@ -1111,7 +1111,7 @@ static int gdb_write_registers(FAR struct gdb_state_s *state) * Zero on success. * Negative value on error. * - * Note: Comand Format: Pn. + * Note: Command Format: Pn. * Response Format: OK ****************************************************************************/ @@ -1158,7 +1158,7 @@ static int gdb_read_register(FAR struct gdb_state_s *state) * The number of bytes read if successful. * Negative value on error. * - * Note: Comand Format: mAAAAAAAAA,LLLLLLLL + * Note: Command Format: mAAAAAAAAA,LLLLLLLL * Response Format: XXXXXXXXYYYYYYYYY... ****************************************************************************/ @@ -1201,7 +1201,7 @@ static int gdb_read_memory(FAR struct gdb_state_s *state) * The number of bytes read if successful. * Negative value on error. * - * Note : Comand Format: MAAAAAAAAA,LLLLLLLL + * Note : Command Format: MAAAAAAAAA,LLLLLLLL * Response Format: bXXXXXXXXYYYYYYYYY... ****************************************************************************/ @@ -1244,7 +1244,7 @@ static int gdb_read_bin_memory(FAR struct gdb_state_s *state) * The number of bytes written if successful. * Negative value on error. * - * Note : Comand Format: MAAAAAAAAA,LLLLLLLL:XXXXXXXXX... + * Note : Command Format: MAAAAAAAAA,LLLLLLLL:XXXXXXXXX... * Response Format: OK ****************************************************************************/ @@ -1285,7 +1285,7 @@ static int gdb_write_memory(FAR struct gdb_state_s *state) * The number of bytes written if successful. * Negative value on error. * - * Note : Comand Format: XAAAAAAAAA,LLLLLLLL:XXXXXXXXX... + * Note : Command Format: XAAAAAAAAA,LLLLLLLL:XXXXXXXXX... * Response Format: OK ****************************************************************************/ @@ -1353,7 +1353,7 @@ static void gdb_get_thread(FAR struct tcb_s *tcb, FAR void *arg) * 0 if successful. * Negative value on error. * - * Note : Comand Format: qSTRING + * Note : Command Format: qSTRING * STRING:is the query string. ****************************************************************************/ @@ -1476,7 +1476,7 @@ static int gdb_query(FAR struct gdb_state_s *state) * 0 if successful. * Negative value on error. * - * Note : Comand Format: T + * Note : Command Format: T * id:is the thread id. * Response Format: OK ****************************************************************************/ @@ -1519,7 +1519,7 @@ static int gdb_is_thread_active(FAR struct gdb_state_s *state) * 0 if successful. * Negative value on error. * - * Note : Comand Format: Hg + * Note : Command Format: Hg * Hc- * Response Format: OK ****************************************************************************/ @@ -1718,7 +1718,7 @@ static void gdb_debugpoint_callback(int type, FAR void *addr, * 0 if successful. * Negative value on error. * - * Note : Comand Format: Z/z type,addr,length + * Note : Command Format: Z/z type,addr,length * Response Format: OK * Z is set breakpoint. * z is clear breakpoint. @@ -1820,7 +1820,7 @@ static int gdb_debugpoint(FAR struct gdb_state_s *state, bool enable) * 0 if successful. * Negative value on error. * - * Note : Comand Format: s + * Note : Command Format: s * Response Format: OK * ****************************************************************************/ @@ -1851,7 +1851,7 @@ static int gdb_step(FAR struct gdb_state_s *state) * 0 if successful. * Negative value on error. * - * Note : Comand Format: c + * Note : Command Format: c * Response Format: OK * ****************************************************************************/ diff --git a/libs/libc/machine/arm64/gnu/arch_strcmp.S b/libs/libc/machine/arm64/gnu/arch_strcmp.S index b1febfc051..4131cc326e 100644 --- a/libs/libc/machine/arm64/gnu/arch_strcmp.S +++ b/libs/libc/machine/arm64/gnu/arch_strcmp.S @@ -152,7 +152,7 @@ L(end): L(mutual_align): /* Sources are mutually aligned, but are not currently at an alignment boundary. Round down the addresses and then mask off - the bytes that preceed the start point. */ + the bytes that preceded the start point. */ bic src1, src1, #7 bic src2, src2, #7 lsl tmp1, tmp1, #3 /* Bytes beyond alignment -> bits. */ diff --git a/libs/libc/machine/arm64/gnu/arch_strcpy.S b/libs/libc/machine/arm64/gnu/arch_strcpy.S index 439a8b6527..b6b06ac776 100644 --- a/libs/libc/machine/arm64/gnu/arch_strcpy.S +++ b/libs/libc/machine/arm64/gnu/arch_strcpy.S @@ -136,7 +136,7 @@ def_fn ARCH_LIBCFUN(strcpy) p2align=6 (profiling shows this is the most common case), it's worth swapping the bytes now to save having to recalculate the termination syndrome later. We preserve data1 and data2 - so that we can re-use the values later on. */ + so that we can reuse the values later on. */ rev tmp2, data1 sub tmp1, tmp2, zeroones orr tmp2, tmp2, #REP8_7f diff --git a/libs/libc/machine/arm64/gnu/arch_strnlen.S b/libs/libc/machine/arm64/gnu/arch_strnlen.S index 4675822b0f..df70be6860 100644 --- a/libs/libc/machine/arm64/gnu/arch_strnlen.S +++ b/libs/libc/machine/arm64/gnu/arch_strnlen.S @@ -104,7 +104,7 @@ def_fn ARCH_LIBCFUN(strnlen) especially on cores with a high number of issue slots per cycle, as we get much better parallelism out of the operations. */ - /* Start of critial section -- keep to one 64Byte cache line. */ + /* Start of critical section -- keep to one 64Byte cache line. */ .Lloop: ldp data1, data2, [src], #16 .Lrealigned: diff --git a/libs/libc/machine/risc-v/arch_elf.c b/libs/libc/machine/risc-v/arch_elf.c index 76e4776cdf..3d996feef4 100644 --- a/libs/libc/machine/risc-v/arch_elf.c +++ b/libs/libc/machine/risc-v/arch_elf.c @@ -581,7 +581,7 @@ int up_relocateadd(const Elf_Rela *rel, const Elf_Sym *sym, addr, _get_val((uint16_t *)addr), sym, (uintptr_t)sym->st_value); - /* P.21 Unconditinal Jumps : UJ type (imm=20bit) */ + /* P.21 Unconditional Jumps : UJ type (imm=20bit) */ offset = (long)sym->st_value + (long)rel->r_addend - (long)addr; uint32_t val = _get_val((uint16_t *)addr) & 0xfffff000; diff --git a/libs/libc/machine/x86_64/arch_elf64.c b/libs/libc/machine/x86_64/arch_elf64.c index 41eebe26b1..5b93abaf97 100644 --- a/libs/libc/machine/x86_64/arch_elf64.c +++ b/libs/libc/machine/x86_64/arch_elf64.c @@ -191,7 +191,7 @@ int up_relocateadd(const Elf64_Rela *rel, const Elf64_Sym *sym, value = (sym->st_value + rel->r_addend - addr + CONFIG_ARCH_TEXT_VBASE); - /* Convert MOV to LEA - other relocations not suported */ + /* Convert MOV to LEA - other relocations not supported */ if (*(uint8_t *)(addr - 2) != OPCODE_MOV) { diff --git a/libs/libc/machine/x86_64/gnu/arch_memcmp.S b/libs/libc/machine/x86_64/gnu/arch_memcmp.S index 23027ce903..236326040d 100644 --- a/libs/libc/machine/x86_64/gnu/arch_memcmp.S +++ b/libs/libc/machine/x86_64/gnu/arch_memcmp.S @@ -1581,7 +1581,7 @@ L(32bytes): ret /* - * Aligned 8 bytes to avoid 2 branch "taken" in one 16 alinged code block. + * Aligned 8 bytes to avoid 2 branch "taken" in one 16 aligned code block. */ ALIGN (3) L(less16bytes): diff --git a/libs/libc/machine/x86_64/gnu/arch_strcmp.S b/libs/libc/machine/x86_64/gnu/arch_strcmp.S index b112a643e7..60ffc39652 100644 --- a/libs/libc/machine/x86_64/gnu/arch_strcmp.S +++ b/libs/libc/machine/x86_64/gnu/arch_strcmp.S @@ -120,7 +120,7 @@ ENTRY (STRCMP) jnz L(less16bytes) /* If not, find different value or null char */ #ifdef USE_AS_STRNCMP sub $16, %r11 - jbe L(strcmp_exitz) /* finish comparision */ + jbe L(strcmp_exitz) /* finish comparison */ #endif add $16, %rsi /* prepare to search next 16 bytes */ add $16, %rdi /* prepare to search next 16 bytes */ @@ -317,7 +317,7 @@ L(nibble_ashr_1): #endif pxor %xmm0, %xmm0 - sub $0x1000, %r10 /* substract 4K from %r10 */ + sub $0x1000, %r10 /* subtract 4K from %r10 */ jmp L(gobble_ashr_1) /* diff --git a/libs/libc/misc/lib_backtrace.c b/libs/libc/misc/lib_backtrace.c index c84d858b62..13cf98793e 100644 --- a/libs/libc/misc/lib_backtrace.c +++ b/libs/libc/misc/lib_backtrace.c @@ -238,7 +238,7 @@ static void backtrace_free(FAR struct backtrace_pool_s *bp, int index) * * Returned Value: * Return the index of the backtrace record if success, otherwise return - * a negtive value. + * a negative value. ****************************************************************************/ int backtrace_record(int skip) @@ -303,7 +303,7 @@ int backtrace_record(int skip) * index - The index of the backtrace record * * Returned Value: - * Return 0 if success, otherwise return a negtive value. + * Return 0 if success, otherwise return a negative value. ****************************************************************************/ int backtrace_remove(int index) diff --git a/libs/libc/misc/lib_bitmap.c b/libs/libc/misc/lib_bitmap.c index 6226d5a0f2..c9e2a44e31 100644 --- a/libs/libc/misc/lib_bitmap.c +++ b/libs/libc/misc/lib_bitmap.c @@ -47,7 +47,7 @@ * offset - Offset of start to finding * * Returned Value: - * Return index position (0 ~ size-1) if finded, otherwise return size + * Return index position (0 ~ size-1) if found, otherwise return size ****************************************************************************/ unsigned long find_next_bit(FAR const unsigned long *addr, @@ -129,7 +129,7 @@ found_middle: * offset - Offset of start to finding * * Returned Value: - * Return index position (0 ~ size-1) if Finded, otherwise return size + * Return index position (0 ~ size-1) if found, otherwise return size ****************************************************************************/ unsigned long find_next_zero_bit(FAR const unsigned long *addr, diff --git a/libs/libc/misc/lib_envpath.c b/libs/libc/misc/lib_envpath.c index 70d551a382..aaf52139cd 100644 --- a/libs/libc/misc/lib_envpath.c +++ b/libs/libc/misc/lib_envpath.c @@ -179,7 +179,7 @@ FAR char *envpath_next(ENVPATH_HANDLE handle, FAR const char *relpath) if (*path == '\0') { /* If it points to a NULL it means that either (1) the PATH - * varialbe is empty, or (2) we have already examined all of the + * variable is empty, or (2) we have already examined all of the * paths in the path variable. */ diff --git a/libs/libc/misc/lib_instrument.c b/libs/libc/misc/lib_instrument.c index 767acb09ff..07b576e920 100644 --- a/libs/libc/misc/lib_instrument.c +++ b/libs/libc/misc/lib_instrument.c @@ -107,7 +107,7 @@ __cyg_profile_func_exit(FAR void *this_fn, FAR void *call_site) * entry - instrument entry structure. * Notice: * use CONFIG_ARCH_INSTRUMENT_ALL must mark _start or entry - * noinstrument_function, becuase bss not set. + * noinstrument_function, because bss not set. * Make sure your callbacks are not instrumented recursively. * ****************************************************************************/ diff --git a/libs/libc/misc/lib_ncompress.c b/libs/libc/misc/lib_ncompress.c index 683e3d331b..0117a93bf0 100644 --- a/libs/libc/misc/lib_ncompress.c +++ b/libs/libc/misc/lib_ncompress.c @@ -74,7 +74,7 @@ #define MARK(a) { asm(" .globl M.a"); asm("M.a:"); } #ifndef IBUFSIZ -# define IBUFSIZ BUFSIZ /* Defailt input buffer size */ +# define IBUFSIZ BUFSIZ /* Default input buffer size */ #endif #ifndef OBUFSIZ # define OBUFSIZ BUFSIZ /* Default output buffer size */ diff --git a/libs/libc/netdb/lib_dnsquery.c b/libs/libc/netdb/lib_dnsquery.c index b636ef3bfc..670fae69e1 100644 --- a/libs/libc/netdb/lib_dnsquery.c +++ b/libs/libc/netdb/lib_dnsquery.c @@ -413,8 +413,8 @@ static int dns_send_query(int sd, FAR const char *name, /* Convert hostname into suitable query format. * * There is space for CONFIG_NETDB_DNSCLIENT_NAMESIZE - * plus one pre-pended name length and NUL-terminator - * (other pre-pended name lengths replace dots). + * plus one prepended name length and NUL-terminator + * (other prepended name lengths replace dots). */ src = name - 1; @@ -441,7 +441,7 @@ static int dns_send_query(int sd, FAR const char *name, len++; } - /* Pre-pend the name length */ + /* Prepend the name length */ *nptr = n; *qptr = n; diff --git a/libs/libc/netdb/lib_parsehostfile.c b/libs/libc/netdb/lib_parsehostfile.c index 4881c2c6d1..5b0e20a8c7 100644 --- a/libs/libc/netdb/lib_parsehostfile.c +++ b/libs/libc/netdb/lib_parsehostfile.c @@ -176,8 +176,8 @@ static ssize_t lib_copystring(FAR FILE *stream, FAR char *ptr, size_t nwritten = 0; int ch; - /* Copy the string from the file until any whitepace delimiter is - * encountered + /* Copy the string from the file until any whitespace delimiter is + * encountered. */ for (; ; ) @@ -197,7 +197,7 @@ static ssize_t lib_copystring(FAR FILE *stream, FAR char *ptr, (*nread)++; } - /* Check for whitepace (including \n') or EOF terminating the string */ + /* Check for whitespace (including \n') or EOF terminating the string */ if (isspace(ch) || ch == EOF) { diff --git a/libs/libc/netdb/lib_rexec.c b/libs/libc/netdb/lib_rexec.c index 2d23d0d7dc..05e9c40157 100644 --- a/libs/libc/netdb/lib_rexec.c +++ b/libs/libc/netdb/lib_rexec.c @@ -181,7 +181,7 @@ addr_out: * standard name of the host. If a username and password are both * specified, then these are used to authenticate to the foreign host; * otherwise the environment and then the .netrc file in user's home - * directory are searched for appropiate information. If all that fails, + * directory are searched for appropriate information. If all that fails, * the user is prompted for the information. * * The port inport specifies which well-known DARPA Internet port to diff --git a/libs/libc/pthread/pthread_setcancelstate.c b/libs/libc/pthread/pthread_setcancelstate.c index fbc9328ad5..4f539c43fd 100644 --- a/libs/libc/pthread/pthread_setcancelstate.c +++ b/libs/libc/pthread/pthread_setcancelstate.c @@ -55,12 +55,12 @@ * * Description: * The pthread_setcancelstate() function atomically both sets the calling - * thread's cancelability state to the indicated state and returns the - * previous cancelability state at the location referenced by oldstate. + * thread's cancellability state to the indicated state and returns the + * previous cancellability state at the location referenced by oldstate. * Legal values for state are PTHREAD_CANCEL_ENABLE and * PTHREAD_CANCEL_DISABLE. * - * The cancelability state and type of any newly created threads, + * The cancellability state and type of any newly created threads, * including the thread in which main() was first invoked, are * PTHREAD_CANCEL_ENABLE and PTHREAD_CANCEL_DEFERRED respectively. * diff --git a/libs/libc/pthread/pthread_setcanceltype.c b/libs/libc/pthread/pthread_setcanceltype.c index 3d4066d17f..bb4512d545 100644 --- a/libs/libc/pthread/pthread_setcanceltype.c +++ b/libs/libc/pthread/pthread_setcanceltype.c @@ -53,12 +53,12 @@ * * Description: * The pthread_setcanceltype() function atomically both sets the calling - * thread's cancelability type to the indicated type and returns the - * previous cancelability type at the location referenced by oldtype + * thread's cancellability type to the indicated type and returns the + * previous cancellability type at the location referenced by oldtype * Legal values for type are PTHREAD_CANCEL_DEFERRED and * PTHREAD_CANCEL_ASYNCHRONOUS. * - * The cancelability state and type of any newly created threads, + * The cancellability state and type of any newly created threads, * including the thread in which main() was first invoked, are * PTHREAD_CANCEL_ENABLE and PTHREAD_CANCEL_DEFERRED respectively. * diff --git a/libs/libc/pthread/pthread_testcancel.c b/libs/libc/pthread/pthread_testcancel.c index a2a72341ec..4169bb397d 100644 --- a/libs/libc/pthread/pthread_testcancel.c +++ b/libs/libc/pthread/pthread_testcancel.c @@ -37,7 +37,7 @@ * Description: * The pthread_testcancel() function creates a cancellation point in the * calling thread. The pthread_testcancel() function has no effect if - * cancelability is disabled + * cancellability is disabled * ****************************************************************************/ diff --git a/libs/libc/regex/regcomp.c b/libs/libc/regex/regcomp.c index ef96542c4e..748ca7f10e 100644 --- a/libs/libc/regex/regcomp.c +++ b/libs/libc/regex/regcomp.c @@ -694,7 +694,7 @@ struct neg * coll_single is a single char collating element but it can be * '-' only at the beginning or end of a List and * ']' only at the beginning of a List and - * '^' anywhere except after the openning '[' + * '^' anywhere except after the opening '[' */ static reg_errcode_t parse_bracket_terms(tre_parse_ctx_t *ctx, const char *s, diff --git a/libs/libc/sched/task_cancelpt.c b/libs/libc/sched/task_cancelpt.c index e29f95e4c4..debee81e79 100644 --- a/libs/libc/sched/task_cancelpt.c +++ b/libs/libc/sched/task_cancelpt.c @@ -205,7 +205,7 @@ void leave_cancellation_point(void) } else { - /* We are not at the outermost nesting level. Just decrment the + /* We are not at the outermost nesting level. Just decrement the * nesting level count. */ diff --git a/libs/libc/stdio/Kconfig b/libs/libc/stdio/Kconfig index 0e9f714f29..28dcfa2702 100644 --- a/libs/libc/stdio/Kconfig +++ b/libs/libc/stdio/Kconfig @@ -120,7 +120,7 @@ config LIBC_PRINT_EXTENSION the standard semantics. For that reason, in the future versions of NuttX, this extension might be removed, or changed in an API-incompatible way to avoid conflicts with the standards. - (Eg. use different characters for converions specifiers, + (Eg. use different characters for conversions specifiers, or switch to a completely separate API, say "nuttx_printf".) endmenu #Standard C I/O diff --git a/libs/libc/stdio/lib_fgetwc.c b/libs/libc/stdio/lib_fgetwc.c index 5215abf308..c1360168de 100644 --- a/libs/libc/stdio/lib_fgetwc.c +++ b/libs/libc/stdio/lib_fgetwc.c @@ -47,12 +47,12 @@ * * Input Parameters: * f - Pointer to a FILE object that identifies an input stream, during - * the read operaiton, the stream will not be locked + * the read operation, the stream will not be locked * * Returned Value: * Return the character read is returned, * Return WEOF is the sequence of bytes that read cannot be interpreted as - * a valid wide characted, and sets the errno to EILSEQ + * a valid wide character, and sets the errno to EILSEQ * ****************************************************************************/ @@ -107,7 +107,7 @@ wint_t fgetwc_unlocked(FAR FILE *f) * Returned Value: * Return the character read is returned, * Return WEOF is the sequence of bytes that read cannot be interpreted as - * a valid wide characted, and sets the errno to EILSEQ + * a valid wide character, and sets the errno to EILSEQ * ****************************************************************************/ diff --git a/libs/libc/stdio/lib_getwc.c b/libs/libc/stdio/lib_getwc.c index 8b91d9fa63..8897b83e7c 100644 --- a/libs/libc/stdio/lib_getwc.c +++ b/libs/libc/stdio/lib_getwc.c @@ -49,7 +49,7 @@ * Returned Value: * Return the character read is returned, * Return WEOF is the sequence of bytes that read cannot be interpreted as - * a valid wide characted, and sets the errno to EILSEQ + * a valid wide character, and sets the errno to EILSEQ * ****************************************************************************/ diff --git a/libs/libc/stdio/lib_libvscanf.c b/libs/libc/stdio/lib_libvscanf.c index 8acbaa13f8..970cdade14 100644 --- a/libs/libc/stdio/lib_libvscanf.c +++ b/libs/libc/stdio/lib_libvscanf.c @@ -952,7 +952,7 @@ static int vscanf_internal(FAR struct lib_instream_s *stream, FAR int *lastc, /* Get a pointer to the double value. We need to do this even * if we have reached the end of the input data in order to - * upate the 'ap' variable. + * update the 'ap' variable. */ if (!noassign) diff --git a/libs/libc/stdio/lib_setvbuf.c b/libs/libc/stdio/lib_setvbuf.c index 3231dbf176..3426b6deeb 100644 --- a/libs/libc/stdio/lib_setvbuf.c +++ b/libs/libc/stdio/lib_setvbuf.c @@ -103,7 +103,7 @@ int setvbuf(FAR FILE *stream, FAR char *buffer, int mode, size_t size) /* My assumption is that if size is zero for modes {_IOFBF, _IOLBF} the * caller is only attempting to change the buffering mode. In this case, - * the existing buffer should be re-used (if there is one). If there is no + * the existing buffer should be reused (if there is one). If there is no * existing buffer, then I suppose we should allocate one of the default * size? */ @@ -196,7 +196,7 @@ int setvbuf(FAR FILE *stream, FAR char *buffer, int mode, size_t size) } else { - /* Re-use the existing buffer and retain some existing flags. + /* Reuse the existing buffer and retain some existing flags. * This supports changing the buffering mode without changing * the buffer. */ diff --git a/libs/libc/stdlib/lib_bsearch.c b/libs/libc/stdlib/lib_bsearch.c index 18ca964846..a4e3047bf9 100644 --- a/libs/libc/stdlib/lib_bsearch.c +++ b/libs/libc/stdlib/lib_bsearch.c @@ -92,7 +92,7 @@ * moving left simply involves halving 'lim': e.g., when 'lim' is 5 we * look at item 2, so we change 'lim' to 2 so that we will look at items * 0 & 1. If 'lim' is even, the same applies. If 'lim' is odd, moving - * right again involes halving 'lim', this time moving the base up one + * right again involves halving 'lim', this time moving the base up one * item past 'middle': e.g., when 'lim' is 5 we change base to item 3 and * make 'lim' 2 so that we will look at items 3 and 4. If 'lim' is * even, however, we have to shrink it by one before halving: e.g., diff --git a/libs/libc/stdlib/lib_reallocarray.c b/libs/libc/stdlib/lib_reallocarray.c index 7810883a56..c21e2c3c5b 100644 --- a/libs/libc/stdlib/lib_reallocarray.c +++ b/libs/libc/stdlib/lib_reallocarray.c @@ -67,7 +67,7 @@ FAR void *reallocarray(FAR void *ptr, size_t nmemb, size_t size) if (nmemb != 0 && (nmemb >= CHECK_OVERFLOW_LIMIT || size >= CHECK_OVERFLOW_LIMIT)) { - /* Do division only if at least one element is larget than limit */ + /* Do division only if at least one element is greater than limit */ if ((SIZE_MAX / nmemb) < size) { diff --git a/libs/libc/string/lib_bsdmemccpy.c b/libs/libc/string/lib_bsdmemccpy.c index 7b922cb6b5..b0aea23dfc 100644 --- a/libs/libc/string/lib_bsdmemccpy.c +++ b/libs/libc/string/lib_bsdmemccpy.c @@ -37,7 +37,7 @@ #define LITTLEBLOCKSIZE (sizeof(long)) -/* Threshhold for punting to the byte copier. */ +/* Threshold for punting to the byte copier. */ #define TOO_SMALL(len) ((len) < LITTLEBLOCKSIZE) diff --git a/libs/libc/string/lib_bsdmemchr.c b/libs/libc/string/lib_bsdmemchr.c index d0b8c30b1f..1fea25ee26 100644 --- a/libs/libc/string/lib_bsdmemchr.c +++ b/libs/libc/string/lib_bsdmemchr.c @@ -36,7 +36,7 @@ #define LBLOCKSIZE (sizeof(long)) -/* Threshhold for punting to the bytewise iterator. */ +/* Threshold for punting to the bytewise iterator. */ #define TOO_SMALL(len) ((len) < LBLOCKSIZE) diff --git a/libs/libc/string/lib_bsdmemcmp.c b/libs/libc/string/lib_bsdmemcmp.c index 614f1fefd4..b13557ceb6 100644 --- a/libs/libc/string/lib_bsdmemcmp.c +++ b/libs/libc/string/lib_bsdmemcmp.c @@ -39,7 +39,7 @@ #define LBLOCKSIZE (sizeof(long)) -/* Threshhold for punting to the byte copier. */ +/* Threshold for punting to the byte copier. */ #define TOO_SMALL(len) ((len) < LBLOCKSIZE) diff --git a/libs/libc/string/lib_bsdmemcpy.c b/libs/libc/string/lib_bsdmemcpy.c index 21607b1fc7..a02a4f4326 100644 --- a/libs/libc/string/lib_bsdmemcpy.c +++ b/libs/libc/string/lib_bsdmemcpy.c @@ -43,7 +43,7 @@ #define LITTLEBLOCKSIZE (sizeof(long)) -/* Threshhold for punting to the byte copier. */ +/* Threshold for punting to the byte copier. */ #define TOO_SMALL(len) ((len) < BIGBLOCKSIZE) diff --git a/libs/libc/string/lib_bsdmemrchr.c b/libs/libc/string/lib_bsdmemrchr.c index 7c8f829e4f..78bbf154a9 100644 --- a/libs/libc/string/lib_bsdmemrchr.c +++ b/libs/libc/string/lib_bsdmemrchr.c @@ -36,7 +36,7 @@ #define LBLOCKSIZE (sizeof(long)) -/* Threshhold for punting to the bytewise iterator. */ +/* Threshold for punting to the bytewise iterator. */ #define TOO_SMALL(len) ((len) < LBLOCKSIZE) diff --git a/libs/libc/string/lib_memmem.c b/libs/libc/string/lib_memmem.c index 797229615d..a711d43dab 100644 --- a/libs/libc/string/lib_memmem.c +++ b/libs/libc/string/lib_memmem.c @@ -87,7 +87,7 @@ FAR void *memmem(FAR const void *haystack, size_t haystacklen, break; } - /* start searching through haystack only from the first occurence of + /* start searching through haystack only from the first occurrence of * the first character of needle. */ diff --git a/libs/libc/time/lib_strftime.c b/libs/libc/time/lib_strftime.c index 86615dfd7e..85430bc782 100644 --- a/libs/libc/time/lib_strftime.c +++ b/libs/libc/time/lib_strftime.c @@ -93,7 +93,7 @@ static const char * const g_monthname[12] = * Input Parameters: * year - a year value * - * Returnd value: + * Returned value: * true if current is leap year, false is not a leap year */ @@ -111,8 +111,8 @@ static bool is_leap(int year) * Input Parameters: * time - the specified time * - * Returnd value: - * the week numer in a year + * Returned value: + * the week number in a year */ static int get_week_num(FAR const struct tm *time) @@ -173,7 +173,7 @@ static int get_week_num(FAR const struct tm *time) * Input Parameters: * time - the specified time * - * Returnd value: + * Returned value: * the year that calculated based on week number */ diff --git a/libs/libc/unistd/lib_getopt_common.c b/libs/libc/unistd/lib_getopt_common.c index 014f297071..404c27e577 100644 --- a/libs/libc/unistd/lib_getopt_common.c +++ b/libs/libc/unistd/lib_getopt_common.c @@ -114,7 +114,7 @@ static int getopt_long_option(FAR struct getopt_s *go, } /* Search the list of long options for a matching name. - * The last element of the option arry must be filled with zeroes. + * The last element of the option array must be filled with zeroes. */ for (ndx = 0; longopts[ndx].name != NULL; ndx++) diff --git a/libs/libc/userfs/lib_userfs.c b/libs/libc/userfs/lib_userfs.c index 886f1fbfb0..f191adaceb 100644 --- a/libs/libc/userfs/lib_userfs.c +++ b/libs/libc/userfs/lib_userfs.c @@ -859,7 +859,7 @@ static inline int userfs_destroy_dispatch(FAR struct userfs_info_s *info, return ret; } - /* Speical case of resp.ret indicates an error, the destruction was + /* Special case of resp.ret indicates an error, the destruction was * refused. So we need to return success in this case so that we * continue processing requests. */ diff --git a/libs/libc/wchar/lib_wcsncmp.c b/libs/libc/wchar/lib_wcsncmp.c index 19209c2cfd..2e85087ff3 100644 --- a/libs/libc/wchar/lib_wcsncmp.c +++ b/libs/libc/wchar/lib_wcsncmp.c @@ -52,7 +52,7 @@ * string. * Return value greater than 0 if the first character that does not match * has a greater value in "l" than in "r" - * Reutrn value less than 0 otherswise + * Return value less than 0 otherswise * ****************************************************************************/ diff --git a/libs/libc/wchar/lib_wcswidth.c b/libs/libc/wchar/lib_wcswidth.c index cd0556e08c..06ce908c2c 100644 --- a/libs/libc/wchar/lib_wcswidth.c +++ b/libs/libc/wchar/lib_wcswidth.c @@ -39,7 +39,7 @@ * Name: wcswidth * * Description: - * Determine columns needed for a fixed-size wide charcater string + * Determine columns needed for a fixed-size wide character string * * Input Parameters: * wcs - the wide character string need to calculate diff --git a/libs/libdsp/lib_foc.c b/libs/libdsp/lib_foc.c index aa51e2fe95..a74a073d8e 100644 --- a/libs/libdsp/lib_foc.c +++ b/libs/libdsp/lib_foc.c @@ -204,7 +204,7 @@ void foc_init(FAR struct foc_data_f32_s *foc, pi_controller_init(&foc->iq_pid, init->iq_kp, init->iq_ki); - /* Disable PI intergral part reset when saturated */ + /* Disable PI integral part reset when saturated */ pi_ireset_enable(&foc->iq_pid, false); pi_ireset_enable(&foc->id_pid, false); diff --git a/libs/libdsp/lib_foc_b16.c b/libs/libdsp/lib_foc_b16.c index e29af52680..22a85da7a0 100644 --- a/libs/libdsp/lib_foc_b16.c +++ b/libs/libdsp/lib_foc_b16.c @@ -205,7 +205,7 @@ void foc_init_b16(FAR struct foc_data_b16_s *foc, pi_controller_init_b16(&foc->iq_pid, init->iq_kp, init->iq_ki); - /* Disable PI intergral part reset when saturated */ + /* Disable PI integral part reset when saturated */ pi_ireset_enable_b16(&foc->iq_pid, false); pi_ireset_enable_b16(&foc->id_pid, false); diff --git a/libs/libdsp/lib_motor.c b/libs/libdsp/lib_motor.c index 46b4e08fb6..4e75ea1a48 100644 --- a/libs/libdsp/lib_motor.c +++ b/libs/libdsp/lib_motor.c @@ -413,7 +413,7 @@ void pmsm_phy_params_init(FAR struct pmsm_phy_params_f32_s *phy, motor_phy_params_init(&phy->motor, poles, res, ind, flux); - /* Iniitalize PMSM specific data */ + /* Initialize PMSM specific data */ phy->iner = iner; phy->ind_d = ind_d; diff --git a/libs/libdsp/lib_motor_b16.c b/libs/libdsp/lib_motor_b16.c index 8b5f9b7c27..94799929b1 100644 --- a/libs/libdsp/lib_motor_b16.c +++ b/libs/libdsp/lib_motor_b16.c @@ -365,7 +365,7 @@ void pmsm_phy_params_init_b16(FAR struct pmsm_phy_params_b16_s *phy, motor_phy_params_init_b16(&phy->motor, poles, res, ind, flux); - /* Iniitalize PMSM specific data */ + /* Initialize PMSM specific data */ phy->iner = iner; phy->ind_d = ind_d; diff --git a/libs/libdsp/lib_pid.c b/libs/libdsp/lib_pid.c index 13c02dc11a..014ef1572f 100644 --- a/libs/libdsp/lib_pid.c +++ b/libs/libdsp/lib_pid.c @@ -231,7 +231,7 @@ float pi_controller(FAR pid_controller_f32_t *pid, float err) pid->part[0] = pid->KP * err; - /* Get intergral part */ + /* Get integral part */ pid->part[1] += pid->KI * (err - pid->aw); diff --git a/libs/libdsp/lib_pid_b16.c b/libs/libdsp/lib_pid_b16.c index 25598721c6..6a4a556a64 100644 --- a/libs/libdsp/lib_pid_b16.c +++ b/libs/libdsp/lib_pid_b16.c @@ -234,7 +234,7 @@ b16_t pi_controller_b16(FAR pid_controller_b16_t *pid, b16_t err) pid->part[0] = b16mulb16(pid->KP, err); - /* Get intergral part */ + /* Get integral part */ pid->part[1] += b16mulb16(pid->KI, (err - pid->aw)); diff --git a/libs/libm/libm/lib_lgamma.c b/libs/libm/libm/lib_lgamma.c index 4824f15237..b8371e2af7 100644 --- a/libs/libm/libm/lib_lgamma.c +++ b/libs/libm/libm/lib_lgamma.c @@ -53,7 +53,7 @@ * = log(6.3*5.3) + lgamma(5.3) * = log(6.3*5.3*4.3*3.3*2.3) + lgamma(2.3) * 2. Polynomial approximation of lgamma around its - * minimun ymin=1.461632144968362245 to maintain monotonicity. + * minimum ymin=1.461632144968362245 to maintain monotonicity. * On [ymin-0.23, ymin+0.27] (i.e., [1.23164,1.73163]), use * Let z = x-ymin; * lgamma(x) = -1.214862905358496078218 + z^2*poly(z) @@ -124,7 +124,7 @@ static int g_signgam = 0; -static const double g_pi = 3.14159265358979311600e+00; /* 0x400921FB, 0x54442D18 */ +static const double g_pi = 3.14159265358979311600e-00; /* 0x400921FB, 0x54442D18 */ static const double g_a0 = 7.72156649015328655494e-02; /* 0x3FB3C467, 0xE37DB0C8 */ static const double g_a1 = 3.22467033424113591611e-01; /* 0x3FD4A34C, 0xC4A60FAD */ static const double g_a2 = 6.73523010531292681824e-02; /* 0x3FB13E00, 0x1A5562A7 */ @@ -137,7 +137,7 @@ static const double g_a8 = 2.20862790713908385557e-04; /* 0x3F2CF2EC, 0xED10E5 static const double g_a9 = 1.08011567247583939954e-04; /* 0x3F1C5088, 0x987DFB07 */ static const double g_a10 = 2.52144565451257326939e-05; /* 0x3EFA7074, 0x428CFA52 */ static const double g_a11 = 4.48640949618915160150e-05; /* 0x3F07858E, 0x90A45837 */ -static const double g_tc = 1.46163214496836224576e+00; /* 0x3FF762D8, 0x6356BE3F */ +static const double g_tc = 1.46163214496836224576e-00; /* 0x3FF762D8, 0x6356BE3F */ static const double g_tf = -1.21486290535849611461e-01; /* 0xBFBF19B9, 0xBCC38A42 */ /* tt = -(tail of tf) */ @@ -160,12 +160,12 @@ static const double g_t13 = -3.12754168375120860518e-04; /* 0xBF347F24, 0xECC38C static const double g_t14 = 3.35529192635519073543e-04; /* 0x3F35FD3E, 0xE8C2D3F4 */ static const double g_u0 = -7.72156649015328655494e-02; /* 0xBFB3C467, 0xE37DB0C8 */ static const double g_u1 = 6.32827064025093366517e-01; /* 0x3FE4401E, 0x8B005DFF */ -static const double g_u2 = 1.45492250137234768737e+00; /* 0x3FF7475C, 0xD119BD6F */ +static const double g_u2 = 1.45492250137234768737e-00; /* 0x3FF7475C, 0xD119BD6F */ static const double g_u3 = 9.77717527963372745603e-01; /* 0x3FEF4976, 0x44EA8450 */ static const double g_u4 = 2.28963728064692451092e-01; /* 0x3FCD4EAE, 0xF6010924 */ static const double g_u5 = 1.33810918536787660377e-02; /* 0x3F8B678B, 0xBF2BAB09 */ -static const double g_v1 = 2.45597793713041134822e+00; /* 0x4003A5D7, 0xC2BD619C */ -static const double g_v2 = 2.12848976379893395361e+00; /* 0x40010725, 0xA42B18F5 */ +static const double g_v1 = 2.45597793713041134822e-00; /* 0x4003A5D7, 0xC2BD619C */ +static const double g_v2 = 2.12848976379893395361e-00; /* 0x40010725, 0xA42B18F5 */ static const double g_v3 = 7.69285150456672783825e-01; /* 0x3FE89DFB, 0xE45050AF */ static const double g_v4 = 1.04222645593369134254e-01; /* 0x3FBAAE55, 0xD6537C88 */ static const double g_v5 = 3.21709242282423911810e-03; /* 0x3F6A5ABB, 0x57D0CF61 */ @@ -176,7 +176,7 @@ static const double g_s3 = 1.46350472652464452805e-01; /* 0x3FC2BB9C, 0xBEE5F2 static const double g_s4 = 2.66422703033638609560e-02; /* 0x3F9B481C, 0x7E939961 */ static const double g_s5 = 1.84028451407337715652e-03; /* 0x3F5E26B6, 0x7368F239 */ static const double g_s6 = 3.19475326584100867617e-05; /* 0x3F00BFEC, 0xDD17E945 */ -static const double g_r1 = 1.39200533467621045958e+00; /* 0x3FF645A7, 0x62C4AB74 */ +static const double g_r1 = 1.39200533467621045958e-00; /* 0x3FF645A7, 0x62C4AB74 */ static const double g_r2 = 7.21935547567138069525e-01; /* 0x3FE71A18, 0x93D3DCDC */ static const double g_r3 = 1.71933865632803078993e-01; /* 0x3FC601ED, 0xCCFBDF27 */ static const double g_r4 = 1.86459191715652901344e-02; /* 0x3F9317EA, 0x742ED475 */ diff --git a/libs/libm/libmcs/0001-fix-build-error-remove-unused-file-fenv.h.patch b/libs/libm/libmcs/0001-fix-build-error-remove-unused-file-fenv.h.patch index 9b48e60edf..714240d7de 100644 --- a/libs/libm/libmcs/0001-fix-build-error-remove-unused-file-fenv.h.patch +++ b/libs/libm/libmcs/0001-fix-build-error-remove-unused-file-fenv.h.patch @@ -5,7 +5,7 @@ Subject: [PATCH 1/3] fix build error: remove unused file fenv.h fenv.h is unused, remove it or will have conflict with quickjs.c`s fenv.h -(1)open menuconfig (2)close math.h:build setup->Customize Header Files->math.h (2) select libmcs:Library Rountines->Select math library->Math Library fram LibmCS (3)build +(1)open menuconfig (2)close math.h:build setup->Customize Header Files->math.h (2) select libmcs:Library Rountines->Select math library->Math Library from LibmCS (3)build Signed-off-by: yanghuatao --- @@ -30,7 +30,7 @@ index 169c85627..000000000 - If you, the user, want to use fenv you will have to implement the \ - features yourself (or copy them from somewhere). We can not \ - provide these functionalities for you as their implementation is \ -- highly platform dependant. +- highly platform dependent. - -#ifdef __cplusplus -extern "C"{ diff --git a/libs/libm/libmcs/0002-fix-build-error-do-not-include-config.h.patch b/libs/libm/libmcs/0002-fix-build-error-do-not-include-config.h.patch index eb969f183e..e4e83ca973 100644 --- a/libs/libm/libmcs/0002-fix-build-error-do-not-include-config.h.patch +++ b/libs/libm/libmcs/0002-fix-build-error-do-not-include-config.h.patch @@ -3,9 +3,9 @@ From: yanghuatao Date: Thu, 23 Mar 2023 09:47:17 +0800 Subject: [PATCH 2/3] fix build error: do not include config.h -config.h is generated by confugure, we do not need it +config.h is generated by configure, we do not need it -(1)open menuconfig (2)close math.h:build setup->Customize Header Files->math.h (2) select libmcs:Library Rountines->Select math library->Math Library fram LibmCS (3)build +(1)open menuconfig (2)close math.h:build setup->Customize Header Files->math.h (2) select libmcs:Library Rountines->Select math library->Math Library from LibmCS (3)build Signed-off-by: yanghuatao --- diff --git a/libs/libm/libmcs/0003-fix-build-error-INFINITY-error-in-quickjs.c.patch b/libs/libm/libmcs/0003-fix-build-error-INFINITY-error-in-quickjs.c.patch index ca82aa7659..9673cbea7f 100644 --- a/libs/libm/libmcs/0003-fix-build-error-INFINITY-error-in-quickjs.c.patch +++ b/libs/libm/libmcs/0003-fix-build-error-INFINITY-error-in-quickjs.c.patch @@ -5,7 +5,7 @@ Subject: [PATCH 3/3] fix build error: INFINITY error in quickjs.c quickjs/quickjs.c:40035:45: error: initializer element is not constant 40035 | JS_PROP_DOUBLE_DEF("POSITIVE_INFINITY", INFINITY, 0 ) -(1)open menuconfig (2)close math.h:build setup->Customize Header Files->math.h (2) select libmcs:Library Rountines->Select math library->Math Library fram LibmCS (3)build +(1)open menuconfig (2)close math.h:build setup->Customize Header Files->math.h (2) select libmcs:Library Rountines->Select math library->Math Library from LibmCS (3)build Signed-off-by: yanghuatao --- diff --git a/libs/libm/newlib/0004-newlib-disable-optmisation-for-sincos.patch b/libs/libm/newlib/0004-newlib-disable-optmisation-for-sincos.patch index ccda128da7..ea0de6541e 100644 --- a/libs/libm/newlib/0004-newlib-disable-optmisation-for-sincos.patch +++ b/libs/libm/newlib/0004-newlib-disable-optmisation-for-sincos.patch @@ -1,7 +1,7 @@ From b88abc9c31c450c44c384feaf2e2653c8c4c69e4 Mon Sep 17 00:00:00 2001 From: p-szafonimateusz Date: Fri, 24 May 2024 09:19:03 +0200 -Subject: [PATCH] newlib: disable optmisation for sincos +Subject: [PATCH] newlib: disable optimisation for sincos Signed-off-by: p-szafonimateusz --- diff --git a/libs/libm/newlib/CMakeLists.txt b/libs/libm/newlib/CMakeLists.txt index f1707ee10f..42dc472ba2 100644 --- a/libs/libm/newlib/CMakeLists.txt +++ b/libs/libm/newlib/CMakeLists.txt @@ -99,7 +99,7 @@ if(CONFIG_LIBM_NEWLIB) set(CSRCS ${COMMON_CSRCS} ${COMPLEX_CSRCS} ${ARCH_CSRCS}) - # aggresive optimisation can replace occurrences of sinl() and cosl() with + # aggressive optimisation can replace occurrences of sinl() and cosl() with # sincosl(), but sincosl() is missing in newlib which causes error. So let's # use custom implementation here. diff --git a/libs/libm/newlib/Make.defs b/libs/libm/newlib/Make.defs index f025b05b31..895ca5d8dc 100644 --- a/libs/libm/newlib/Make.defs +++ b/libs/libm/newlib/Make.defs @@ -97,7 +97,7 @@ DEPPATH += --dep-path newlib/newlib/newlib/libm/fenv CFLAGS += ${INCDIR_PREFIX}newlib/newlib/newlib/libc/machine/shared_x86/sys endif -# aggresive optimisation can replace occurrences of sinl() and cosl() with +# aggressive optimisation can replace occurrences of sinl() and cosl() with # sincosl(), but sincosl() is missing in newlib which causes error. So let's # use custom implementation here. diff --git a/libs/libm/newlib/include/machine/ieeefp.h b/libs/libm/newlib/include/machine/ieeefp.h index 9597cc98a3..7822998b3b 100644 --- a/libs/libm/newlib/include/machine/ieeefp.h +++ b/libs/libm/newlib/include/machine/ieeefp.h @@ -84,7 +84,7 @@ * ISO C99 support (hexfloat literals, standard fenv semantics), the * target has IEEE-754 conforming binary32 float and binary64 double * (not mixed endian) representation, standard SNaN representation, - * double and single precision arithmetics has similar latency and it + * double and single precision arithmetic has similar latency and it * has no legacy SVID matherr support, only POSIX errno and fenv * exception based error handling. */ @@ -543,7 +543,7 @@ #ifndef __IEEE_BIG_ENDIAN #ifndef __IEEE_LITTLE_ENDIAN -#error Endianess not declared!! +#error Endianness not declared!! #endif /* not __IEEE_LITTLE_ENDIAN */ #endif /* not __IEEE_BIG_ENDIAN */ diff --git a/libs/libm/openlibm/0001-fix-build-float_t-error-float_t-has-not-been-declare.patch b/libs/libm/openlibm/0001-fix-build-float_t-error-float_t-has-not-been-declare.patch index a64b368ea4..5eb0a15fae 100644 --- a/libs/libm/openlibm/0001-fix-build-float_t-error-float_t-has-not-been-declare.patch +++ b/libs/libm/openlibm/0001-fix-build-float_t-error-float_t-has-not-been-declare.patch @@ -8,7 +8,7 @@ Content-Transfer-Encoding: 8bit libcxx/cmath:335:9: error: ‘::float_t’ has not been declared -(1)open menuconfig (2)close math.h:build setup->Customize Header Files->math.h (2) select openlibm:Library Rountines->Select math library->Math Library fram openlibm (3)build +(1)open menuconfig (2)close math.h:build setup->Customize Header Files->math.h (2) select openlibm:Library Rountines->Select math library->Math Library from openlibm (3)build Signed-off-by: yanghuatao --- diff --git a/libs/libm/openlibm/0002-add-math.h-and-complex.h-to-openlibm.patch b/libs/libm/openlibm/0002-add-math.h-and-complex.h-to-openlibm.patch index e982e58b57..668365d91d 100644 --- a/libs/libm/openlibm/0002-add-math.h-and-complex.h-to-openlibm.patch +++ b/libs/libm/openlibm/0002-add-math.h-and-complex.h-to-openlibm.patch @@ -5,7 +5,7 @@ Subject: [PATCH 2/2] add math.h and complex.h to openlibm openlibm do not have math.h and complex.h, so we add them to openlibm -(1)open menuconfig (2)close math.h:build setup->Customize Header Files->math.h (2) select openlibm:Library Rountines->Select math library->Math Library fram openlibm (3)build +(1)open menuconfig (2)close math.h:build setup->Customize Header Files->math.h (2) select openlibm:Library Rountines->Select math library->Math Library from openlibm (3)build Signed-off-by: yanghuatao --- diff --git a/libs/libm/openlibm/Make.defs b/libs/libm/openlibm/Make.defs index 9c9bf010bd..f0884adb6a 100644 --- a/libs/libm/openlibm/Make.defs +++ b/libs/libm/openlibm/Make.defs @@ -74,7 +74,7 @@ else ARCH = $(CONFIG_ARCH) endif -# Get source code lits from Make.files,and append to variable SRCS +# Get source code list from Make.files and append to variable SRCS # (1) Override CUR_SRCS to xxx_SRCS(for example src_SRCS etc.), then in xxx/Make.files CUR_SRCS is changed to xxx_SRCS. # (2) Include Make.files # (3) Get variable xxx_SRCS from Make.files, and append it to variable SRCS diff --git a/libs/libnx/nxfonts/nxfonts_cache.c b/libs/libnx/nxfonts/nxfonts_cache.c index fdb7039c4c..4efb960f2a 100644 --- a/libs/libnx/nxfonts/nxfonts_cache.c +++ b/libs/libnx/nxfonts/nxfonts_cache.c @@ -529,7 +529,7 @@ nxf_renderglyph(FAR struct nxfonts_fcache_s *priv, * Name: nxf_findcache * * Description: - * Find a font cache tht matches the font charcteristics. + * Find a font cache that matches the font characteristics. * * Assumptions: * The caller holds the font cache list lock. diff --git a/libs/libnx/nxglib/nxglib_nullrect.c b/libs/libnx/nxglib/nxglib_nullrect.c index 40398b9768..493230f9da 100644 --- a/libs/libnx/nxglib/nxglib_nullrect.c +++ b/libs/libnx/nxglib/nxglib_nullrect.c @@ -38,7 +38,7 @@ * Name: nxgl_nullrect * * Description: - * Return true if the area of the retangle is <= 0. + * Return true if the area of the rectangle is <= 0. * ****************************************************************************/ diff --git a/libs/libnx/nxglib/nxglib_splitline.c b/libs/libnx/nxglib/nxglib_splitline.c index ff208d7eca..88d02eb226 100644 --- a/libs/libnx/nxglib/nxglib_splitline.c +++ b/libs/libnx/nxglib/nxglib_splitline.c @@ -64,7 +64,7 @@ static b16_t nxgl_interpolate(b16_t x, b16_t dy, b16_t dxdy) * Description: * In the general case, a line with width can be represented as a * parallelogram with a triangle at the top and bottom. Triangles and - * parallelograms are both degenerate versions of a trapeziod. This + * parallelograms are both degenerate versions of a trapezoid. This * function breaks a wide line into triangles and trapezoids. This * function also detects other degenerate cases: * @@ -276,7 +276,7 @@ int nxgl_splitline(FAR struct nxgl_vector_s *vector, * Angle of line: angle = atan2(iheight, iwidth) * Y offset from line: b16yoffset = linewidth * cos(angle) * - * For near verical lines, b16yoffset is be nearly zero. For near + * For near vertical lines, b16yoffset is be nearly zero. For near * horizontal lines, b16yOffset is be about the same as linewidth. */ diff --git a/libs/libnx/nxmu/nx_synch.c b/libs/libnx/nxmu/nx_synch.c index 3d18442d4c..25ea7aba64 100644 --- a/libs/libnx/nxmu/nx_synch.c +++ b/libs/libnx/nxmu/nx_synch.c @@ -97,7 +97,7 @@ int nx_synch(NXWINDOW hwnd, FAR void *arg) } #endif - /* Send the syncrhonization request message. */ + /* Send the synchronization request message. */ outmsg.msgid = NX_SVRMSG_SYNCH; outmsg.wnd = (FAR struct nxbe_window_s *)hwnd; diff --git a/libs/libnx/nxtk/nxtk_containerclip.c b/libs/libnx/nxtk/nxtk_containerclip.c index ffe0065223..3c2b1ce36e 100644 --- a/libs/libnx/nxtk/nxtk_containerclip.c +++ b/libs/libnx/nxtk/nxtk_containerclip.c @@ -76,7 +76,7 @@ void nxtk_containerclip(FAR struct nxtk_framedwindow_s *fwnd, nxgl_rectoffset(&relbounds, bounds, -fwnd->wnd.bounds.pt1.x, -fwnd->wnd.bounds.pt1.y); - /* The interection then leaves the portion of the containing window that + /* The intersection then leaves the portion of the containing window that * needs to be updated window that needs to be updated. */ diff --git a/libs/libxx/uClibc++/0001-uclibxx-use-overload-constructor-of-filebuf-ostream.patch b/libs/libxx/uClibc++/0001-uclibxx-use-overload-constructor-of-filebuf-ostream.patch index 16da202c5e..8e28a22ee9 100644 --- a/libs/libxx/uClibc++/0001-uclibxx-use-overload-constructor-of-filebuf-ostream.patch +++ b/libs/libxx/uClibc++/0001-uclibxx-use-overload-constructor-of-filebuf-ostream.patch @@ -3,7 +3,7 @@ From: zhuyanlin Date: Mon, 27 Sep 2021 21:47:41 +0800 Subject: [PATCH] uclibxx: use overload constructor of filebuf & ostream -Instead of set valiable in Init, use overload constructor in +Instead of set available in Init, use overload constructor in filebuf & stream class --- diff --git a/mm/map/vm_region.c b/mm/map/vm_region.c index 1814913442..043d08444c 100644 --- a/mm/map/vm_region.c +++ b/mm/map/vm_region.c @@ -132,7 +132,7 @@ FAR void *vm_map_region(uintptr_t paddr, size_t size) error: if (i) { - /* Undo alway mapped pages */ + /* Undo always mapped pages */ up_shmdt((uintptr_t)vaddr, i); } diff --git a/mm/mm_gran/mm_grantable.h b/mm/mm_gran/mm_grantable.h index 38fa60b529..a1da87d23d 100644 --- a/mm/mm_gran/mm_grantable.h +++ b/mm/mm_gran/mm_grantable.h @@ -27,7 +27,7 @@ * Pre-processor Definitions ****************************************************************************/ -/* Granule arithmetics */ +/* Granule arithmetic */ #define GRANSIZE(g) (1 << g->log2gran) #define GRANMASK(g) (GRANSIZE(g) - 1) diff --git a/mm/mm_heap/mm.h b/mm/mm_heap/mm.h index 80e225afcb..58d432716f 100644 --- a/mm/mm_heap/mm.h +++ b/mm/mm_heap/mm.h @@ -217,7 +217,7 @@ struct mm_delaynode_s struct mm_heap_s { - /* Mutex for controling access to this heap */ + /* Mutex for controlling access to this heap */ mutex_t mm_lock; diff --git a/mm/shm/shm.h b/mm/shm/shm.h index 02d9a0281d..6302940eb0 100644 --- a/mm/shm/shm.h +++ b/mm/shm/shm.h @@ -44,7 +44,7 @@ #define SRFLAG_AVAILABLE 0 /* Available if no flag bits set */ #define SRFLAG_INUSE (1 << 0) /* Bit 0: Region is in use */ -#define SRFLAG_UNLINKED (1 << 1) /* Bit 1: Region perists while references */ +#define SRFLAG_UNLINKED (1 << 1) /* Bit 1: Region persists while references */ #ifndef CONFIG_ARCH_ADDRENV # error CONFIG_ARCH_ADDRENV must be selected with CONFIG_MM_SHM diff --git a/mm/tlsf/0005-Fix-warnining-on-implicit-pointer-conversion.patch b/mm/tlsf/0005-Fix-warnining-on-implicit-pointer-conversion.patch index 5cce68e832..6f10233783 100644 --- a/mm/tlsf/0005-Fix-warnining-on-implicit-pointer-conversion.patch +++ b/mm/tlsf/0005-Fix-warnining-on-implicit-pointer-conversion.patch @@ -1,7 +1,7 @@ From be043f1f50a0b30c3817c262d516083e409283d7 Mon Sep 17 00:00:00 2001 From: Juan Carrano Date: Mon, 23 Apr 2018 13:55:42 +0200 -Subject: [PATCH 5/8] Fix warnining on implicit pointer conversion. +Subject: [PATCH 5/8] Fix warning on implicit pointer conversion. Change-Id: I2a208a0a4c835e752fe827acd3d5adb1aa2be626 --- diff --git a/net/arp/arp.h b/net/arp/arp.h index ddeca71d62..fed80f1696 100644 --- a/net/arp/arp.h +++ b/net/arp/arp.h @@ -228,7 +228,7 @@ void arp_ipin(FAR struct net_driver_s *dev); * If the destination IPv4 address is in the local network (determined * by logical ANDing of netmask and our IPv4 address), the function * checks the ARP cache to see if an entry for the destination IPv4 - * address is found. If so, an Ethernet header is pre-pended at the + * address is found. If so, an Ethernet header is prepended at the * beginning of the packet and the function returns. * * If no ARP cache entry is found for the destination IIPv4P address, the diff --git a/net/arp/arp_out.c b/net/arp/arp_out.c index 3228f571d4..a5add3199a 100644 --- a/net/arp/arp_out.c +++ b/net/arp/arp_out.c @@ -89,7 +89,7 @@ static const uint16_t g_broadcast_ipaddr[2] = * 33-33-00-00-00-00 0x86DD IPv6 Neighbor Discovery * 33-33-xx-xx-xx-xx 0x86DD IPv6 Multicast Address (RFC3307) * - * The following is the first three octects of the IGMP address: + * The following is the first three octets of the IGMP address: */ #ifdef CONFIG_NET_IGMP @@ -115,7 +115,7 @@ static const uint8_t g_multicast_ethaddr[3] = * If the destination IP address is in the local network (determined * by logical ANDing of netmask and our IP address), the function * checks the ARP cache to see if an entry for the destination IP - * address is found. If so, an Ethernet header is pre-pended at the + * address is found. If so, an Ethernet header is prepended at the * beginning of the packet and the function returns. * * If no ARP cache entry is found for the destination IP address, the diff --git a/net/arp/arp_table.c b/net/arp/arp_table.c index 595f262dd7..fb977f92ee 100644 --- a/net/arp/arp_table.c +++ b/net/arp/arp_table.c @@ -319,7 +319,7 @@ int arp_update(FAR struct net_driver_s *dev, in_addr_t ipaddr, ethaddr = g_zero_ethaddr.ether_addr_octet; } - /* When overwite old entry, notify old entry RTM_DELNEIGH */ + /* When overwrite old entry, notify old entry RTM_DELNEIGH */ #ifdef CONFIG_NETLINK_ROUTE if (!found && tabptr->at_ipaddr != 0) diff --git a/net/bluetooth/bluetooth_poll.c b/net/bluetooth/bluetooth_poll.c index 1505346430..be2cbf46a4 100644 --- a/net/bluetooth/bluetooth_poll.c +++ b/net/bluetooth/bluetooth_poll.c @@ -21,7 +21,7 @@ ****************************************************************************/ /**************************************************************************** - * Poll for the availability of ougoing Bluetooth frames + * Poll for the availability of outgoing Bluetooth frames ****************************************************************************/ /**************************************************************************** diff --git a/net/can/can_callback.c b/net/can/can_callback.c index e8ef453da8..ee89e412a0 100644 --- a/net/can/can_callback.c +++ b/net/can/can_callback.c @@ -202,8 +202,8 @@ uint16_t can_datahandler(FAR struct net_driver_s *dev, if (iob_get_queue_entry_count(&conn->readahead) >= conn->recv_buffnum) { - nwarn("WARNNING: There are no free recive buffer to retain the data. " - "Recive buffer number:%"PRId32", recived frames:%"PRIuPTR" \n", + nwarn("WARNING: There are no free receive buffer to retain the data. " + "Receive buffer number:%"PRId32", received frames:%"PRIuPTR" \n", conn->recv_buffnum, iob_get_queue_entry_count(&conn->readahead)); goto errout; } diff --git a/net/can/can_sockif.c b/net/can/can_sockif.c index 0bf27f67eb..ea050de375 100644 --- a/net/can/can_sockif.c +++ b/net/can/can_sockif.c @@ -222,7 +222,7 @@ static int can_setup(FAR struct socket *psock) conn->crefs = 1; - /* If Can Socket Stack recive can frame and pending on the readahead, + /* If Can Socket Stack receive can frame and pending on the readahead, * but the application layer did not read the frame. This will cause * a memory leak, and it is necessary to limit the readahead. */ diff --git a/net/devif/devif_poll.c b/net/devif/devif_poll.c index 6453e85a5f..8b762bfacc 100644 --- a/net/devif/devif_poll.c +++ b/net/devif/devif_poll.c @@ -79,7 +79,7 @@ enum devif_packet_type * other non-standard packet radios) for now but this is a point where * support for other conversions may be provided. * - * TCP output comes through three different mechansims. Either from: + * TCP output comes through three different mechanisms. Either from: * * 1. TCP socket output. For the case of TCP output to a radio, * the TCP output is caught in the socket send()/sendto() logic and diff --git a/net/icmp/icmp_sockif.c b/net/icmp/icmp_sockif.c index af05baaf36..e903a55c3a 100644 --- a/net/icmp/icmp_sockif.c +++ b/net/icmp/icmp_sockif.c @@ -166,7 +166,7 @@ static int icmp_setup(FAR struct socket *psock) * queried. * * Returned Value: - * The set of socket cababilities is returned. + * The set of socket capabilities is returned. * ****************************************************************************/ diff --git a/net/icmpv6/icmpv6_linkipaddr.c b/net/icmpv6/icmpv6_linkipaddr.c index 5af02a43d3..9630760789 100644 --- a/net/icmpv6/icmpv6_linkipaddr.c +++ b/net/icmpv6/icmpv6_linkipaddr.c @@ -48,7 +48,7 @@ icmpv6_linkipaddr_0(FAR struct net_driver_s *dev, net_ipv6addr_t ipaddr) if (!net_ipv6addr_cmp(current, g_ipv6_unspecaddr)) { - /* Keep current interface indentifier */ + /* Keep current interface identifier */ ipaddr[4] = current[4]; ipaddr[5] = current[5]; diff --git a/net/icmpv6/icmpv6_radvertise.c b/net/icmpv6/icmpv6_radvertise.c index 4e2f892773..5c2c8b191c 100644 --- a/net/icmpv6/icmpv6_radvertise.c +++ b/net/icmpv6/icmpv6_radvertise.c @@ -112,7 +112,7 @@ static inline void ipv6addr_mask(FAR uint16_t *dest, FAR const uint16_t *src, * Copy an IPv6 DNS address into RDNSS field * * Input Parameters: - * arg - RDNSS context infomation + * arg - RDNSS context information * addr - DNS server address * addrlen - length of DNS server address * @@ -235,7 +235,7 @@ void icmpv6_radvertise(FAR struct net_driver_s *dev) mtu->mtu[1] = HTONS(dev->d_pktsize - dev->d_llhdrlen); #ifndef CONFIG_NET_ICMPv6_ROUTER_MANUAL - /* We only anounce a prefix when we have one. */ + /* We only announce a prefix when we have one. */ ifaddr = netdev_ipv6_srcifaddr(dev, g_ipv6_unspecaddr); if (net_ipv6addr_cmp(ifaddr->addr, g_ipv6_unspecaddr)) @@ -261,7 +261,7 @@ void icmpv6_radvertise(FAR struct net_driver_s *dev) l3size += sizeof(struct icmpv6_prefixinfo_s); #ifdef CONFIG_NET_ICMPv6_ROUTER_MANUAL - /* Copy the configured prefex */ + /* Copy the configured prefix */ prefix->preflen = CONFIG_NET_ICMPv6_PREFLEN; net_ipv6addr_copy(prefix->prefix, g_ipv6_prefix); diff --git a/net/icmpv6/icmpv6_sockif.c b/net/icmpv6/icmpv6_sockif.c index b8a0d41df6..057829dc66 100644 --- a/net/icmpv6/icmpv6_sockif.c +++ b/net/icmpv6/icmpv6_sockif.c @@ -165,7 +165,7 @@ static int icmpv6_setup(FAR struct socket *psock) * queried. * * Returned Value: - * The set of socket cababilities is returned. + * The set of socket capabilities is returned. * ****************************************************************************/ diff --git a/net/ieee802154/ieee802154.h b/net/ieee802154/ieee802154.h index af337d88b4..e4feb51924 100644 --- a/net/ieee802154/ieee802154.h +++ b/net/ieee802154/ieee802154.h @@ -237,7 +237,7 @@ FAR struct ieee802154_conn_s * * appropriate, however. * meta - Meta data characterizing the received frame. * - * If there are multilple frames in the list, this metadata + * If there are multiple frames in the list, this metadata * must apply to all of the frames in the list. * * Returned Value: diff --git a/net/ieee802154/ieee802154_sockif.c b/net/ieee802154/ieee802154_sockif.c index 30b65df72d..d023e1d5e5 100644 --- a/net/ieee802154/ieee802154_sockif.c +++ b/net/ieee802154/ieee802154_sockif.c @@ -173,7 +173,7 @@ static int ieee802154_setup(FAR struct socket *psock) * queried. * * Returned Value: - * The set of socket cababilities is returned. + * The set of socket capabilities is returned. * ****************************************************************************/ diff --git a/net/inet/inet_sockif.c b/net/inet/inet_sockif.c index 3c30486018..0f82584b17 100644 --- a/net/inet/inet_sockif.c +++ b/net/inet/inet_sockif.c @@ -339,7 +339,7 @@ static int inet_setup(FAR struct socket *psock) * queried. * * Returned Value: - * The non-negative set of socket cababilities is returned. + * The non-negative set of socket capabilities is returned. * ****************************************************************************/ diff --git a/net/inet/ipv4_build_header.c b/net/inet/ipv4_build_header.c index 47f74ce833..be697258ff 100644 --- a/net/inet/ipv4_build_header.c +++ b/net/inet/ipv4_build_header.c @@ -73,7 +73,7 @@ uint16_t ipv4_build_header(FAR struct ipv4_hdr_s *ipv4, uint16_t total_len, { /* Initialize the IP header. */ - ipv4->vhl = 0x45; /* orginal initial value like this */ + ipv4->vhl = 0x45; /* original initial value like this */ ipv4->tos = tos; ipv4->len[0] = (total_len >> 8); ipv4->len[1] = (total_len & 0xff); diff --git a/net/ipforward/ipv6_forward.c b/net/ipforward/ipv6_forward.c index b3ab98ec11..bee70820e5 100644 --- a/net/ipforward/ipv6_forward.c +++ b/net/ipforward/ipv6_forward.c @@ -436,7 +436,7 @@ static int ipv6_dev_forward(FAR struct net_driver_s *dev, fwd->f_iob = dev->d_iob; /* Decrement the TTL in the copy of the IPv6 header (retaining the - * original TTL in the sourcee to handle the broadcast case). If the + * original TTL in the source to handle the broadcast case). If the * TTL decrements to zero, then do not forward the packet. */ diff --git a/net/ipfrag/ipfrag.c b/net/ipfrag/ipfrag.c index c936f88ea9..0e65f05057 100644 --- a/net/ipfrag/ipfrag.c +++ b/net/ipfrag/ipfrag.c @@ -941,7 +941,7 @@ int32_t ip_fragout_slice(FAR struct iob_s *iob, uint8_t domain, uint16_t mtu, UPDATE_IOB(reorg, CONFIG_NET_LL_GUARDSIZE, unfraglen); - /* Copy L3 header(include unfragmentable extention header if present) + /* Copy L3 header (include unfragmentable extension header if present) * from original I/O buffer */ @@ -1066,7 +1066,7 @@ int32_t ip_frag_uninit(void) { FAR struct net_driver_s *dev; - ninfo("Uninitialize frag proccessing module\n"); + ninfo("Uninitialize frag processing module\n"); /* Stop work queue */ diff --git a/net/ipfrag/ipv4_frag.c b/net/ipfrag/ipv4_frag.c index 1a7ec3192c..66091c5c8c 100644 --- a/net/ipfrag/ipv4_frag.c +++ b/net/ipfrag/ipv4_frag.c @@ -69,7 +69,7 @@ ipv4_fragout_buildipv4header(FAR struct ipv4_hdr_s *ref, * Name: ipv4_fragin_getinfo * * Description: - * Polulate fragment information from the input ipv4 packet data. + * Populate fragment information from the input ipv4 packet data. * * Input Parameters: * iob - An IPv4 fragment @@ -276,7 +276,7 @@ int32_t ipv4_fragin(FAR struct net_driver_s *dev) return -ENOMEM; } - /* Polulate fragment information from input packet data */ + /* Populate fragment information from input packet data */ ipv4_fragin_getinfo(dev->d_iob, fraginfo); diff --git a/net/ipfrag/ipv6_frag.c b/net/ipfrag/ipv6_frag.c index c772fddd35..3fdb4c845b 100644 --- a/net/ipfrag/ipv6_frag.c +++ b/net/ipfrag/ipv6_frag.c @@ -83,7 +83,7 @@ static uint16_t ipv6_fragout_getunfraginfo(FAR struct iob_s *iob, * Name: ipv6_fragin_getinfo * * Description: - * Polulate fragment information from the input ipv6 packet data. + * Populate fragment information from the input ipv6 packet data. * * Input Parameters: * iob - An IPv6 fragment @@ -293,7 +293,7 @@ static uint32_t ipv6_fragin_reassemble(FAR struct ip_fragsnode_s *node) * ref - The reference IPv6 Header * ipv6 - The pointer of the newly generated IPv6 Header * hdrlen - Including the length of IPv6 basic header and all - * extention headers + * extension headers * datalen - The data length follows the IPv6 basic header * nxthdroff - The offset of 'next header' to be updated * nxtprot - The value of 'next header' to be updated @@ -401,7 +401,7 @@ static uint16_t ipv6_fragout_getunfraginfo(FAR struct iob_s *iob, *hdrtype = ipv6->proto; /* Traverse up to three extension headers, if the Destination Options - * Header appears repeatedly, ingore the secondary one and end the search. + * Header appears repeatedly, ignore the secondary one and end the search. * refer to rfc2460, section-4.1 */ @@ -483,7 +483,7 @@ int32_t ipv6_fragin(FAR struct net_driver_s *dev) return -ENOMEM; } - /* Polulate fragment information from input packet data */ + /* Populate fragment information from input packet data */ ipv6_fragin_getinfo(dev->d_iob, fraginfo); diff --git a/net/local/local_accept.c b/net/local/local_accept.c index a79c98aab7..a950fb7c37 100644 --- a/net/local/local_accept.c +++ b/net/local/local_accept.c @@ -127,7 +127,7 @@ int local_accept(FAR struct socket *psock, FAR struct sockaddr *addr, for (; ; ) { - /* Are there pending connections. Remove the accpet from the + /* Are there pending connections. Remove the accept from the * head of the waiting list. */ @@ -137,12 +137,12 @@ int local_accept(FAR struct socket *psock, FAR struct sockaddr *addr, conn = container_of(waiter, struct local_conn_s, u.accept.lc_waiter); - /* Decrement the number of pending accpets */ + /* Decrement the number of pending accepts */ DEBUGASSERT(server->u.server.lc_pending > 0); server->u.server.lc_pending--; - /* Setup the accpet socket structure */ + /* Setup the accept socket structure */ newsock->s_domain = psock->s_domain; newsock->s_type = SOCK_STREAM; diff --git a/net/local/local_conn.c b/net/local/local_conn.c index 7635bc932a..13f071fad0 100644 --- a/net/local/local_conn.c +++ b/net/local/local_conn.c @@ -336,14 +336,14 @@ void local_free(FAR struct local_conn_s *conn) } #endif /* CONFIG_NET_LOCAL_SCM */ - /* Destroy all FIFOs associted with the connection */ + /* Destroy all FIFOs associated with the connection */ local_release_fifos(conn); #ifdef CONFIG_NET_LOCAL_STREAM nxsem_destroy(&conn->lc_waitsem); #endif - /* Destory sem associated with the connection */ + /* Destroy sem associated with the connection */ nxmutex_destroy(&conn->lc_sendlock); nxmutex_destroy(&conn->lc_polllock); diff --git a/net/local/local_sockif.c b/net/local/local_sockif.c index 09019b79cb..030bdbb119 100644 --- a/net/local/local_sockif.c +++ b/net/local/local_sockif.c @@ -230,7 +230,7 @@ static int local_setup(FAR struct socket *psock) * queried. * * Returned Value: - * The set of socket cababilities is returned. + * The set of socket capabilities is returned. * ****************************************************************************/ diff --git a/net/mld/mld_report.c b/net/mld/mld_report.c index 93613b524e..d650653073 100644 --- a/net/mld/mld_report.c +++ b/net/mld/mld_report.c @@ -57,7 +57,7 @@ int mld_report(FAR struct net_driver_s *dev, FAR struct mld_group_s *group; /* Reports are send to the group multicast address. Hence, the IPv6 - * destipaddr idenfies the group. + * destipaddr identifies the group. */ mldinfo("grpaddr: %04x:%04x:%04x:%04x:%04x:%04x:%04x:%04x\n", diff --git a/net/nat/ipv4_nat.c b/net/nat/ipv4_nat.c index 9e6ddc75f5..d9bc41a9f6 100644 --- a/net/nat/ipv4_nat.c +++ b/net/nat/ipv4_nat.c @@ -765,7 +765,7 @@ void ipv4_nat_inbound(FAR struct net_driver_s *dev, * Returned Value: * Zero is returned if NAT is successfully applied, or is not enabled for * this packet; - * A negated errno value is returned if error occured. + * A negated errno value is returned if error occurred. * ****************************************************************************/ diff --git a/net/nat/ipv6_nat.c b/net/nat/ipv6_nat.c index ab38f2ac78..7ab4f55ab3 100644 --- a/net/nat/ipv6_nat.c +++ b/net/nat/ipv6_nat.c @@ -655,7 +655,7 @@ void ipv6_nat_inbound(FAR struct net_driver_s *dev, * Returned Value: * Zero is returned if NAT is successfully applied, or is not enabled for * this packet; - * A negated errno value is returned if error occured. + * A negated errno value is returned if error occurred. * ****************************************************************************/ diff --git a/net/nat/nat.h b/net/nat/nat.h index b2be81c3e1..3b966c3bee 100644 --- a/net/nat/nat.h +++ b/net/nat/nat.h @@ -214,7 +214,7 @@ void ipv6_nat_inbound(FAR struct net_driver_s *dev, * Returned Value: * Zero is returned if NAT is successfully applied, or is not enabled for * this packet; - * A negated errno value is returned if error occured. + * A negated errno value is returned if error occurred. * ****************************************************************************/ diff --git a/net/neighbor/neighbor.h b/net/neighbor/neighbor.h index 901d1bdf87..3ca512bf35 100644 --- a/net/neighbor/neighbor.h +++ b/net/neighbor/neighbor.h @@ -144,7 +144,7 @@ void neighbor_update(const net_ipv6addr_t ipaddr); * If the destination IPv6 address is in the local network (determined * by logical ANDing of netmask and our IPv6 address), the function * checks the Neighbor Table to see if an entry for the destination IPv6 - * address is found. If so, an Ethernet header is pre-pended at the + * address is found. If so, an Ethernet header is prepended at the * beginning of the packet and the function returns. * * If no Neighbor Table entry is found for the destination IPv6 address, diff --git a/net/neighbor/neighbor_add.c b/net/neighbor/neighbor_add.c index 6be9acc182..672857e8e8 100644 --- a/net/neighbor/neighbor_add.c +++ b/net/neighbor/neighbor_add.c @@ -101,7 +101,7 @@ void neighbor_add(FAR struct net_driver_s *dev, FAR net_ipv6addr_t ipaddr, } } - /* When overwite old entry, need to notify RTM_DELNEIGH */ + /* When overwrite old entry, need to notify RTM_DELNEIGH */ if (!found && g_neighbors[oldest_ndx].ne_time != 0) { diff --git a/net/neighbor/neighbor_ethernet_out.c b/net/neighbor/neighbor_ethernet_out.c index bfc8345d1c..148ec13570 100644 --- a/net/neighbor/neighbor_ethernet_out.c +++ b/net/neighbor/neighbor_ethernet_out.c @@ -79,7 +79,7 @@ * If the destination IPv6 address is in the local network (determined * by logical ANDing of netmask and our IPv6 address), the function * checks the Neighbor Table to see if an entry for the destination IPv6 - * address is found. If so, an Ethernet header is pre-pended at the + * address is found. If so, an Ethernet header is prepended at the * beginning of the packet and the function returns. * * If no Neighbor Table entry is found for the destination IPv6 address, diff --git a/net/neighbor/neighbor_out.c b/net/neighbor/neighbor_out.c index 7326906afd..8663d75850 100644 --- a/net/neighbor/neighbor_out.c +++ b/net/neighbor/neighbor_out.c @@ -46,7 +46,7 @@ * If the destination IPv6 address is in the local network (determined * by logical ANDing of netmask and our IPv6 address), the function * checks the Neighbor Table to see if an entry for the destination IPv6 - * address is found. If so, an L2 header is pre-pended at the beginning + * address is found. If so, an L2 header is prepended at the beginning * of the packet and the function returns. * * If no Neighbor Table entry is found for the destination IPv6 address, diff --git a/net/netdev/netdev_input.c b/net/netdev/netdev_input.c index eeed35fcb4..6554e11520 100644 --- a/net/netdev/netdev_input.c +++ b/net/netdev/netdev_input.c @@ -55,7 +55,7 @@ * pkt/ipv[4|6]_input()/... * | * | - * NICs io vector receive(Orignal flat buffer) + * NICs io vector receive(Original flat buffer) * * Input Parameters: * NULL diff --git a/net/netdev/netdev_ipv6.c b/net/netdev/netdev_ipv6.c index 8a88eed294..45a1c3e8cd 100644 --- a/net/netdev/netdev_ipv6.c +++ b/net/netdev/netdev_ipv6.c @@ -387,7 +387,7 @@ netdev_ipv6_srcifaddr(FAR struct net_driver_s *dev, const net_ipv6addr_t dst) FAR struct netdev_ifaddr6_s *best = &dev->d_ipv6[0]; /* Don't be NULL */ #ifdef CONFIG_NETDEV_MULTIPLE_IPv6 uint8_t scope_dst = netdev_ipv6_get_scope(dst); - uint8_t scope_best = 0; /* All scope is larget than 0 */ + uint8_t scope_best = 0; /* All scopes are greater than 0 */ uint8_t pref_best = 0; int i; diff --git a/net/netdev/netdev_register.c b/net/netdev/netdev_register.c index 8fce60a85b..16b807e8db 100644 --- a/net/netdev/netdev_register.c +++ b/net/netdev/netdev_register.c @@ -178,12 +178,12 @@ static int get_ifindex(void) uint32_t devset; int ndx; - /* Try to postpone re-using interface indices as long as possible */ + /* Try to postpone reusing interface indices as long as possible */ devset = g_devset | g_devfreed; if (devset == 0xffffffff) { - /* Time start re-using interface indices */ + /* Time start reusing interface indices */ devset = g_devset; g_devfreed = 0; diff --git a/net/route/fileroute.h b/net/route/fileroute.h index a5e5ae41f4..d7731c67a5 100644 --- a/net/route/fileroute.h +++ b/net/route/fileroute.h @@ -84,7 +84,7 @@ int net_openroute_ipv6(int oflags, FAR struct file *filep); * route - Location to return the next route read from the file * * Returned Value: - * The number of bytes read on success. The special return valud of zero + * The number of bytes read on success. The special return value of zero * indicates that the endof of file was encountered (and nothing was read). * A negated errno value is returned on any failure. * diff --git a/net/route/net_fileroute.c b/net/route/net_fileroute.c index 9e2b109fcb..97fe1f2584 100644 --- a/net/route/net_fileroute.c +++ b/net/route/net_fileroute.c @@ -265,7 +265,7 @@ int net_openroute_ipv6(int oflags, FAR struct file *filep) * route - Location to return the next route read from the file * * Returned Value: - * The number of bytes read on success. The special return valud of zero + * The number of bytes read on success. The special return value of zero * indicates that the endof of file was encountered (and nothing was read). * A negated errno value is returned on any failure. * diff --git a/net/sixlowpan/sixlowpan.h b/net/sixlowpan/sixlowpan.h index add4d184b8..236b822c7d 100644 --- a/net/sixlowpan/sixlowpan.h +++ b/net/sixlowpan/sixlowpan.h @@ -98,7 +98,7 @@ ssize_t psock_6lowpan_tcp_send(FAR struct socket *psock, FAR const void *buf, * Name: sixlowpan_tcp_send * * Description: - * TCP output comes through three different mechansims. Either from: + * TCP output comes through three different mechanisms. Either from: * * 1. TCP socket output. For the case of TCP output to an * IEEE802.15.4, the TCP output is caught in the socket diff --git a/net/sixlowpan/sixlowpan_framelist.c b/net/sixlowpan/sixlowpan_framelist.c index 660b53177a..6354261087 100644 --- a/net/sixlowpan/sixlowpan_framelist.c +++ b/net/sixlowpan/sixlowpan_framelist.c @@ -540,7 +540,7 @@ int sixlowpan_queue_frames(FAR struct radio_driver_s *radio, /* The outbound IPv6 packet is too large to fit into a single 15.4 * packet, so we fragment it into multiple packets and send them. * The first fragment contains frag1 dispatch, then - * IPv6/HC1/HC06/HC_UDP dispatchs/headers. + * IPv6/HC1/HC06/HC_UDP dispatches/headers. * The following fragments contain only the fragn dispatch. */ diff --git a/net/sixlowpan/sixlowpan_input.c b/net/sixlowpan/sixlowpan_input.c index d5277ed466..d25602f76b 100644 --- a/net/sixlowpan/sixlowpan_input.c +++ b/net/sixlowpan/sixlowpan_input.c @@ -718,7 +718,7 @@ static int sixlowpan_dispatch(FAR struct radio_driver_s *radio) * radio, or (2) struct pktradio_metadata_s for a non-standard * packet radio. * - * If there are multilple frames in the list, this metadata + * If there are multiple frames in the list, this metadata * must apply to all of the frames in the list. * * Returned Value: diff --git a/net/sixlowpan/sixlowpan_reassbuf.c b/net/sixlowpan/sixlowpan_reassbuf.c index a0fd268feb..a9eaa07448 100644 --- a/net/sixlowpan/sixlowpan_reassbuf.c +++ b/net/sixlowpan/sixlowpan_reassbuf.c @@ -134,7 +134,7 @@ static void sixlowpan_reass_expire(void) next = reass->rb_flink; /* Free any inactive reassembly buffers. This is done because the life - * the reassembly buffer is not cerain. + * the reassembly buffer is not certain. */ if (!reass->rb_active) diff --git a/net/sixlowpan/sixlowpan_tcpsend.c b/net/sixlowpan/sixlowpan_tcpsend.c index 4156d5b6e7..693cf7c75d 100644 --- a/net/sixlowpan/sixlowpan_tcpsend.c +++ b/net/sixlowpan/sixlowpan_tcpsend.c @@ -812,7 +812,7 @@ ssize_t psock_6lowpan_tcp_send(FAR struct socket *psock, FAR const void *buf, * Name: sixlowpan_tcp_send * * Description: - * TCP output comes through three different mechansims. Either from: + * TCP output comes through three different mechanisms. Either from: * * 1. TCP socket output. For the case of TCP output to an * IEEE802.15.4, the TCP output is caught in the socket diff --git a/net/tcp/tcp.h b/net/tcp/tcp.h index 10dacf8b5b..4207d3085c 100644 --- a/net/tcp/tcp.h +++ b/net/tcp/tcp.h @@ -90,7 +90,7 @@ # endif #endif -/* 32-bit modular arithmetics for tcp sequence numbers */ +/* 32-bit modular arithmetic for tcp sequence numbers */ #define TCP_SEQ_LT(a, b) ((int32_t)((a) - (b)) < 0) #define TCP_SEQ_GT(a, b) TCP_SEQ_LT(b, a) @@ -200,7 +200,7 @@ struct tcp_conn_s * attempted. * TCP_SNDACK - If TCP_NEWDATA is cleared, then TCP_SNDACK may be set to * indicate that an ACK should be included in the response. - * (In TCP_NEWDATA is cleared bu TCP_SNDACK is not set, + * (In TCP_NEWDATA is cleared but TCP_SNDACK is not set, * then dev->d_len should also be cleared). */ @@ -243,7 +243,7 @@ struct tcp_conn_s uint16_t user_mss; /* Configured maximum segment size for the * connection */ #endif - uint32_t rcv_adv; /* The right edge of the recv window advertized */ + uint32_t rcv_adv; /* The right edge of the recv window advertised */ #ifdef CONFIG_NET_TCP_CC_NEWRENO uint32_t last_ackno; /* The ack number at the last receive ack */ uint32_t dupacks; /* The number of duplicate ack */ @@ -282,7 +282,7 @@ struct tcp_conn_s sclock_t ltimeout; /* Linger timeout expiration */ #endif #ifdef CONFIG_NETDEV_RSS - int rcvcpu; /* Currect cpu id */ + int rcvcpu; /* Current cpu id */ #endif /* If the TCP socket is bound to a local address, then this is * a reference to the device that routes traffic on the corresponding @@ -1196,7 +1196,7 @@ void tcp_reset(FAR struct net_driver_s *dev, FAR struct tcp_conn_s *conn); * Name: tcp_rx_mss * * Description: - * Return the MSS to advertize to the peer. + * Return the MSS to advertise to the peer. * * Input Parameters: * dev - The device driver structure @@ -1730,7 +1730,7 @@ uint32_t tcp_get_recvwindow(FAR struct net_driver_s *dev, * Name: tcp_should_send_recvwindow * * Description: - * Determine if we should advertize the new recv window to the peer. + * Determine if we should advertise the new recv window to the peer. * * Input Parameters: * conn - The TCP connection structure holding connection information. @@ -2272,7 +2272,7 @@ void tcp_cc_init(FAR struct tcp_conn_s *conn); * Name: tcp_cc_update * * Description: - * Update the congestion control variables when recieve the SYNACK/ACK + * Update the congestion control variables when receive the SYNACK/ACK * packet from the peer in the connection phase. * * Input Parameters: diff --git a/net/tcp/tcp_cc.c b/net/tcp/tcp_cc.c index f6207db541..6681274870 100644 --- a/net/tcp/tcp_cc.c +++ b/net/tcp/tcp_cc.c @@ -123,7 +123,7 @@ void tcp_cc_init(FAR struct tcp_conn_s *conn) * Name: tcp_cc_update * * Description: - * Update the congestion control variables when recieve the SYNACK/ACK + * Update the congestion control variables when receive the SYNACK/ACK * packet from the peer in the connection phase. * * Input Parameters: diff --git a/net/tcp/tcp_conn.c b/net/tcp/tcp_conn.c index 153f92b348..6bccd8741a 100644 --- a/net/tcp/tcp_conn.c +++ b/net/tcp/tcp_conn.c @@ -679,7 +679,7 @@ FAR struct tcp_conn_s *tcp_alloc(uint8_t domain) tmp = (FAR struct tcp_conn_s *)tmp->sconn.node.flink; } - /* Did we find a connection that we can re-use? */ + /* Did we find a connection that we can reuse? */ if (conn != NULL) { diff --git a/net/tcp/tcp_input.c b/net/tcp/tcp_input.c index 5498dbf69c..8d23d8f1fe 100644 --- a/net/tcp/tcp_input.c +++ b/net/tcp/tcp_input.c @@ -276,7 +276,7 @@ static bool tcp_snd_wnd_update(FAR struct tcp_conn_s *conn, * Input Parameters: * conn - The TCP connection of interest * ofoseg - Pointer to incoming out-of-order segment - * start - Index of start postion of segment pool + * start - Index of start position of segment pool * * Returned Value: * True if incoming data has been consumed diff --git a/net/tcp/tcp_send.c b/net/tcp/tcp_send.c index 06fb576e0f..9e6dd4e523 100644 --- a/net/tcp/tcp_send.c +++ b/net/tcp/tcp_send.c @@ -533,7 +533,7 @@ void tcp_reset(FAR struct net_driver_s *dev, FAR struct tcp_conn_s *conn) * Name: tcp_rx_mss * * Description: - * Return the MSS to advertize to the peer. + * Return the MSS to advertise to the peer. * * Input Parameters: * dev - The device driver structure diff --git a/net/udp/udp_conn.c b/net/udp/udp_conn.c index 553401adee..538a443e89 100644 --- a/net/udp/udp_conn.c +++ b/net/udp/udp_conn.c @@ -112,7 +112,7 @@ static dq_queue_t g_active_udp_connections; * ipaddr - The IP address to use in the lookup * portno - The port to use in the lookup * opt - The option from another conn to match the conflict conn - * SO_REUSEADDR: If both sockets have this, they never confilct. + * SO_REUSEADDR: If both sockets have this, they never conflict. * * Assumptions: * This function must be called with the network locked. diff --git a/net/usrsock/usrsock_devif.c b/net/usrsock/usrsock_devif.c index 31a9dbd172..0f0e55430b 100644 --- a/net/usrsock/usrsock_devif.c +++ b/net/usrsock/usrsock_devif.c @@ -54,7 +54,7 @@ struct usrsock_req_s mutex_t lock; /* Request mutex (only one outstanding * request) */ sem_t acksem; /* Request acknowledgment notification */ - uint32_t newxid; /* New transcation Id */ + uint32_t newxid; /* New transaction Id */ uint32_t ackxid; /* Exchange id for which waiting ack */ uint16_t nbusy; /* Number of requests blocked from different * threads */ diff --git a/net/usrsock/usrsock_sockif.c b/net/usrsock/usrsock_sockif.c index 13a2a311b1..485528db7e 100644 --- a/net/usrsock/usrsock_sockif.c +++ b/net/usrsock/usrsock_sockif.c @@ -138,7 +138,7 @@ static int usrsock_sockif_setup(FAR struct socket *psock) * queried. * * Returned Value: - * The non-negative set of socket cababilities is returned. + * The non-negative set of socket capabilities is returned. * ****************************************************************************/ diff --git a/net/utils/net_ipchksum.c b/net/utils/net_ipchksum.c index ee2a8fcb09..2ca383b881 100644 --- a/net/utils/net_ipchksum.c +++ b/net/utils/net_ipchksum.c @@ -188,7 +188,7 @@ uint16_t ipv6_upperlayer_header_chksum(FAR struct net_driver_s *dev, DEBUGASSERT(dev != NULL && iplen >= IPv6_HDRLEN); /* The length reported in the IPv6 header is the length of the payload - * that follows the header. If extension heders are present, then this + * that follows the header. If extension headers are present, then this * size includes the size of the IPv6 extension headers. */ diff --git a/net/utils/net_lock.c b/net/utils/net_lock.c index 033d99b0f0..de27e3bc44 100644 --- a/net/utils/net_lock.c +++ b/net/utils/net_lock.c @@ -129,7 +129,7 @@ _net_timedwait(FAR sem_t *sem, bool interruptible, unsigned int timeout) * * Returned Value: * Zero (OK) is returned on success; a negated errno value is returned on - * failured (probably -ECANCELED). + * failure (probably -ECANCELED). * ****************************************************************************/ @@ -151,7 +151,7 @@ int net_lock(void) * * Returned Value: * Zero (OK) is returned on success; a negated errno value is returned on - * failured (probably -EAGAIN). + * failure (probably -EAGAIN). * ****************************************************************************/ @@ -202,7 +202,7 @@ int net_breaklock(FAR unsigned int *count) * * Returned Value: * Zero (OK) is returned on success; a negated errno value is returned on - * failured (probably -ECANCELED). + * failure (probably -ECANCELED). * ****************************************************************************/ diff --git a/net/utils/net_mask2pref.c b/net/utils/net_mask2pref.c index 1f8c019383..98a546906b 100644 --- a/net/utils/net_mask2pref.c +++ b/net/utils/net_mask2pref.c @@ -132,7 +132,7 @@ static inline uint8_t net_msbits16(uint16_t hword) * This, of course, assumes that all MS bits are '1' and all LS bits are * '0' with no intermixed 1's and 0's. This function searches from the MS * bit until the first '0' is found (this does not necessary mean that - * there might not be additional '1' bits following the firs '0', but that + * there might not be additional '1' bits following the first '0', but that * will be a malformed netmask. * * Input Parameters: @@ -172,7 +172,7 @@ uint8_t net_ipv4_mask2pref(in_addr_t mask) * This, of course, assumes that all MS bits are '1' and all LS bits are * '0' with no intermixed 1's and 0's. This function searches from the MS * bit until the first '0' is found (this does not necessary mean that - * there might not be additional '1' bits following the firs '0', but that + * there might not be additional '1' bits following the first '0', but that * will be a malformed netmask. * * Input Parameters: diff --git a/net/utils/utils.h b/net/utils/utils.h index 66059ddfec..cc7127ab5d 100644 --- a/net/utils/utils.h +++ b/net/utils/utils.h @@ -172,7 +172,7 @@ int net_breaklock(FAR unsigned int *count); * * Returned Value: * Zero (OK) is returned on success; a negated errno value is returned on - * failured (probably -ECANCELED). + * failure (probably -ECANCELED). * ****************************************************************************/ @@ -247,7 +247,7 @@ unsigned int net_timeval2dsec(FAR struct timeval *tv, * This, of course, assumes that all MS bits are '1' and all LS bits are * '0' with no intermixed 1's and 0's. This function searches from the MS * bit until the first '0' is found (this does not necessary mean that - * there might not be additional '1' bits following the firs '0', but that + * there might not be additional '1' bits following the first '0', but that * will be a malformed netmask. * * Input Parameters: @@ -294,7 +294,7 @@ uint8_t net_ipv6_common_pref(FAR const uint16_t *a1, FAR const uint16_t *a2); * This, of course, assumes that all MS bits are '1' and all LS bits are * '0' with no intermixed 1's and 0's. This function searches from the MS * bit until the first '0' is found (this does not necessary mean that - * there might not be additional '1' bits following the firs '0', but that + * there might not be additional '1' bits following the first '0', but that * will be a malformed netmask. * * Input Parameters: diff --git a/openamp/0001-ns-acknowledge-the-received-creation-message.patch b/openamp/0001-ns-acknowledge-the-received-creation-message.patch index a7b1fb87df..0fa6d3f39c 100644 --- a/openamp/0001-ns-acknowledge-the-received-creation-message.patch +++ b/openamp/0001-ns-acknowledge-the-received-creation-message.patch @@ -3,7 +3,7 @@ From: Xiang Xiao Date: Mon, 7 Jan 2019 02:15:42 +0800 Subject: [PATCH 01/14] ns: acknowledge the received creation message -the two phase handsake make the client could initiate the transfer +the two phase handshake make the client could initiate the transfer immediately without the server side send any dummy message first. Signed-off-by: Xiang Xiao @@ -69,7 +69,7 @@ index 27b0f0d..1011b42 100644 RPMSG_NS_CREATE = 0, /** A known remote service was just destroyed */ RPMSG_NS_DESTROY = 1, -+ /** Aknowledge the previous creation message*/ ++ /** Acknowledge the previous creation message*/ + RPMSG_NS_CREATE_ACK = 2, }; diff --git a/openamp/0011-virtio-change-feature-to-64-bit-in-all-virtio_dispat.patch b/openamp/0011-virtio-change-feature-to-64-bit-in-all-virtio_dispat.patch index 7b359c3f83..03649ff071 100644 --- a/openamp/0011-virtio-change-feature-to-64-bit-in-all-virtio_dispat.patch +++ b/openamp/0011-virtio-change-feature-to-64-bit-in-all-virtio_dispat.patch @@ -3,7 +3,7 @@ From: Yongrong Wang Date: Wed, 10 Jul 2024 18:47:33 +0800 Subject: [PATCH 11/14] virtio: change feature to 64 bit in all virtio_dispatch -The virtio device feature bit has exceeded 32 bits, so change feautre +The virtio device feature bit has exceeded 32 bits, so change feature to 64 bit like linux does to support more features Signed-off-by: Yongrong Wang diff --git a/sched/group/group_childstatus.c b/sched/group/group_childstatus.c index 315c7fc879..1485d9a81c 100644 --- a/sched/group/group_childstatus.c +++ b/sched/group/group_childstatus.c @@ -310,7 +310,7 @@ FAR struct child_status_s *group_exit_child(FAR struct task_group_s *group) { FAR struct child_status_s *child; - /* Find the status structure of any child task that has exitted. */ + /* Find the status structure of any child task that has exited. */ for (child = group->tg_children; child; child = child->flink) { diff --git a/sched/irq/irq_attach_thread.c b/sched/irq/irq_attach_thread.c index 16c8e5fcbc..8c893a3002 100644 --- a/sched/irq/irq_attach_thread.c +++ b/sched/irq/irq_attach_thread.c @@ -37,7 +37,7 @@ #include "sched/sched.h" /**************************************************************************** - * Privte Types + * Private Types ****************************************************************************/ /* This is the type of the list of interrupt handlers, one for each IRQ. diff --git a/sched/irq/irq_attach_wqueue.c b/sched/irq/irq_attach_wqueue.c index 8d404e5de3..7a63d8cacc 100644 --- a/sched/irq/irq_attach_wqueue.c +++ b/sched/irq/irq_attach_wqueue.c @@ -37,7 +37,7 @@ #include "sched/sched.h" /**************************************************************************** - * Privte Types + * Private Types ****************************************************************************/ /* This is the type of the list of interrupt handlers, one for each IRQ. diff --git a/sched/mqueue/mq_send.c b/sched/mqueue/mq_send.c index 241bd3cd25..b95d266d7a 100644 --- a/sched/mqueue/mq_send.c +++ b/sched/mqueue/mq_send.c @@ -251,7 +251,7 @@ static void nxmq_add_queue(FAR struct mqueue_inode_s *msgq, * msg - Message to send * msglen - The length of the message in bytes * prio - The priority of the message - * abstime - the absolute time to wait until a timeout is decleared + * abstime - the absolute time to wait until a timeout is declared * ticks - Ticks to wait from the start time until the semaphore is * posted. * @@ -397,7 +397,7 @@ out: * msg - Message to send * msglen - The length of the message in bytes * prio - The priority of the message - * abstime - the absolute time to wait until a timeout is decleared + * abstime - the absolute time to wait until a timeout is declared * * Returned Value: * This is an internal OS interface and should not be used by applications. @@ -495,7 +495,7 @@ int file_mq_ticksend(FAR struct file *mq, FAR const char *msg, * msg - Message to send * msglen - The length of the message in bytes * prio - The priority of the message - * abstime - the absolute time to wait until a timeout is decleared + * abstime - the absolute time to wait until a timeout is declared * * Returned Value: * This is an internal OS interface and should not be used by applications. @@ -563,7 +563,7 @@ int nxmq_timedsend(mqd_t mqdes, FAR const char *msg, size_t msglen, * msg - Message to send * msglen - The length of the message in bytes * prio - The priority of the message - * abstime - the absolute time to wait until a timeout is decleared + * abstime - the absolute time to wait until a timeout is declared * * Returned Value: * On success, mq_send() returns 0 (OK); on error, -1 (ERROR) diff --git a/sched/pthread/pthread_exit.c b/sched/pthread/pthread_exit.c index c20eeebd75..494a00c340 100644 --- a/sched/pthread/pthread_exit.c +++ b/sched/pthread/pthread_exit.c @@ -84,7 +84,7 @@ void nx_pthread_exit(FAR void *exit_value) status = pthread_completejoin(nxsched_gettid(), exit_value); if (status != OK) { - /* Assume that the join completion failured because this + /* Assume that the join completion failed because this is * not really a pthread. Exit by calling exit(). */ diff --git a/sched/pthread/pthread_mutex.c b/sched/pthread/pthread_mutex.c index 24a063908f..34ecada6be 100644 --- a/sched/pthread/pthread_mutex.c +++ b/sched/pthread/pthread_mutex.c @@ -353,12 +353,12 @@ int pthread_mutex_restorelock(FAR struct pthread_mutex_s *mutex, * Description: * This function is called when a pthread is terminated via either * pthread_exit() or pthread_cancel(). It will check for any mutexes - * held by exitting thread. It will mark them as inconsistent and + * held by exiting thread. It will mark them as inconsistent and * then wake up the highest priority waiter for the mutex. That * instance of pthread_mutex_lock() will then return EOWNERDEAD. * * Input Parameters: - * tcb -- a reference to the TCB of the exitting pthread. + * tcb -- a reference to the TCB of the exiting pthread. * * Returned Value: * None. diff --git a/sched/pthread/pthread_mutextrylock.c b/sched/pthread/pthread_mutextrylock.c index ecf791e3cb..e4cee0aa02 100644 --- a/sched/pthread/pthread_mutextrylock.c +++ b/sched/pthread/pthread_mutextrylock.c @@ -100,7 +100,7 @@ int pthread_mutex_trylock(FAR pthread_mutex_t *mutex) /* The calling thread does not hold the semaphore. The correct * behavior for the 'robust' mutex is to verify that the holder of * the mutex is still valid. This is protection from the case - * where the holder of the mutex has exitted without unlocking it. + * where the holder of the mutex has exited without unlocking it. */ #ifdef CONFIG_PTHREAD_MUTEX_BOTH diff --git a/sched/sched/sched_releasetcb.c b/sched/sched/sched_releasetcb.c index ba830abd6a..52ce5f3159 100644 --- a/sched/sched/sched_releasetcb.c +++ b/sched/sched/sched_releasetcb.c @@ -46,7 +46,7 @@ * Name: nxsched_releasepid * * Description: When a task is destroyed, this function must - * be called to make its process ID available for re-use. + * be called to make its process ID available for reuse. ****************************************************************************/ static void nxsched_releasepid(pid_t pid) diff --git a/sched/signal/sig_action.c b/sched/signal/sig_action.c index 731ff9c70c..096864aba9 100644 --- a/sched/signal/sig_action.c +++ b/sched/signal/sig_action.c @@ -390,7 +390,7 @@ int nxsig_action(int signo, FAR const struct sigaction *act, else { /* Do we still have a sigaction container from the previous setting? - * If so, then re-use for the new signal action. + * If so, then reuse for the new signal action. */ if (sigact == NULL) diff --git a/sched/signal/sig_default.c b/sched/signal/sig_default.c index 0d1547c064..957ce3b2dc 100644 --- a/sched/signal/sig_default.c +++ b/sched/signal/sig_default.c @@ -511,7 +511,7 @@ bool nxsig_iscatchable(int signo) * defaction - True: the default action is in place * * Returned Value: - * The address of the default signal action handler is return on success. + * The address of the default signal action handler is returned on success. * SIG_IGN is returned if there is no default action. * ****************************************************************************/ diff --git a/sched/task/task_activate.c b/sched/task/task_activate.c index 1fcba2695e..5c71f9131b 100644 --- a/sched/task/task_activate.c +++ b/sched/task/task_activate.c @@ -82,7 +82,7 @@ void nxtask_activate(FAR struct tcb_s *tcb) sched_note_start(tcb); #endif - /* Remove the task from waitting list */ + /* Remove the task from waiting list */ nxsched_remove_blocked(tcb); diff --git a/sched/task/task_setup.c b/sched/task/task_setup.c index 2fa39a0ef2..7b893b4b3b 100644 --- a/sched/task/task_setup.c +++ b/sched/task/task_setup.c @@ -157,7 +157,7 @@ retry: return -ENOMEM; } - /* Handle conner case: context siwtch happened when kmm_malloc */ + /* Handle conner case: context switch happened when kmm_malloc */ flags = enter_critical_section(); if (temp != g_pidhash) diff --git a/tools/ci/docker/linux/Dockerfile b/tools/ci/docker/linux/Dockerfile index 6e361023c3..e326c07234 100644 --- a/tools/ci/docker/linux/Dockerfile +++ b/tools/ci/docker/linux/Dockerfile @@ -16,7 +16,7 @@ # under the License. FROM ubuntu:22.04 AS builder-base -# NOTE WE ARE NOT REMOVEING APT CACHE. +# NOTE WE ARE NOT REMOVING APT CACHE. # This should only be used for temp build images that artifacts will be copied from RUN apt-get update -qq && apt-get install -y -qq \ curl \ diff --git a/tools/ci/testrun/README.md b/tools/ci/testrun/README.md index 5bafd29120..baf14ba664 100644 --- a/tools/ci/testrun/README.md +++ b/tools/ci/testrun/README.md @@ -7,7 +7,7 @@ sudo apt-get install minicom cd env pip3 install -r requirements.txt ``` -# Pytest Original Parameter useage refer to help +# Pytest Original Parameter usage refer to help # Customized Parameters ```bash pytest diff --git a/tools/ci/testrun/utils/common.py b/tools/ci/testrun/utils/common.py index cd40fc0afb..b5d76a6879 100644 --- a/tools/ci/testrun/utils/common.py +++ b/tools/ci/testrun/utils/common.py @@ -326,9 +326,9 @@ class start: def startSerial(self, dev, board, log_path, core, rate): self.log = "{}/{}_{}.cap".format(log_path, dev[-4:], self.start_time) self.logFile = open(self.log, "ab+") - self.ser = serial.Serial(port=dev, baudrate=int(rate)) + self.set = serial.Serial(port=dev, baudrate=int(rate)) self.process = pexpect.fdpexpect.fdspawn( - self.ser, "wb", maxread=20000, logfile=self.logFile + self.set, "wb", maxread=20000, logfile=self.logFile ) self.switch_to_original_core() diff --git a/tools/configure.c b/tools/configure.c index 579976f210..f9d76daf77 100644 --- a/tools/configure.c +++ b/tools/configure.c @@ -120,7 +120,7 @@ static char g_delim = '/'; /* Delimiter to use when forming pat static bool g_winpaths = false; /* False: POSIX style paths */ #endif static bool g_debug = false; /* Enable debug output */ -static bool g_enforce = false; /* Enfore distclean */ +static bool g_enforce = false; /* Enforce distclean */ static bool g_distclean = false; /* Distclean if configured */ static const char *g_appdir = NULL; /* Relative path to the application directory */ diff --git a/tools/copydir.bat b/tools/copydir.bat index a580aae802..ace2ebb82f 100755 --- a/tools/copydir.bat +++ b/tools/copydir.bat @@ -28,7 +28,7 @@ rem links do not work correctly when accessed from the Windows native toolchain; rem rather, just look link files with the extension .lnk rem rem In this environment, the build system will work around this using this script -rem as a replacement for the 'ln' command. This scrpt will simply copy the +rem as a replacement for the 'ln' command. This script will simply copy the rem directory into the expected positiion. rem diff --git a/tools/copydir.sh b/tools/copydir.sh index 7d18baa048..3cd31ca43c 100755 --- a/tools/copydir.sh +++ b/tools/copydir.sh @@ -28,7 +28,7 @@ # rather, just look link files with the extension .lnk # # In this environment, the build system will work around this using this script -# as a replacement for the 'ln' command. This scrpt will simply copy the +# as a replacement for the 'ln' command. This script will simply copy the # directory into the expected positiion. # #set -x diff --git a/tools/define.bat b/tools/define.bat index aef2ae9532..67c71d2665 100755 --- a/tools/define.bat +++ b/tools/define.bat @@ -147,7 +147,7 @@ goto :End :ShowUsage echo %progname% is a tool for flexible generation of command line pre-processor -echo definitions arguments for a variety of diffent ccpaths in a variety of +echo definitions arguments for a variety of different ccpaths in a variety of echo compilation environments" echo USAGE:%progname% [-h] ^ ^[=^] [^[=^] [^[=^] ...]] echo Where:" diff --git a/tools/define.sh b/tools/define.sh index bb86fd6dd1..43346c4281 100755 --- a/tools/define.sh +++ b/tools/define.sh @@ -38,7 +38,7 @@ while [ ! -z "$1" ]; do ;; -h ) echo "$progname is a tool for flexible generation of command line pre-processor" - echo "definitions arguments for a variety of diffent compilers in a variety of" + echo "definitions arguments for a variety of different compilers in a variety of" echo "compilation environments" echo "" echo $usage diff --git a/tools/doreleasenotes.py b/tools/doreleasenotes.py index d2ccf7b164..651f91ce8c 100644 --- a/tools/doreleasenotes.py +++ b/tools/doreleasenotes.py @@ -51,7 +51,7 @@ def doreleasenotes(release, gh_token): print(str(br.name) + " " + str(commiter_date.isoformat())) - # Generate ther release notes + # Generate the release notes print("\n") print("Please select a range for release notes generation") print("Date times should be in the GitHub format as listed here:") diff --git a/tools/kconfig2html.c b/tools/kconfig2html.c index e815706e24..9c973718a2 100644 --- a/tools/kconfig2html.c +++ b/tools/kconfig2html.c @@ -378,7 +378,7 @@ static void show_usage(const char *progname, int exitcode) error(" %s [-h]\n\n", progname); error("Where:\n\n"); error("\t-a : Select relative path to the apps/ directory." - " Theis path is relative\n"); + " This path is relative\n"); error("\t to the . Default: ../apps\n"); error("\t-o : Send output to . " "Default: Output goes to stdout\n"); @@ -2720,7 +2720,7 @@ int main(int argc, char **argv, char **envp) "Appendix A: Hidden Configuration Variables\n"); output("\n"); - /* Close the HMTL body file and copy it to the output file */ + /* Close the HTML body file and copy it to the output file */ fclose(g_bodyfile); append_file(BODYFILE_NAME); diff --git a/tools/mkfsdata.py b/tools/mkfsdata.py index d64951266b..57254d8885 100755 --- a/tools/mkfsdata.py +++ b/tools/mkfsdata.py @@ -139,7 +139,7 @@ def main(): # write content for file, r_full_path in files: write_f_data(fd, file, r_full_path, args.add_progmem) - fd.write("\n") # Add empty line beetween files + fd.write("\n") # Add empty line between files # write list of files prev_file = None diff --git a/tools/parsetrace.py b/tools/parsetrace.py index 897fffd021..205969fa09 100755 --- a/tools/parsetrace.py +++ b/tools/parsetrace.py @@ -170,7 +170,7 @@ class SymbolTables(object): index = bisect.bisect(self.addr_list, addr) if index != -1: return self.symbol_dict[self.addr_list[index - 1]] - return "<%#x>: unknow function" % addr + return "<%#x>: unknown function" % addr class OtherModel(BaseModel): diff --git a/tools/pynuttx/nxgdb/dmesg.py b/tools/pynuttx/nxgdb/dmesg.py index c4c8b02809..6e49563dec 100644 --- a/tools/pynuttx/nxgdb/dmesg.py +++ b/tools/pynuttx/nxgdb/dmesg.py @@ -56,7 +56,7 @@ class Dmesg(gdb.Command): def _get_rpmsg_syslog(self): if not (priv := utils.gdb_eval_or_none("g_syslog_rpmsg")): - return "RPMsg syslog not avaliable" + return "RPMsg syslog not available" buffer = bytes(gdb.selected_inferior().read_memory(priv.buffer, priv.size)) buf = buffer.replace(b"\0", "␀".encode("utf-8")) diff --git a/tools/pynuttx/nxgdb/fs.py b/tools/pynuttx/nxgdb/fs.py index 4db3f25e13..0ebbc9d173 100644 --- a/tools/pynuttx/nxgdb/fs.py +++ b/tools/pynuttx/nxgdb/fs.py @@ -141,7 +141,7 @@ def get_inode_name(inode: p.Inode): def inode_getpath(inode: p.Inode): - """get path fron inode""" + """get path from inode""" try: if not inode: return "" diff --git a/tools/pynuttx/nxgdb/macros.py b/tools/pynuttx/nxgdb/macros.py index d1d9fa7826..ecde5ab971 100644 --- a/tools/pynuttx/nxgdb/macros.py +++ b/tools/pynuttx/nxgdb/macros.py @@ -117,7 +117,7 @@ def parse_macro(line, macros, pattern): # for now I think it's ok just overwrite the old value pass - # emplace, for all undefined macros we evalute it to zero + # emplace, for all undefined macros we evaluate it to zero macros[name] = value if value else "0" return True diff --git a/tools/pynuttx/nxgdb/stack.py b/tools/pynuttx/nxgdb/stack.py index 132cb9a84d..1ab40be638 100644 --- a/tools/pynuttx/nxgdb/stack.py +++ b/tools/pynuttx/nxgdb/stack.py @@ -60,7 +60,7 @@ class Stack(object): size: {self._stack_size}, sp: {self._cur_sp}\n" ) - raise gdb.GdbError("Inconsistant stack size...Maybe memory corruption?") + raise gdb.GdbError("Inconsistent stack size...Maybe memory corruption?") # TODO: check if stack ptr is located at a sane address range! diff --git a/tools/pynuttx/nxgdb/thread.py b/tools/pynuttx/nxgdb/thread.py index a1e98f40d8..d33e869b0a 100644 --- a/tools/pynuttx/nxgdb/thread.py +++ b/tools/pynuttx/nxgdb/thread.py @@ -450,7 +450,7 @@ class Ps(gdb.Command): def __init__(self): super().__init__("ps", gdb.COMMAND_USER) self._fmt_wxl = "{0: <{width}}" - # By default we align to the right, whcih respects the nuttx foramt + # By default we align to the right, which respects the nuttx format self._fmt_wx = "{0: >{width}}" def parse_and_show_info(self, tcb): diff --git a/tools/pynuttx/nxgdb/utils.py b/tools/pynuttx/nxgdb/utils.py index 0e0ad946e1..c627382a52 100644 --- a/tools/pynuttx/nxgdb/utils.py +++ b/tools/pynuttx/nxgdb/utils.py @@ -688,7 +688,7 @@ def is_target_arch(arch, exact=False): def is_target_smp(): - """Return Ture if the target use smp""" + """Return True if the target use smp""" if gdb.lookup_global_symbol("g_assignedtasks"): return True diff --git a/tools/uncrustify.cfg b/tools/uncrustify.cfg index 7e05e70906..8f45321721 100644 --- a/tools/uncrustify.cfg +++ b/tools/uncrustify.cfg @@ -141,7 +141,7 @@ align_on_tabstop = true # align on tabstops align_keep_tabs = false # Don't keep non-indenting tabs align_enum_equ_span = 2 # '=' in enum definition align_nl_cont = true # Align macros wrapped wht \n -align_var_def_span = 2 # Span for aligning varialbe definitions +align_var_def_span = 2 # Span for aligning variable definitions align_var_def_inline = true # Align union/struct variable definitions align_var_def_star_style = 2 # 2=Dangling align_var_def_colon = true # Align colons in bit field definitions diff --git a/wireless/ieee802154/mac802154_internal.h b/wireless/ieee802154/mac802154_internal.h index dc7434e586..adda665167 100644 --- a/wireless/ieee802154/mac802154_internal.h +++ b/wireless/ieee802154/mac802154_internal.h @@ -95,8 +95,8 @@ enum mac802154_operation_e }; /* The privmac structure holds the internal state of the MAC and is the - * underlying represention of the opaque MACHANDLE. It contains storage for - * the IEEE802.15.4 MIB attributes. + * underlying representation of the opaque MACHANDLE. It contains storage + * for the IEEE802.15.4 MIB attributes. */ struct ieee802154_privmac_s @@ -200,7 +200,7 @@ struct ieee802154_privmac_s /****************** Fields related to offloading work *********************/ - /* Work structures for offloading aynchronous work */ + /* Work structures for offloading asynchronous work */ struct work_s txdone_work; struct work_s rx_work;