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arch: arm: armv7-a: fix nxstyle errors

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Fix nxstyle errors to pass CI

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
This commit is contained in:
Alin Jerpelea 2021-03-24 09:12:51 +01:00 • committed by Xiang Xiao
parent 1d1da330da
commit 3ea545e7f3
29 changed files with 563 additions and 424 deletions
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1
arch/arm/src/armv7-a/arm.h
View file

@ -48,6 +48,7 @@
# define PSR_MODE_HYP (26 << PSR_MODE_SHIFT) /* Hyp mode */
# define PSR_MODE_UND (27 << PSR_MODE_SHIFT) /* Undefined mode */
# define PSR_MODE_SYS (31 << PSR_MODE_SHIFT) /* System mode */
#define PSR_T_BIT (1 << 5) /* Bit 5: Thumb execution state bit */
#define PSR_MASK_SHIFT (6) /* Bits 6-8: Mask Bits */
#define PSR_MASK_MASK (7 << PSR_GE_SHIFT)

4
arch/arm/src/armv7-a/arm_addrenv.c
View file

@ -157,7 +157,9 @@ static int up_addrenv_initdata(uintptr_t l2table)
flags = enter_critical_section();
#ifdef CONFIG_ARCH_PGPOOL_MAPPING
/* Get the virtual address corresponding to the physical page table address */
/* Get the virtual address corresponding to the physical page table
* address
*/
virtptr = (FAR uint32_t *)arm_pgvaddr(l2table);
#else

4
arch/arm/src/armv7-a/arm_addrenv_utils.c
View file

@ -204,7 +204,9 @@ void arm_addrenv_destroy_region(FAR uintptr_t **list, unsigned int listlen,
flags = enter_critical_section();
#ifdef CONFIG_ARCH_PGPOOL_MAPPING
/* Get the virtual address corresponding to the physical page address */
/* Get the virtual address corresponding to the physical page
* address
*/
l2table = (FAR uint32_t *)arm_pgvaddr(paddr);
#else

31
arch/arm/src/armv7-a/arm_allocpage.c
View file

@ -72,11 +72,11 @@ typedef uint32_t L1ndx_t;
static pgndx_t g_pgndx;
/* After CONFIG_PAGING_NPAGED have been allocated, the pages will be re-used.
* In order to re-used the page, we will have un-map the page from its previous
* mapping. In order to that, we need to be able to map a physical address to
* to an index into the PTE where it was mapped. The following table supports
* this backward lookup - it is indexed by the page number index, and holds
* another index to the mapped virtual page.
* In order to re-used the page, we will have un-map the page from its
* previous mapping. In order to that, we need to be able to map a physical
* address to to an index into the PTE where it was mapped. The following
* table supports this backward lookup - it is indexed by the page number
* index, and holds another index to the mapped virtual page.
*/
static L1ndx_t g_ptemap[CONFIG_PAGING_NPPAGED];
@ -111,11 +111,12 @@ static bool g_pgwrap;
* NOTE 2: If an in-use page is un-mapped, it may be necessary to flush the
* instruction cache in some architectures.
*
* NOTE 3: Allocating and filling a page is a two step process. arm_allocpage()
* allocates the page, and up_fillpage() fills it with data from some non-
* volatile storage device. This distinction is made because arm_allocpage()
* can probably be implemented in board-independent logic whereas up_fillpage()
* probably must be implemented as board-specific logic.
* NOTE 3: Allocating and filling a page is a two step process.
* arm_allocpage() allocates the page, and up_fillpage() fills it with data
* from some non- volatile storage device. This distinction is made because
* arm_allocpage() can probably be implemented in board-independent logic
* whereas up_fillpage() probably must be implemented as board-specific
* logic.
*
* NOTE 4: The initial mapping of vpage should be read-able and write-
* able (but not cached). No special actions will be required of
@ -181,14 +182,16 @@ int arm_allocpage(FAR struct tcb_s *tcb, FAR void **vpage)
pte = arm_va2pte(oldvaddr);
*pte = 0;
/* Invalidate the instruction TLB corresponding to the virtual address */
/* Invalidate the instruction TLB corresponding to the virtual
* address
*/
tlb_inst_invalidate_single(oldvaddr);
/* I do not believe that it is necessary to flush the I-Cache in this
* case: The I-Cache uses a virtual address index and, hence, since the
* NuttX address space is flat, the cached instruction value should be
* correct even if the page mapping is no longer in place.
* case: The I-Cache uses a virtual address index and, hence, since
* the NuttX address space is flat, the cached instruction value should
* be correct even if the page mapping is no longer in place.
*/
}

6
arch/arm/src/armv7-a/arm_checkmapping.c
View file

@ -51,9 +51,9 @@
* tcb - A reference to the task control block of the task that we believe
* needs to have a page fill. Architecture-specific logic can
* retrieve page fault information from the architecture-specific
* context information in this TCB and can consult processor resources
* (page tables or TLBs or ???) to determine if the fill still needs
* to be performed or not.
* context information in this TCB and can consult processor
* resources (page tables or TLBs or ???) to determine if the fill
* still needs to be performed or not.
*
* Returned Value:
* This function will return true if the mapping is in place and false

4
arch/arm/src/armv7-a/arm_cpuhead.S
View file

@ -39,9 +39,9 @@
.file "arm_cpuhead.S"
/**********************************************************************************
/****************************************************************************
* Configuration
**********************************************************************************/
****************************************************************************/
/* Hard-coded options */

2
arch/arm/src/armv7-a/arm_cpuindex.c
View file

@ -59,7 +59,7 @@
int up_cpu_index(void)
{
/* Read the Multiprocessor Affinity Register (MPIDR) */
/* Read the Multiprocessor Affinity Register (MPIDR) */
uint32_t mpidr = cp15_rdmpidr();

12
arch/arm/src/armv7-a/arm_dataabort.c
View file

@ -51,8 +51,8 @@
* additional input values are expected:
*
* dfar - Fault address register. On a data abort, the ARM MMU places the
* miss virtual address (MVA) into the DFAR register. This is the address
* of the data which, when accessed, caused the fault.
* miss virtual address (MVA) into the DFAR register. This is the
* address of the data which, when accessed, caused the fault.
* dfsr - Fault status register. On a data a abort, the ARM MMU places an
* encoded four-bit value, the fault status, along with the four-bit
* encoded domain number, in the data DFSR
@ -69,8 +69,8 @@ uint32_t *arm_dataabort(uint32_t *regs, uint32_t dfar, uint32_t dfsr)
struct tcb_s *tcb = this_task();
uint32_t *savestate;
/* Save the saved processor context in CURRENT_REGS where it can be accessed
* for register dumps and possibly context switching.
/* Save the saved processor context in CURRENT_REGS where it can be
* accessed for register dumps and possibly context switching.
*/
savestate = (uint32_t *)CURRENT_REGS;
@ -147,8 +147,8 @@ segfault:
uint32_t *arm_dataabort(uint32_t *regs, uint32_t dfar, uint32_t dfsr)
{
/* Save the saved processor context in CURRENT_REGS where it can be accessed
* for register dumps and possibly context switching.
/* Save the saved processor context in CURRENT_REGS where it can be
* accessed for register dumps and possibly context switching.
*/
CURRENT_REGS = regs;

2
arch/arm/src/armv7-a/arm_doirq.c
View file

@ -213,7 +213,7 @@ uint32_t *arm_doirq(int irq, uint32_t *regs)
/* Dispatch the interrupt to its attached handler */
regs = _arm_doirq(irq, regs);
regs = _arm_doirq(irq, regs);
/* Then loop dispatching any pending SGI interrupts that occcurred during
* processing of the interrupts.

4
arch/arm/src/armv7-a/arm_head.S
View file

@ -37,9 +37,9 @@
.file "arm_head.S"
/**********************************************************************************
/****************************************************************************
* Configuration
**********************************************************************************/
****************************************************************************/
/* Hard-coded options */

5
arch/arm/src/armv7-a/arm_pghead.S
View file

@ -39,9 +39,10 @@
.file "arm_pghead.S"
/**********************************************************************************
/****************************************************************************
* Configuration
**********************************************************************************/
****************************************************************************/
/* Assume these are not needed */
#undef ALIGNMENT_TRAP

4
arch/arm/src/armv7-a/arm_pginitialize.c
View file

@ -51,8 +51,8 @@
* initialization
*
* Assumptions:
* - Called early in the platform initialization sequence so that no special
* concurrency protection is required.
* - Called early in the platform initialization sequence so that no
* special concurrency protection is required.
*
****************************************************************************/

19
arch/arm/src/armv7-a/arm_physpgaddr.c
View file

@ -89,22 +89,25 @@ uintptr_t arm_physpgaddr(uintptr_t vaddr)
/* Temporarily map the page into the virtual address space */
l1save = mmu_l1_getentry(ARCH_SCRATCH_VBASE);
mmu_l1_setentry(paddr & ~SECTION_MASK, ARCH_SCRATCH_VBASE, MMU_MEMFLAGS);
l2table = (FAR uint32_t *)(ARCH_SCRATCH_VBASE | (paddr & SECTION_MASK));
mmu_l1_setentry(paddr & ~SECTION_MASK,
ARCH_SCRATCH_VBASE, MMU_MEMFLAGS);
l2table = (FAR uint32_t *)(ARCH_SCRATCH_VBASE |
(paddr & SECTION_MASK));
#endif
if (l2table)
{
/* Invalidate D-Cache line containing this virtual address so that
* we re-read from physical memory
/* Invalidate D-Cache line containing this virtual address so
* that we re-read from physical memory
*/
index = (vaddr & SECTION_MASK) >> MM_PGSHIFT;
up_invalidate_dcache((uintptr_t)&l2table[index],
(uintptr_t)&l2table[index] + sizeof(uint32_t));
(uintptr_t)&l2table[index] +
sizeof(uint32_t));
/* Get the Level 2 page table entry corresponding to this virtual
* address. Extract the physical address of the page containing
* the mapping of the virtual address.
/* Get the Level 2 page table entry corresponding to this
* virtual address. Extract the physical address of the page
* containing the mapping of the virtual address.
*/
paddr = ((uintptr_t)l2table[index] & PTE_SMALL_PADDR_MASK);

32
arch/arm/src/armv7-a/arm_prefetchabort.c
View file

@ -53,19 +53,19 @@
uint32_t *arm_prefetchabort(uint32_t *regs, uint32_t ifar, uint32_t ifsr)
{
uint32_t *savestate;
uint32_t *savestate;
/* Save the saved processor context in CURRENT_REGS where it can be accessed
* for register dumps and possibly context switching.
/* Save the saved processor context in CURRENT_REGS where it can be
* accessed for register dumps and possibly context switching.
*/
savestate = (uint32_t *)CURRENT_REGS;
CURRENT_REGS = regs;
/* Get the (virtual) address of instruction that caused the prefetch abort.
* When the exception occurred, this address was provided in the lr register
* and this value was saved in the context save area as the PC at the
* REG_R15 index.
/* Get the (virtual) address of instruction that caused the prefetch
* abort. When the exception occurred, this address was provided in the
* lr register and this value was saved in the context save area as the
* PC at the REG_R15 index.
*
* Check to see if this miss address is within the configured range of
* virtual addresses.
@ -76,10 +76,10 @@ uint32_t *arm_prefetchabort(uint32_t *regs, uint32_t ifar, uint32_t ifsr)
if (regs[REG_R15] >= PG_PAGED_VBASE && regs[REG_R15] < PG_PAGED_VEND)
{
/* Save the offending PC as the fault address in the TCB of the currently
* executing task. This value is, of course, already known in regs[REG_R15],
* but saving it in this location will allow common paging logic for both
* prefetch and data aborts.
/* Save the offending PC as the fault address in the TCB of the
* currently executing task. This value is, of course, already known
* in regs[REG_R15], but saving it in this location will allow common
* paging logic for both prefetch and data aborts.
*/
struct tcb_s *tcb = this_task();
@ -99,9 +99,9 @@ uint32_t *arm_prefetchabort(uint32_t *regs, uint32_t ifar, uint32_t ifsr)
pg_miss();
/* Restore the previous value of CURRENT_REGS. NULL would indicate that
* we are no longer in an interrupt handler. It will be non-NULL if we
* are returning from a nested interrupt.
/* Restore the previous value of CURRENT_REGS.
* NULL would indicate thatwe are no longer in an interrupt handler.
* It will be non-NULL if we are returning from a nested interrupt.
*/
CURRENT_REGS = savestate;
@ -120,8 +120,8 @@ uint32_t *arm_prefetchabort(uint32_t *regs, uint32_t ifar, uint32_t ifsr)
uint32_t *arm_prefetchabort(uint32_t *regs, uint32_t ifar, uint32_t ifsr)
{
/* Save the saved processor context in CURRENT_REGS where it can be accessed
* for register dumps and possibly context switching.
/* Save the saved processor context in CURRENT_REGS where it can be
* accessed for register dumps and possibly context switching.
*/
CURRENT_REGS = regs;

20
arch/arm/src/armv7-a/arm_restorefpu.S
View file

@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/armv7-a/arm_restorefpu.S
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@ -16,11 +16,11 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************/
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
@ -30,19 +30,19 @@
.file "arm_restorefpu.S"
/************************************************************************************
/****************************************************************************
* Public Symbols
************************************************************************************/
****************************************************************************/
.globl arm_restorefpu
/************************************************************************************
/****************************************************************************
* Public Functions
************************************************************************************/
****************************************************************************/
.text
/************************************************************************************
/****************************************************************************
* Name: arm_restorefpu
*
* Description:
@ -60,7 +60,7 @@
* This function does not return anything explicitly. However, it is called from
* interrupt level assembly logic that assumes that r0 is preserved.
*
************************************************************************************/
****************************************************************************/
.globl arm_restorefpu
.type arm_restorefpu, function

24
arch/arm/src/armv7-a/arm_savefpu.S
View file

@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/armv7-a/arm_savefpu.S
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@ -16,11 +16,11 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************/
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
@ -30,23 +30,23 @@
.file "arm_savefpu.S"
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Public Symbols
************************************************************************************/
****************************************************************************/
.globl arm_savefpu
/************************************************************************************
/****************************************************************************
* Public Functions
************************************************************************************/
****************************************************************************/
.text
/************************************************************************************
/****************************************************************************
* Name: arm_savefpu
*
* Description:
@ -63,7 +63,7 @@
* Returned Value:
* None
*
************************************************************************************/
****************************************************************************/
.globl arm_savefpu
.type arm_savefpu, function

68
arch/arm/src/armv7-a/arm_vectors.S
View file

@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/armv7-a/arm_vectors.S
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@ -16,11 +16,11 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************/
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/irq.h>
@ -31,9 +31,9 @@
.file "arm_vectors.S"
/************************************************************************************
/****************************************************************************
* Private Data
************************************************************************************/
****************************************************************************/
.data
g_irqtmp:
@ -67,18 +67,18 @@ g_nestlevel:
#endif /* CONFIG_ARCH_INTERRUPTSTACK > 7 && CONFIG_ARMV7A_HAVE_GICv2 */
/************************************************************************************
/****************************************************************************
* Macro Definitions
************************************************************************************/
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Name: cpuindex
*
* Description:
* Return an index idenifying the current CPU. Single CPU case. Must be
* provided by MCU-specific logic in chip.h for the SMP case.
*
************************************************************************************/
****************************************************************************/
#if !defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7
.macro cpuindex, index
@ -86,14 +86,14 @@ g_nestlevel:
.endm
#endif
/************************************************************************************
/****************************************************************************
* Name: setirqstack
*
* Description:
* Set the current stack pointer to the "top" of the IRQ interrupt stack. Single
* CPU case. Must be provided by MCU-specific logic in chip.h for the SMP case.
*
************************************************************************************/
****************************************************************************/
#if !defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7
.macro setirqstack, tmp1, tmp2
@ -101,14 +101,14 @@ g_nestlevel:
.endm
#endif
/************************************************************************************
/****************************************************************************
* Name: setfiqstack
*
* Description:
* Set the current stack pointer to the "top" of the FIQ interrupt stack. Single
* CPU case. Must be provided by MCU-specific logic in chip.h for the SMP case.
*
************************************************************************************/
****************************************************************************/
#if !defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7
.macro setfiqstack, tmp1, tmp2
@ -116,23 +116,23 @@ g_nestlevel:
.endm
#endif
/************************************************************************************
/****************************************************************************
* Private Functions
************************************************************************************/
****************************************************************************/
.text
/************************************************************************************
/****************************************************************************
* Public Functions
************************************************************************************/
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Name: arm_vectorirq
*
* Description:
* Interrupt exception. Entered in IRQ mode with spsr = SVC CPSR, lr = SVC PC
*
************************************************************************************/
****************************************************************************/
.globl arm_decodeirq
.globl arm_vectorirq
@ -336,13 +336,13 @@ arm_vectorirq:
.size arm_vectorirq, . - arm_vectorirq
.align 5
/************************************************************************************
/****************************************************************************
* Function: arm_vectorsvc
*
* Description:
* SVC interrupt. We enter the SVC in SVC mode.
*
************************************************************************************/
****************************************************************************/
.globl arm_syscall
.globl arm_vectorsvc
@ -460,7 +460,7 @@ arm_vectorsvc:
.align 5
/************************************************************************************
/****************************************************************************
* Name: arm_vectordata
*
* Description:
@ -469,7 +469,7 @@ arm_vectorsvc:
* current processor state and gives control to data abort handler. This function
* is entered in ABORT mode with spsr = SVC CPSR, lr = SVC PC
*
************************************************************************************/
****************************************************************************/
.globl arm_dataabort
.globl arm_vectordata
@ -606,7 +606,7 @@ arm_vectordata:
.align 5
/************************************************************************************
/****************************************************************************
* Name: arm_vectorprefetch
*
* Description:
@ -615,7 +615,7 @@ arm_vectordata:
* handler saves the current processor state and gives control to prefetch abort
* handler. This function is entered in ABT mode with spsr = SVC CPSR, lr = SVC PC.
*
************************************************************************************/
****************************************************************************/
.globl arm_prefetchabort
.globl arm_vectorprefetch
@ -752,14 +752,14 @@ arm_vectorprefetch:
.align 5
/************************************************************************************
/****************************************************************************
* Name: arm_vectorundefinsn
*
* Description:
* Undefined instruction entry exception. Entered in UND mode, spsr = SVC CPSR,
* lr = SVC PC
*
************************************************************************************/
****************************************************************************/
.globl arm_undefinedinsn
.globl arm_vectorundefinsn
@ -893,14 +893,14 @@ arm_vectorundefinsn:
.align 5
/************************************************************************************
/****************************************************************************
* Name: arm_vectorfiq
*
* Description:
* Shouldn't happen unless a arm_decodefiq() is provided. FIQ is primarily used
* with the TrustZone feature in order to handle secure interrupts.
*
************************************************************************************/
****************************************************************************/
#ifdef CONFIG_ARMV7A_DECODEFIQ
.globl arm_decodefiq
@ -1051,9 +1051,9 @@ arm_vectorfiq:
#endif
.size arm_vectorfiq, . - arm_vectorfiq
/************************************************************************************
/****************************************************************************
* Name: g_intstackalloc/g_intstackbase
************************************************************************************/
****************************************************************************/
#if !defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7
.bss
@ -1071,9 +1071,9 @@ g_intstackbase:
.size g_intstackbase, 4
.size g_intstackalloc, (CONFIG_ARCH_INTERRUPTSTACK & ~7)
/************************************************************************************
/****************************************************************************
* Name: g_fiqstackalloc/g_fiqstackbase
************************************************************************************/
****************************************************************************/
.globl g_fiqstackalloc
.type g_fiqstackalloc, object

12
arch/arm/src/armv7-a/barriers.h
View file

@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/armv7-a/barriers.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@ -16,18 +16,18 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_COMMON_ARMV7_A_BARRIERS_H
#define __ARCH_ARM_SRC_COMMON_ARMV7_A_BARRIERS_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
****************************************************************************/
/* ARMv7-A memory barriers */

13
arch/arm/src/armv7-a/cp15.h
View file

@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/armv7-a/cp15.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@ -16,7 +16,7 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************/
****************************************************************************/
/* References:
*
@ -30,15 +30,16 @@
#ifndef __ARCH_ARM_SRC_ARMV7_A_CP15_H
#define __ARCH_ARM_SRC_ARMV7_A_CP15_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
****************************************************************************/
/* System control register descriptions.
*
* CP15 registers are accessed with MRC and MCR instructions as follows:

208
arch/arm/src/armv7-a/cp15_cacheops.h
View file

@ -1,18 +1,11 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/armv7-a/cp15_cacheops.h
*
* Copyright (C) 2013-2014 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* References:
*
* "Cortex-A5™ MPCore, Technical Reference Manual", Revision: r0p1, Copyright © 2010
* ARM. All rights reserved. ARM DDI 0434B (ID101810)
* "ARM® Architecture Reference Manual, ARMv7-A and ARMv7-R edition", Copyright ©
* 1996-1998, 2000, 2004-2012 ARM. All rights reserved. ARM DDI 0406C.b (ID072512)
*
* Portions of this file derive from Atmel sample code for the SAMA5D3 Cortex-A5
* which also has a modified BSD-style license:
* Portions of this file derive from Atmel sample code for the SAMA5D3
* Cortex-A5 which also has a modified BSD-style license:
*
* Copyright (c) 2012, Atmel Corporation
* All rights reserved.
@ -44,34 +37,47 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
****************************************************************************/
/* References:
*
* "Cortex-A5™ MPCore, Technical Reference Manual", Revision: r0p1,
* Copyright © 2010 ARM. All rights reserved. ARM DDI 0434B (ID101810)
* "ARM® Architecture Reference Manual, ARMv7-A and ARMv7-R edition",
* Copyright © 1996-1998, 2000, 2004-2012 ARM.
* All rights reserved. ARM DDI 0406C.b (ID072512)
*/
#ifndef __ARCH_ARM_SRC_ARMV7_A_CP15_CACHEOPS_H
#define __ARCH_ARM_SRC_ARMV7_A_CP15_CACHEOPS_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Cache definitions ****************************************************************/
****************************************************************************/
/* Cache definitions ********************************************************/
/* L1 Memory */
#define CP15_L1_LINESIZE 32
/* CP15 Registers *******************************************************************/
/* Reference: Cortex-A5™ MPCore Paragraph 4.1.5, "Cache Operations Registers."
/* CP15 Registers ***********************************************************/
/* Reference: Cortex-A5™ MPCore
* Paragraph 4.1.5, "Cache Operations Registers."
*
* Terms:
* 1) Point of coherency (PoC)
* The PoC is the point at which all agents that can access memory are guaranteed
* to see the same copy of a memory location
* The PoC is the point at which all agents that can access memory are
* guaranteed to see the same copy of a memory location
* 2) Point of unification (PoU)
* The PoU is the point by which the instruction and data caches and the
* translation table walks of the processor are guaranteed to see the same copy
* of a memory location.
* translation table walks of the processor are guaranteed to see the same
* copy of a memory location.
*
* Cache Operations:
*
@ -80,12 +86,13 @@
* Register Format: Should be zero (SBZ)
* Instruction: MCR p15, 0, <Rd>, c7, c1, 0
* CP15 Register: BPIALLIS
* Description: Invalidate entire branch predictor array Inner Shareable.
* Description: Invalidate entire branch predictor array Inner
* Shareable.
* Register Format: Should be zero (SBZ)
* Instruction: MCR p15, 0, <Rd>, c7, c1, 6
* CP15 Register: ICIALLU
* Description: Invalidate all instruction caches to PoU. Also flushes branch
* target cache.
* Description: Invalidate all instruction caches to PoU. Also flushes
* branch target cache.
* Register Format: Should be zero (SBZ)
* Instruction: MCR p15, 0, <Rd>, c7, c5, 0
* CP15 Register: ICIMVAU
@ -157,9 +164,10 @@
#define CACHE_SBZ_MASK (31 << TLB_SBZ_SHIFT)
#define CACHE_VA_MASK (0xfffffffe0) /* Bits 5-31: Virtual address */
/************************************************************************************
/****************************************************************************
* Assembly Macros
************************************************************************************/
****************************************************************************/
/* cp15_cache Cache Operations
*
* Usage
@ -193,7 +201,7 @@
#ifdef __ASSEMBLY__
/************************************************************************************
/****************************************************************************
* Name: cp15_enable_dcache
*
* Description:
@ -205,7 +213,7 @@
* Returned Value:
* None
*
************************************************************************************/
****************************************************************************/
.macro cp15_enable_dcache, tmp
mrc p15, 0, \tmp, c1, c0, 0 /* Read SCTLR */
@ -213,7 +221,7 @@
mcr p15, 0, \tmp, c1, c0, 0 /* Update the SCTLR */
.endm
/************************************************************************************
/****************************************************************************
* Name: cp15_disable_dcache
*
* Description:
@ -225,7 +233,7 @@
* Returned Value:
* None
*
************************************************************************************/
****************************************************************************/
.macro cp15_disable_dcache, tmp
mrc p15, 0, \tmp, c1, c0, 0 /* Read SCTLR */
@ -233,7 +241,7 @@
mcr p15, 0, \tmp, c1, c0, 0 /* Update the SCTLR */
.endm
/************************************************************************************
/****************************************************************************
* Name: cp15_enable_icache
*
* Description:
@ -245,7 +253,7 @@
* Returned Value:
* None
*
************************************************************************************/
****************************************************************************/
.macro cp15_enable_icache, tmp
mrc p15, 0, \tmp, c1, c0, 0 /* Read SCTLR */
@ -253,7 +261,7 @@
mcr p15, 0, \tmp, c1, c0, 0 /* Update the SCTLR */
.endm
/************************************************************************************
/****************************************************************************
* Name: cp15_disable_icache
*
* Description:
@ -265,7 +273,7 @@
* Returned Value:
* None
*
************************************************************************************/
****************************************************************************/
.macro cp15_disable_icache, tmp
mrc p15, 0, \tmp, c1, c0, 0 /* Read SCTLR */
@ -273,7 +281,7 @@
mcr p15, 0, \tmp, c1, c0, 0 /* Update the SCTLR */
.endm
/************************************************************************************
/****************************************************************************
* Name: cp15_invalidate_icache_inner_sharable
*
* Description:
@ -285,14 +293,14 @@
* Returned Value:
* None
*
************************************************************************************/
****************************************************************************/
.macro cp15_invalidate_icache_inner_sharable, tmp
mov \tmp, #0
mrc p15, 0, \tmp, c7, c1, 0 /* ICIALLUIS */
.endm
/************************************************************************************
/****************************************************************************
* Name: cp15_invalidate_btb_inner_sharable
*
* Description:
@ -304,18 +312,19 @@
* Returned Value:
* None
*
************************************************************************************/
****************************************************************************/
.macro cp15_invalidate_btb_inner_sharable, tmp
mov \tmp, #0
mrc p15, 0, \tmp, c7, c1, 6 /* BPIALLIS */
.endm
/************************************************************************************
/****************************************************************************
* Name: cp15_invalidate_icache
*
* Description:
* Invalidate all instruction caches to PoU, also flushes branch target cache
* Invalidate all instruction caches to PoU, also flushes branch target
* cache
*
* Input Parameters:
* None
@ -323,14 +332,14 @@
* Returned Value:
* None
*
************************************************************************************/
****************************************************************************/
.macro cp15_invalidate_icache, tmp
mov \tmp, #0
mrc p15, 0, \tmp, c7, c5, 0 /* ICIALLU */
.endm
/************************************************************************************
/****************************************************************************
* Name: cp15_invalidate_icache_bymva
*
* Description:
@ -342,13 +351,13 @@
* Returned Value:
* None
*
************************************************************************************/
****************************************************************************/
.macro cp15_invalidate_icache_bymva, va
mrc p15, 0, \va, c7, c5, 1 /* ICIMVAU */
.endm
/************************************************************************************
/****************************************************************************
* Name: cp15_flush_btb
*
* Description:
@ -360,14 +369,14 @@
* Returned Value:
* None
*
************************************************************************************/
****************************************************************************/
.macro cp15_flush_btb, tmp
mov \tmp, #0
mrc p15, 0, \tmp, c7, c5, 6 /* BPIALL */
.endm
/************************************************************************************
/****************************************************************************
* Name: cp15_flush_btb_bymva
*
* Description:
@ -379,14 +388,14 @@
* Returned Value:
* None
*
************************************************************************************/
****************************************************************************/
.macro cp15_flush_btb_bymva, tmp
mov \tmp, #0
mrc p15, 0, \tmp, c7, c5, 7 /* BPIMVA */
.endm
/************************************************************************************
/****************************************************************************
* Name: cp15_invalidate_dcacheline_bymva
*
* Description:
@ -398,13 +407,13 @@
* Returned Value:
* None
*
************************************************************************************/
****************************************************************************/
.macro cp15_invalidate_dcacheline_bymva, va
mrc p15, 0, \va, c7, c6, 1 /* DCIMVAC */
.endm
/************************************************************************************
/****************************************************************************
* Name: cp15_invalidate_dcacheline_bysetway
*
* Description:
@ -416,13 +425,13 @@
* Returned Value:
* None
*
************************************************************************************/
****************************************************************************/
.macro cp15_invalidate_dcacheline_bysetway, setway
mrc p15, 0, \setway, c7, c6, 2 /* DCISW */
.endm
/************************************************************************************
/****************************************************************************
* Name: cp15_clean_dcache_bymva
*
* Description:
@ -434,13 +443,13 @@
* Returned Value:
* None
*
************************************************************************************/
****************************************************************************/
.macro cp15_clean_dcache_bymva, va
mrc p15, 0, \va, c7, c10, 1 /* DCCMVAC */
.endm
/************************************************************************************
/****************************************************************************
* Name: cp15_clean_dcache_bysetway
*
* Description:
@ -452,13 +461,13 @@
* Returned Value:
* None
*
************************************************************************************/
****************************************************************************/
.macro cp15_clean_dcache_bysetway, setway
mrc p15, 0, \setway, c7, c10, 2 /* DCCSW */
.endm
/************************************************************************************
/****************************************************************************
* Name: cp15_clean_ucache_bymva
*
* Description:
@ -470,13 +479,13 @@
* Returned Value:
* None
*
************************************************************************************/
****************************************************************************/
.macro cp15_clean_ucache_bymva, setway
mrc p15, 0, \setway, c7, c11, 1 /* DCCMVAU */
.endm
/************************************************************************************
/****************************************************************************
* Name: cp15_cleaninvalidate_dcacheline_bymva
*
* Description:
@ -488,13 +497,13 @@
* Returned Value:
* None
*
************************************************************************************/
****************************************************************************/
.macro cp15_cleaninvalidate_dcacheline_bymva, va
mrc p15, 0, \va, c7, c14, 1 /* DCCIMVAC */
.endm
/************************************************************************************
/****************************************************************************
* Name: cp15_cleaninvalidate_dcacheline
*
* Description:
@ -506,7 +515,7 @@
* Returned Value:
* None
*
************************************************************************************/
****************************************************************************/
.macro cp15_cleaninvalidate_dcacheline, setway
mrc p15, 0, \setway, c7, c14, 2 /* DCCISW */
@ -514,13 +523,13 @@
#endif /* __ASSEMBLY__ */
/************************************************************************************
/****************************************************************************
* Inline Functions
************************************************************************************/
****************************************************************************/
#ifndef __ASSEMBLY__
/************************************************************************************
/****************************************************************************
* Name: cp15_enable_dcache
*
* Description:
@ -532,7 +541,7 @@
* Returned Value:
* None
*
************************************************************************************/
****************************************************************************/
static inline void cp15_enable_dcache(void)
{
@ -547,7 +556,7 @@ static inline void cp15_enable_dcache(void)
);
}
/************************************************************************************
/****************************************************************************
* Name: cp15_disable_dcache
*
* Description:
@ -559,7 +568,7 @@ static inline void cp15_enable_dcache(void)
* Returned Value:
* None
*
************************************************************************************/
****************************************************************************/
static inline void cp15_disable_dcache(void)
{
@ -574,7 +583,7 @@ static inline void cp15_disable_dcache(void)
);
}
/************************************************************************************
/****************************************************************************
* Name: cp15_enable_icache
*
* Description:
@ -586,7 +595,7 @@ static inline void cp15_disable_dcache(void)
* Returned Value:
* None
*
************************************************************************************/
****************************************************************************/
static inline void cp15_enable_icache(void)
{
@ -601,7 +610,7 @@ static inline void cp15_enable_icache(void)
);
}
/************************************************************************************
/****************************************************************************
* Name: cp15_disable_icache
*
* Description:
@ -613,7 +622,7 @@ static inline void cp15_enable_icache(void)
* Returned Value:
* None
*
************************************************************************************/
****************************************************************************/
static inline void cp15_disable_icache(void)
{
@ -628,7 +637,7 @@ static inline void cp15_disable_icache(void)
);
}
/************************************************************************************
/****************************************************************************
* Name: cp15_invalidate_icache_inner_sharable
*
* Description:
@ -640,7 +649,7 @@ static inline void cp15_disable_icache(void)
* Returned Value:
* None
*
************************************************************************************/
****************************************************************************/
static inline void cp15_invalidate_icache_inner_sharable(void)
{
@ -654,7 +663,7 @@ static inline void cp15_invalidate_icache_inner_sharable(void)
);
}
/************************************************************************************
/****************************************************************************
* Name: cp15_invalidate_btb_inner_sharable
*
* Description:
@ -666,7 +675,7 @@ static inline void cp15_invalidate_icache_inner_sharable(void)
* Returned Value:
* None
*
************************************************************************************/
****************************************************************************/
static inline void cp15_invalidate_btb_inner_sharable(void)
{
@ -680,11 +689,12 @@ static inline void cp15_invalidate_btb_inner_sharable(void)
);
}
/************************************************************************************
/****************************************************************************
* Name: cp15_invalidate_icache
*
* Description:
* Invalidate all instruction caches to PoU, also flushes branch target cache
* Invalidate all instruction caches to PoU, also flushes branch target
* cache
*
* Input Parameters:
* None
@ -692,7 +702,7 @@ static inline void cp15_invalidate_btb_inner_sharable(void)
* Returned Value:
* None
*
************************************************************************************/
****************************************************************************/
static inline void cp15_invalidate_icache(void)
{
@ -706,7 +716,7 @@ static inline void cp15_invalidate_icache(void)
);
}
/************************************************************************************
/****************************************************************************
* Name: cp15_invalidate_icache_bymva
*
* Description:
@ -718,7 +728,7 @@ static inline void cp15_invalidate_icache(void)
* Returned Value:
* None
*
************************************************************************************/
****************************************************************************/
static inline void cp15_invalidate_icache_bymva(unsigned int va)
{
@ -731,7 +741,7 @@ static inline void cp15_invalidate_icache_bymva(unsigned int va)
);
}
/************************************************************************************
/****************************************************************************
* Name: cp15_flush_btb
*
* Description:
@ -743,7 +753,7 @@ static inline void cp15_invalidate_icache_bymva(unsigned int va)
* Returned Value:
* None
*
************************************************************************************/
****************************************************************************/
static inline void cp15_flush_btb(void)
{
@ -757,7 +767,7 @@ static inline void cp15_flush_btb(void)
);
}
/************************************************************************************
/****************************************************************************
* Name: cp15_flush_btb_bymva
*
* Description:
@ -769,7 +779,7 @@ static inline void cp15_flush_btb(void)
* Returned Value:
* None
*
************************************************************************************/
****************************************************************************/
static inline void cp15_flush_btb_bymva(void)
{
@ -783,7 +793,7 @@ static inline void cp15_flush_btb_bymva(void)
);
}
/************************************************************************************
/****************************************************************************
* Name: cp15_invalidate_dcacheline_bymva
*
* Description:
@ -795,7 +805,7 @@ static inline void cp15_flush_btb_bymva(void)
* Returned Value:
* None
*
************************************************************************************/
****************************************************************************/
/* Invalidate data cache line by VA to PoC */
@ -810,7 +820,7 @@ static inline void cp15_invalidate_dcacheline_bymva(unsigned int va)
);
}
/************************************************************************************
/****************************************************************************
* Name: cp15_invalidate_dcacheline_bysetway
*
* Description:
@ -822,7 +832,7 @@ static inline void cp15_invalidate_dcacheline_bymva(unsigned int va)
* Returned Value:
* None
*
************************************************************************************/
****************************************************************************/
/* Invalidate data cache line by set/way */
@ -837,7 +847,7 @@ static inline void cp15_invalidate_dcacheline_bysetway(unsigned int setway)
);
}
/************************************************************************************
/****************************************************************************
* Name: cp15_clean_dcache_bymva
*
* Description:
@ -849,7 +859,7 @@ static inline void cp15_invalidate_dcacheline_bysetway(unsigned int setway)
* Returned Value:
* None
*
************************************************************************************/
****************************************************************************/
/* Clean data cache line by MVA */
@ -864,7 +874,7 @@ static inline void cp15_clean_dcache_bymva(unsigned int va)
);
}
/************************************************************************************
/****************************************************************************
* Name: cp15_clean_dcache_bysetway
*
* Description:
@ -876,7 +886,7 @@ static inline void cp15_clean_dcache_bymva(unsigned int va)
* Returned Value:
* None
*
************************************************************************************/
****************************************************************************/
static inline void cp15_clean_dcache_bysetway(unsigned int setway)
{
@ -889,7 +899,7 @@ static inline void cp15_clean_dcache_bysetway(unsigned int setway)
);
}
/************************************************************************************
/****************************************************************************
* Name: cp15_clean_ucache_bymva
*
* Description:
@ -901,7 +911,7 @@ static inline void cp15_clean_dcache_bysetway(unsigned int setway)
* Returned Value:
* None
*
************************************************************************************/
****************************************************************************/
static inline void cp15_clean_ucache_bymva(unsigned int setway)
{
@ -914,7 +924,7 @@ static inline void cp15_clean_ucache_bymva(unsigned int setway)
);
}
/************************************************************************************
/****************************************************************************
* Name: cp15_cleaninvalidate_dcacheline_bymva
*
* Description:
@ -926,7 +936,7 @@ static inline void cp15_clean_ucache_bymva(unsigned int setway)
* Returned Value:
* None
*
************************************************************************************/
****************************************************************************/
static inline void cp15_cleaninvalidate_dcacheline_bymva(unsigned int va)
{
@ -939,7 +949,7 @@ static inline void cp15_cleaninvalidate_dcacheline_bymva(unsigned int va)
);
}
/************************************************************************************
/****************************************************************************
* Name: cp15_cleaninvalidate_dcacheline
*
* Description:
@ -951,7 +961,7 @@ static inline void cp15_cleaninvalidate_dcacheline_bymva(unsigned int va)
* Returned Value:
* None
*
************************************************************************************/
****************************************************************************/
static inline void cp15_cleaninvalidate_dcacheline(unsigned int setway)
{

2
arch/arm/src/armv7-a/crt0.c
View file

@ -117,7 +117,9 @@ void _start(int argc, FAR char *argv[])
ARCH_DATA_RESERVE->ar_sigtramp = (addrenv_sigtramp_t)sig_trampoline;
/* Call C++ constructors */
/* Setup so that C++ destructors called on task exit */
/* REVISIT: Missing logic */
/* Call the main() entry point passing argc and argv. */

59
arch/arm/src/armv7-a/gic.h
View file

@ -48,7 +48,9 @@
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Generic indexing helpers *************************************************/
/* 1x32 bit field per register */
#define GIC_INDEX1(n) (n) /* 1 field per word */
@ -92,6 +94,7 @@
#define GIC_MASK32(n) (1 << GIC_SHIFT32(n)) /* 1-bit mask */
/* GIC Register Offsets *****************************************************/
/* CPU Interface registers */
#define GIC_ICCICR_OFFSET 0x0000 /* CPU Interface Control Register */
@ -127,6 +130,7 @@
/* 0x000c-0x001c: Reserved */
/* 0x0020-0x003c: Implementation defined */
/* 0x0040-0x007c: Reserved */
/* Interrupt Security Registers: 0x0080-0x009c */
#define GIC_ICDISR_OFFSET(n) (0x0080 + GIC_OFFSET32(n))
@ -160,23 +164,28 @@
#define GIC_ICDIPR_OFFSET(n) (0x0400 + GIC_OFFSET4(n))
/* 0x0500-0x07fc: Reserved */
/* Interrupt Processor Target Registers: 0x0800-0x08fc */
#define GIC_ICDIPTR_OFFSET(n) (0x0800 + GIC_OFFSET4(n))
/* 0x0900-0x0bfc: Reserved */
/* Interrupt Configuration Registers: 0x0c00-0x0c3c */
#define GIC_ICDICFR_OFFSET(n) (0x0c00 + GIC_OFFSET16(n))
/* 0x0d00-0x0dfc: Implementation defined */
/* PPI Status Register: 0x0d00 */
/* SPI Status Registers: 0x0d04-0x0d1c */
#define GIC_ICDPPISR_OFFSET 0x0d00 /* PPI Status Register */
#define GIC_ICDSPISR_OFFSET(n) (0x0d00 + GIC_OFFSET32(n))
/* 0x0d80-0x0dfc: Reserved */
/* Non-secure Access Control Registers, optional: 00xe00-0x0efc */
#define GIC_ICDNSACR_OFFSET(n) (0x0e00 + GIC_OFFSET32(n))
@ -186,6 +195,7 @@
#define GIC_ICDSGIR_OFFSET 0x0f00 /* Software Generated Interrupt Register */
/* 0x0f0c-0x0f0c: Reserved */
/* Peripheral Identification Registers: 0x0fd0-0xfe8 */
#define GIC_ICDPIDR_OFFSET(n) (0x0fd0 + ((n) << 2))
@ -199,7 +209,9 @@
#define GIC_ICDSSPR_OFFSET(n) (0x0f20 + GIC_OFFSET8(n))
/* 0x0f30-0x0fcc: Reserved */
/* 0x0fd0-0x0ffc: Implementation defined */
/* Component Identification Registers: 0x0ff0-0x0ffc */
#define GIC_ICDCIDR_OFFSET(n) (0x0ff0 + ((n) << 2))
@ -207,6 +219,7 @@
/* 0x0f04-0x0ffc: Reserved */
/* GIC Register Addresses ***************************************************/
/* The Interrupt Controller is a single functional unit that is located in a
* Cortex-A9 MPCore design. There is one interrupt interface per Cortex-A9
* processor. Registers are memory mapped and accessed through a chip-
@ -264,11 +277,15 @@
/* GIC Register Bit Definitions *********************************************/
/* CPU Interface registers */
/* CPU Interface Control Register -- without security extensions */
#define GIC_ICCICR_ENABLE (1 << 0) /* Bit 0: Enable the CPU interface for this GIC */
/* Bits 1-31: Reserved */
/* CPU Interface Control Register -- with security extensions, non-secure copy */
/* CPU Interface Control Register -- with security extensions,
* non-secure copy
*/
#define GIC_ICCICRU_ENABLEGRP1 (1 << 0) /* Bit 0: Enable Group 1 interrupts for the CPU */
/* Bits 1-4: Reserved */
@ -277,7 +294,10 @@
/* Bits 7-8: Reserved */
#define GIC_ICCICRU_EOIMODENS (1 << 9) /* Bit 9: Control EIOIR access (non-secure) */
/* Bits 10-31: Reserved */
/* CPU Interface Control Register -- with security extensions, secure copy */
/* CPU Interface Control Register -- with security extensions,
* secure copy
*/
#define GIC_ICCICRS_ENABLEGRP0 (1 << 0) /* Bit 0: Enable Group 0 interrupts for the CPU */
#define GIC_ICCICRS_ENABLEGRP1 (1 << 1) /* Bit 1: Enable Group 1 interrupts for the CPU */
@ -291,6 +311,7 @@
#define GIC_ICCICRS_EOIMODES (1 << 9) /* Bit 6: Control EIOIR access (secure) */
#define GIC_ICCICRS_EOIMODENS (1 << 10) /* Bit 10: Control EIOIR access (non-secure) */
/* Bits 11-31: Reserved */
/* Interrupt Priority Mask Register. Priority values are 8-bit unsigned
* binary. A GIC supports a minimum of 16 and a maximum of 256 priority
* levels. As a result, PMR settings make sense.
@ -300,6 +321,7 @@
#define GIC_ICCPMR_MASK (0xff << GIC_ICCPMR_SHIFT)
# define GIC_ICCPMR_VALUE(n) ((uint32_t)(n) << GIC_ICCPMR_SHIFT)
/* Bits 8-31: Reserved */
/* Binary point Register and Aliased Non-secure Binary Point Register.
* Priority values are 8-bit unsigned binary. A GIC supports a minimum of
* 16 and a maximum of 256 priority levels. As a result, not all binary
@ -316,7 +338,9 @@
# define GIC_ICCBPR_6_7 (5 << GIC_ICCBPR_SHIFT) /* Priority bits [7:6] compared for pre-emption */
# define GIC_ICCBPR_7_7 (6 << GIC_ICCBPR_SHIFT) /* Priority bit [7] compared for pre-emption */
# define GIC_ICCBPR_NOPREMPT (7 << GIC_ICCBPR_SHIFT) /* No pre-emption is performed */
/* Bits 3-31: Reserved */
/* Interrupt Acknowledge Register */
#define GIC_ICCIAR_INTID_SHIFT (0) /* Bits 0-9: Interrupt ID */
@ -325,7 +349,9 @@
#define GIC_ICCIAR_CPUSRC_SHIFT (10) /* Bits 10-12: CPU source ID */
#define GIC_ICCIAR_CPUSRC_MASK (7 << GIC_ICCIAR_CPUSRC_SHIFT)
# define GIC_ICCIAR_CPUSRC(n) ((uint32_t)(n) << GIC_ICCIAR_CPUSRC_SHIFT)
/* Bits 13-31: Reserved */
/* End of Interrupt Register */
#define GIC_ICCEOIR_SPURIOUS (0x3ff)
@ -336,14 +362,18 @@
#define GIC_ICCEOIR_CPUSRC_SHIFT (10) /* Bits 10-12: CPU source ID */
#define GIC_ICCEOIR_CPUSRC_MASK (7 << GIC_ICCEOIR_CPUSRC_SHIFT)
# define GIC_ICCEOIR_CPUSRC(n) ((uint32_t)(n) << GIC_ICCEOIR_CPUSRC_SHIFT)
/* Bits 13-31: Reserved */
/* Running Interrupt Register */
/* Bits 0-3: Reserved */
#define GIC_ICCRPR_PRIO_SHIFT (4) /* Bits 4-7: Priority mask */
#define GIC_ICCRPR_PRIO_MASK (15 << GIC_ICCRPR_PRIO_SHIFT)
# define GIC_ICCRPR_PRIO_VALUE(n) ((uint32_t)(n) << GIC_ICCRPR_PRIO_SHIFT)
/* Bits 8-31: Reserved */
/* Highest Pending Interrupt Register */
#define GIC_ICCHPIR_INTID_SHIFT (0) /* Bits 0-9: Interrupt ID */
@ -352,28 +382,39 @@
#define GIC_ICCHPIR_CPUSRC_SHIFT (10) /* Bits 10-12: CPU source ID */
#define GIC_ICCHPIR_CPUSRC_MASK (7 << GIC_ICCHPIR_CPUSRC_SHIFT)
# define GIC_ICCHPIR_CPUSRC(n) ((uint32_t)(n) << GIC_ICCHPIR_CPUSRC_SHIFT)
/* Bits 13-31: Reserved */
/* Aliased Interrupt Acknowledge Register */
#define GIC_ICCAIAR_
/* Aliased End of Interrupt Register */
#define GIC_ICCAEOIR_
/* Aliased Highest Priority Pending Interrupt Register */
#define GIC_ICCAHPIR_
/* Active Priorities Register 1 */
#define GIC_ICCAPR1_
/* Active Priorities Register 2 */
#define GIC_ICCAPR2_
/* Active Priorities Register 3 */
#define GIC_ICCAPR3_
/* Active Priorities Register 4 */
#define GIC_ICCAPR4_
/* Non-secure Active Priorities Register 1 */
#define GIC_ICCNSAPR1_
/* Non-secure Active Priorities Register 2 */
#define GIC_ICCNSAPR2_
/* Non-secure Active Priorities Register 3 */
#define GIC_ICCNSAPR3_
/* Non-secure Active Priorities Register 4 */
#define GIC_ICCNSAPR4_
@ -392,15 +433,18 @@
#define GIC_ICCDIR_
/* Distributor Registers */
/* Distributor Control Register -- without security extensions */
#define GIC_ICDDCR_ENABLE (1 << 0) /* Bit 0: Enable forwarding of interrupts */
/* Bits 1-31: Reserved */
/* Distributor Control Register -- with security extensions */
#define GIC_ICDDCR_ENABLEGRP0 (1 << 0) /* Bit 0: Enable forwarding of Group 0 interrupts */
#define GIC_ICDDCR_ENABLEGRP1 (1 << 1) /* Bit 1: Enable forwarding of Group 1 interrupts */
/* Bits 2-31: Reserved */
/* Interrupt Controller Type Register */
#define GIC_ICDICTR_ITLINES_SHIFT (0) /* Bits 0-4: It lines number */
@ -412,6 +456,7 @@
#define GIC_ICDICTR_LSPI_SHIFT (11) /* Bits 11-15: Number of Lockable Shared Peripheral Interrupts */
#define GIC_ICDICTR_LSPI_MASK (0x1f << GIC_ICDICTR_LSPI_SHIFT)
/* Bits 16-31: Reserved */
/* Distributor Implementer ID Register */
#define GIC_ICDIIDR_IMPL_SHIFT (0) /* Bits 0-11: Implementer */
@ -427,7 +472,8 @@
/* Interrupt Set-Enable.
*
* NOTE: In the Cortex-A9 MPCore, SGIs are always enabled. The corresponding bits
* NOTE:
* In the Cortex-A9 MPCore, SGIs are always enabled. The corresponding bits
* in the ICDISERn are read as one, write ignored
*/
@ -435,7 +481,8 @@
/* Interrupt Clear-Enable.
*
* NOTE: In the Cortex-A9 MPCore, SGIs are always enabled. The corresponding bits
* NOTE:
* In the Cortex-A9 MPCore, SGIs are always enabled. The corresponding bits
* in the ICDICERn are read as one, write ignored
*/
@ -488,6 +535,7 @@
/* PPI Status Register */
#define GIC_ICDPPISR_PPI(n) (1 << ((n) + 11)) /* Bits 11-15: PPI(n) status, n=0-4 */
# define GIC_ICDPPISR_GTM (1 << 11) /* Bit 11: PPI[0], Global Timer */
# define GIC_ICDPPISR_NFIQ (1 << 12) /* Bit 12: PPI[1], FIQ, active low */
# define GIC_ICDPPISR_PTM (1 << 13) /* Bit 13: PPI[2], Private Timer */
@ -520,10 +568,12 @@
/* SGI Clear-Pending Registers */
#define GIC_ICDSCPR_
/* SGI Set-Pending Registers */
#define GIC_ICDSSPR_
/* Interrupt IDs ************************************************************/
/* The Global Interrupt Controller (GIC) collects up to 224 interrupt
* requests and provides a memory mapped interface to each of the CPU core.
*
@ -539,6 +589,7 @@
*/
/* Private Peripheral Interrupts (PPI) **************************************/
/* Each Cortex-A9 processor has private interrupts, ID0-ID15, that can only
* be triggered by software. These interrupts are aliased so that there is
* no requirement for a requesting Cortex-A9 processor to determine its own

2
arch/arm/src/armv7-a/gtm.h
View file

@ -39,6 +39,7 @@
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* GTM Register Offsets *****************************************************/
#define GTM_COUNT0_OFFSET 0x0000 /* Global Timer Counter Register 0 */
@ -81,6 +82,7 @@
/* Bits 1-31: Reserved */
/* Comparator Value Register 0/1 -- 64-bit timer compare value */
/* Auto-increment Register -- 32-bit auto-increment value */
/****************************************************************************

31
arch/arm/src/armv7-a/l2cc_pl310.h
View file

@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/armv7-a/l2cc_pl310.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@ -16,7 +16,7 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************/
****************************************************************************/
/* Reference: "CoreLink™ Level 2 Cache Controller L2C-310", Revision r3p2,
* Technical Reference Manual, ARM DDI 0246F (ID011711), ARM
@ -25,9 +25,9 @@
#ifndef __ARCH_ARM_SRC_ARMV7_A_L2CC_PL310_H
#define __ARCH_ARM_SRC_ARMV7_A_L2CC_PL310_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
@ -37,11 +37,11 @@
#include "chip.h"
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
****************************************************************************/
/* General Definitions **************************************************************/
/* General Definitions ******************************************************/
#define PL310_CACHE_LINE_SIZE 32
@ -51,7 +51,7 @@
# define PL310_NLOCKREGS 1
#endif
/* L2CC Register Offsets ************************************************************/
/* L2CC Register Offsets ****************************************************/
#define L2CC_IDR_OFFSET 0x0000 /* Cache ID Register */
#define L2CC_TYPR_OFFSET 0x0004 /* Cache Type Register */
@ -87,9 +87,10 @@
#define L2CC_CIWR_OFFSET 0x07fc /* Clean Invalidate Way Register */
/* 0x0800-0x08fc Reserved */
/* Data and Instruction Lockdown registers where n=0-7. The registers for n > 0 are
* implemented if the option pl310_LOCKDOWN_BY_MASTER is enabled. Otherwise, they are
* unused
/* Data and Instruction Lockdown registers where n=0-7.
* The registers for n > 0 are implemented if the option
* pl310_LOCKDOWN_BY_MASTER is enabled.
* Otherwise, they are unused
*/
#define L2CC_DLKR_OFFSET(n) (0x0900 + ((n) << 3)) /* Data Lockdown Register */
@ -109,7 +110,7 @@
/* 0x0f64-0x0f7c Reserved */
#define L2CC_POWCR_OFFSET 0x0f80 /* Power Control Register */
/* L2CC Register Addresses **********************************************************/
/* L2CC Register Addresses **************************************************/
#define L2CC_IDR (L2CC_VBASE+L2CC_IDR_OFFSET)
#define L2CC_TYPR (L2CC_VBASE+L2CC_TYPR_OFFSET)
@ -149,7 +150,7 @@
#define L2CC_PCR (L2CC_VBASE+L2CC_PCR_OFFSET)
#define L2CC_POWCR (L2CC_VBASE+L2CC_POWCR_OFFSET)
/* L2CC Register Bit Definitions ****************************************************/
/* L2CC Register Bit Definitions ********************************************/
/* Cache ID Register (32-bit ID) */
@ -299,8 +300,8 @@
/* Event Counter 0 Value Register (32-bit value) */
/* Interrupt Mask Register, Masked Interrupt Status Register, Raw Interrupt Status
* Register, and Interrupt Clear Register.
/* Interrupt Mask Register, Masked Interrupt Status Register,
* Raw Interrupt Status Register, and Interrupt Clear Register.
*/
#define L2CC_INT_ECNTR (1 << 0) /* Bit 0: Event Counter 1/0 Overflow Increment */

288
arch/arm/src/armv7-a/mmu.h
View file

@ -1,4 +1,4 @@
/************************************************************************************************************
/****************************************************************************
* arch/arm/src/armv7-a/mmu.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@ -16,22 +16,22 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************************************/
****************************************************************************/
/* References:
* "Cortex-A5™ MPCore, Technical Reference Manual", Revision: r0p1, Copyright ©
* 2010 ARM. All rights reserved. ARM DDI 0434B (ID101810)
* "ARM® Architecture Reference Manual, ARMv7-A and ARMv7-R edition", Copyright ©
* 1996-1998, 2000, 2004-2012 ARM. All rights reserved. ARM
* DDI 0406C.b (ID072512)
* "Cortex-A5™ MPCore, Technical Reference Manual", Revision: r0p1,
* Copyright © 2010 ARM. All rights reserved. ARM DDI 0434B (ID101810)
* "ARM® Architecture Reference Manual, ARMv7-A and ARMv7-R edition",
* Copyright © 1996-1998, 2000, 2004-2012 ARM.
* All rights reserved. ARM DDI 0406C.b (ID072512)
*/
#ifndef __ARCH_ARM_SRC_ARMV7_A_MMU_H
#define __ARCH_ARM_SRC_ARMV7_A_MMU_H
/************************************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
@ -41,11 +41,11 @@
# include "chip.h"
#endif /* __ASSEMBLY__ */
/************************************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************************************/
****************************************************************************/
/* Configuration ********************************************************************************************/
/* Configuration ************************************************************/
#if defined(CONFIG_PAGING) || defined(CONFIG_ARCH_ADDRENV)
@ -58,15 +58,17 @@
#endif
#endif /* CONFIG_PAGING */
/* MMU CP15 Register Bit Definitions ************************************************************************/
/* MMU CP15 Register Bit Definitions ****************************************/
/* Reference: Cortex-A5™ MPCore Paragraph 6.7, "MMU software accessible registers." */
/* Reference: Cortex-A5™ MPCore
* Paragraph 6.7, "MMU software accessible registers."
*/
/* TLB Type Register TLB Type Register
*
* The Translation Lookaside Buffer (TLB) Type Register, TLBTR, returns the number of
* lockable entries for the TLB. The Cortex-A5 MPCore processor does not implement
* this feature, so this register always RAZ.
* The Translation Lookaside Buffer (TLB) Type Register, TLBTR, returns the
* number of lockable entries for the TLB. The Cortex-A5 MPCore processor
* does not implement this feature, so this register always RAZ.
*/
/* System Control Register (SCTLR). see cstlr.h */
@ -90,7 +92,10 @@
/* Bits 7-n: Reserved, n=7-13 */
#define _TTBR0_LOWER(n) (0xffffffff << (n))
/* Bits (n+1)-31: Translation table base 0 */
/* Bits (n+1)-31:
* Translation table base 0
*/
#define TTBR0_BASE_MASK(n) (~_TTBR0_LOWER(n))
@ -160,11 +165,11 @@
#define IFSR_EXT (1 << 12) /* Bit 12: External Abort Qualifier */
/* Bits 13-31: Reserved */
/* Data Fault Address Register(DFAR). Holds the MVA of the faulting address when a
* synchronous fault occurs
/* Data Fault Address Register(DFAR). Holds the MVA of the faulting address
* when a synchronous fault occurs
*
* Instruction Fault Address Register(IFAR). Holds the MVA of the faulting address
* of the instruction that caused a prefetch abort.
* Instruction Fault Address Register(IFAR). Holds the MVA of the faulting
* address of the instruction that caused a prefetch abort.
*/
/* TLB operations.
@ -225,10 +230,10 @@
/* Context ID Register (CONTEXTIDR). See cstlr.h */
/* Translation Table Definitions ****************************************************************************/
/* Translation Table Definitions ********************************************/
/* Hardware translation table definitions. Only the "short descriptor format" is
* supported.
/* Hardware translation table definitions.
* Only the "short descriptor format" is supported.
*
* Level 1 Descriptor (PMD)
*
@ -245,15 +250,16 @@
/* Level 1 Fault Translation Table Format.
*
* Invalid or fault entry. "The associated VA is unmapped, and any attempt to
* access it generates a Translation fault. Software can use bits[31:2] of the
* descriptor for its own purposes, because the hardware ignores
* Invalid or fault entry. "The associated VA is unmapped, and any attempt
* to access it generates a Translation fault. Software can use bits[31:2]
* of the descriptor for its own purposes, because the hardware ignores
* these bits."
*/
/* Level 1 Page Table Translation Table Format.
*
* Page table. "The descriptor gives the address of a second-level translation
* Page table.
* "The descriptor gives the address of a second-level translation
* table, that specifies the mapping of the associated 1MByte VA range."
*/
@ -269,18 +275,21 @@
/* Level 1 Section/Supersection Descriptor.
*
* Section or Supersection. "The descriptor gives the base address of the
* Section or Supersection. Bit[18] determines whether the entry describes a
* Section or a Supersection. If the implementation supports the PXN
* attribute, this encoding also defines the PXN bit as 0. Section descriptors
* allow fast, single level mapping between 1Mb address regions."
* Section or Supersection.
* "The descriptor gives the base address of the Section or Supersection.
* Bit[18] determines whether the entry describes a Section or a
* Supersection. If the implementation supports the PXN attribute, this
* encoding also defines the PXN bit as 0. Section descriptors allow fast,
* single level mapping between 1Mb address regions."
* PXN Section or Supersection. "If an implementation supports the PXN attribute,
* this encoding is identical..., except that it defines the PXN bit as 1.
* PXN Section or Supersection.
* "If an implementation supports the PXN attribute, this encoding is
* identical..., except that it defines the PXN bit as 1.
*
* "If the implementation does not support the PXN attribute, an attempt to access
* the associated VA generates a Translation fault. On an implementation that
* does not support the PXN attribute, this encoding must not be used."
* "If the implementation does not support the PXN attribute, an attempt to
* access the associated VA generates a Translation fault. On an
* implementation that does not support the PXN attribute, this encoding
* must not be used."
*/
/* Section */
@ -300,6 +309,7 @@
#define PMD_SECT_AP1 (2 << PMD_SECT_AP_SHIFT) /* AP[1]: Access permission bit 1 */
#define PMD_SECT_TEX_SHIFT (12) /* Bits 12-14: Memory region attribute bits */
#define PMD_SECT_TEX_MASK (7 << PMD_SECT_TEX_SHIFT)
#define PMD_SECT_AP2 (1 << 15) /* Bit 15: AP[2]: Access permission bit 2 */
#define PMD_SECT_S (1 << 16) /* Bit 16: Shareable bit */
#define PMD_SECT_NG (1 << 17) /* Bit 17: Not global bit. */
@ -351,6 +361,7 @@
# define PMD_SECT_AP_R01 (PMD_SECT_AP1 | PMD_SECT_AP2)
#else
/* AP[2:0] access permissions control, Short-descriptor format only:
*
* AP[2] AP[1] AP[0] PL1/2 PL0 Description
@ -383,8 +394,9 @@
/* Short-descriptor translation table second-level descriptor formats
*
* A PMD_TYPE_PTE level-one table entry provides the base address of the beginning
* of a second-level page table. There are two types of page table entries:
* A PMD_TYPE_PTE level-one table entry provides the base address of the
* beginning of a second-level page table. There are two types of page
* table entries:
*
* - Large page table entries support mapping of 64KB memory regions.
* - Small page table entries support mapping of 4KB memory regions.
@ -446,6 +458,7 @@
*/
#ifdef CONFIG_AFE_ENABLE
/* AP[2:1] access permissions model. AP[0] is used as an access flag:
*
* AP[2] AP[1] PL1 PL0 Description
@ -630,7 +643,7 @@
#define PGTABLE_SIZE 0x00004000
/* Virtual Page Table Location ******************************************************************************/
/* Virtual Page Table Location **********************************************/
#ifdef CONFIG_PAGING
/* Check if the virtual address of the page table has been defined. It
@ -652,7 +665,7 @@
#endif /* PGTABLE_BASE_VADDR */
/* MMU flags ************************************************************************************************/
/* MMU flags ****************************************************************/
/* Create some friendly definitions to handle page table entries */
@ -674,7 +687,7 @@
#define PG_L1_PADDRMASK PMD_SECT_PADDR_MASK
/* Addresses of Memory Regions ******************************************************************************/
/* Addresses of Memory Regions **********************************************/
/* We position the locked region PTEs at an offset into the first
* L2 page table. The L1 entry points to an 1Mb aligned virtual
@ -724,10 +737,10 @@
#define PG_L2_DATA_VADDR (PG_L2_LOCKED_VADDR + PG_L2_TEXT_SIZE)
#define PG_L2_DATA_SIZE (4*PG_DATA_NPAGES)
/* Page Table Info ******************************************************************************************/
/* Page Table Info **********************************************************/
/* The number of pages in the in the page table (PG_PGTABLE_NPAGES). We
* position the page table PTEs just after the data section PTEs.
/* The number of pages in the in the page table (PG_PGTABLE_NPAGES).
* We position the page table PTEs just after the data section PTEs.
*/
#define PG_PGTABLE_NPAGES (PGTABLE_SIZE >> PAGESHIFT)
@ -738,12 +751,12 @@
#define PG_L2_PGTABLE_VADDR (PG_L2_DATA_VADDR + PG_L2_DATA_SIZE)
#define PG_L2_PGTABLE_SIZE (4*PG_DATA_NPAGES)
/* Vector Mapping *******************************************************************************************/
/* Vector Mapping ***********************************************************/
/* One page is required to map the vector table. The vector table could lie
* at virtual address zero (or at the start of RAM which is aliased to address
* zero on the ea3131) or at virtual address 0xfff00000. We only have logic
* here to support the former case.
* at virtual address zero (or at the start of RAM which is aliased to
* address zero on the ea3131) or at virtual address 0xfff00000. We only
* have logic here to support the former case.
*
* NOTE: If the vectors are at address zero, the page table will be
* forced to the highest RAM addresses. If the vectors are at 0xfff0000,
@ -786,13 +799,15 @@
# define PG_L2_VECT_PADDR (PGTABLE_L2_BASE_PADDR + PG_L2_VECT_OFFSET)
# define PG_L2_VECT_VADDR (PGTABLE_L2_BASE_VADDR + PG_L2_VECT_OFFSET)
/* Case 3: High vectors or the locked region is not at the beginning or SRAM */
/* Case 3:
* High vectors or the locked region is not at the beginning or SRAM
*/
#else
# error "Logic missing for high vectors in this case"
#endif
/* Page Usage ***********************************************************************************************/
/* Page Usage ***************************************************************/
/* This is the total number of pages used in the text/data mapping: */
@ -807,7 +822,7 @@
# error "Total pages required exceeds RAM size"
#endif
/* Page Management ******************************************************************************************/
/* Page Management **********************************************************/
/* For page management purposes, the following summarize the "heap" of
* free pages, operations on free pages and the L2 page table.
@ -849,10 +864,10 @@
* (virtual)address of the backing page memory.
*
* These are used as follows: If a miss occurs at some virtual address, va,
* A new page index, ndx, is allocated. PG_POOL_PGPADDR(i) converts the index
* into the physical address of the page memory; PG_POOL_L2VADDR(va) converts
* the virtual address in the L2 page table there the new mapping will be
* written.
* A new page index, ndx, is allocated. PG_POOL_PGPADDR(i) converts the
* index into the physical address of the page memory; PG_POOL_L2VADDR(va)
* converts the virtual address in the L2 page table there the new mapping
* will be written.
*/
#define PG_POOL_VA2L1OFFSET(va) (((va) >> 20) << 2)
@ -872,13 +887,13 @@
#endif /* CONFIG_PAGING */
/************************************************************************************************************
/****************************************************************************
* Public Types
************************************************************************************************************/
****************************************************************************/
#ifndef __ASSEMBLY__
/* struct section_mapping_s describes the L1 mapping of a large region of memory
* consisting of one or more 1MB sections (nsections).
/* struct section_mapping_s describes the L1 mapping of a large region of
* memory consisting of one or more 1MB sections (nsections).
*
* All addresses must be aligned to 1MB address boundaries.
*/
@ -892,13 +907,13 @@ struct section_mapping_s
};
#endif
/************************************************************************************************************
/****************************************************************************
* Assembly Macros
************************************************************************************************************/
****************************************************************************/
#ifdef __ASSEMBLY__
/************************************************************************************************************
/****************************************************************************
* Name: cp15_disable_mmu
*
* Description:
@ -907,7 +922,7 @@ struct section_mapping_s
* Input Parameters:
* None
*
************************************************************************************************************/
****************************************************************************/
.macro cp15_disable_mmu, scratch
mrc p15, 0, \scratch, c1, c0, 0
@ -915,27 +930,27 @@ struct section_mapping_s
mcr p15, 0, \scratch, c1, c0, 0
.endm
/************************************************************************************************************
/****************************************************************************
* Name: cp15_invalidate_tlbs
*
* Description:
* Invalidate entire unified TLB
*
* The Invalidate entire TLB operations invalidate all unlocked entries in the
* TLB. The operation ignores the value in the register Rt specified by the MCR
* instruction that performs the operation. Software does not have to write a
* value to the register before issuing the MCR instruction.
* The Invalidate entire TLB operations invalidate all unlocked entries in
* the TLB. The operation ignores the value in the register Rt specified by
* the MCR instruction that performs the operation. Software does not have
* to write a value to the register before issuing the MCR instruction.
*
* Input Parameters:
* None
*
************************************************************************************************************/
****************************************************************************/
.macro cp15_invalidate_tlbs, scratch
mcr p15, 0, \scratch, c8, c7, 0 /* TLBIALL */
.endm
/************************************************************************************************************
/****************************************************************************
* Name: cp15_invalidate_tlb_bymva
*
* Description:
@ -944,7 +959,7 @@ struct section_mapping_s
* Input Parameters:
* vaddr - The virtual address to be invalidated
*
************************************************************************************************************/
****************************************************************************/
.macro cp15_invalidate_tlb_bymva, vaddr
dsb
@ -957,7 +972,7 @@ struct section_mapping_s
isb
.endm
/************************************************************************************************************
/****************************************************************************
* Name: cp15_wrdacr
*
* Description:
@ -966,7 +981,7 @@ struct section_mapping_s
* Input Parameters:
* dacr - The new value of the DACR
*
************************************************************************************************************/
****************************************************************************/
.macro cp15_wrdacr, dacr
mcr p15, 0, \dacr, c3, c0, 0
@ -980,7 +995,7 @@ struct section_mapping_s
nop
.endm
/************************************************************************************************************
/****************************************************************************
* Name: cp15_wrttb
*
* Description:
@ -993,7 +1008,7 @@ struct section_mapping_s
* Input Parameters:
* ttb - The new value of the TTBR0 register
*
************************************************************************************************************/
****************************************************************************/
.macro cp15_wrttb, ttb, scratch
mcr p15, 0, \ttb, c2, c0, 0
@ -1009,7 +1024,7 @@ struct section_mapping_s
mcr p15, 0, \scratch, c2, c0, 2
.endm
/************************************************************************************************************
/****************************************************************************
* Name: pg_l2map
*
* Description:
@ -1042,7 +1057,7 @@ struct section_mapping_s
* - The L2 page tables have been zeroed prior to calling this function
* - pg_l1span has been called to initialize the L1 table.
*
************************************************************************************************************/
****************************************************************************/
#ifdef CONFIG_PAGING
.macro pg_l2map, l2, ppage, npages, mmuflags, tmp
@ -1079,13 +1094,14 @@ struct section_mapping_s
.endm
#endif /* CONFIG_PAGING */
/************************************************************************************************************
/****************************************************************************
* Name: pg_l1span
*
* Description:
* Write several, contiguous, unmapped, small L1 page table entries. As many
* entries will be written as many as needed to span npages. This macro is
* used when CONFIG_PAGING is enable. In this case, it is used as follows:
* Write several, contiguous, unmapped, small L1 page table entries.
* As many entries will be written as many as needed to span npages.
* This macro is used when CONFIG_PAGING is enable. In this case,
* it is used as follows:
*
* ldr r0, =PG_L1_PGTABLE_PADDR <-- Address in the L1 table
* ldr r1, =PG_L2_PGTABLE_PADDR <-- Physical address of L2 page table
@ -1095,9 +1111,11 @@ struct section_mapping_s
* pg_l1span r0, r1, r2, r3, r4, r4
*
* Input Parameters (unmodified unless noted):
* l1 - Physical or virtual address in the L1 table to begin writing (modified)
* l1 - Physical or virtual address in the L1 table to begin writing
* (modified)
* l2 - Physical start address in the L2 page table (modified)
* npages - Number of pages to required to span that memory region (modified)
* npages - Number of pages to required to span that memory region
* (modified)
* ppage - The number of pages in page 1 (modified)
* mmuflags - L1 MMU flags to use
*
@ -1115,7 +1133,7 @@ struct section_mapping_s
* - The MMU is not yet enabled
* - The L2 page tables have been zeroed prior to calling this function
*
************************************************************************************************************/
****************************************************************************/
#ifdef CONFIG_PAGING
.macro pg_l1span, l1, l2, npages, ppage, mmuflags, tmp
@ -1158,13 +1176,13 @@ struct section_mapping_s
#endif /* CONFIG_PAGING */
#endif /* __ASSEMBLY__ */
/************************************************************************************************************
/****************************************************************************
* Inline Functions
************************************************************************************************************/
****************************************************************************/
#ifndef __ASSEMBLY__
/************************************************************************************************************
/****************************************************************************
* Name: cp15_disable_mmu
*
* Description:
@ -1173,7 +1191,7 @@ struct section_mapping_s
* Input Parameters:
* None
*
************************************************************************************************************/
****************************************************************************/
static inline void cp15_disable_mmu(void)
{
@ -1188,21 +1206,22 @@ static inline void cp15_disable_mmu(void)
);
}
/************************************************************************************************************
/****************************************************************************
* Name: cp15_invalidate_tlbs
*
* Description:
* Invalidate entire unified TLB
*
* The Invalidate entire TLB operations invalidate all unlocked entries in the
* TLB. The operation ignores the value in the register Rt specified by the MCR
* instruction that performs the operation. Software does not have to write a
* value to the register before issuing the MCR instruction.
* The Invalidate entire TLB operations invalidate all unlocked entries
* in the TLB. The operation ignores the value in the register Rt specified
* by the MCR instruction that performs the operation. Software does not
* have to write a value to the register before issuing the MCR
* instruction.
*
* Input Parameters:
* None
*
************************************************************************************************************/
****************************************************************************/
static inline void cp15_invalidate_tlbs(void)
{
@ -1215,7 +1234,7 @@ static inline void cp15_invalidate_tlbs(void)
);
}
/************************************************************************************************************
/****************************************************************************
* Name: cp15_invalidate_tlb_bymva
*
* Description:
@ -1224,7 +1243,7 @@ static inline void cp15_invalidate_tlbs(void)
* Input Parameters:
* vaddr - The virtual address to be invalidated
*
************************************************************************************************************/
****************************************************************************/
static inline void cp15_invalidate_tlb_bymva(uint32_t vaddr)
{
@ -1244,7 +1263,7 @@ static inline void cp15_invalidate_tlb_bymva(uint32_t vaddr)
);
}
/************************************************************************************************************
/****************************************************************************
* Name: cp15_wrdacr
*
* Description:
@ -1253,7 +1272,7 @@ static inline void cp15_invalidate_tlb_bymva(uint32_t vaddr)
* Input Parameters:
* dacr - The new value of the DACR
*
************************************************************************************************************/
****************************************************************************/
static inline void cp15_wrdacr(unsigned int dacr)
{
@ -1274,7 +1293,7 @@ static inline void cp15_wrdacr(unsigned int dacr)
);
}
/************************************************************************************************************
/****************************************************************************
* Name: cp15_wrttb
*
* Description:
@ -1287,7 +1306,7 @@ static inline void cp15_wrdacr(unsigned int dacr)
* Input Parameters:
* ttb - The new value of the TTBR0 register
*
************************************************************************************************************/
****************************************************************************/
static inline void cp15_wrttb(unsigned int ttb)
{
@ -1310,16 +1329,17 @@ static inline void cp15_wrttb(unsigned int ttb)
);
}
/************************************************************************************************************
/****************************************************************************
* Name: mmu_l1_getentry
*
* Description:
* Given a virtual address, return the value of the corresponding L1 table entry.
* Given a virtual address, return the value of the corresponding L1 table
* entry.
*
* Input Parameters:
* vaddr - The virtual address to be mapped.
*
************************************************************************************************************/
****************************************************************************/
#ifndef CONFIG_ARCH_ROMPGTABLE
static inline uint32_t mmu_l1_getentry(uint32_t vaddr)
@ -1333,18 +1353,18 @@ static inline uint32_t mmu_l1_getentry(uint32_t vaddr)
}
#endif
/************************************************************************************************************
/****************************************************************************
* Name: mmu_l2_getentry
*
* Description:
* Given a address of the beginning of an L2 page table and a virtual address,
* return the value of the corresponding L2 page table entry.
* Given a address of the beginning of an L2 page table and a virtual
* address, return the value of the corresponding L2 page table entry.
*
* Input Parameters:
* l2vaddr - The virtual address of the beginning of the L2 page table
* vaddr - The virtual address to be mapped.
*
************************************************************************************************************/
****************************************************************************/
#ifndef CONFIG_ARCH_ROMPGTABLE
static inline uint32_t mmu_l2_getentry(uint32_t l2vaddr, uint32_t vaddr)
@ -1367,13 +1387,13 @@ static inline uint32_t mmu_l2_getentry(uint32_t l2vaddr, uint32_t vaddr)
#endif /* __ASSEMBLY__ */
/************************************************************************************************************
/****************************************************************************
* Public Data
************************************************************************************************************/
****************************************************************************/
/************************************************************************************************************
/****************************************************************************
* Public Function Prototypes
************************************************************************************************************/
****************************************************************************/
#ifndef __ASSEMBLY__
#ifdef __cplusplus
@ -1384,27 +1404,27 @@ extern "C"
#define EXTERN extern
#endif
/************************************************************************************************************
/****************************************************************************
* Name: mmu_l1_setentry
*
* Description:
* Set a one level 1 translation table entry. Only a single L1 page table is
* supported.
* Set a one level 1 translation table entry. Only a single L1 page table
* is supported.
*
* Input Parameters:
* paddr - The physical address to be mapped. Must be aligned to a 1MB address
* boundary
* vaddr - The virtual address to be mapped. Must be aligned to a 1MB address
* boundary
* paddr - The physical address to be mapped. Must be aligned to a 1MB
* address boundary
* vaddr - The virtual address to be mapped. Must be aligned to a 1MB
* address boundary
* mmuflags - The MMU flags to use in the mapping.
*
************************************************************************************************************/
****************************************************************************/
#ifndef CONFIG_ARCH_ROMPGTABLE
void mmu_l1_setentry(uint32_t paddr, uint32_t vaddr, uint32_t mmuflags);
#endif
/************************************************************************************************************
/****************************************************************************
* Name: mmu_l1_restore
*
* Description:
@ -1415,13 +1435,13 @@ void mmu_l1_setentry(uint32_t paddr, uint32_t vaddr, uint32_t mmuflags);
* vaddr - A virtual address to be mapped
* l1entry - The value to write into the page table entry
*
************************************************************************************************************/
****************************************************************************/
#if !defined(CONFIG_ARCH_ROMPGTABLE) && defined(CONFIG_ARCH_ADDRENV)
void mmu_l1_restore(uintptr_t vaddr, uint32_t l1entry);
#endif
/************************************************************************************************************
/****************************************************************************
* Name: mmu_l1_clrentry
*
* Description:
@ -1431,13 +1451,13 @@ void mmu_l1_restore(uintptr_t vaddr, uint32_t l1entry);
* Input Parameters:
* vaddr - A virtual address within the L1 address region to be unmapped.
*
************************************************************************************************************/
****************************************************************************/
#if !defined (CONFIG_ARCH_ROMPGTABLE) && defined(CONFIG_ARCH_ADDRENV)
# define mmu_l1_clrentry(v) mmu_l1_restore(v,0)
#endif
/************************************************************************************************************
/****************************************************************************
* Name: mmu_l2_setentry
*
* Description:
@ -1452,14 +1472,14 @@ void mmu_l1_restore(uintptr_t vaddr, uint32_t l1entry);
* address boundary
* mmuflags - The MMU flags to use in the mapping.
*
************************************************************************************************************/
****************************************************************************/
#ifndef CONFIG_ARCH_ROMPGTABLE
void mmu_l2_setentry(uint32_t l2vaddr, uint32_t paddr, uint32_t vaddr,
uint32_t mmuflags);
#endif
/************************************************************************************************************
/****************************************************************************
* Name: mmu_l1_map_region
*
* Description:
@ -1469,13 +1489,13 @@ void mmu_l2_setentry(uint32_t l2vaddr, uint32_t paddr, uint32_t vaddr,
* Input Parameters:
* mapping - Describes the mapping to be performed.
*
************************************************************************************************************/
****************************************************************************/
#ifndef CONFIG_ARCH_ROMPGTABLE
void mmu_l1_map_region(const struct section_mapping_s *mapping);
#endif
/************************************************************************************************************
/****************************************************************************
* Name: mmu_l1_map_regions
*
* Description:
@ -1486,14 +1506,14 @@ void mmu_l1_map_region(const struct section_mapping_s *mapping);
* mappings - Describes the array of mappings to be performed.
* count - The number of mappings to be performed.
*
************************************************************************************************************/
****************************************************************************/
#ifndef CONFIG_ARCH_ROMPGTABLE
void mmu_l1_map_regions(const struct section_mapping_s *mappings,
size_t count);
#endif
/************************************************************************************************************
/****************************************************************************
* Name: mmu_invalidate_region
*
* Description:
@ -1503,7 +1523,7 @@ void mmu_l1_map_regions(const struct section_mapping_s *mappings,
* vaddr - The beginning of the region to invalidate.
* size - The size of the region in bytes to be invalidated.
*
************************************************************************************************************/
****************************************************************************/
#ifndef CONFIG_ARCH_ROMPGTABLE
void mmu_invalidate_region(uint32_t vstart, size_t size);

2
arch/arm/src/armv7-a/pgalloc.h
View file

@ -205,7 +205,7 @@ static inline uintptr_t get_l2_entry(FAR uint32_t *l2table, uintptr_t vaddr)
}
/****************************************************************************
* Public Functions
* Public Functions Prototypes
****************************************************************************/
/****************************************************************************

97
arch/arm/src/armv7-a/sctlr.h
View file

@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/armv7-a/sctlr.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@ -16,42 +16,47 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************/
****************************************************************************/
/* References:
* "Cortex-A5™ MPCore, Technical Reference Manual", Revision: r0p1, Copyright © 2010
* ARM. All rights reserved. ARM DDI 0434B (ID101810)
* "ARM® Architecture Reference Manual, ARMv7-A and ARMv7-R edition", Copyright ©
* 1996-1998, 2000, 2004-2012 ARM. All rights reserved. ARM DDI 0406C.b (ID072512)
* "Cortex-A5™ MPCore, Technical Reference Manual",
* Revision: r0p1, Copyright © 2010 ARM.
* All rights reserved. ARM DDI 0434B (ID101810)
* "ARM® Architecture Reference Manual, ARMv7-A and ARMv7-R edition",
* Copyright © 1996-1998, 2000, 2004-2012 ARM.
* All rights reserved. ARM DDI 0406C.b (ID072512)
*/
#ifndef __ARCH_ARM_SRC_ARMV7_A_SCTLR_H
#define __ARCH_ARM_SRC_ARMV7_A_SCTLR_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
****************************************************************************/
/* Reference: Cortex-A5™ MPCore Paragraph 4.2, "Register summary." */
/* Main ID Register (MIDR) */
/* TODO: To be provided */
/* Cache Type Register (CTR) */
/* TODO: To be provided */
/* TCM Type Register
*
* The Cortex-A5 MPCore processor does not implement instruction or data Tightly
* Coupled Memory (TCM), so this register always Reads-As-Zero (RAZ).
* The Cortex-A5 MPCore processor does not implement instruction or data
* Tightly Coupled Memory (TCM), so this register always Reads-As-Zero (RAZ).
*
* TLB Type Register
*
* The Cortex-A5 MPCore processor does not implement instruction or data Tightly
* CoupledMemory (TCM), so this register always Reads-As-Zero (RAZ).
* The Cortex-A5 MPCore processor does not implement instruction or data
* Tightly CoupledMemory (TCM), so this register always Reads-As-Zero (RAZ).
*/
/* Multiprocessor Affinity Register (MPIDR) */
@ -69,42 +74,61 @@
#define MPIDR_U (1 << 30) /* Bit 30: Multiprocessing Extensions. */
/* Processor Feature Register 0 (ID_PFR0) */
/* TODO: To be provided */
/* Processor Feature Register 1 (ID_PFR1) */
/* TODO: To be provided */
/* Debug Feature Register 0 (ID_DFR0) */
/* TODO: To be provided */
/* Auxiliary Feature Register 0 (ID_AFR0) */
/* TODO: To be provided */
/* Memory Model Features Register 0 (ID_MMFR0) */
/* Memory Model Features Register 1 (ID_MMFR1) */
/* Memory Model Features Register 2 (ID_MMFR2) */
/* Memory Model Features Register 3 (ID_MMFR3) */
/* TODO: To be provided */
/* Instruction Set Attributes Register 0 (ID_ISAR0) */
/* Instruction Set Attributes Register 1 (ID_ISAR1) */
/* Instruction Set Attributes Register 2 (ID_ISAR2) */
/* Instruction Set Attributes Register 3 (ID_ISAR3) */
/* Instruction Set Attributes Register 4 (ID_ISAR4) */
/* Instruction Set Attributes Register 5 (ID_ISAR5) */
/* Instruction Set Attributes Register 6-7 (ID_ISAR6-7). Reserved. */
/* TODO: Others to be provided */
/* Cache Size Identification Register (CCSIDR) */
/* TODO: To be provided */
/* Cache Level ID Register (CLIDR) */
/* TODO: To be provided */
/* Auxiliary ID Register (AIDR) */
/* TODO: To be provided */
/* Cache Size Selection Register (CSSELR) */
/* TODO: To be provided */
/* System Control Register (SCTLR)
@ -148,6 +172,7 @@
/* Bits 10-31: Reserved */
/* Coprocessor Access Control Register (CPACR) */
/* TODO: To be provided */
/* Secure Configuration Register (SCR) */
@ -166,6 +191,7 @@
/* Bits 10-31: Reserved */
/* Secure Debug Enable Register (SDER) */
/* TODO: To be provided */
/* Non-secure Access Control Register (NSACR) */
@ -181,16 +207,24 @@
/* Bits 19-31: Reserved */
/* Virtualization Control Register (VCR) */
/* TODO: To be provided */
/* Translation Table Base Register 0 (TTBR0). See mmu.h */
/* Translation Table Base Register 1 (TTBR1). See mmu.h */
/* Translation Table Base Control Register (TTBCR). See mmu.h */
/* Domain Access Control Register (DACR). See mmu.h */
/* Data Fault Status Register (DFSR). See mmu.h */
/* Instruction Fault Status Register (IFSR). See mmu.h */
/* Auxiliary Data Fault Status Register (ADFSR). Not used in this implementation. */
/* Auxiliary Data Fault Status Register (ADFSR).
* Not used in this implementation.
*/
/* Data Fault Address Register(DFAR)
*
@ -198,13 +232,13 @@
*
* Instruction Fault Address Register(IFAR)
*
* Holds the MVA of the faulting address of the instruction that caused a prefetch
* abort.
* Holds the MVA of the faulting address of the instruction that caused a
* prefetch abort.
*
* NOP Register
*
* The use of this register is optional and deprecated. Use the NOP instruction
* instead.
* The use of this register is optional and deprecated.
* Use the NOP instruction instead.
*
* Physical Address Register (PAR)
*
@ -214,11 +248,12 @@
*
* Instruction Synchronization Barrier
*
* The use of ISB is optional and deprecated. Use the instruction ISB instead.
* The use of ISB is optional and deprecated.
* Use the instruction ISB instead.
*
* Data Memory Barrier
* The use of DMB is deprecated and, on Cortex-A5 MPCore, behaves as NOP. Use the
* instruction DMB instead.
* The use of DMB is deprecated and, on Cortex-A5 MPCore, behaves as NOP.
* Use the instruction DMB instead.
*/
/* Vector Base Address Register (VBAR) */
@ -226,12 +261,15 @@
#define VBAR_MASK (0xffffffe0)
/* Monitor Vector Base Address Register (MVBAR) */
/* TODO: To be provided */
/* Interrupt Status Register (ISR) */
/* TODO: To be provided */
/* Virtualization Interrupt Register (VIR) */
/* TODO: To be provided */
/* Context ID Register (CONTEXTIDR) */
@ -242,28 +280,29 @@
#define CONTEXTIDR_PROCID_MASK (0x00ffffff << CONTEXTIDR_PROCID_SHIFT)
/* Configuration Base Address Register (CBAR) */
/* TODO: To be provided */
/************************************************************************************
/****************************************************************************
* Assembly Macros
************************************************************************************/
****************************************************************************/
#ifdef __ASSEMBLY__
/* Get the device ID */
.macro cp15_rdid, id
mrc p15, 0, \id, c0, c0, 0
mrc p15, 0, \id, c0, c0, 0
.endm
/* Read/write the system control register (SCTLR) */
.macro cp15_rdsctlr, sctlr
mrc p15, 0, \sctlr, c1, c0, 0
mrc p15, 0, \sctlr, c1, c0, 0
.endm
.macro cp15_wrsctlr, sctlr
mcr p15, 0, \sctlr, c1, c0, 0
mcr p15, 0, \sctlr, c1, c0, 0
nop
nop
nop
@ -275,9 +314,9 @@
.endm
#endif /* __ASSEMBLY__ */
/************************************************************************************
/****************************************************************************
* Inline Functions
************************************************************************************/
****************************************************************************/
#ifndef __ASSEMBLY__

2
arch/arm/src/armv7-a/scu.h
View file

@ -144,7 +144,7 @@
#define SCU_SNSAC_GTIM_CPU(n) (1 << ((n)+8)) /* CPUn has non-secure access to global timer */
/****************************************************************************
* Public Functions
* Public Functions Prototypes
****************************************************************************/
/****************************************************************************

29
arch/arm/src/armv7-a/svcall.h
View file

@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/armv7-a/svcall.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@ -16,14 +16,14 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_ARMV7_A_SVCALL_H
#define __ARCH_ARM_SRC_ARMV7_A_SVCALL_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
@ -33,15 +33,15 @@
#ifdef CONFIG_LIB_SYSCALL
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
****************************************************************************/
/* Configuration ********************************************************************/
/* Configuration ************************************************************/
/* This logic uses one system call for the syscall return. So a minimum of one
* syscall values must be reserved. If CONFIG_BUILD_KERNEL is defined, then four
* more syscall values must be reserved.
/* This logic uses one system call for the syscall return. So a minimum of
* one syscall values must be reserved. If CONFIG_BUILD_KERNEL is defined,
* then four more syscall values must be reserved.
*/
#ifdef CONFIG_BUILD_KERNEL
@ -58,7 +58,7 @@
# endif
#endif
/* Cortex-A system calls ************************************************************/
/* Cortex-A system calls ****************************************************/
/* SYS call 0:
*
@ -93,7 +93,8 @@
/* SYS call 4:
*
* void signal_handler(_sa_sigaction_t sighand, int signo, FAR siginfo_t *info,
* void signal_handler(_sa_sigaction_t sighand,
* int signo, FAR siginfo_t *info,
* FAR void *ucontext);
*/
@ -108,9 +109,9 @@
#endif /* CONFIG_BUILD_KERNEL */
/************************************************************************************
/****************************************************************************
* Inline Functions
************************************************************************************/
****************************************************************************/
#endif /* CONFIG_LIB_SYSCALL */
#endif /* __ARCH_ARM_SRC_ARMV7_A_SVCALL_H */