From 3f85df583c28e54eedbf97148e2bc1685ad79bc9 Mon Sep 17 00:00:00 2001 From: Yanfeng Liu Date: Fri, 17 Jan 2025 15:08:58 +0800 Subject: [PATCH] arch/armv7-r: revise headers to support QEMU armv7-r This revise armv7-r/ header files needed to support QEMU cortex-r5 virtual process for armv7-r family. Signed-off-by: Yanfeng Liu --- arch/arm/include/armv7-r/cp15.h | 2 ++ arch/arm/src/armv7-r/mpcore.h | 4 ++++ arch/arm/src/armv7-r/sctlr.h | 4 ++++ 3 files changed, 10 insertions(+) diff --git a/arch/arm/include/armv7-r/cp15.h b/arch/arm/include/armv7-r/cp15.h index fef41b769a..12cb11956e 100644 --- a/arch/arm/include/armv7-r/cp15.h +++ b/arch/arm/include/armv7-r/cp15.h @@ -161,6 +161,8 @@ #define CP15_CNTPCT(lo,hi) _CP15_64(0, lo, hi, c14) /* Physical Count register */ +#define CP15_CNTP_CVAL(lo,hi) _CP15_64(2, lo, hi, c14) /* Physical Timer CompareValue register */ + #define CP15_DCIALLU(r) _CP15(0, r, c15, c5, 0) /* Invalidate data cache */ #define CP15_SET(reg, value) \ diff --git a/arch/arm/src/armv7-r/mpcore.h b/arch/arm/src/armv7-r/mpcore.h index 4ec17d056f..b9178feb96 100644 --- a/arch/arm/src/armv7-r/mpcore.h +++ b/arch/arm/src/armv7-r/mpcore.h @@ -47,14 +47,18 @@ /* Peripheral Base Offsets **************************************************/ #define MPCORE_SCU_OFFSET 0x0000 /* 0x0000-0x00fc SCU registers */ +#ifndef MPCORE_ICC_OFFSET #define MPCORE_ICC_OFFSET 0x2000 /* 0x0000-0x00FC Interrupt controller interface */ +#endif #define MPCORE_GTM_OFFSET 0x0200 /* 0x0200-0x02ff Global timer */ /* 0x0300-0x05ff Reserved */ #define MPCORE_PTM_OFFSET 0x0600 /* 0x0600-0x06ff Private timers and watchdogs */ /* 0x0700-0x07ff Reserved */ +#ifndef MPCORE_ICD_OFFSET #define MPCORE_ICD_OFFSET 0x1000 /* 0x1000-0x1fff Interrupt Distributor */ +#endif /* Peripheral Base Addresses ************************************************/ diff --git a/arch/arm/src/armv7-r/sctlr.h b/arch/arm/src/armv7-r/sctlr.h index e8e8f0dcbf..331d9375f7 100644 --- a/arch/arm/src/armv7-r/sctlr.h +++ b/arch/arm/src/armv7-r/sctlr.h @@ -42,6 +42,10 @@ * Pre-processor Definitions ****************************************************************************/ +/* Vector Base Address Register (VBAR) */ + +#define VBAR_MASK (0xffffffe0) + /* CP15 c0 Registers ********************************************************/ /* Main ID Register (MIDR): CRn=c0, opc1=0, CRm=c0, opc2=0