From 41d3ef5f1b61837d16dc33fec8edef3b64c60a0d Mon Sep 17 00:00:00 2001 From: Augusto Fraga Giachero Date: Wed, 7 Aug 2019 09:01:10 -0600 Subject: [PATCH] arch/arm/src/lpc17xx_40xx/lpc17_40_ethernet.c: Follow the procedure listed in the LPC176x/5x User Manual when reading from and writing to the PHY's registers (section 10.11.14). I couldn't see any behavioral change after this commit, but nonetheless is a good practice to follow the manufacturer's recommended procedure. --- arch/arm/src/lpc17xx_40xx/lpc17_40_ethernet.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/arm/src/lpc17xx_40xx/lpc17_40_ethernet.c b/arch/arm/src/lpc17xx_40xx/lpc17_40_ethernet.c index 7c3c9c0321..31c33161b1 100644 --- a/arch/arm/src/lpc17xx_40xx/lpc17_40_ethernet.c +++ b/arch/arm/src/lpc17xx_40xx/lpc17_40_ethernet.c @@ -2317,6 +2317,8 @@ static void lpc17_40_phywrite(uint8_t phyaddr, uint8_t regaddr, uint16_t phydata { uint32_t regval; + lpc17_40_putreg(0, LPC17_40_ETH_MCMD); + /* Set PHY address and PHY register address */ regval = ((uint32_t)phyaddr << ETH_MADR_PHYADDR_SHIFT) | @@ -2359,7 +2361,7 @@ static uint16_t lpc17_40_phyread(uint8_t phyaddr, uint8_t regaddr) { uint32_t regval; - lpc17_40_putreg(0, LPC17_40_ETH_MCMD); + lpc17_40_putreg(1, LPC17_40_ETH_MCMD); /* Set PHY address and PHY register address */