riscv/saveusercontext: Fix FPU state save

2023-06-01 15:37:57 +03:00 · 2023-06-01 15:37:57 +03:00 · 4a468b8d3b
commit 4a468b8d3b
parent 0ea9debfce
1 changed files with 4 additions and 1 deletions
--- a/arch/risc-v/src/common/riscv_saveusercontext.S
+++ b/arch/risc-v/src/common/riscv_saveusercontext.S
@ -56,7 +56,10 @@ up_saveusercontext:
  REGSTORE   sp, REG_X2(a0)       /* original SP */
  REGSTORE   x1, REG_EPC(a0)

-  riscv_savefpu   a0
+#ifdef CONFIG_ARCH_FPU
+  addi       a0, a0, INT_XCPT_SIZE /* Save FPU after integer regs */
+  riscv_savefpu a0
+#endif

  li         a0, 0
  jr         ra