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Add support for STM32F429N (TFBGA) chip

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Signed-off-by: Marten Svanfeldt <marten@intuitiveaerial.com>
This commit is contained in:
Marten Svanfeldt 2015-10-21 10:30:57 +08:00
parent ddf936c913
commit 4d879a33ee
6 changed files with 58 additions and 1 deletions
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38
arch/arm/include/stm32/chip.h
View file

@ -2307,6 +2307,44 @@
# define STM32_NRNG 0 /* Random number generator (RNG) */
# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */
#elif defined(CONFIG_ARCH_CHIP_STM32F429N) /* TFBGA216 1024/2048KiB flash 256KiB SRAM */
# undef CONFIG_STM32_STM32L15XX /* STM32L151xx and STM32L152xx family */
# undef CONFIG_STM32_ENERGYLITE /* STM32L EnergyLite family */
# undef CONFIG_STM32_STM32F10XX /* STM32F10xxx family */
# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
# undef CONFIG_STM32_MEDIUMPLUSDENSITY /* STM32L15xxC w/ 32/256 Kbytes */
# undef CONFIG_STM32_HIGHDENSITY /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */
# undef CONFIG_STM32_VALUELINE /* STM32F100x */
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */
# define CONFIG_STM32_STM32F40XX 1 /* STM32F405xx, STM32407xx and STM32F427/437 */
# define STM32_NFSMC 1 /* FSMC */
# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */
# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA
* 32-bit general timers TIM2 and 5 with DMA */
# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */
# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */
# define STM32_NDMA 2 /* DMA1-2 */
# define STM32_NSPI 4 /* SPI1-4 */
# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */
# define STM32_NUSART 8 /* USART1-3 and 6, UART 4-5 and 7-8 */
# define STM32_NI2C 3 /* I2C1-3 */
# define STM32_NCAN 2 /* CAN1-2 */
# define STM32_NSDIO 1 /* SDIO */
# define STM32_NLCD 0 /* No LCD */
# define STM32_NUSBOTG 1 /* USB OTG FS/HS */
# define STM32_NGPIO 168 /* GPIOA-K */
# define STM32_NADC 3 /* 12-bit ADC1-3, 24 channels */
# define STM32_NDAC 2 /* 12-bit DAC1-2 */
# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */
# define STM32_NCRC 1 /* CRC */
# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */
# define STM32_NRNG 1 /* Random number generator (RNG) */
# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */
#else
# error "Unsupported STM32 chip"
#endif

1
arch/arm/src/stm32/chip/stm32f40xxx_memorymap.h
View file

@ -187,6 +187,7 @@
#define STM32_GPIOG_BASE 0x40021800 /* 0x40021800-0x40021bff: GPIO Port G */
#define STM32_GPIOH_BASE 0x40021C00 /* 0x40021C00-0x40021fff: GPIO Port H */
#define STM32_GPIOI_BASE 0x40022000 /* 0x40022000-0x400223ff: GPIO Port I */
#define STM32_GPIOJ_BASE 0x40022400 /* 0x40022400-0x400227ff: GPIO Port J */
#define STM32_GPIOK_BASE 0x40022800 /* 0x40022800-0x40022Bff: GPIO Port K */
#define STM32_CRC_BASE 0x40023000 /* 0x40023000-0x400233ff: CRC */
#define STM32_RCC_BASE 0x40023800 /* 0x40023800-0x40023bff: Reset and Clock control RCC */

2
arch/arm/src/stm32/chip/stm32f40xxx_rcc.h
View file

@ -317,6 +317,8 @@
#define RCC_AHB1ENR_GPIOGEN (1 << 6) /* Bit 6: IO port G clock enable */
#define RCC_AHB1ENR_GPIOHEN (1 << 7) /* Bit 7: IO port H clock enable */
#define RCC_AHB1ENR_GPIOIEN (1 << 8) /* Bit 8: IO port I clock enable */
#define RCC_AHB1ENR_GPIOJEN (1 << 9) /* Bit 9: IO port J clock enable */
#define RCC_AHB1ENR_GPIOKEN (1 << 10) /* Bit 10: IO port K clock enable */
#define RCC_AHB1ENR_CRCEN (1 << 12) /* Bit 12: CRC clock enable */
#define RCC_AHB1ENR_BKPSRAMEN (1 << 18) /* Bit 18: Backup SRAM interface clock enable */
#define RCC_AHB1ENR_CCMDATARAMEN (1 << 20) /* Bit 20: CCM data RAM clock enable */

6
arch/arm/src/stm32/stm32_dumpgpio.c
View file

@ -58,8 +58,12 @@
#ifdef CONFIG_DEBUG
static const char g_portchar[STM32_NGPIO_PORTS] =
{
#if STM32_NGPIO_PORTS > 9
#if STM32_NGPIO_PORTS > 11
# error "Additional support required for this number of GPIOs"
#elif STM32_NGPIO_PORTS > 10
'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I', 'J', 'K'
#elif STM32_NGPIO_PORTS > 9
'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I', 'J'
#elif STM32_NGPIO_PORTS > 8
'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I'
#elif STM32_NGPIO_PORTS > 7

6
arch/arm/src/stm32/stm32_gpio.c
View file

@ -117,6 +117,12 @@ const uint32_t g_gpiobase[STM32_NGPIO_PORTS] =
#if STM32_NGPIO_PORTS > 8
STM32_GPIOI_BASE,
#endif
#if STM32_NGPIO_PORTS > 9
STM32_GPIOJ_BASE,
#endif
#if STM32_NGPIO_PORTS > 10
STM32_GPIOK_BASE,
#endif
#endif /* CONFIG_STM32_STM32L15XX */
};

6
arch/arm/src/stm32/stm32f40xxx_rcc.c
View file

@ -159,6 +159,12 @@ static inline void rcc_enableahb1(void)
#endif
#if STM32_NGPIO > 128
|RCC_AHB1ENR_GPIOIEN
#endif
#if STM32_NGPIO > 144
|RCC_AHB1ENR_GPIOJEN
#endif
#if STM32_NGPIO > 160
|RCC_AHB1ENR_GPIOKEN
#endif
);
#endif