From 51171d66f28b73a28a6edfe51fbc814f58b49c49 Mon Sep 17 00:00:00 2001 From: Ville Juven Date: Wed, 27 Nov 2024 13:00:07 +0200 Subject: [PATCH] riscv/riscv_ipi.h: Do not write to CSR_MIP.MSIP as it is read-only From the RISV-V Privileged Spec v1.10 (3.1.14 MIP/MIE): Only the bits corresponding to lower-privilege software interrupts (USIP, SSIP), timer interrupts (UTIP, STIP), and external interrupts (UEIP, SEIP) in mip are writable through this CSR address; the remaining bits are read-only. Thus, it is futile to write to the M-mode status bit via the CSR, only access via RISCV_IPI is valid. --- arch/risc-v/src/common/riscv_ipi.h | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/arch/risc-v/src/common/riscv_ipi.h b/arch/risc-v/src/common/riscv_ipi.h index 9f61e58798..666aa546d1 100644 --- a/arch/risc-v/src/common/riscv_ipi.h +++ b/arch/risc-v/src/common/riscv_ipi.h @@ -46,10 +46,13 @@ static inline void riscv_ipi_send(int cpu) static inline void riscv_ipi_clear(int cpu) { -#if defined(RISCV_IPI) && !defined(CONFIG_ARCH_USE_S_MODE) - putreg32(0, (uintptr_t)RISCV_IPI + (4 * riscv_cpuid_to_hartid(cpu))); -#endif +#if defined(CONFIG_ARCH_USE_S_MODE) CLEAR_CSR(CSR_IP, IP_SIP); +#elif defined(RISCV_IPI) + putreg32(0, (uintptr_t)RISCV_IPI + (4 * riscv_cpuid_to_hartid(cpu))); +#else +# error "No IPI support for this SoC" +#endif } #endif /* __ARCH_RISCV_SRC_COMMON_RISCV_IPI_H */