diff --git a/arch/README.txt b/arch/README.txt index bd49fb31a7..ffdb4ba317 100644 --- a/arch/README.txt +++ b/arch/README.txt @@ -244,6 +244,21 @@ arch/x86 - Intel x86 architectures arch/x86/include/i486 and arch/x86/src/i486 arch/x86/include/qemu and arch/x86/src/qemu +arch/xtensa + + Implementations based on the Cadence® Tensilica® Xtensa® processors, + such as the Xtensa LX6 dataplane processing units (DPUs). At + present, this includes the following subdirectories: + + Common XTENSA support: + arch/xtensa/include and arch/xtensa/src/common + + LX6 DPU support: + arch/xtensa/include/lx6 and arch/xtensa/xtensa/lx6 + + Expressif ESP32 implemenation of the LX6 DPU: + arch/xtensa/include/esp32 and arch/xtensa/xtensa/esp32 + arch/z16 - ZiLOG 16-bit processors This directory holds related, 16-bit architectures from ZiLOG. At present, this includes the following subdirectories: diff --git a/configs/Kconfig b/configs/Kconfig index 2b629c1a4f..2506d8c081 100644 --- a/configs/Kconfig +++ b/configs/Kconfig @@ -170,14 +170,17 @@ config ARCH_BOARD_EKKLM3S9B96 TI/Stellaris EKK-LM3S9B96 board. This board is based on the an EKK-LM3S9B96 which is a Cortex-M3. -config ARCH_BOARD_EZ80F910200KITG - bool "ZiLOG ez80f910200kitg development kit" - depends on ARCH_CHIP_EZ80F91 +config ARCH_BOARD_ESP32CORE + bool "Expressif ESP32 Core board V2" + depends on ARCH_CHIP_ESP32 select ARCH_HAVE_LEDS ---help--- - ez80Acclaim! Microcontroller. This port use the ZiLOG ez80f910200kitg - development kit, eZ80F091 part, and the Zilog ZDS-II Windows command line - tools. The development environment is Cygwin under WinXP. + The ESP32 is a dual-core system from Expressif with two Harvard + architecture Xtensa LX6 CPUs. All embedded memory, external memory + and peripherals are located on the data bus and/or the instruction + bus of these CPUs. With some minor exceptions, the address mapping + of two CPUs is symmetric, meaning they use the same addresses to + access the same memory. config ARCH_BOARD_EZ80F910200ZCO bool "ZiLOG ez80f910200zco development kit" @@ -1383,6 +1386,7 @@ config ARCH_BOARD default "efm32-g8xx-stk" if ARCH_BOARD_EFM32G8XXSTK default "efm32gg-stk3700" if ARCH_BOARD_EFM32GG_STK3700 default "ekk-lm3s9b96" if ARCH_BOARD_EKKLM3S9B96 + default "esp32-core" if ARCH_BOARD_ESP32CORE default "ez80f910200kitg" if ARCH_BOARD_EZ80F910200KITG default "ez80f910200zco" if ARCH_BOARD_EZ80F910200ZCO default "fire-stm32v2" if ARCH_BOARD_FIRE_STM32 @@ -1581,6 +1585,9 @@ endif if ARCH_BOARD_EKKLM3S9B96 source "configs/ekk-lm3s9b96/Kconfig" endif +if ARCH_BOARD_ESP32CORE +source "configs/esp32-core/Kconfig" +endif if ARCH_BOARD_EZ80F910200KITG source "configs/ez80f910200kitg/Kconfig" endif diff --git a/configs/README.txt b/configs/README.txt index 8bf546a298..fa34391328 100644 --- a/configs/README.txt +++ b/configs/README.txt @@ -246,6 +246,14 @@ configs/ekk-lm3s9b96 TI/Stellaris EKK-LM3S9B96 board. This board is based on the an EKK-LM3S9B96 which is a Cortex-M3. +configs/esp-core + The ESP32 is a dual-core system from Expressif with two Harvard + architecture Xtensa LX6 CPUs. All embedded memory, external memory and + nd peripherals are located on the data bus and/or the instruction bus of + bus of these CPUs. With some minor exceptions, the address mapping of two + CPUs is symmetric, meaning they use the same addresses to access the same + memory. + configs/ez80f0910200kitg ez80Acclaim! Microcontroller. This port use the Zilog ez80f0910200kitg development kit, eZ80F091 part, and the Zilog ZDS-II Windows command line diff --git a/configs/esp32-core/Kconfig b/configs/esp32-core/Kconfig new file mode 100644 index 0000000000..719b83d1a5 --- /dev/null +++ b/configs/esp32-core/Kconfig @@ -0,0 +1,8 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +if ARCH_BOARD_ESP32CORE + +endif # ARCH_BOARD_ESP32CORE diff --git a/configs/esp32-core/README.txt b/configs/esp32-core/README.txt new file mode 100644 index 0000000000..84fd259b58 --- /dev/null +++ b/configs/esp32-core/README.txt @@ -0,0 +1,41 @@ +README for the Expressif ESP32 Core board (V2) +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + + The ESP32 is a dual-core system from Expressif with two Harvard + architecture Xtensa LX6 CPUs. All embedded memory, external memory and + peripherals are located on the data bus and/or the instruction bus of + these CPUs. With some minor exceptions, the address mapping of two CPUs + is symmetric, meaning they use the same addresses to access the same + memory. Multiple peripherals in the system can access embedded memory via + DMA. + + The two CPUs are named "PRO_CPU" and "APP_CPU" (for "protocol" and + "application"), however for most purposes the two CPUs are + interchangeable. + + Features: + + * Address Space + - Symmetric address mapping + - 4 GB (32-bit) address space for both data bus and instruction bus + - 1296 KB embedded memory address space + - 19704 KB external memory address space + - 512 KB peripheral address space + - Some embedded and external memory regions can be accessed by either + data bus or instruction bus + - 328 KB DMA address space + * Embedded Memory + - 448 KB Internal ROM + - 520 KB Internal SRAM + - 8 KB RTC FAST Memory + - 8 KB RTC SLOW Memory + * External Memory + Off-chip SPI memory can be mapped into the available address space as + external memory. Parts of the embedded memory can be used as transparent + cache for this external memory. + - Supports up to 16 MB off-Chip SPI Flash. + - Supports up to 8 MB off-Chip SPI SRAM. + * Peripherals + - 41 peripherals + * DMA + - 13 modules are capable of DMA operation \ No newline at end of file