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spi: Adopt CPHA as the abbreviation for clock phase

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This commit is contained in:
Gustavo Henrique Nihei 2021-05-05 15:03:23 -03:00 • committed by Alan Carvalho de Assis
parent 92dba32c8c
commit 534c058d93
10 changed files with 48 additions and 48 deletions
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8
arch/arm/src/imx1/imx_spi.c
View file

@ -826,19 +826,19 @@ static void spi_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode)
switch (mode)
{
case SPIDEV_MODE0: /* CPOL=0 CHPHA=0 */
case SPIDEV_MODE0: /* CPOL=0 CPHA=0 */
modebits = 0;
break;
case SPIDEV_MODE1: /* CPOL=0 CHPHA=1 */
case SPIDEV_MODE1: /* CPOL=0 CPHA=1 */
modebits = CSPI_CTRL_PHA;
break;
case SPIDEV_MODE2: /* CPOL=1 CHPHA=0 */
case SPIDEV_MODE2: /* CPOL=1 CPHA=0 */
modebits = CSPI_CTRL_POL;
break;
case SPIDEV_MODE3: /* CPOL=1 CHPHA=1 */
case SPIDEV_MODE3: /* CPOL=1 CPHA=1 */
modebits = CSPI_CTRL_PHA | CSPI_CTRL_POL;
break;

8
arch/arm/src/imx6/imx_ecspi.c
View file

@ -929,19 +929,19 @@ static void spi_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode)
switch (mode)
{
case SPIDEV_MODE0: /* CPOL=0 CHPHA=0 */
case SPIDEV_MODE0: /* CPOL=0 CPHA=0 */
modebits = 0;
break;
case SPIDEV_MODE1: /* CPOL=0 CHPHA=1 */
case SPIDEV_MODE1: /* CPOL=0 CPHA=1 */
modebits = ECSPI_CONREG_PHA;
break;
case SPIDEV_MODE2: /* CPOL=1 CHPHA=0 */
case SPIDEV_MODE2: /* CPOL=1 CPHA=0 */
modebits = ECSPI_CONREG_POL;
break;
case SPIDEV_MODE3: /* CPOL=1 CHPHA=1 */
case SPIDEV_MODE3: /* CPOL=1 CPHA=1 */
modebits = ECSPI_CONREG_PHA | ECSPI_CONREG_POL;
break;

8
arch/arm/src/tiva/common/tiva_ssi.c
View file

@ -1250,19 +1250,19 @@ static void ssi_setmodeinternal(struct tiva_ssidev_s *priv,
switch (mode)
{
case SPIDEV_MODE0: /* CPOL=0 CHPHA=0 */
case SPIDEV_MODE0: /* CPOL=0 CPHA=0 */
modebits = 0;
break;
case SPIDEV_MODE1: /* CPOL=0 CHPHA=1 */
case SPIDEV_MODE1: /* CPOL=0 CPHA=1 */
modebits = SSI_CR0_SPH;
break;
case SPIDEV_MODE2: /* CPOL=1 CHPHA=0 */
case SPIDEV_MODE2: /* CPOL=1 CPHA=0 */
modebits = SSI_CR0_SPO;
break;
case SPIDEV_MODE3: /* CPOL=1 CHPHA=1 */
case SPIDEV_MODE3: /* CPOL=1 CPHA=1 */
modebits = SSI_CR0_SPH | SSI_CR0_SPO;
break;

8
arch/renesas/src/rx65n/rx65n_rspi.c
View file

@ -1841,19 +1841,19 @@ static void rspi_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode)
switch (mode)
{
case SPIDEV_MODE0: /* CPOL=0 CHPHA=0 */
case SPIDEV_MODE0: /* CPOL=0 CPHA=0 */
modebits = 0;
break;
case SPIDEV_MODE1: /* CPOL=0 CHPHA=1 */
case SPIDEV_MODE1: /* CPOL=0 CPHA=1 */
modebits = RSPI_SPCMD_PHA;
break;
case SPIDEV_MODE2: /* CPOL=1 CHPHA=0 */
case SPIDEV_MODE2: /* CPOL=1 CPHA=0 */
modebits = RSPI_SPCMD_POL;
break;
case SPIDEV_MODE3: /* CPOL=1 CHPHA=1 */
case SPIDEV_MODE3: /* CPOL=1 CPHA=1 */
modebits = RSPI_SPCMD_PHA | RSPI_SPCMD_POL;
break;

8
arch/renesas/src/rx65n/rx65n_rspi_sw.c
View file

@ -1476,19 +1476,19 @@ static void rspi_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode)
switch (mode)
{
case SPIDEV_MODE0: /* CPOL=0 CHPHA=0 */
case SPIDEV_MODE0: /* CPOL=0 CPHA=0 */
modebits = 0;
break;
case SPIDEV_MODE1: /* CPOL=0 CHPHA=1 */
case SPIDEV_MODE1: /* CPOL=0 CPHA=1 */
modebits = RSPI_SPCMD_PHA;
break;
case SPIDEV_MODE2: /* CPOL=1 CHPHA=0 */
case SPIDEV_MODE2: /* CPOL=1 CPHA=0 */
modebits = RSPI_SPCMD_POL;
break;
case SPIDEV_MODE3: /* CPOL=1 CHPHA=1 */
case SPIDEV_MODE3: /* CPOL=1 CPHA=1 */
modebits = RSPI_SPCMD_PHA | RSPI_SPCMD_POL;
break;

8
arch/z80/src/ez80/ez80_spi.c
View file

@ -274,19 +274,19 @@ static void spi_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode)
switch (mode)
{
case SPIDEV_MODE0: /* CPOL=0 CHPHA=0 */
case SPIDEV_MODE0: /* CPOL=0 CPHA=0 */
modebits = 0;
break;
case SPIDEV_MODE1: /* CPOL=0 CHPHA=1 */
case SPIDEV_MODE1: /* CPOL=0 CPHA=1 */
modebits = SPI_CTL_CPHA;
break;
case SPIDEV_MODE2: /* CPOL=1 CHPHA=0 */
case SPIDEV_MODE2: /* CPOL=1 CPHA=0 */
modebits = SPI_CTL_CPOL;
break;
case SPIDEV_MODE3: /* CPOL=1 CHPHA=1 */
case SPIDEV_MODE3: /* CPOL=1 CPHA=1 */
modebits = (SPI_CTL_CPOL | SPI_CTL_CPHA);
break;

24
boards/arm/stm32f7/nucleo-144/Kconfig
View file

@ -154,16 +154,16 @@ choice
Sets SPI 1 clock mode
config NUCLEO_SPI1_TEST_MODE0
bool "CPOL=0 CHPHA=0"
bool "CPOL=0 CPHA=0"
config NUCLEO_SPI1_TEST_MODE1
bool "CPOL=0 CHPHA=1"
bool "CPOL=0 CPHA=1"
config NUCLEO_SPI1_TEST_MODE2
bool "CPOL=1 CHPHA=0"
bool "CPOL=1 CPHA=0"
config NUCLEO_SPI1_TEST_MODE3
bool "CPOL=1 CHPHA=1"
bool "CPOL=1 CPHA=1"
endchoice # "SPI BUS 1 Clock Mode"
@ -199,16 +199,16 @@ choice
Sets SPI 2 clock mode
config NUCLEO_SPI2_TEST_MODE0
bool "CPOL=0 CHPHA=0"
bool "CPOL=0 CPHA=0"
config NUCLEO_SPI2_TEST_MODE1
bool "CPOL=0 CHPHA=1"
bool "CPOL=0 CPHA=1"
config NUCLEO_SPI2_TEST_MODE2
bool "CPOL=1 CHPHA=0"
bool "CPOL=1 CPHA=0"
config NUCLEO_SPI2_TEST_MODE3
bool "CPOL=1 CHPHA=1"
bool "CPOL=1 CPHA=1"
endchoice # "SPI BUS 2 Clock Mode"
@ -244,16 +244,16 @@ choice
Sets SPI 3 clock mode
config NUCLEO_SPI3_TEST_MODE0
bool "CPOL=0 CHPHA=0"
bool "CPOL=0 CPHA=0"
config NUCLEO_SPI3_TEST_MODE1
bool "CPOL=0 CHPHA=1"
bool "CPOL=0 CPHA=1"
config NUCLEO_SPI3_TEST_MODE2
bool "CPOL=1 CHPHA=0"
bool "CPOL=1 CPHA=0"
config NUCLEO_SPI3_TEST_MODE3
bool "CPOL=1 CHPHA=1"
bool "CPOL=1 CPHA=1"
endchoice # "SPI BUS 3 Clock Mode"

8
include/nuttx/spi/qspi.h
View file

@ -228,10 +228,10 @@
enum qspi_mode_e
{
QSPIDEV_MODE0 = 0, /* CPOL=0 CHPHA=0 */
QSPIDEV_MODE1, /* CPOL=0 CHPHA=1 */
QSPIDEV_MODE2, /* CPOL=1 CHPHA=0 */
QSPIDEV_MODE3 /* CPOL=1 CHPHA=1 */
QSPIDEV_MODE0 = 0, /* CPOL=0 CPHA=0 */
QSPIDEV_MODE1, /* CPOL=0 CPHA=1 */
QSPIDEV_MODE2, /* CPOL=1 CPHA=0 */
QSPIDEV_MODE3 /* CPOL=1 CPHA=1 */
};
/* This structure describes one command transfer */

8
include/nuttx/spi/slave.h
View file

@ -467,10 +467,10 @@
enum spi_smode_e
{
SPISLAVE_MODE0 = 0, /* CPOL=0 CHPHA=0 */
SPISLAVE_MODE1, /* CPOL=0 CHPHA=1 */
SPISLAVE_MODE2, /* CPOL=1 CHPHA=0 */
SPISLAVE_MODE3 /* CPOL=1 CHPHA=1 */
SPISLAVE_MODE0 = 0, /* CPOL=0 CPHA=0 */
SPISLAVE_MODE1, /* CPOL=0 CPHA=1 */
SPISLAVE_MODE2, /* CPOL=1 CPHA=0 */
SPISLAVE_MODE3 /* CPOL=1 CPHA=1 */
};
/* The SPI slave controller driver vtable */

8
include/nuttx/spi/spi.h
View file

@ -521,10 +521,10 @@ enum spi_devtype_e
enum spi_mode_e
{
SPIDEV_MODE0 = 0, /* CPOL=0 CHPHA=0 */
SPIDEV_MODE1, /* CPOL=0 CHPHA=1 */
SPIDEV_MODE2, /* CPOL=1 CHPHA=0 */
SPIDEV_MODE3, /* CPOL=1 CHPHA=1 */
SPIDEV_MODE0 = 0, /* CPOL=0 CPHA=0 */
SPIDEV_MODE1, /* CPOL=0 CPHA=1 */
SPIDEV_MODE2, /* CPOL=1 CPHA=0 */
SPIDEV_MODE3, /* CPOL=1 CPHA=1 */
SPIDEV_MODETI, /* CPOL=0 CPHA=1 TI Synchronous Serial Frame Format */
};