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arch/stm32f0l0g0: remove references to CONFIG_STM32F0L0G0_FORCEPOWER

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this is copy-paste from stm32, but CONFIG_STM32F0L0G0_FORCEPOWER
is not used in stm32f0l0g0

Signed-off-by: raiden00pl <raiden00@railab.me>
This commit is contained in:
raiden00pl 2025-06-11 14:33:07 +02:00 • committed by Xiang Xiao
parent 840ae60b60
commit 5437dabbff
4 changed files with 1 additions and 124 deletions
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24
arch/arm/src/stm32f0l0g0/stm32c0_rcc.c
View file

@ -163,18 +163,14 @@ static inline void rcc_enableapb1(void)
#ifdef CONFIG_STM32F0L0G0_TIM2
/* Timer 2 clock enable */
#ifdef CONFIG_STM32F0L0G0_FORCEPOWER
regval |= RCC_APB1ENR_TIM2EN;
#endif
#endif
#ifdef CONFIG_STM32F0L0G0_TIM3
/* Timer 3 clock enable */
#ifdef CONFIG_STM32F0L0G0_FORCEPOWER
regval |= RCC_APB1ENR_TIM3EN;
#endif
#endif
#ifdef CONFIG_STM32F0L0G0_FDCAN1
/* FDCAN1 clock enable */
@ -203,34 +199,26 @@ static inline void rcc_enableapb1(void)
#ifdef CONFIG_STM32F0L0G0_USART2
/* USART 2 clock enable */
#ifdef CONFIG_STM32F0L0G0_FORCEPOWER
regval |= RCC_APB1ENR_USART2EN;
#endif
#endif
#ifdef CONFIG_STM32F0L0G0_USART3
/* USART 3 clock enable */
#ifdef CONFIG_STM32F0L0G0_FORCEPOWER
regval |= RCC_APB1ENR_USART3EN;
#endif
#endif
#ifdef CONFIG_STM32F0L0G0_USART4
/* USART 4 clock enable */
#ifdef CONFIG_STM32F0L0G0_FORCEPOWER
regval |= RCC_APB1ENR_USART4EN;
#endif
#endif
#ifdef CONFIG_STM32F0L0G0_I2C1
/* I2C 1 clock enable */
#ifdef CONFIG_STM32F0L0G0_FORCEPOWER
regval |= RCC_APB1ENR_I2C1EN;
#endif
#endif
#ifdef CONFIG_STM32F0L0G0_PWR
/* Power interface clock enable */
@ -268,10 +256,8 @@ static inline void rcc_enableapb2(void)
#ifdef CONFIG_STM32F0L0G0_TIM1
/* TIM1 Timer clock enable */
#ifdef CONFIG_STM32F0L0G0_FORCEPOWER
regval |= RCC_APB2ENR_TIM1EN;
#endif
#endif
#ifdef CONFIG_STM32F0L0G0_SPI1
/* SPI 1 clock enable */
@ -282,42 +268,32 @@ static inline void rcc_enableapb2(void)
#ifdef CONFIG_STM32F0L0G0_USART1
/* USART1 clock enable */
#ifdef CONFIG_STM32F0L0G0_FORCEPOWER
regval |= RCC_APB2ENR_USART1EN;
#endif
#endif
#ifdef CONFIG_STM32F0L0G0_TIM14
/* TIM14 Timer clock enable */
#ifdef CONFIG_STM32F0L0G0_FORCEPOWER
regval |= RCC_APB2ENR_TIM14EN;
#endif
#endif
#ifdef CONFIG_STM32F0L0G0_TIM15
/* TIM5 Timer clock enable */
#ifdef CONFIG_STM32F0L0G0_FORCEPOWER
regval |= RCC_APB2ENR_TIM15EN;
#endif
#endif
#ifdef CONFIG_STM32F0L0G0_TIM16
/* TIM16 Timer clock enable */
#ifdef CONFIG_STM32F0L0G0_FORCEPOWER
regval |= RCC_APB2ENR_TIM16EN;
#endif
#endif
#ifdef CONFIG_STM32F0L0G0_TIM17
/* TIM17 Timer clock enable */
#ifdef CONFIG_STM32F0L0G0_FORCEPOWER
regval |= RCC_APB2ENR_TIM17EN;
#endif
#endif
#ifdef CONFIG_STM32F0L0G0_ADC1
/* ADC 1 clock enable */

40
arch/arm/src/stm32f0l0g0/stm32f0_rcc.c
View file

@ -155,50 +155,38 @@ static inline void rcc_enableapb1(void)
#ifdef CONFIG_STM32F0L0G0_TIM2
/* Timer 2 clock enable */
#ifdef CONFIG_STM32F0L0G0_FORCEPOWER
regval |= RCC_APB1ENR_TIM2EN;
#endif
#endif
#ifdef CONFIG_STM32F0L0G0_TIM3
/* Timer 3 clock enable */
#ifdef CONFIG_STM32F0L0G0_FORCEPOWER
regval |= RCC_APB1ENR_TIM3EN;
#endif
#endif
#ifdef CONFIG_STM32F0L0G0_TIM4
/* Timer 4 clock enable */
#ifdef CONFIG_STM32F0L0G0_FORCEPOWER
regval |= RCC_APB1ENR_TIM4EN;
#endif
#endif
#ifdef CONFIG_STM32F0L0G0_TIM6
/* Timer 6 clock enable */
#ifdef CONFIG_STM32F0L0G0_FORCEPOWER
regval |= RCC_APB1ENR_TIM6EN;
#endif
#endif
#ifdef CONFIG_STM32F0L0G0_TIM7
/* Timer 7 clock enable */
#ifdef CONFIG_STM32F0L0G0_FORCEPOWER
regval |= RCC_APB1ENR_TIM7EN;
#endif
#endif
#ifdef CONFIG_STM32F0L0G0_TIM14
/* Timer 14 clock enable */
#ifdef CONFIG_STM32F0L0G0_FORCEPOWER
regval |= RCC_APB1ENR_TIM14EN;
#endif
#endif
#ifdef CONFIG_STM32F0L0G0_WWDG
/* Window Watchdog clock enable */
@ -215,50 +203,38 @@ static inline void rcc_enableapb1(void)
#ifdef CONFIG_STM32F0L0G0_USART2
/* USART 2 clock enable */
#ifdef CONFIG_STM32F0L0G0_FORCEPOWER
regval |= RCC_APB1ENR_USART2EN;
#endif
#endif
#ifdef CONFIG_STM32F0L0G0_USART3
/* USART 3 clock enable */
#ifdef CONFIG_STM32F0L0G0_FORCEPOWER
regval |= RCC_APB1ENR_USART3EN;
#endif
#endif
#ifdef CONFIG_STM32F0L0G0_USART4
/* USART 4 clock enable */
#ifdef CONFIG_STM32F0L0G0_FORCEPOWER
regval |= RCC_APB1ENR_USART4EN;
#endif
#endif
#ifdef CONFIG_STM32F0L0G0_USART5
/* USART 5 clock enable */
#ifdef CONFIG_STM32F0L0G0_FORCEPOWER
regval |= RCC_APB1ENR_USART5EN;
#endif
#endif
#ifdef CONFIG_STM32F0L0G0_I2C1
/* I2C 1 clock enable */
#ifdef CONFIG_STM32F0L0G0_FORCEPOWER
regval |= RCC_APB1ENR_I2C1EN;
#endif
#endif
#ifdef CONFIG_STM32F0L0G0_I2C2
/* I2C 2 clock enable */
#ifdef CONFIG_STM32F0L0G0_FORCEPOWER
regval |= RCC_APB1ENR_I2C2EN;
#endif
#endif
#ifdef CONFIG_STM32F0L0G0_USB
/* USB clock enable */
@ -326,26 +302,20 @@ static inline void rcc_enableapb2(void)
#ifdef CONFIG_STM32F0L0G0_USART6
/* USART 6 clock enable */
#ifdef CONFIG_STM32F0L0G0_FORCEPOWER
regval |= RCC_APB2ENR_USART6EN;
#endif
#endif
#ifdef CONFIG_STM32F0L0G0_USART7
/* USART 7 clock enable */
#ifdef CONFIG_STM32F0L0G0_FORCEPOWER
regval |= RCC_APB2ENR_USART7EN;
#endif
#endif
#ifdef CONFIG_STM32F0L0G0_USART8
/* USART 8 clock enable */
#ifdef CONFIG_STM32F0L0G0_FORCEPOWER
regval |= RCC_APB2ENR_USART8EN;
#endif
#endif
#ifdef CONFIG_STM32F0L0G0_ADC1
/* ADC 1 clock enable */
@ -356,10 +326,8 @@ static inline void rcc_enableapb2(void)
#ifdef CONFIG_STM32F0L0G0_TIM1
/* Timer 1 clock enable */
#ifdef CONFIG_STM32F0L0G0_FORCEPOWER
regval |= RCC_APB2ENR_TIM1EN;
#endif
#endif
#ifdef CONFIG_STM32F0L0G0_SPI1
/* SPI 1 clock enable */
@ -370,34 +338,26 @@ static inline void rcc_enableapb2(void)
#ifdef CONFIG_STM32F0L0G0_USART1
/* USART1 clock enable */
#ifdef CONFIG_STM32F0L0G0_FORCEPOWER
regval |= RCC_APB2ENR_USART1EN;
#endif
#endif
#ifdef CONFIG_STM32F0L0G0_TIM15
/* Timer 15 clock enable */
#ifdef CONFIG_STM32F0L0G0_FORCEPOWER
regval |= RCC_APB2ENR_TIM15EN;
#endif
#endif
#ifdef CONFIG_STM32F0L0G0_TIM16
/* Timer 16 clock enable */
#ifdef CONFIG_STM32F0L0G0_FORCEPOWER
regval |= RCC_APB2ENR_TIM16EN;
#endif
#endif
#ifdef CONFIG_STM32F0L0G0_TIM17
/* Timer 17 clock enable */
#ifdef CONFIG_STM32F0L0G0_FORCEPOWER
regval |= RCC_APB2ENR_TIM17EN;
#endif
#endif
#if 0
/* DBG clock enable */

33
arch/arm/src/stm32f0l0g0/stm32g0_rcc.c
View file

@ -173,34 +173,26 @@ static inline void rcc_enableapb1(void)
#ifdef CONFIG_STM32F0L0G0_TIM2
/* Timer 2 clock enable */
#ifdef CONFIG_STM32F0L0G0_FORCEPOWER
regval |= RCC_APB1ENR_TIM2EN;
#endif
#endif
#ifdef CONFIG_STM32F0L0G0_TIM3
/* Timer 3 clock enable */
#ifdef CONFIG_STM32F0L0G0_FORCEPOWER
regval |= RCC_APB1ENR_TIM3EN;
#endif
#endif
#ifdef CONFIG_STM32F0L0G0_TIM6
/* Timer 6 clock enable */
#ifdef CONFIG_STM32F0L0G0_FORCEPOWER
regval |= RCC_APB1ENR_TIM6EN;
#endif
#endif
#ifdef CONFIG_STM32F0L0G0_TIM7
/* Timer 7 clock enable */
#ifdef CONFIG_STM32F0L0G0_FORCEPOWER
regval |= RCC_APB1ENR_TIM7EN;
#endif
#endif
#ifdef CONFIG_STM32F0L0G0_SPI2
/* SPI 2 clock enable */
@ -211,50 +203,39 @@ static inline void rcc_enableapb1(void)
#ifdef CONFIG_STM32F0L0G0_USART2
/* USART 2 clock enable */
#ifdef CONFIG_STM32F0L0G0_FORCEPOWER
regval |= RCC_APB1ENR_USART2EN;
#endif
#endif
#ifdef CONFIG_STM32F0L0G0_USART3
/* USART 3 clock enable */
#ifdef CONFIG_STM32F0L0G0_FORCEPOWER
regval |= RCC_APB1ENR_USART3EN;
#endif
#endif
#ifdef CONFIG_STM32F0L0G0_USART4
/* USART 4 clock enable */
#ifdef CONFIG_STM32F0L0G0_FORCEPOWER
regval |= RCC_APB1ENR_USART4EN;
#endif
#endif
#ifdef CONFIG_STM32F0L0G0_LPUSART1
/* USART 5 clock enable */
#ifdef CONFIG_STM32F0L0G0_FORCEPOWER
regval |= RCC_APB1ENR_LPUSART1EN;
#endif
#endif
#ifdef CONFIG_STM32F0L0G0_I2C1
/* I2C 1 clock enable */
#ifdef CONFIG_STM32F0L0G0_FORCEPOWER
regval |= RCC_APB1ENR_I2C1EN;
#endif
#endif
#ifdef CONFIG_STM32F0L0G0_I2C2
/* I2C 2 clock enable */
#ifdef CONFIG_STM32F0L0G0_FORCEPOWER
regval |= RCC_APB1ENR_I2C2EN;
#endif
#endif
#ifdef CONFIG_STM32F0L0G0_PWR
/* Power interface clock enable */
@ -309,10 +290,8 @@ static inline void rcc_enableapb2(void)
#ifdef CONFIG_STM32F0L0G0_TIM1
/* TIM1 Timer clock enable */
#ifdef CONFIG_STM32F0L0G0_FORCEPOWER
regval |= RCC_APB2ENR_TIM1EN;
#endif
#endif
#ifdef CONFIG_STM32F0L0G0_SPI1
/* SPI 1 clock enable */
@ -323,42 +302,32 @@ static inline void rcc_enableapb2(void)
#ifdef CONFIG_STM32F0L0G0_USART1
/* USART1 clock enable */
#ifdef CONFIG_STM32F0L0G0_FORCEPOWER
regval |= RCC_APB2ENR_USART1EN;
#endif
#endif
#ifdef CONFIG_STM32F0L0G0_TIM14
/* TIM14 Timer clock enable */
#ifdef CONFIG_STM32F0L0G0_FORCEPOWER
regval |= RCC_APB2ENR_TIM14EN;
#endif
#endif
#ifdef CONFIG_STM32F0L0G0_TIM15
/* TIM5 Timer clock enable */
#ifdef CONFIG_STM32F0L0G0_FORCEPOWER
regval |= RCC_APB2ENR_TIM15EN;
#endif
#endif
#ifdef CONFIG_STM32F0L0G0_TIM16
/* TIM16 Timer clock enable */
#ifdef CONFIG_STM32F0L0G0_FORCEPOWER
regval |= RCC_APB2ENR_TIM16EN;
#endif
#endif
#ifdef CONFIG_STM32F0L0G0_TIM17
/* TIM17 Timer clock enable */
#ifdef CONFIG_STM32F0L0G0_FORCEPOWER
regval |= RCC_APB2ENR_TIM17EN;
#endif
#endif
#ifdef CONFIG_STM32F0L0G0_ADC1
/* ADC 1 clock enable */

28
arch/arm/src/stm32f0l0g0/stm32l0_rcc.c
View file

@ -182,34 +182,26 @@ static inline void rcc_enableapb1(void)
#ifdef CONFIG_STM32F0L0G0_TIM2
/* Timer 2 clock enable */
#ifdef CONFIG_STM32F0L0G0_FORCEPOWER
regval |= RCC_APB1ENR_TIM2EN;
#endif
#endif
#ifdef CONFIG_STM32F0L0G0_TIM3
/* Timer 3 clock enable */
#ifdef CONFIG_STM32F0L0G0_FORCEPOWER
regval |= RCC_APB1ENR_TIM3EN;
#endif
#endif
#ifdef CONFIG_STM32F0L0G0_TIM6
/* Timer 6 clock enable */
#ifdef CONFIG_STM32F0L0G0_FORCEPOWER
regval |= RCC_APB1ENR_TIM6EN;
#endif
#endif
#ifdef CONFIG_STM32F0L0G0_TIM7
/* Timer 7 clock enable */
#ifdef CONFIG_STM32F0L0G0_FORCEPOWER
regval |= RCC_APB1ENR_TIM7EN;
#endif
#endif
#ifdef CONFIG_STM32F0L0G0_LCD
/* LCD clock enable */
@ -232,50 +224,38 @@ static inline void rcc_enableapb1(void)
#ifdef CONFIG_STM32F0L0G0_USART2
/* USART 2 clock enable */
#ifdef CONFIG_STM32F0L0G0_FORCEPOWER
regval |= RCC_APB1ENR_USART2EN;
#endif
#endif
#ifdef CONFIG_STM32F0L0G0_USART3
/* USART 3 clock enable */
#ifdef CONFIG_STM32F0L0G0_FORCEPOWER
regval |= RCC_APB1ENR_USART3EN;
#endif
#endif
#ifdef CONFIG_STM32F0L0G0_USART4
/* USART 4 clock enable */
#ifdef CONFIG_STM32F0L0G0_FORCEPOWER
regval |= RCC_APB1ENR_USART4EN;
#endif
#endif
#ifdef CONFIG_STM32F0L0G0_USART5
/* USART 5 clock enable */
#ifdef CONFIG_STM32F0L0G0_FORCEPOWER
regval |= RCC_APB1ENR_USART5EN;
#endif
#endif
#ifdef CONFIG_STM32F0L0G0_I2C1
/* I2C 1 clock enable */
#ifdef CONFIG_STM32F0L0G0_FORCEPOWER
regval |= RCC_APB1ENR_I2C1EN;
#endif
#endif
#ifdef CONFIG_STM32F0L0G0_I2C2
/* I2C 2 clock enable */
#ifdef CONFIG_STM32F0L0G0_FORCEPOWER
regval |= RCC_APB1ENR_I2C2EN;
#endif
#endif
#ifdef CONFIG_STM32F0L0G0_USB
/* USB clock enable */
@ -304,10 +284,8 @@ static inline void rcc_enableapb1(void)
#ifdef CONFIG_STM32F0L0G0_I2C3
/* I2C 3 clock enable */
#ifdef CONFIG_STM32F0L0G0_FORCEPOWER
regval |= RCC_APB1ENR_I2C4EN;
#endif
#endif
#ifdef CONFIG_STM32F0L0G0_LPTIM1
/* LPTIM1 clock enable */
@ -345,18 +323,14 @@ static inline void rcc_enableapb2(void)
#ifdef CONFIG_STM32F0L0G0_TIM21
/* TIM21 Timer clock enable */
#ifdef CONFIG_STM32F0L0G0_FORCEPOWER
regval |= RCC_APB2ENR_TIM21EN;
#endif
#endif
#ifdef CONFIG_STM32F0L0G0_TIM22
/* TIM22 Timer clock enable */
#ifdef CONFIG_STM32F0L0G0_FORCEPOWER
regval |= RCC_APB2ENR_TIM10EN;
#endif
#endif
#ifdef CONFIG_STM32F0L0G0_ADC1
/* ADC 1 clock enable */
@ -373,10 +347,8 @@ static inline void rcc_enableapb2(void)
#ifdef CONFIG_STM32F0L0G0_USART1
/* USART1 clock enable */
#ifdef CONFIG_STM32F0L0G0_FORCEPOWER
regval |= RCC_APB2ENR_USART1EN;
#endif
#endif
#if 0
/* DBG clock enable */