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sem:remove sem default protocl

Browse source 
Signed-off-by: anjiahao <anjiahao@xiaomi.com>
This commit is contained in:
anjiahao 2022-10-18 17:09:22 +08:00 • committed by Xiang Xiao
parent 205c8934a3
commit 5724c6b2e4
216 changed files with 2 additions and 1155 deletions
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1
arch/arm/src/cxd56xx/cxd56_emmc.c
View file

@ -942,7 +942,6 @@ int cxd56_emmcinitialize(void)
memset(priv, 0, sizeof(struct cxd56_emmc_state_s));
nxmutex_init(&priv->lock);
nxsem_init(&g_waitsem, 0, 0);
nxsem_set_protocol(&g_waitsem, SEM_PRIO_NONE);
ret = emmc_hwinitialize();
if (ret != OK)

1
arch/arm/src/cxd56xx/cxd56_farapi.c
View file

@ -292,7 +292,6 @@ void cxd56_farapiinitialize(void)
#endif
nxmutex_init(&g_farlock);
nxsem_init(&g_farwait, 0, 0);
nxsem_set_protocol(&g_farwait, SEM_PRIO_NONE);
cxd56_iccinit(CXD56_PROTO_MBX);
cxd56_iccinit(CXD56_PROTO_FLG);

1
arch/arm/src/cxd56xx/cxd56_ge2d.c
View file

@ -186,7 +186,6 @@ int cxd56_ge2dinitialize(const char *devname)
nxmutex_init(&g_lock);
nxsem_init(&g_wait, 0, 0);
nxsem_set_protocol(&g_wait, SEM_PRIO_NONE);
ret = register_driver(devname, &g_ge2dfops, 0666, NULL);
if (ret != 0)

4
arch/arm/src/cxd56xx/cxd56_gnss.c
View file

@ -2609,8 +2609,6 @@ static int cxd56_gnss_open(struct file *filep)
goto err0;
}
nxsem_set_protocol(&priv->syncsem, SEM_PRIO_NONE);
/* Prohibit the clock change during loading image */
up_pm_acquire_freqlock(&g_hold_lock);
@ -3029,8 +3027,6 @@ static int cxd56_gnss_register(const char *devpath)
goto err0;
}
nxsem_set_protocol(&priv->apiwait, SEM_PRIO_NONE);
ret = nxmutex_init(&priv->ioctllock);
if (ret < 0)
{

1
arch/arm/src/cxd56xx/cxd56_hostif.c
View file

@ -442,7 +442,6 @@ static int hif_initialize(struct hostif_buff_s *buffer)
cxd56_iccinit(CXD56_PROTO_HOSTIF);
nxsem_init(&drv->sync, 0, 0);
nxsem_set_protocol(&drv->sync, SEM_PRIO_NONE);
ret = cxd56_iccregisterhandler(CXD56_PROTO_HOSTIF, hif_rxhandler, NULL);

1
arch/arm/src/cxd56xx/cxd56_icc.c
View file

@ -348,7 +348,6 @@ static struct iccdev_s *icc_devnew(void)
memset(priv, 0, sizeof(struct iccdev_s));
nxsem_init(&priv->rxwait, 0, 0);
nxsem_set_protocol(&priv->rxwait, SEM_PRIO_NONE);
/* Initialize receive queue and free list */

2
arch/arm/src/cxd56xx/cxd56_powermgr.c
View file

@ -837,14 +837,12 @@ int cxd56_pm_initialize(void)
}
ret = nxsem_init(&g_freqlockwait, 0, 0);
nxsem_set_protocol(&g_freqlockwait, SEM_PRIO_NONE);
if (ret < 0)
{
return ret;
}
ret = nxsem_init(&g_bootsync, 0, 0);
nxsem_set_protocol(&g_bootsync, SEM_PRIO_NONE);
if (ret < 0)
{
return ret;

3
arch/arm/src/cxd56xx/cxd56_scu.c
View file

@ -1990,7 +1990,6 @@ static int seq_fifoinit(struct seq_s *seq, int fifoid, uint16_t fsize)
/* Initialize DMA done wait semaphore */
nxsem_init(&fifo->dmawait, 0, 0);
nxsem_set_protocol(&fifo->dmawait, SEM_PRIO_NONE);
fifo->dmaresult = -1;
#endif
@ -3429,12 +3428,10 @@ void scu_initialize(void)
nxmutex_init(&priv->synclock);
nxsem_init(&priv->syncwait, 0, 0);
nxsem_set_protocol(&priv->syncwait, SEM_PRIO_NONE);
for (i = 0; i < 3; i++)
{
nxsem_init(&priv->oneshotwait[i], 0, 0);
nxsem_set_protocol(&priv->oneshotwait[i], SEM_PRIO_NONE);
}
scufifo_initialize();

6
arch/arm/src/cxd56xx/cxd56_sdhci.c
View file

@ -1319,12 +1319,6 @@ static void cxd56_sdio_sdhci_reset(struct sdio_dev_s *dev)
nxsem_init(&priv->waitsem, 0, 0);
/* The waitsem semaphore is used for signaling and, hence, should not have
* priority inheritance enabled.
*/
nxsem_set_protocol(&priv->waitsem, SEM_PRIO_NONE);
/* The next phase of the hardware reset would be to set the SYSCTRL INITA
* bit to send 80 clock ticks for card to power up and then reset the card
* with CMD0. This is done elsewhere.

1
arch/arm/src/cxd56xx/cxd56_sph.c
View file

@ -231,7 +231,6 @@ static inline int cxd56_sphdevinit(const char *devname, int num)
}
nxsem_init(&priv->wait, 0, 0);
nxsem_set_protocol(&priv->wait, SEM_PRIO_NONE);
priv->id = num;
irq_attach(CXD56_IRQ_SPH0 + num, cxd56_sphirqhandler, NULL);

2
arch/arm/src/cxd56xx/cxd56_spi.c
View file

@ -1332,7 +1332,6 @@ void cxd56_spi_dmaconfig(int port, int chtype, DMA_HANDLE handle,
if (!priv->dmaenable)
{
nxsem_init(&priv->dmasem, 0, 0);
nxsem_set_protocol(&priv->dmasem, SEM_PRIO_NONE);
priv->dmaenable = true;
}
}
@ -1346,7 +1345,6 @@ void cxd56_spi_dmaconfig(int port, int chtype, DMA_HANDLE handle,
if (!priv->dmaenable)
{
nxsem_init(&priv->dmasem, 0, 0);
nxsem_set_protocol(&priv->dmasem, SEM_PRIO_NONE);
priv->dmaenable = true;
}
}

1
arch/arm/src/cxd56xx/cxd56_sysctl.c
View file

@ -162,7 +162,6 @@ void cxd56_sysctlinitialize(void)
nxmutex_init(&g_lock);
nxsem_init(&g_sync, 0, 0);
nxsem_set_protocol(&g_sync, SEM_PRIO_NONE);
cxd56_iccregisterhandler(CXD56_PROTO_SYSCTL, sysctl_rxhandler, NULL);

6
arch/arm/src/efm32/efm32_spi.c
View file

@ -1607,12 +1607,6 @@ static int spi_portinitialize(struct efm32_spidev_s *priv)
nxsem_init(&priv->rxdmasem, 0, 0);
nxsem_init(&priv->txdmasem, 0, 0);
/* These semaphores are used for signaling and, hence, should not have
* priority inheritance enabled.
*/
nxsem_set_protocol(&priv->rxdmasem, SEM_PRIO_NONE);
nxsem_set_protocol(&priv->txdmasem, SEM_PRIO_NONE);
#endif
/* Enable SPI */

12
arch/arm/src/efm32/efm32_usbhost.c
View file

@ -5264,12 +5264,6 @@ static inline void efm32_sw_initialize(struct efm32_usbhost_s *priv)
nxsem_init(&priv->pscsem, 0, 0);
nxmutex_init(&priv->lock);
/* The pscsem semaphore is used for signaling and, hence, should not have
* priority inheritance enabled.
*/
nxsem_set_protocol(&priv->pscsem, SEM_PRIO_NONE);
/* Initialize the driver state data */
priv->smstate = SMSTATE_DETACHED;
@ -5287,13 +5281,7 @@ static inline void efm32_sw_initialize(struct efm32_usbhost_s *priv)
struct efm32_chan_s *chan = &priv->chan[i];
chan->chidx = i;
/* The waitsem semaphore is used for signaling and, hence, should not
* have priority inheritance enabled.
*/
nxsem_init(&chan->waitsem, 0, 0);
nxsem_set_protocol(&chan->waitsem, SEM_PRIO_NONE);
}
}

3
arch/arm/src/gd32f4/gd32f4xx_spi.c
View file

@ -2129,9 +2129,6 @@ static void spi_bus_initialize(struct gd32_spidev_s *priv)
nxsem_init(&priv->rxsem, 0, 0);
nxsem_init(&priv->txsem, 0, 0);
nxsem_set_protocol(&priv->rxsem, SEM_PRIO_NONE);
nxsem_set_protocol(&priv->txsem, SEM_PRIO_NONE);
/* Get DMA channels */
priv->rxdma = gd32_dma_channel_alloc(priv->rxch);

6
arch/arm/src/imx1/imx_spi.c
View file

@ -1109,13 +1109,7 @@ struct spi_dev_s *imx_spibus_initialize(int port)
/* Initialize the state structure */
#ifndef CONFIG_SPI_POLLWAIT
/* Initialize the semaphore that is used to wake up the waiting
* thread when the DMA transfer completes. This semaphore is used for
* signaling and, hence, should not have priority inheritance enabled.
*/
nxsem_init(&priv->waitsem, 0, 0);
nxsem_set_protocol(&priv->waitsem, SEM_PRIO_NONE);
#endif
nxmutex_init(&priv->lock);

6
arch/arm/src/imx6/imx_ecspi.c
View file

@ -1285,13 +1285,7 @@ struct spi_dev_s *imx_spibus_initialize(int port)
/* Initialize Semaphores */
#ifndef CONFIG_SPI_POLLWAIT
/* Initialize the semaphore that is used to wake up the waiting
* thread when the DMA transfer completes. This semaphore is used for
* signaling and, hence, should not have priority inheritance enabled.
*/
nxsem_init(&priv->waitsem, 0, 0);
nxsem_set_protocol(&priv->waitsem, SEM_PRIO_NONE);
#endif
nxmutex_init(&priv->lock);

6
arch/arm/src/imxrt/imxrt_edma.c
View file

@ -752,12 +752,6 @@ void weak_function arm_dma_initialize(void)
#if CONFIG_IMXRT_EDMA_NTCD > 0
nxsem_init(&g_edma.dsem, 0, CONFIG_IMXRT_EDMA_NTCD);
/* The 'dsem' is used for signaling rather than mutual exclusion and,
* hence, should not have priority inheritance enabled.
*/
nxsem_set_protocol(&g_edma.dsem, SEM_PRIO_NONE);
/* Initialize the list of free TCDs from the pool of pre-allocated TCDs. */
imxrt_tcd_initialize();

17
arch/arm/src/imxrt/imxrt_ehci.c
View file

@ -3968,12 +3968,7 @@ static int imxrt_epalloc(struct usbhost_driver_s *drvr,
epinfo->xfrtype = epdesc->xfrtype;
epinfo->speed = hport->speed;
/* The iocsem semaphore is used for signaling and, hence, should not have
* priority inheritance enabled.
*/
nxsem_init(&epinfo->iocsem, 0, 0);
nxsem_set_protocol(&epinfo->iocsem, SEM_PRIO_NONE);
/* Success.. return an opaque reference to the endpoint information
* structure instance
@ -5003,12 +4998,6 @@ struct usbhost_connection_s *imxrt_ehci_initialize(int controller)
nxmutex_init(&g_ehci.lock);
nxsem_init(&g_ehci.pscsem, 0, 0);
/* The pscsem semaphore is used for signaling and, hence, should not have
* priority inheritance enabled.
*/
nxsem_set_protocol(&g_ehci.pscsem, SEM_PRIO_NONE);
/* Initialize EP0 */
nxsem_init(&g_ehci.ep0.iocsem, 0, 1);
@ -5045,13 +5034,7 @@ struct usbhost_connection_s *imxrt_ehci_initialize(int controller)
rhport->ep0.xfrtype = USB_EP_ATTR_XFER_CONTROL;
rhport->ep0.speed = USB_SPEED_FULL;
rhport->ep0.maxpacket = 8;
/* The EP0 iocsem semaphore is used for signaling and, hence, should
* not have priority inheritance enabled.
*/
nxsem_init(&rhport->ep0.iocsem, 0, 0);
nxsem_set_protocol(&rhport->ep0.iocsem, SEM_PRIO_NONE);
/* Initialize the public port representation */

3
arch/arm/src/imxrt/imxrt_lpspi.c
View file

@ -2053,9 +2053,6 @@ struct spi_dev_s *imxrt_lpspibus_initialize(int bus)
nxsem_init(&priv->rxsem, 0, 0);
nxsem_init(&priv->txsem, 0, 0);
nxsem_set_protocol(&priv->rxsem, SEM_PRIO_NONE);
nxsem_set_protocol(&priv->txsem, SEM_PRIO_NONE);
priv->txdma = imxrt_dmach_alloc(priv->txch | DMAMUX_CHCFG_ENBL,
0);
priv->rxdma = imxrt_dmach_alloc(priv->rxch | DMAMUX_CHCFG_ENBL,

1
arch/arm/src/imxrt/imxrt_serial.c
View file

@ -1459,7 +1459,6 @@ static int imxrt_dma_setup(struct uart_dev_s *dev)
}
nxsem_init(&priv->txdmasem, 0, 1);
nxsem_set_protocol(&priv->txdmasem, SEM_PRIO_NONE);
}
/* Enable Tx DMA for the UART */

7
arch/arm/src/imxrt/imxrt_usdhc.c
View file

@ -3220,13 +3220,6 @@ struct sdio_dev_s *imxrt_usdhc_initialize(int slotno)
*/
nxsem_init(&priv->waitsem, 0, 0);
/* The waitsem semaphore is used for signaling and, hence, should not
* have priority inheritance enabled.
*/
nxsem_set_protocol(&priv->waitsem, SEM_PRIO_NONE);
switch (priv->addr)
{
case IMXRT_USDHC1_BASE:

6
arch/arm/src/kinetis/kinetis_edma.c
View file

@ -733,12 +733,6 @@ void weak_function arm_dma_initialize(void)
#if CONFIG_KINETIS_EDMA_NTCD > 0
nxsem_init(&g_edma.dsem, 0, CONFIG_KINETIS_EDMA_NTCD);
/* The 'dsem' is used for signaling rather than mutual exclusion and,
* hence, should not have priority inheritance enabled.
*/
nxsem_set_protocol(&g_edma.dsem, SEM_PRIO_NONE);
/* Initialize the list of free TCDs from the pool of pre-allocated TCDs. */
kinetis_tcd_initialize();

6
arch/arm/src/kinetis/kinetis_sdhc.c
View file

@ -2855,12 +2855,6 @@ struct sdio_dev_s *sdhc_initialize(int slotno)
nxsem_init(&priv->waitsem, 0, 0);
/* The waitsem semaphore is used for signaling and, hence, should not have
* priority inheritance enabled.
*/
nxsem_set_protocol(&priv->waitsem, SEM_PRIO_NONE);
/* In addition to the system clock, the SDHC module needs a clock for the
* base for the external card clock. There are four possible sources for
* this clock, selected by the SIM's SOPT2 register:

3
arch/arm/src/kinetis/kinetis_spi.c
View file

@ -1682,9 +1682,6 @@ struct spi_dev_s *kinetis_spibus_initialize(int port)
nxsem_init(&priv->rxsem, 0, 0);
nxsem_init(&priv->txsem, 0, 0);
nxsem_set_protocol(&priv->rxsem, SEM_PRIO_NONE);
nxsem_set_protocol(&priv->txsem, SEM_PRIO_NONE);
priv->txdma = kinetis_dmach_alloc(priv->txch | DMAMUX_CHCFG_ENBL,
0);
priv->rxdma = kinetis_dmach_alloc(priv->rxch | DMAMUX_CHCFG_ENBL,

13
arch/arm/src/kinetis/kinetis_usbhshost.c
View file

@ -4042,7 +4042,6 @@ static int kinetis_epalloc(struct usbhost_driver_s *drvr,
*/
nxsem_init(&epinfo->iocsem, 0, 0);
nxsem_set_protocol(&epinfo->iocsem, SEM_PRIO_NONE);
/* Success.. return an opaque reference to the endpoint information
* structure instance
@ -5073,12 +5072,6 @@ struct usbhost_connection_s *kinetis_ehci_initialize(int controller)
nxmutex_init(&g_ehci.lock);
nxsem_init(&g_ehci.pscsem, 0, 0);
/* The pscsem semaphore is used for signaling and, hence, should not have
* priority inheritance enabled.
*/
nxsem_set_protocol(&g_ehci.pscsem, SEM_PRIO_NONE);
/* Initialize EP0 */
nxsem_init(&g_ehci.ep0.iocsem, 0, 1);
@ -5115,13 +5108,7 @@ struct usbhost_connection_s *kinetis_ehci_initialize(int controller)
rhport->ep0.xfrtype = USB_EP_ATTR_XFER_CONTROL;
rhport->ep0.speed = USB_SPEED_FULL;
rhport->ep0.maxpacket = 8;
/* The EP0 iocsem semaphore is used for signaling and, hence, should
* not have priority inheritance enabled.
*/
nxsem_init(&rhport->ep0.iocsem, 0, 0);
nxsem_set_protocol(&rhport->ep0.iocsem, SEM_PRIO_NONE);
/* Initialize the public port representation */

6
arch/arm/src/lpc17xx_40xx/lpc17_40_i2c.c
View file

@ -622,12 +622,6 @@ struct i2c_master_s *lpc17_40_i2cbus_initialize(int port)
nxmutex_init(&priv->lock);
nxsem_init(&priv->wait, 0, 0);
/* The wait semaphore is used for signaling and, hence, should not have
* priority inheritance enabled.
*/
nxsem_set_protocol(&priv->wait, SEM_PRIO_NONE);
/* Attach Interrupt Handler */
irq_attach(priv->irqid, lpc17_40_i2c_interrupt, priv);

6
arch/arm/src/lpc17xx_40xx/lpc17_40_sdcard.c
View file

@ -2747,12 +2747,6 @@ struct sdio_dev_s *sdio_initialize(int slotno)
nxsem_init(&priv->waitsem, 0, 0);
/* The waitsem semaphore is used for signaling and, hence, should not have
* priority inheritance enabled.
*/
nxsem_set_protocol(&priv->waitsem, SEM_PRIO_NONE);
#ifdef CONFIG_LPC17_40_SDCARD_DMA
/* Configure the SDCARD DMA request */

18
arch/arm/src/lpc17xx_40xx/lpc17_40_usbhost.c
View file

@ -2297,14 +2297,7 @@ static int lpc17_40_epalloc(struct usbhost_driver_s *drvr,
#endif
uinfo("EP%d CTRL:%08" PRIx32 "\n", epdesc->addr, ed->hw.ctrl);
/* Initialize the semaphore that is used to wait for the endpoint
* WDH event. The wdhsem semaphore is used for signaling and, hence,
* should not have priority inheritance enabled.
*/
nxsem_init(&ed->wdhsem, 0, 0);
nxsem_set_protocol(&ed->wdhsem, SEM_PRIO_NONE);
/* Link the common tail TD to the ED's TD list */
@ -3748,12 +3741,6 @@ struct usbhost_connection_s *lpc17_40_usbhost_initialize(int controller)
nxsem_init(&priv->pscsem, 0, 0);
nxmutex_init(&priv->lock);
/* The pscsem semaphore is used for signaling and, hence, should not
* have priority inheritance enabled.
*/
nxsem_set_protocol(&priv->pscsem, SEM_PRIO_NONE);
#ifndef CONFIG_USBHOST_INT_DISABLE
priv->ininterval = MAX_PERINTERVAL;
priv->outinterval = MAX_PERINTERVAL;
@ -3845,12 +3832,7 @@ struct usbhost_connection_s *lpc17_40_usbhost_initialize(int controller)
memset((void *)TDTAIL, 0, sizeof(struct ohci_gtd_s));
memset((void *)EDCTRL, 0, sizeof(struct lpc17_40_ed_s));
/* The EDCTRL wdhsem semaphore is used for signaling and, hence, should
* not have priority inheritance enabled.
*/
nxsem_init(&EDCTRL->wdhsem, 0, 0);
nxsem_set_protocol(&EDCTRL->wdhsem, SEM_PRIO_NONE);
/* Initialize user-configurable EDs */

6
arch/arm/src/lpc2378/lpc23xx_i2c.c
View file

@ -585,12 +585,6 @@ struct i2c_master_s *lpc2378_i2cbus_initialize(int port)
nxmutex_init(&priv->lock);
nxsem_init(&priv->wait, 0, 0);
/* The wait semaphore is used for signaling and, hence, should not have
* priority inheritance enabled.
*/
nxsem_set_protocol(&priv->wait, SEM_PRIO_NONE);
/* Attach Interrupt Handler */
irq_attach(priv->irqid, lpc2378_i2c_interrupt, priv);

16
arch/arm/src/lpc31xx/lpc31_ehci.c
View file

@ -3987,12 +3987,7 @@ static int lpc31_epalloc(struct usbhost_driver_s *drvr,
epinfo->xfrtype = epdesc->xfrtype;
epinfo->speed = hport->speed;
/* The iocsem semaphore is used for signaling and, hence, should not have
* priority inheritance enabled.
*/
nxsem_init(&epinfo->iocsem, 0, 0);
nxsem_set_protocol(&epinfo->iocsem, SEM_PRIO_NONE);
/* Success.. return an opaque reference to the endpoint information
* structure instance
@ -5026,12 +5021,6 @@ struct usbhost_connection_s *lpc31_ehci_initialize(int controller)
nxmutex_init(&g_ehci.lock);
nxsem_init(&g_ehci.pscsem, 0, 0);
/* The pscsem semaphore is used for signaling and, hence, should not have
* priority inheritance enabled.
*/
nxsem_set_protocol(&g_ehci.pscsem, SEM_PRIO_NONE);
/* Initialize EP0 */
nxsem_init(&g_ehci.ep0.iocsem, 0, 1);
@ -5069,12 +5058,7 @@ struct usbhost_connection_s *lpc31_ehci_initialize(int controller)
rhport->ep0.speed = USB_SPEED_FULL;
rhport->ep0.maxpacket = 8;
/* The port iocsem semaphore is used for signaling and, hence,
* should not have priority inheritance enabled.
*/
nxsem_init(&rhport->ep0.iocsem, 0, 0);
nxsem_set_protocol(&rhport->iocsem, SEM_PRIO_NONE);
/* Initialize the public port representation */

6
arch/arm/src/lpc31xx/lpc31_i2c.c
View file

@ -561,12 +561,6 @@ struct i2c_master_s *lpc31_i2cbus_initialize(int port)
nxmutex_init(&priv->lock);
nxsem_init(&priv->wait, 0, 0);
/* The wait semaphore is used for signaling and, hence, should not have
* priority inheritance enabled.
*/
nxsem_set_protocol(&priv->wait, SEM_PRIO_NONE);
/* Enable I2C system clocks */
lpc31_enableclock(priv->clkid);

18
arch/arm/src/lpc43xx/lpc43_ehci.c
View file

@ -3824,13 +3824,7 @@ static int lpc43_epalloc(struct usbhost_driver_s *drvr,
epinfo->maxpacket = epdesc->mxpacketsize;
epinfo->xfrtype = epdesc->xfrtype;
epinfo->speed = hport->speed;
/* The endpoint iocsem semaphore is used for signaling and, hence,
* should not have priority inheritance enabled.
*/
nxsem_init(&epinfo->iocsem, 0, 0);
nxsem_set_protocol(&epinfo->iocsem, SEM_PRIO_NONE);
/* Success.. return an opaque reference to the endpoint information
* structure instance
@ -4851,12 +4845,6 @@ struct usbhost_connection_s *lpc43_ehci_initialize(int controller)
nxmutex_init(&g_ehci.lock);
nxsem_init(&g_ehci.pscsem, 0, 0);
/* The pscsem semaphore is used for signaling and, hence, should not have
* priority inheritance enabled.
*/
nxsem_set_protocol(&g_ehci.pscsem, SEM_PRIO_NONE);
/* Initialize EP0 */
nxsem_init(&g_ehci.ep0.iocsem, 0, 1);
@ -4893,13 +4881,7 @@ struct usbhost_connection_s *lpc43_ehci_initialize(int controller)
rhport->ep0.xfrtype = USB_EP_ATTR_XFER_CONTROL;
rhport->ep0.speed = USB_SPEED_FULL;
rhport->ep0.maxpacket = 8;
/* The EP0 iocsem semaphore is used for signaling and, hence, should
* not have priority inheritance enabled.
*/
nxsem_init(&rhport->ep0.iocsem, 0, 0);
nxsem_set_protocol(&rhport->ep0.iocsem, SEM_PRIO_NONE);
/* Initialize the public port representation */

6
arch/arm/src/lpc43xx/lpc43_i2c.c
View file

@ -533,12 +533,6 @@ struct i2c_master_s *lpc43_i2cbus_initialize(int port)
nxmutex_init(&priv->lock);
nxsem_init(&priv->wait, 0, 0);
/* The wait semaphore is used for signaling and, hence, should not have
* priority inheritance enabled.
*/
nxsem_set_protocol(&priv->wait, SEM_PRIO_NONE);
/* Attach Interrupt Handler */
irq_attach(priv->irqid, lpc43_i2c_interrupt, priv);

6
arch/arm/src/lpc43xx/lpc43_sdmmc.c
View file

@ -2828,12 +2828,6 @@ struct sdio_dev_s *lpc43_sdmmc_initialize(int slotno)
nxsem_init(&priv->waitsem, 0, 0);
/* The waitsem semaphore is used for signaling and, hence, should not have
* priority inheritance enabled.
*/
nxsem_set_protocol(&priv->waitsem, SEM_PRIO_NONE);
/* Configure GPIOs for 4-bit, wide-bus operation */
lpc43_pin_config(GPIO_SD_D0);

6
arch/arm/src/lpc54xx/lpc54_i2c_master.c
View file

@ -1212,12 +1212,6 @@ struct i2c_master_s *lpc54_i2cbus_initialize(int port)
nxmutex_init(&priv->lock);
#ifndef CONFIG_I2C_POLLED
nxsem_init(&priv->waitsem, 0, 0);
/* The waitsem semaphore is used for signaling and, hence, should not have
* priority inheritance enabled.
*/
nxsem_set_protocol(&priv->waitsem, SEM_PRIO_NONE);
#endif
#ifndef CONFIG_I2C_POLLED

6
arch/arm/src/lpc54xx/lpc54_sdmmc.c
View file

@ -2831,12 +2831,6 @@ struct sdio_dev_s *lpc54_sdmmc_initialize(int slotno)
nxsem_init(&priv->waitsem, 0, 0);
/* The waitsem semaphore is used for signaling and, hence, should not have
* priority inheritance enabled.
*/
nxsem_set_protocol(&priv->waitsem, SEM_PRIO_NONE);
/* Configure GPIOs for 4-bit, wide-bus operation */
lpc54_gpio_config(GPIO_SD_D0);

18
arch/arm/src/lpc54xx/lpc54_usb0_ohci.c
View file

@ -2390,14 +2390,7 @@ static int lpc54_epalloc(struct usbhost_driver_s *drvr,
#endif
uinfo("EP%d CTRL:%08x\n", epdesc->addr, ed->hw.ctrl);
/* Initialize the semaphore that is used to wait for the endpoint
* WDH event. The wdhsem semaphore is used for signaling and, hence,
* should not have priority inheritance enabled.
*/
nxsem_init(&ed->wdhsem, 0, 0);
nxsem_set_protocol(&ed->wdhsem, SEM_PRIO_NONE);
/* Link the common tail TD to the ED's TD list */
@ -3834,12 +3827,6 @@ struct usbhost_connection_s *lpc54_usbhost_initialize(int controller)
nxsem_init(&priv->pscsem, 0, 0);
nxmutex_init(&priv->lock);
/* The pscsem semaphore is used for signaling and, hence, should not have
* priority inheritance enabled.
*/
nxsem_set_protocol(&priv->pscsem, SEM_PRIO_NONE);
#ifndef CONFIG_OHCI_INT_DISABLE
priv->ininterval = MAX_PERINTERVAL;
priv->outinterval = MAX_PERINTERVAL;
@ -3923,12 +3910,7 @@ struct usbhost_connection_s *lpc54_usbhost_initialize(int controller)
memset((void *)TDTAIL, 0, sizeof(struct ohci_gtd_s));
memset((void *)EDCTRL, 0, sizeof(struct lpc54_ed_s));
/* The EDCTRL wdhsem semaphore is used for signaling and, hence, should
* not have priority inheritance enabled.
*/
nxsem_init(&EDCTRL->wdhsem, 0, 0);
nxsem_set_protocol(&EDCTRL->wdhsem, SEM_PRIO_NONE);
/* Initialize user-configurable EDs */

6
arch/arm/src/nrf52/nrf52_radio.c
View file

@ -1163,13 +1163,7 @@ nrf52_radio_initialize(int intf, struct nrf52_radio_board_s *board)
/* Initialize mutex */
nxmutex_init(&dev->lock);
/* This semaphore is used for signaling and, hence, should not have
* priority inheritance enabled.
*/
nxsem_init(&dev->sem_isr, 0, 0);
nxsem_set_protocol(&dev->sem_isr, SEM_PRIO_NONE);
/* Connect board-specific data */

2
arch/arm/src/nrf52/nrf52_rng.c
View file

@ -129,8 +129,6 @@ static int nrf52_rng_initialize(void)
memset(&g_rngdev, 0, sizeof(struct rng_dev_s));
nxsem_init(&g_rngdev.rd_sem, 0, 0);
nxsem_set_protocol(&g_rngdev.rd_sem, SEM_PRIO_NONE);
nxmutex_init(&g_rngdev.lock);
_info("Ready to stop\n");

5
arch/arm/src/nrf52/nrf52_spi.c
View file

@ -1475,12 +1475,7 @@ struct spi_dev_s *nrf52_spibus_initialize(int port)
nxmutex_init(&priv->lock);
#ifdef CONFIG_NRF52_SPI_MASTER_INTERRUPTS
/* This semaphore is used for signaling and, hence, should not have
* priority inheritance enabled.
*/
nxsem_init(&priv->sem_isr, 0, 0);
nxsem_set_protocol(&priv->sem_isr, SEM_PRIO_NONE);
/* Attach SPI interrupt */

1
arch/arm/src/rp2040/rp2040_spi.c
View file

@ -818,7 +818,6 @@ struct spi_dev_s *rp2040_spibus_initialize(int port)
#ifdef CONFIG_RP2040_SPI_DMA
nxsem_init(&priv->dmasem, 0, 0);
nxsem_set_protocol(&priv->dmasem, SEM_PRIO_NONE);
priv->txdmach = rp2040_dmachannel();
txconf.size = RP2040_DMA_SIZE_BYTE;

6
arch/arm/src/s32k1xx/s32k1xx_edma.c
View file

@ -718,12 +718,6 @@ void weak_function arm_dma_initialize(void)
#if CONFIG_S32K1XX_EDMA_NTCD > 0
nxsem_init(&g_edma.dsem, 0, CONFIG_S32K1XX_EDMA_NTCD);
/* The 'dsem' is used for signaling rather than mutual exclusion and,
* hence, should not have priority inheritance enabled.
*/
nxsem_set_protocol(&g_edma.dsem, SEM_PRIO_NONE);
/* Initialize the list of free TCDs from the pool of pre-allocated TCDs. */
s32k1xx_tcd_initialize();

6
arch/arm/src/s32k3xx/s32k3xx_edma.c
View file

@ -928,12 +928,6 @@ void weak_function arm_dma_initialize(void)
#if CONFIG_S32K3XX_EDMA_NTCD > 0
nxsem_init(&g_edma.dsem, 0, CONFIG_S32K3XX_EDMA_NTCD);
/* The 'dsem' is used for signaling rather than mutual exclusion and,
* hence, should not have priority inheritance enabled.
*/
nxsem_set_protocol(&g_edma.dsem, SEM_PRIO_NONE);
/* Initialize the list of free TCDs from the pool of pre-allocated TCDs. */
s32k3xx_tcd_initialize();

4
arch/arm/src/s32k3xx/s32k3xx_lpspi.c
View file

@ -2399,10 +2399,6 @@ struct spi_dev_s *s32k3xx_lpspibus_initialize(int bus)
{
nxsem_init(&priv->rxsem, 0, 0);
nxsem_init(&priv->txsem, 0, 0);
nxsem_set_protocol(&priv->rxsem, SEM_PRIO_NONE);
nxsem_set_protocol(&priv->txsem, SEM_PRIO_NONE);
priv->txdma = s32k3xx_dmach_alloc(priv->txch | DMAMUX_CHCFG_ENBL,
0);
priv->rxdma = s32k3xx_dmach_alloc(priv->rxch | DMAMUX_CHCFG_ENBL,

10
arch/arm/src/s32k3xx/s32k3xx_qspi.c
View file

@ -1802,13 +1802,7 @@ struct qspi_dev_s *s32k3xx_qspi_initialize(int intf)
spierr("ERROR: Failed to attach irq %d\n", priv->irq);
}
/* Initialize the semaphore that blocks until the operation completes.
* This semaphore is used for signaling and, hence, should not have
* priority inheritance enabled.
*/
nxsem_init(&priv->op_sem, 0, 0);
nxsem_set_protocol(&priv->op_sem, SEM_PRIO_NONE);
#endif
/* Perform hardware initialization. Puts the QSPI into an active
@ -1841,10 +1835,6 @@ struct qspi_dev_s *s32k3xx_qspi_initialize(int intf)
{
nxsem_init(&priv->rxsem, 0, 0);
nxsem_init(&priv->txsem, 0, 0);
nxsem_set_protocol(&priv->rxsem, SEM_PRIO_NONE);
nxsem_set_protocol(&priv->txsem, SEM_PRIO_NONE);
priv->txdma = s32k3xx_dmach_alloc(priv->txch
| DMAMUX_CHCFG_ENBL, 0);
priv->rxdma = s32k3xx_dmach_alloc(priv->rxch

7
arch/arm/src/sam34/sam_hsmci.c
View file

@ -2702,13 +2702,6 @@ struct sdio_dev_s *sdio_initialize(int slotno)
/* Initialize semaphores */
nxsem_init(&priv->waitsem, 0, 0);
/* The waitsem semaphore is used for signaling and, hence, should not have
* priority inheritance enabled.
*/
nxsem_set_protocol(&priv->waitsem, SEM_PRIO_NONE);
#ifdef CONFIG_SAM34_DMAC0
/* Allocate a DMA channel. A FIFO size of 8 is sufficient. */

6
arch/arm/src/sam34/sam_spi.c
View file

@ -1865,13 +1865,7 @@ struct spi_dev_s *sam_spibus_initialize(int port)
spi->initialized = true;
#ifdef CONFIG_SAM34_SPI_DMA
/* Initialize the SPI semaphore that is used to wake up the waiting
* thread when the DMA transfer completes. This semaphore is used for
* signaling and, hence, should not have priority inheritance enabled.
*/
nxsem_init(&spics->dmawait, 0, 0);
nxsem_set_protocol(&spics->dmawait, SEM_PRIO_NONE);
#endif
spi_dumpregs(spi, "After initialization");

6
arch/arm/src/sam34/sam_twi.c
View file

@ -955,12 +955,6 @@ struct i2c_master_s *sam_i2cbus_initialize(int bus)
nxmutex_init(&priv->lock);
nxsem_init(&priv->waitsem, 0, 0);
/* The waitsem semaphore is used for signaling and, hence, should not have
* priority inheritance enabled.
*/
nxsem_set_protocol(&priv->waitsem, SEM_PRIO_NONE);
/* Configure and enable the TWI hardware */
priv->pid = pid;

18
arch/arm/src/sama5/sam_ehci.c
View file

@ -3747,13 +3747,7 @@ static int sam_epalloc(struct usbhost_driver_s *drvr,
epinfo->maxpacket = epdesc->mxpacketsize;
epinfo->xfrtype = epdesc->xfrtype;
epinfo->speed = hport->speed;
/* The endpoint iocsem semaphore is used for signaling and, hence,
* should not have priority inheritance enabled.
*/
nxsem_init(&epinfo->iocsem, 0, 0);
nxsem_set_protocol(&epinfo->iocsem, SEM_PRIO_NONE);
/* Success.. return an opaque reference to the endpoint information
* structure instance
@ -4831,12 +4825,6 @@ struct usbhost_connection_s *sam_ehci_initialize(int controller)
nxmutex_init(&g_ehci.lock);
nxsem_init(&g_ehci.pscsem, 0, 0);
/* The pscsem semaphore is used for signaling and, hence, should not have
* priority inheritance enabled.
*/
nxsem_set_protocol(&g_ehci.pscsem, SEM_PRIO_NONE);
/* Initialize EP0 */
nxsem_init(&g_ehci.ep0.iocsem, 0, 1);
@ -4873,13 +4861,7 @@ struct usbhost_connection_s *sam_ehci_initialize(int controller)
rhport->ep0.xfrtype = USB_EP_ATTR_XFER_CONTROL;
rhport->ep0.speed = USB_SPEED_FULL;
rhport->ep0.maxpacket = 8;
/* The endpoint 0 iocsem semaphore is used for signaling and, hence,
* should not have priority inheritance enabled.
*/
nxsem_init(&rhport->ep0.iocsem, 0, 0);
nxsem_set_protocol(&rhport->ep0.iocsem, SEM_PRIO_NONE);
/* Initialize the public port representation */

6
arch/arm/src/sama5/sam_hsmci.c
View file

@ -3318,12 +3318,6 @@ struct sdio_dev_s *sdio_initialize(int slotno)
nxsem_init(&priv->waitsem, 0, 0);
/* The waitsem semaphore is used for signaling and, hence, should not have
* priority inheritance enabled.
*/
nxsem_set_protocol(&priv->waitsem, SEM_PRIO_NONE);
/* Initialize the callbacks */
memcpy(&priv->dev, &g_callbacks, sizeof(struct sdio_dev_s));

10
arch/arm/src/sama5/sam_nand.c
View file

@ -2981,12 +2981,7 @@ struct mtd_dev_s *sam_nand_initialize(int cs)
priv->cs = cs;
#ifdef CONFIG_SAMA5_NAND_DMA
/* The waitsem semaphore is used for signaling and, hence, should not have
* priority inheritance enabled.
*/
nxsem_init(&priv->waitsem, 0, 0);
nxsem_set_protocol(&priv->waitsem, SEM_PRIO_NONE);
#endif
/* Perform one-time, global NFC/PMECC initialization */
@ -3000,12 +2995,7 @@ struct mtd_dev_s *sam_nand_initialize(int cs)
#endif
#ifdef CONFIG_SAMA5_NAND_HSMCINTERRUPTS
/* The waitsem semaphore is used for signaling and, hence, should not
* have priority inheritance enabled.
*/
nxsem_init(&g_nand.waitsem, 0, 0);
nxsem_set_protocol(&g_nand.waitsem, SEM_PRIO_NONE);
#endif
/* Enable the NAND FLASH Controller (The NFC is always used) */

12
arch/arm/src/sama5/sam_ohci.c
View file

@ -2665,12 +2665,6 @@ static int sam_epalloc(struct usbhost_driver_s *drvr,
nxsem_init(&eplist->wdhsem, 0, 0);
/* The wdhsem semaphore is used for signaling and, hence, should not have
* priority inheritance enabled.
*/
nxsem_set_protocol(&eplist->wdhsem, SEM_PRIO_NONE);
/* We must have exclusive access to the ED pool, the bulk list, the
* periodic list, and the interrupt table.
*/
@ -3965,12 +3959,6 @@ struct usbhost_connection_s *sam_ohci_initialize(int controller)
nxsem_init(&g_ohci.pscsem, 0, 0);
nxmutex_init(&g_ohci.lock);
/* The pscsem semaphore is used for signaling and, hence, should not have
* priority inheritance enabled.
*/
nxsem_set_protocol(&g_ohci.pscsem, SEM_PRIO_NONE);
#ifndef CONFIG_USBHOST_INT_DISABLE
g_ohci.ininterval = MAX_PERINTERVAL;
g_ohci.outinterval = MAX_PERINTERVAL;

6
arch/arm/src/sama5/sam_sdmmc.c
View file

@ -3594,12 +3594,6 @@ struct sdio_dev_s *sam_sdmmc_sdio_initialize(int slotno)
nxsem_init(&priv->waitsem, 0, 0);
/* The waitsem semaphore is used for signaling and, hence, should not
* have priority inheritance enabled.
*/
nxsem_set_protocol(&priv->waitsem, SEM_PRIO_NONE);
switch (priv->addr)
{
case SAM_SDMMC0_VBASE:

6
arch/arm/src/sama5/sam_spi.c
View file

@ -1791,13 +1791,7 @@ struct spi_dev_s *sam_spibus_initialize(int port)
spi->initialized = true;
#ifdef CONFIG_SAMA5_SPI_DMA
/* Initialize the SPI semaphore that is used to wake up the waiting
* thread when the DMA transfer completes. This semaphore is used for
* signaling and, hence, should not have priority inheritance enabled.
*/
nxsem_init(&spics->dmawait, 0, 0);
nxsem_set_protocol(&spics->dmawait, SEM_PRIO_NONE);
#endif
spi_dumpregs(spi, "After initialization");

6
arch/arm/src/sama5/sam_trng.c
View file

@ -342,12 +342,6 @@ static int sam_rng_initialize(void)
nxmutex_init(&g_trngdev.lock);
nxsem_init(&g_trngdev.waitsem, 0, 0);
/* The waitsem semaphore is used for signaling and, hence, should not have
* priority inheritance enabled.
*/
nxsem_set_protocol(&g_trngdev.waitsem, SEM_PRIO_NONE);
/* Enable clocking to the TRNG */
sam_trng_enableclk();

6
arch/arm/src/sama5/sam_tsd.c
View file

@ -1654,13 +1654,7 @@ int sam_tsd_register(struct sam_adc_s *adc, int minor)
priv->adc = adc; /* Save the ADC device handle */
priv->threshx = INVALID_THRESHOLD; /* Initialize thresholding logic */
priv->threshy = INVALID_THRESHOLD; /* Initialize thresholding logic */
/* Initialize pen event wait semaphore. This semaphore is used for
* signaling and, hence, should not have priority inheritance enabled.
*/
nxsem_init(&priv->waitsem, 0, 0);
nxsem_set_protocol(&priv->waitsem, SEM_PRIO_NONE);
/* Register the device as an input device */

6
arch/arm/src/sama5/sam_twi.c
View file

@ -1257,12 +1257,6 @@ struct i2c_master_s *sam_i2cbus_initialize(int bus)
nxmutex_init(&priv->lock);
nxsem_init(&priv->waitsem, 0, 0);
/* The waitsem semaphore is used for signaling and, hence, should not have
* priority inheritance enabled.
*/
nxsem_set_protocol(&priv->waitsem, SEM_PRIO_NONE);
/* Perform repeatable TWI hardware initialization */
twi_hw_initialize(priv, frequency);

6
arch/arm/src/sama5/sam_xdmac.c
View file

@ -1984,12 +1984,6 @@ void sam_dmainitialize(struct sam_xdmac_s *xdmac)
nxmutex_init(&xdmac->chlock);
nxsem_init(&xdmac->dsem, 0, SAM_NDMACHAN);
/* The 'dsem' is used for signaling rather than mutual exclusion and,
* hence, should not have priority inheritance enabled.
*/
nxsem_set_protocol(&xdmac->dsem, SEM_PRIO_NONE);
}
/****************************************************************************

1
arch/arm/src/samd2l2/sam_spi.c
View file

@ -1434,7 +1434,6 @@ static void spi_dma_setup(struct sam_spidev_s *priv)
/* Initialize the semaphore used to notify when DMA is complete */
nxsem_init(&priv->dmasem, 0, 0);
nxsem_set_protocol(&priv->dmasem, SEM_PRIO_NONE);
}
#endif

1
arch/arm/src/samd5e5/sam_spi.c
View file

@ -1523,7 +1523,6 @@ static void spi_dma_setup(struct sam_spidev_s *priv)
/* Initialize the semaphore used to notify when DMA is complete */
nxsem_init(&priv->dmasem, 0, 0);
nxsem_set_protocol(&priv->dmasem, SEM_PRIO_NONE);
}
#endif

6
arch/arm/src/samv7/sam_hsmci.c
View file

@ -3315,12 +3315,6 @@ struct sdio_dev_s *sdio_initialize(int slotno)
nxsem_init(&priv->waitsem, 0, 0);
/* The waitsem semaphore is used for signaling and, hence, should not have
* priority inheritance enabled.
*/
nxsem_set_protocol(&priv->waitsem, SEM_PRIO_NONE);
/* Initialize the callbacks */
memcpy(&priv->dev, &g_callbacks, sizeof(struct sdio_dev_s));

6
arch/arm/src/samv7/sam_qspi.c
View file

@ -1775,13 +1775,7 @@ struct qspi_dev_s *sam_qspi_initialize(int intf)
}
}
/* Initialize the QSPI semaphore that is used to wake up the waiting
* thread when the DMA transfer completes. This semaphore is used for
* signaling and, hence, should not have priority inheritance enabled.
*/
nxsem_init(&priv->dmawait, 0, 0);
nxsem_set_protocol(&priv->dmawait, SEM_PRIO_NONE);
#endif
#ifdef QSPI_USE_INTERRUPTS

6
arch/arm/src/samv7/sam_spi.c
View file

@ -2165,13 +2165,7 @@ struct spi_dev_s *sam_spibus_initialize(int port)
spi->initialized = true;
#ifdef CONFIG_SAMV7_SPI_DMA
/* Initialize the SPI semaphore that is used to wake up the waiting
* thread when the DMA transfer completes. This semaphore is used for
* signaling and, hence, should not have priority inheritance enabled.
*/
nxsem_init(&spics->dmawait, 0, 0);
nxsem_set_protocol(&spics->dmawait, SEM_PRIO_NONE);
#endif
spi_dumpregs(spi, "After initialization");

6
arch/arm/src/samv7/sam_trng.c
View file

@ -344,12 +344,6 @@ static int sam_rng_initialize(void)
nxmutex_init(&g_trngdev.lock);
nxsem_init(&g_trngdev.waitsem, 0, 0);
/* The waitsem semaphore is used for signaling and, hence, should not have
* priority inheritance enabled.
*/
nxsem_set_protocol(&g_trngdev.waitsem, SEM_PRIO_NONE);
/* Enable clocking to the TRNG */
sam_trng_enableclk();

6
arch/arm/src/samv7/sam_xdmac.c
View file

@ -1566,12 +1566,6 @@ void sam_dmainitialize(struct sam_xdmac_s *xdmac)
nxmutex_init(&xdmac->chlock);
nxsem_init(&xdmac->dsem, 0, SAMV7_NDMACHAN);
/* The 'dsem' is used for signaling rather than mutual exclusion and,
* hence, should not have priority inheritance enabled.
*/
nxsem_set_protocol(&xdmac->dsem, SEM_PRIO_NONE);
}
/****************************************************************************

7
arch/arm/src/stm32/stm32_dma2d.c
View file

@ -1100,14 +1100,7 @@ int stm32_dma2dinitialize(void)
*/
nxmutex_init(&g_lock);
/* Initialize the semaphore for interrupt handling. This waitsem
* semaphore is used for signaling and, hence, should not have
* priority inheritance enabled.
*/
nxsem_init(g_interrupt.sem, 0, 0);
nxsem_set_protocol(g_interrupt.sem, SEM_PRIO_NONE);
#ifdef CONFIG_STM32_FB_CMAP
/* Enable dma2d transfer and clut loading interrupts only */

1
arch/arm/src/stm32/stm32_foc.c
View file

@ -2364,7 +2364,6 @@ stm32_foc_initialize(int inst, struct stm32_foc_board_s *board)
/* Initialize calibration semaphore */
nxsem_init(&foc_priv->cal_done_sem, 0, 0);
nxsem_set_protocol(&foc_priv->cal_done_sem, SEM_PRIO_NONE);
/* Get FOC device */

3
arch/arm/src/stm32/stm32_hciuart.c
View file

@ -2589,10 +2589,7 @@ void hciuart_initialize(void)
/* Initialize signalling semaphores */
nxsem_init(&state->rxwait, 0, 0);
nxsem_set_protocol(&state->rxwait, SEM_PRIO_NONE);
nxsem_init(&state->txwait, 0, 0);
nxsem_set_protocol(&state->txwait, SEM_PRIO_NONE);
/* Attach and enable the HCI UART IRQ */

7
arch/arm/src/stm32/stm32_ltdc.c
View file

@ -1611,14 +1611,7 @@ static void stm32_ltdc_irqconfig(void)
/* Initialize the LTDC mutex that enforces mutually exclusive access */
nxmutex_init(&g_lock);
/* Initialize the semaphore for interrupt handling. This waitsem
* semaphore is used for signaling and, hence, should not have priority
* inheritance enabled.
*/
nxsem_init(g_interrupt.sem, 0, 0);
nxsem_set_protocol(g_interrupt.sem, SEM_PRIO_NONE);
/* Attach LTDC interrupt vector */

12
arch/arm/src/stm32/stm32_otgfshost.c
View file

@ -5255,12 +5255,6 @@ static inline void stm32_sw_initialize(struct stm32_usbhost_s *priv)
nxsem_init(&priv->pscsem, 0, 0);
nxmutex_init(&priv->lock);
/* The pscsem semaphore is used for signaling and, hence, should not have
* priority inheritance enabled.
*/
nxsem_set_protocol(&priv->pscsem, SEM_PRIO_NONE);
/* Initialize the driver state data */
priv->smstate = SMSTATE_DETACHED;
@ -5278,13 +5272,7 @@ static inline void stm32_sw_initialize(struct stm32_usbhost_s *priv)
struct stm32_chan_s *chan = &priv->chan[i];
chan->chidx = i;
/* The waitsem semaphore is used for signaling and, hence, should not
* have priority inheritance enabled.
*/
nxsem_init(&chan->waitsem, 0, 0);
nxsem_set_protocol(&chan->waitsem, SEM_PRIO_NONE);
}
}

12
arch/arm/src/stm32/stm32_otghshost.c
View file

@ -5254,12 +5254,6 @@ static inline void stm32_sw_initialize(struct stm32_usbhost_s *priv)
nxsem_init(&priv->pscsem, 0, 0);
nxmutex_init(&priv->lock);
/* The pscsem semaphore is used for signaling and, hence, should not have
* priority inheritance enabled.
*/
nxsem_set_protocol(&priv->pscsem, SEM_PRIO_NONE);
/* Initialize the driver state data */
priv->smstate = SMSTATE_DETACHED;
@ -5277,13 +5271,7 @@ static inline void stm32_sw_initialize(struct stm32_usbhost_s *priv)
struct stm32_chan_s *chan = &priv->chan[i];
chan->chidx = i;
/* The waitsem semaphore is used for signaling and, hence, should not
* have priority inheritance enabled.
*/
nxsem_init(&chan->waitsem, 0, 0);
nxsem_set_protocol(&chan->waitsem, SEM_PRIO_NONE);
}
}

7
arch/arm/src/stm32/stm32_rng.c
View file

@ -241,14 +241,7 @@ static ssize_t stm32_rng_read(struct file *filep, char *buffer,
/* We've got the mutex. */
/* Initialize the operation semaphore with 0 for blocking until the
* buffer is filled from interrupts. The readsem semaphore is used
* for signaling and, hence, should not have priority inheritance
* enabled.
*/
nxsem_init(&g_rngdev.rd_readsem, 0, 0);
nxsem_set_protocol(&g_rngdev.rd_readsem, SEM_PRIO_NONE);
g_rngdev.rd_buflen = buflen;
g_rngdev.rd_buf = buffer;

6
arch/arm/src/stm32/stm32_sdio.c
View file

@ -3047,12 +3047,6 @@ struct sdio_dev_s *sdio_initialize(int slotno)
nxsem_init(&priv->waitsem, 0, 0);
/* The waitsem semaphore is used for signaling and, hence, should not have
* priority inheritance enabled.
*/
nxsem_set_protocol(&priv->waitsem, SEM_PRIO_NONE);
/* Allocate a DMA channel */
#ifdef CONFIG_STM32_SDIO_DMA

8
arch/arm/src/stm32/stm32_spi.c
View file

@ -2093,19 +2093,11 @@ static void spi_bus_initialize(struct stm32_spidev_s *priv)
nxmutex_init(&priv->lock);
#ifdef CONFIG_STM32_SPI_DMA
/* Initialize the SPI semaphores that is used to wait for DMA completion.
* This semaphore is used for signaling and, hence, should not have
* priority inheritance enabled.
*/
if (priv->rxch && priv->txch)
{
nxsem_init(&priv->rxsem, 0, 0);
nxsem_init(&priv->txsem, 0, 0);
nxsem_set_protocol(&priv->rxsem, SEM_PRIO_NONE);
nxsem_set_protocol(&priv->txsem, SEM_PRIO_NONE);
/* Get DMA channels. NOTE: stm32_dmachannel() will always assign the
* DMA channel. If the channel is not available, then
* stm32_dmachannel() will block and wait until the channel becomes

7
arch/arm/src/stm32f0l0g0/stm32_rng.c
View file

@ -240,14 +240,7 @@ static ssize_t stm32_rng_read(struct file *filep,
/* We've got the semaphore. */
/* Initialize the operation semaphore with 0 for blocking until the
* buffer is filled from interrupts. The readsem semaphore is used
* for signaling and, hence, should not have priority inheritance
* enabled.
*/
nxsem_init(&g_rngdev.rd_readsem, 0, 0);
nxsem_set_protocol(&g_rngdev.rd_readsem, SEM_PRIO_NONE);
g_rngdev.rd_buflen = buflen;
g_rngdev.rd_buf = buffer;

7
arch/arm/src/stm32f0l0g0/stm32_spi.c
View file

@ -1960,13 +1960,6 @@ static void spi_bus_initialize(struct stm32_spidev_s *priv)
nxsem_init(&priv->rxsem, 0, 0);
nxsem_init(&priv->txsem, 0, 0);
/* These semaphores are used for signaling and, hence, should not have
* priority inheritance enabled.
*/
nxsem_set_protocol(&priv->rxsem, SEM_PRIO_NONE);
nxsem_set_protocol(&priv->txsem, SEM_PRIO_NONE);
/* Get DMA channels. NOTE: stm32_dmachannel() will always assign the
* DMA channel. If the channel is not available, then
* stm32_dmachannel() will block and wait until the channel becomes

7
arch/arm/src/stm32f7/stm32_dma2d.c
View file

@ -1097,14 +1097,7 @@ int stm32_dma2dinitialize(void)
*/
nxmutex_init(&g_lock);
/* Initialize the semaphore for interrupt handling. This waitsem
* semaphore is used for signaling and, hence, should not have
* priority inheritance enabled.
*/
nxsem_init(g_interrupt.sem, 0, 0);
nxsem_set_protocol(g_interrupt.sem, SEM_PRIO_NONE);
#ifdef CONFIG_STM32F7_FB_CMAP
/* Enable dma2d transfer and clut loading interrupts only */

1
arch/arm/src/stm32f7/stm32_foc.c
View file

@ -2093,7 +2093,6 @@ stm32_foc_initialize(int inst, struct stm32_foc_board_s *board)
/* Initialize calibration semaphore */
nxsem_init(&foc_priv->cal_done_sem, 0, 0);
nxsem_set_protocol(&foc_priv->cal_done_sem, SEM_PRIO_NONE);
/* Get FOC device */

7
arch/arm/src/stm32f7/stm32_ltdc.c
View file

@ -1614,14 +1614,7 @@ static void stm32_ltdc_irqconfig(void)
/* Initialize the LTDC mutex that enforces mutually exclusive access */
nxmutex_init(&g_lock);
/* Initialize the semaphore for interrupt handling. This waitsem
* semaphore is used for signaling and, hence, should not have priority
* inheritance enabled.
*/
nxsem_init(g_interrupt.sem, 0, 0);
nxsem_set_protocol(g_interrupt.sem, SEM_PRIO_NONE);
/* Attach LTDC interrupt vector */

12
arch/arm/src/stm32f7/stm32_otghost.c
View file

@ -5227,12 +5227,6 @@ static inline void stm32_sw_initialize(struct stm32_usbhost_s *priv)
nxsem_init(&priv->pscsem, 0, 0);
nxmutex_init(&priv->lock);
/* The pscsem semaphore is used for signaling and, hence, should not have
* priority inheritance enabled.
*/
nxsem_set_protocol(&priv->pscsem, SEM_PRIO_NONE);
/* Initialize the driver state data */
priv->smstate = SMSTATE_DETACHED;
@ -5250,13 +5244,7 @@ static inline void stm32_sw_initialize(struct stm32_usbhost_s *priv)
struct stm32_chan_s *chan = &priv->chan[i];
chan->chidx = i;
/* The waitsem semaphore is used for signaling and, hence, should not
* have priority inheritance enabled.
*/
nxsem_init(&chan->waitsem, 0, 0);
nxsem_set_protocol(&chan->waitsem, SEM_PRIO_NONE);
}
}

12
arch/arm/src/stm32f7/stm32_qspi.c
View file

@ -2577,13 +2577,7 @@ struct qspi_dev_s *stm32f7_qspi_initialize(int intf)
}
}
/* Initialize the QSPI semaphore that is used to wake up the waiting
* thread when the DMA transfer completes. This semaphore is used for
* signaling and, hence, should not have priority inheritance enabled.
*/
nxsem_init(&priv->dmawait, 0, 0);
nxsem_set_protocol(&priv->dmawait, SEM_PRIO_NONE);
#endif
#ifdef CONFIG_STM32F7_QSPI_INTERRUPTS
@ -2596,13 +2590,7 @@ struct qspi_dev_s *stm32f7_qspi_initialize(int intf)
goto errout_with_dmawait;
}
/* Initialize the semaphore that blocks until the operation completes.
* This semaphore is used for signaling and, hence, should not have
* priority inheritance enabled.
*/
nxsem_init(&priv->op_sem, 0, 0);
nxsem_set_protocol(&priv->op_sem, SEM_PRIO_NONE);
#endif
/* Perform hardware initialization. Puts the QSPI into an active

7
arch/arm/src/stm32f7/stm32_rng.c
View file

@ -259,14 +259,7 @@ static ssize_t stm32_rngread(struct file *filep, char *buffer, size_t buflen)
/* We've got the device semaphore, proceed with reading */
/* Initialize the operation semaphore with 0 for blocking until the
* buffer is filled from interrupts. The readsem semaphore is used
* for signaling and, hence, should not have priority inheritance
* enabled.
*/
nxsem_init(&g_rngdev.rd_readsem, 0, 0);
nxsem_set_protocol(&g_rngdev.rd_readsem, SEM_PRIO_NONE);
g_rngdev.rd_buflen = buflen;
g_rngdev.rd_buf = buffer;

6
arch/arm/src/stm32f7/stm32_sdmmc.c
View file

@ -3415,12 +3415,6 @@ struct sdio_dev_s *sdio_initialize(int slotno)
nxsem_init(&priv->waitsem, 0, 0);
/* The waitsem semaphore is used for signaling and, hence, should not have
* priority inheritance enabled.
*/
nxsem_set_protocol(&priv->waitsem, SEM_PRIO_NONE);
#ifdef CONFIG_STM32F7_SDMMC_DMA
/* Allocate a DMA channel */

8
arch/arm/src/stm32f7/stm32_spi.c
View file

@ -2158,19 +2158,11 @@ static void spi_bus_initialize(struct stm32_spidev_s *priv)
nxmutex_init(&priv->lock);
#ifdef CONFIG_STM32F7_SPI_DMA
/* Initialize the SPI semaphores that is used to wait for DMA completion.
* This semaphore is used for signaling and, hence, should not have
* priority inheritance enabled.
*/
if (priv->rxch && priv->txch)
{
nxsem_init(&priv->rxsem, 0, 0);
nxsem_init(&priv->txsem, 0, 0);
nxsem_set_protocol(&priv->rxsem, SEM_PRIO_NONE);
nxsem_set_protocol(&priv->txsem, SEM_PRIO_NONE);
/* Get DMA channels. NOTE: stm32_dmachannel() will always assign the
* DMA channel. If the channel is not available, then
* stm32_dmachannel() will block and wait until the channel becomes

12
arch/arm/src/stm32h7/stm32_otghost.c
View file

@ -5231,12 +5231,6 @@ static inline void stm32_sw_initialize(struct stm32_usbhost_s *priv)
nxsem_init(&priv->pscsem, 0, 0);
nxmutex_init(&priv->lock);
/* The pscsem semaphore is used for signaling and, hence, should not have
* priority inheritance enabled.
*/
nxsem_set_protocol(&priv->pscsem, SEM_PRIO_NONE);
/* Initialize the driver state data */
priv->smstate = SMSTATE_DETACHED;
@ -5254,13 +5248,7 @@ static inline void stm32_sw_initialize(struct stm32_usbhost_s *priv)
struct stm32_chan_s *chan = &priv->chan[i];
chan->chidx = i;
/* The waitsem semaphore is used for signaling and, hence, should not
* have priority inheritance enabled.
*/
nxsem_init(&chan->waitsem, 0, 0);
nxsem_set_protocol(&chan->waitsem, SEM_PRIO_NONE);
}
}

12
arch/arm/src/stm32h7/stm32_qspi.c
View file

@ -2635,13 +2635,7 @@ struct qspi_dev_s *stm32h7_qspi_initialize(int intf)
}
}
/* Initialize the QSPI semaphore that is used to wake up the waiting
* thread when the DMA transfer completes. This semaphore is used for
* signaling and, hence, should not have priority inheritance enabled.
*/
nxsem_init(&priv->dmawait, 0, 0);
nxsem_set_protocol(&priv->dmawait, SEM_PRIO_NONE);
#endif
#ifdef CONFIG_STM32H7_QSPI_INTERRUPTS
@ -2654,13 +2648,7 @@ struct qspi_dev_s *stm32h7_qspi_initialize(int intf)
goto errout_with_dmawait;
}
/* Initialize the semaphore that blocks until the operation completes.
* This semaphore is used for signaling and, hence, should not have
* priority inheritance enabled.
*/
nxsem_init(&priv->op_sem, 0, 0);
nxsem_set_protocol(&priv->op_sem, SEM_PRIO_NONE);
#endif
/* Perform hardware initialization. Puts the QSPI into an active

6
arch/arm/src/stm32h7/stm32_sdmmc.c
View file

@ -3513,12 +3513,6 @@ struct sdio_dev_s *sdio_initialize(int slotno)
nxsem_init(&priv->waitsem, 0, 0);
/* The waitsem semaphore is used for signaling and, hence, should not have
* priority inheritance enabled.
*/
nxsem_set_protocol(&priv->waitsem, SEM_PRIO_NONE);
/* Reset the card and assure that it is in the initial, unconfigured
* state.
*/

1
arch/arm/src/stm32h7/stm32_serial.c
View file

@ -2225,7 +2225,6 @@ static int up_dma_setup(struct uart_dev_s *dev)
priv->txdma = stm32_dmachannel(priv->txdma_channel);
nxsem_init(&priv->txdmasem, 0, 1);
nxsem_set_protocol(&priv->txdmasem, SEM_PRIO_NONE);
/* Enable receive Tx DMA for the UART */

8
arch/arm/src/stm32h7/stm32_spi.c
View file

@ -2502,17 +2502,9 @@ static void spi_bus_initialize(struct stm32_spidev_s *priv)
nxmutex_init(&priv->lock);
#ifdef CONFIG_STM32H7_SPI_DMA
/* Initialize the SPI semaphores that is used to wait for DMA completion.
* This semaphore is used for signaling and, hence, should not have
* priority inheritance enabled.
*/
nxsem_init(&priv->rxsem, 0, 0);
nxsem_init(&priv->txsem, 0, 0);
nxsem_set_protocol(&priv->rxsem, SEM_PRIO_NONE);
nxsem_set_protocol(&priv->txsem, SEM_PRIO_NONE);
/* Get DMA channels. NOTE: stm32_dmachannel() will always assign the DMA
* channel. If the channel is not available, then stm32_dmachannel() will
* block and wait until the channel becomes available. WARNING: If you

12
arch/arm/src/stm32l4/stm32l4_otgfshost.c
View file

@ -5268,12 +5268,6 @@ static inline void stm32l4_sw_initialize(struct stm32l4_usbhost_s *priv)
nxsem_init(&priv->pscsem, 0, 0);
nxmutex_init(&priv->lock);
/* The pscsem semaphore is used for signaling and, hence, should not have
* priority inheritance enabled.
*/
nxsem_set_protocol(&priv->pscsem, SEM_PRIO_NONE);
/* Initialize the driver state data */
priv->smstate = SMSTATE_DETACHED;
@ -5292,13 +5286,7 @@ static inline void stm32l4_sw_initialize(struct stm32l4_usbhost_s *priv)
struct stm32l4_chan_s *chan = &priv->chan[i];
chan->chidx = i;
/* The waitsem semaphore is used for signaling and, hence, should not
* have priority inheritance enabled.
*/
nxsem_init(&chan->waitsem, 0, 0);
nxsem_set_protocol(&chan->waitsem, SEM_PRIO_NONE);
}
}

12
arch/arm/src/stm32l4/stm32l4_qspi.c
View file

@ -2518,13 +2518,7 @@ struct qspi_dev_s *stm32l4_qspi_initialize(int intf)
}
}
/* Initialize the QSPI semaphore that is used to wake up the waiting
* thread when the DMA transfer completes. This semaphore is used for
* signaling and, hence, should not have priority inheritance enabled.
*/
nxsem_init(&priv->dmawait, 0, 0);
nxsem_set_protocol(&priv->dmawait, SEM_PRIO_NONE);
#endif
#ifdef STM32L4_QSPI_INTERRUPTS
@ -2537,13 +2531,7 @@ struct qspi_dev_s *stm32l4_qspi_initialize(int intf)
goto errout_with_dmawait;
}
/* Initialize the semaphore that blocks until the operation completes.
* This semaphore is used for signaling and, hence, should not have
* priority inheritance enabled.
*/
nxsem_init(&priv->op_sem, 0, 0);
nxsem_set_protocol(&priv->op_sem, SEM_PRIO_NONE);
#endif
/* Perform hardware initialization. Puts the QSPI into an active

7
arch/arm/src/stm32l4/stm32l4_rng.c
View file

@ -245,14 +245,7 @@ static ssize_t stm32l4_rngread(struct file *filep,
/* We've got the device semaphore, proceed with reading */
/* Initialize the operation semaphore with 0 for blocking until the
* buffer is filled from interrupts. The readsem semaphore is used
* for signaling and, hence, should not have priority inheritance
* enabled.
*/
nxsem_init(&g_rngdev.rd_readsem, 0, 0);
nxsem_set_protocol(&g_rngdev.rd_readsem, SEM_PRIO_NONE);
g_rngdev.rd_buflen = buflen;
g_rngdev.rd_buf = buffer;

6
arch/arm/src/stm32l4/stm32l4_sdmmc.c
View file

@ -3123,12 +3123,6 @@ struct sdio_dev_s *sdio_initialize(int slotno)
nxsem_init(&priv->waitsem, 0, 0);
/* The waitsem semaphore is used for signaling and, hence, should not have
* priority inheritance enabled.
*/
nxsem_set_protocol(&priv->waitsem, SEM_PRIO_NONE);
#ifdef CONFIG_STM32L4_SDMMC_DMA
/* Allocate a DMA channel */

7
arch/arm/src/stm32l4/stm32l4_spi.c
View file

@ -1755,13 +1755,6 @@ static void spi_bus_initialize(struct stm32l4_spidev_s *priv)
nxsem_init(&priv->rxsem, 0, 0);
nxsem_init(&priv->txsem, 0, 0);
/* These semaphores are used for signaling and, hence, should not have
* priority inheritance enabled.
*/
nxsem_set_protocol(&priv->rxsem, SEM_PRIO_NONE);
nxsem_set_protocol(&priv->txsem, SEM_PRIO_NONE);
/* Get DMA channels. NOTE: stm32l4_dmachannel() will always assign the DMA
* channel. If the channel is not available, then stm32l4_dmachannel()
* will block and wait until the channel becomes available. WARNING: If

8
arch/arm/src/stm32u5/stm32_spi.c
View file

@ -2244,17 +2244,9 @@ static void spi_bus_initialize(struct stm32_spidev_s *priv)
nxmutex_init(&priv->lock);
#ifdef CONFIG_STM32U5_SPI_DMA
/* Initialize the SPI semaphores that is used to wait for DMA completion.
* This semaphore is used for signaling and, hence, should not have
* priority inheritance enabled.
*/
nxsem_init(&priv->rxsem, 0, 0);
nxsem_init(&priv->txsem, 0, 0);
nxsem_set_protocol(&priv->rxsem, SEM_PRIO_NONE);
nxsem_set_protocol(&priv->txsem, SEM_PRIO_NONE);
/* Get DMA channels. NOTE: stm32_dmachannel() will always assign the DMA
* channel. If the channel is not available, then stm32_dmachannel() will
* block and wait until the channel becomes available. WARNING: If you

7
arch/arm/src/stm32wb/stm32wb_spi.c
View file

@ -1690,13 +1690,6 @@ static void spi_bus_initialize(struct stm32wb_spidev_s *priv)
nxsem_init(&priv->rxsem, 0, 0);
nxsem_init(&priv->txsem, 0, 0);
/* These semaphores are used for signaling and, hence, should not have
* priority inheritance enabled.
*/
nxsem_set_protocol(&priv->rxsem, SEM_PRIO_NONE);
nxsem_set_protocol(&priv->txsem, SEM_PRIO_NONE);
/* Get DMA channels. NOTE: stm32wb_dmachannel() will always assign the DMA
* channel. If the channel is not available, then stm32wb_dmachannel()
* will block and wait until the channel becomes available. WARNING: If

8
arch/arm/src/stm32wl5/stm32wl5_spi.c
View file

@ -1733,19 +1733,11 @@ static void spi_bus_initialize(struct stm32wl5_spidev_s *priv)
nxmutex_init(&priv->lock);
#ifdef CONFIG_STM32WL5_SPI_DMA
/* Initialize the SPI semaphores that is used to wait for DMA completion.
* This semaphore is used for signaling and, hence, should not have
* priority inheritance enabled.
*/
if (priv->rxch && priv->txch)
{
nxsem_init(&priv->rxsem, 0, 0);
nxsem_init(&priv->txsem, 0, 0);
nxsem_set_protocol(&priv->rxsem, SEM_PRIO_NONE);
nxsem_set_protocol(&priv->txsem, SEM_PRIO_NONE);
/* Get DMA channels. NOTE: stm32wl5_dmachannel() will always assign
* the DMA channel. If the channel is not available, then
* stm32wl5_dmachannel() will block and wait until the channel becomes

3
arch/arm/src/tiva/common/tiva_hciuart.c
View file

@ -1846,10 +1846,7 @@ void hciuart_initialize(void)
/* Initialize signalling semaphores */
nxsem_init(&state->rxwait, 0, 0);
nxsem_set_protocol(&state->rxwait, SEM_PRIO_NONE);
nxsem_init(&state->txwait, 0, 0);
nxsem_set_protocol(&state->txwait, SEM_PRIO_NONE);
/* Attach and enable the HCI UART IRQ */

5
arch/arm/src/tiva/common/tiva_ssi.c
View file

@ -1599,12 +1599,7 @@ struct spi_dev_s *tiva_ssibus_initialize(int port)
/* Initialize the state structure */
#ifndef CONFIG_SSI_POLLWAIT
/* The xfrsem semaphore is used for signaling and, hence, should not have
* priority inheritance enabled.
*/
nxsem_init(&priv->xfrsem, 0, 0);
nxsem_set_protocol(&priv->xfrsem, SEM_PRIO_NONE);
#endif
nxmutex_init(&priv->lock);

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