arch/arm/imxrt: Initial modification to support two USB Controllers
Many iMXRT MCUs have internally two USB OTG controllers, however NuttX currently only supports one USB controllers. This patch will prepare the "house" to support both ports at same time. Signed-off-by: Alan C. Assis <acassis@gmail.com>
This commit is contained in:
Alan Carvalho de Assis
Alin Jerpelea
parent
d2282ec26a
commit
59dc9a3884
3 changed files with 139 additions and 41 deletions
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@ -15,69 +15,95 @@ choice
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config ARCH_CHIP_MIMXRT1021CAG4A
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bool "MIMXRT1021CAG4A"
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select ARCH_FAMILY_MIMXRT1021C
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select IMXRT_HAVE_USBOTG1
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config ARCH_CHIP_MIMXRT1021CAF4A
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bool "MIMXRT1021CAF4A"
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select ARCH_FAMILY_MIMXRT1021C
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select IMXRT_HAVE_USBOTG1
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config ARCH_CHIP_MIMXRT1021DAF5A
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bool "MIMXRT1021DAF5A"
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select ARCH_FAMILY_MIMXRT1021D
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select IMXRT_HAVE_USBOTG1
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config ARCH_CHIP_MIMXRT1021DAG5A
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bool "MIMXRT1021DAG5A"
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select ARCH_FAMILY_MIMXRT1021D
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select IMXRT_HAVE_USBOTG1
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config ARCH_CHIP_MIMXRT1051DVL6A
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bool "MIMXRT1051DVL6A"
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select ARCH_FAMILY_MIMXRT105xDVL6A
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select IMXRT_HAVE_USBOTG1
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select IMXRT_HAVE_USBOTG2
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config ARCH_CHIP_MIMXRT1051CVL5A
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bool "MIMXRT1051CVL5A"
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select ARCH_FAMILY_MIMXRT105xCVL5A
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select IMXRT_HAVE_USBOTG1
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select IMXRT_HAVE_USBOTG2
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config ARCH_CHIP_MIMXRT1052DVL6A
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bool "MIMXRT1052DVL6A"
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select ARCH_FAMILY_MIMXRT105xDVL6A
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select IMXRT_HAVE_LCD
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select IMXRT_HAVE_USBOTG1
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select IMXRT_HAVE_USBOTG2
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config ARCH_CHIP_MIMXRT1052CVL5A
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bool "MIMXRT1052CVL5A"
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select ARCH_FAMILY_MIMXRT105xCVL5A
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select IMXRT_HAVE_LCD
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select IMXRT_HAVE_USBOTG1
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select IMXRT_HAVE_USBOTG2
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config ARCH_CHIP_MIMXRT1061DVL6A
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bool "MIMXRT1061DVL6A"
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select ARCH_FAMILY_MXRT106xDVL6A
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select IMXRT_HAVE_USBOTG1
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select IMXRT_HAVE_USBOTG2
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config ARCH_CHIP_MIMXRT1061CVL5A
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bool "MIMXRT1061CVL5A"
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select ARCH_FAMILY_MIMXRT106xCVL5A
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select IMXRT_HAVE_USBOTG1
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select IMXRT_HAVE_USBOTG2
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config ARCH_CHIP_MIMXRT1062DVL6A
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bool "MIMXRT1062DVL6A"
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select ARCH_FAMILY_MXRT106xDVL6A
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select IMXRT_HAVE_LCD
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select IMXRT_HAVE_USBOTG1
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select IMXRT_HAVE_USBOTG2
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config ARCH_CHIP_MIMXRT1062CVL5A
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bool "MIMXRT1062DVL6A"
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select ARCH_FAMILY_MIMXRT106xCVL5A
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select IMXRT_HAVE_LCD
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select IMXRT_HAVE_USBOTG1
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select IMXRT_HAVE_USBOTG2
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config ARCH_CHIP_MIMXRT1064DVL6A
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bool "MIMXRT1064DVL6A"
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select ARCH_FAMILY_MXRT106xDVL6A
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select IMXRT_HAVE_LCD
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select IMXRT_HAVE_USBOTG1
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select IMXRT_HAVE_USBOTG2
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config ARCH_CHIP_MIMXRT1064CVL5A
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bool "MIMXRT1064DVL6A"
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select ARCH_FAMILY_MIMXRT106xCVL5A
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select IMXRT_HAVE_LCD
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select IMXRT_HAVE_USBOTG1
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select IMXRT_HAVE_USBOTG2
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config ARCH_CHIP_MIMXRT1176DVMAA
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bool "MIMXRT1176DVMAA"
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select ARCH_FAMILY_IMXRT117x
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select IMXRT_HAVE_LCD
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select IMXRT_HAVE_USBOTG1
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select IMXRT_HAVE_USBOTG2
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endchoice # i.MX RT Chip Selection
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@ -333,9 +359,19 @@ config IMXRT_EDMA
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default n
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select ARCH_DMA
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config IMXRT_USBOTG
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bool "USB EHCI"
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config IMXRT_USBOTG1
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bool "USB EHCI OTG1"
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default n
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depends on IMXRT_HAVE_USBOTG1
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select IMXRT_USBOTG
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select USBHOST_HAVE_ASYNCH if USBHOST
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select USBHOST_ASYNCH
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config IMXRT_USBOTG2
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bool "USB EHCI OTG2: NOT SUPPORTED YET"
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default n
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depends on IMXRT_HAVE_USBOTG2
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select IMXRT_USBOTG
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select USBHOST_HAVE_ASYNCH if USBHOST
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select USBHOST_ASYNCH
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@ -3088,25 +3124,25 @@ endif # SCHED_TICKLESS
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endmenu # Timer Configuration
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if IMXRT_USBOTG && USBHOST
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if IMXRT_USBOTG1 && USBHOST
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menu "USB host controller driver (HCD) options"
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menu "USB OTG1 Host Controller Driver (HCD) options"
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config IMXRT_EHCI_NQHS
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config IMXRT_EHCI_USB1_NQHS
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int "Number of Queue Head (QH) structures"
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default 4
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---help---
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Configurable number of Queue Head (QH) structures. The default is
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one per Root hub port plus one for EP0 (4).
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config IMXRT_EHCI_NQTDS
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config IMXRT_EHCI_USB1_NQTDS
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int "Number of Queue Element Transfer Descriptor (qTDs)"
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default 6
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---help---
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Configurable number of Queue Element Transfer Descriptor (qTDs).
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The default is one per root hub plus three from EP0 (6).
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config IMXRT_EHCI_BUFSIZE
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config IMXRT_EHCI_USB1_BUFSIZE
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int "Size of one request/descriptor buffer"
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default 128
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---help---
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@ -3114,7 +3150,7 @@ config IMXRT_EHCI_BUFSIZE
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size must be an even number of 32-bit words and must be large enough
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to hangle the largest transfer via a SETUP request.
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config IMXRT_EHCI_PREALLOCATE
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config IMXRT_EHCI_USB1_PREALLOCATE
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bool "Preallocate descriptor pool"
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default y
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---help---
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@ -3123,7 +3159,44 @@ config IMXRT_EHCI_PREALLOCATE
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dynamically allocated using kmm_memalign().
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endmenu # USB host controller driver (HCD) options
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endif # IMXRT_USBOTG && USBHOST
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endif # IMXRT_USBOTG1 && USBHOST
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if IMXRT_USBOTG2 && USBHOST
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menu "USB OTG2 Host Controller Driver (HCD) options: NOT SUPPORTED YET"
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config IMXRT_EHCI_USB2_NQHS
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int "Number of Queue Head (QH) structures"
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default 4
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---help---
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Configurable number of Queue Head (QH) structures. The default is
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one per Root hub port plus one for EP0 (4).
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config IMXRT_EHCI_USB2_NQTDS
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int "Number of Queue Element Transfer Descriptor (qTDs)"
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default 6
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---help---
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Configurable number of Queue Element Transfer Descriptor (qTDs).
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The default is one per root hub plus three from EP0 (6).
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config IMXRT_EHCI_USB2_BUFSIZE
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int "Size of one request/descriptor buffer"
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default 128
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---help---
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The size of one request/descriptor buffer in bytes. The TD buffe
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size must be an even number of 32-bit words and must be large enough
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to hangle the largest transfer via a SETUP request.
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config IMXRT_EHCI_USB2_PREALLOCATE
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bool "Preallocate descriptor pool"
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default y
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---help---
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Select this option to pre-allocate EHCI queue and descriptor
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structure pools in .bss. Otherwise, these pools will be
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dynamically allocated using kmm_memalign().
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endmenu # USB host controller driver (HCD) options
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endif # IMXRT_USBOTG2
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if IMXRT_USBDEV
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@ -242,7 +242,7 @@ static void imxrt_pllsetup(void)
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{
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}
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/* Init USB PLL3 */
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/* Init USB1 PLL3 */
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/* capture it's original value */
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@ -267,6 +267,31 @@ static void imxrt_pllsetup(void)
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putreg32(pll3reg, IMXRT_CCM_ANALOG_PFD_480);
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#ifdef CONFIG_IMXRT_USBOTG2
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/* Init USB2 PLL */
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/* Enable the USB2 PLL */
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reg = getreg32(IMXRT_CCM_ANALOG_PLL_USB2);
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reg |= IMXRT_USB2_PLL_DIV_SELECT |
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CCM_ANALOG_PLL_USB2_ENABLE |
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CCM_ANALOG_PLL_USB2_EN_USB_CLKS |
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CCM_ANALOG_PLL_USB2_POWER |
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CCM_ANALOG_PLL_USB2_DIV_SELECT_20;
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putreg32(reg, IMXRT_CCM_ANALOG_PLL_USB2);
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while ((getreg32(IMXRT_CCM_ANALOG_PLL_USB2) &
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CCM_ANALOG_PLL_USB2_LOCK) == 0)
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{
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}
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/* Disable bypass */
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reg = getreg32(IMXRT_CCM_ANALOG_PLL_USB2);
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reg &= ~CCM_ANALOG_PLL_USB2_BYPASS;
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putreg32(reg, IMXRT_CCM_ANALOG_PLL_USB2);
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#endif
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#ifdef CONFIG_IMXRT_LCD
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/* Init Video PLL5 */
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@ -71,16 +71,16 @@
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* Root hub port plus one for EP0.
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*/
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#ifndef CONFIG_IMXRT_EHCI_NQHS
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# define CONFIG_IMXRT_EHCI_NQHS (IMXRT_EHCI_NRHPORT + 1)
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#ifndef CONFIG_IMXRT_EHCI_USB1_NQHS
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# define CONFIG_IMXRT_EHCI_USB1_NQHS (IMXRT_EHCI_NRHPORT + 1)
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#endif
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/* Configurable number of Queue Element Transfer Descriptor (qTDs). The
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* default is one per root hub plus three from EP0.
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*/
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#ifndef CONFIG_IMXRT_EHCI_NQTDS
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# define CONFIG_IMXRT_EHCI_NQTDS (IMXRT_EHCI_NRHPORT + 3)
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#ifndef CONFIG_IMXRT_EHCI_USB1_NQTDS
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# define CONFIG_IMXRT_EHCI_USB1_NQTDS (IMXRT_EHCI_NRHPORT + 3)
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#endif
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/* Buffers must be aligned to the cache line size */
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@ -89,17 +89,17 @@
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/* Configurable size of a request/descriptor buffers */
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#ifndef CONFIG_IMXRT_EHCI_BUFSIZE
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# define CONFIG_IMXRT_EHCI_BUFSIZE 128
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#ifndef CONFIG_IMXRT_EHCI_USB1_BUFSIZE
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# define CONFIG_IMXRT_EHCI_USB1_BUFSIZE 128
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#endif
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#define IMXRT_EHCI_BUFSIZE \
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((CONFIG_IMXRT_EHCI_BUFSIZE + DCACHE_LINEMASK) & ~DCACHE_LINEMASK)
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((CONFIG_IMXRT_EHCI_USB1_BUFSIZE + DCACHE_LINEMASK) & ~DCACHE_LINEMASK)
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/* Debug options */
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#ifndef CONFIG_DEBUG_USB_INFO
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# undef CONFIG_IMXRT_EHCI_REGDEBUG
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# undef CONFIG_IMXRT_EHCI_USB1_REGDEBUG
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#endif
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/* Isochronous transfers are not currently supported */
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@ -407,7 +407,7 @@ static uint32_t imxrt_swap32(uint32_t value);
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# define imxrt_swap32(value) (value)
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#endif
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#ifdef CONFIG_IMXRT_EHCI_REGDEBUG
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#ifdef CONFIG_IMXRT_EHCI_USB1_REGDEBUG
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static void imxrt_printreg(volatile uint32_t *regaddr, uint32_t regval,
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bool iswrite);
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static void imxrt_checkreg(volatile uint32_t *regaddr, uint32_t regval,
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@ -451,7 +451,7 @@ static int imxrt_qh_flush(struct imxrt_qh_s *qh);
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/* Endpoint Transfer Handling ***********************************************/
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#ifdef CONFIG_IMXRT_EHCI_REGDEBUG
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#ifdef CONFIG_IMXRT_EHCI_USB1_REGDEBUG
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static void imxrt_qtd_print(struct imxrt_qtd_s *qtd);
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static void imxrt_qh_print(struct imxrt_qh_s *qh);
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static int imxrt_qtd_dump(struct imxrt_qtd_s *qtd, uint32_t **bp, void *arg);
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@ -604,26 +604,26 @@ static struct imxrt_qh_s g_intrhead aligned_data(32);
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/* The frame list */
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#ifdef CONFIG_IMXRT_EHCI_PREALLOCATE
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#ifdef CONFIG_IMXRT_EHCI_USB1_PREALLOCATE
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static uint32_t g_framelist[FRAME_LIST_SIZE] aligned_data(4096);
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#else
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static uint32_t *g_framelist;
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#endif
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#endif /* CONFIG_USBHOST_INT_DISABLE */
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#ifdef CONFIG_IMXRT_EHCI_PREALLOCATE
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#ifdef CONFIG_IMXRT_EHCI_USB1_PREALLOCATE
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/* Pools of pre-allocated data structures. These will all be linked into the
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* free lists within g_ehci. These must all be aligned to 32-byte boundaries
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*/
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/* Queue Head (QH) pool */
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static struct imxrt_qh_s g_qhpool[CONFIG_IMXRT_EHCI_NQHS]
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static struct imxrt_qh_s g_qhpool[CONFIG_IMXRT_EHCI_USB1_NQHS]
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aligned_data(32);
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/* Queue Element Transfer Descriptor (qTD) pool */
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static struct imxrt_qtd_s g_qtdpool[CONFIG_IMXRT_EHCI_NQTDS]
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static struct imxrt_qtd_s g_qtdpool[CONFIG_IMXRT_EHCI_USB1_NQTDS]
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aligned_data(32);
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#else
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@ -884,7 +884,7 @@ static uint32_t imxrt_swap32(uint32_t value)
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*
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****************************************************************************/
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#ifdef CONFIG_IMXRT_EHCI_REGDEBUG
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#ifdef CONFIG_IMXRT_EHCI_USB1_REGDEBUG
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static void imxrt_printreg(volatile uint32_t *regaddr, uint32_t regval,
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bool iswrite)
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{
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@ -901,7 +901,7 @@ static void imxrt_printreg(volatile uint32_t *regaddr, uint32_t regval,
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*
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****************************************************************************/
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#ifdef CONFIG_IMXRT_EHCI_REGDEBUG
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#ifdef CONFIG_IMXRT_EHCI_USB1_REGDEBUG
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static void imxrt_checkreg(volatile uint32_t *regaddr, uint32_t regval,
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bool iswrite)
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{
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@ -966,7 +966,7 @@ static void imxrt_checkreg(volatile uint32_t *regaddr, uint32_t regval,
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*
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****************************************************************************/
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#ifdef CONFIG_IMXRT_EHCI_REGDEBUG
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#ifdef CONFIG_IMXRT_EHCI_USB1_REGDEBUG
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static uint32_t imxrt_getreg(volatile uint32_t *regaddr)
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{
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/* Read the value from the register */
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@ -993,7 +993,7 @@ static inline uint32_t imxrt_getreg(volatile uint32_t *regaddr)
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*
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****************************************************************************/
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#ifdef CONFIG_IMXRT_EHCI_REGDEBUG
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#ifdef CONFIG_IMXRT_EHCI_USB1_REGDEBUG
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static void imxrt_putreg(uint32_t regval, volatile uint32_t *regaddr)
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{
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/* Check if we need to print this value */
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@ -1477,7 +1477,7 @@ static int imxrt_qh_flush(struct imxrt_qh_s *qh)
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*
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****************************************************************************/
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#ifdef CONFIG_IMXRT_EHCI_REGDEBUG
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#ifdef CONFIG_IMXRT_EHCI_USB1_REGDEBUG
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static void imxrt_qtd_print(struct imxrt_qtd_s *qtd)
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{
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uinfo(" QTD[%p]:\n", qtd);
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@ -1498,7 +1498,7 @@ static void imxrt_qtd_print(struct imxrt_qtd_s *qtd)
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*
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****************************************************************************/
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#ifdef CONFIG_IMXRT_EHCI_REGDEBUG
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#ifdef CONFIG_IMXRT_EHCI_USB1_REGDEBUG
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static void imxrt_qh_print(struct imxrt_qh_s *qh)
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{
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struct imxrt_epinfo_s *epinfo;
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@ -1541,7 +1541,7 @@ static void imxrt_qh_print(struct imxrt_qh_s *qh)
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*
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****************************************************************************/
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#ifdef CONFIG_IMXRT_EHCI_REGDEBUG
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#ifdef CONFIG_IMXRT_EHCI_USB1_REGDEBUG
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static int imxrt_qtd_dump(struct imxrt_qtd_s *qtd, uint32_t **bp, void *arg)
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{
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imxrt_qtd_print(qtd);
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@ -1558,7 +1558,7 @@ static int imxrt_qtd_dump(struct imxrt_qtd_s *qtd, uint32_t **bp, void *arg)
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*
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****************************************************************************/
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#ifdef CONFIG_IMXRT_EHCI_REGDEBUG
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#ifdef CONFIG_IMXRT_EHCI_USB1_REGDEBUG
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static int imxrt_qh_dump(struct imxrt_qh_s *qh, uint32_t **bp, void *arg)
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{
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imxrt_qh_print(qh);
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@ -4988,7 +4988,7 @@ struct usbhost_connection_s *imxrt_ehci_initialize(int controller)
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DEBUGASSERT((sizeof(struct imxrt_qh_s) & 0x1f) == 0);
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DEBUGASSERT((sizeof(struct imxrt_qtd_s) & 0x1f) == 0);
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# ifdef CONFIG_IMXRT_EHCI_PREALLOCATE
|
||||
# ifdef CONFIG_IMXRT_EHCI_USB1_PREALLOCATE
|
||||
DEBUGASSERT(((uintptr_t)&g_qhpool & 0x1f) == 0);
|
||||
DEBUGASSERT(((uintptr_t)&g_qtdpool & 0x1f) == 0);
|
||||
# endif
|
||||
|
|
@ -5058,7 +5058,7 @@ struct usbhost_connection_s *imxrt_ehci_initialize(int controller)
|
|||
# ifndef CONFIG_IMXRT_EHCI_PREALLOCATE
|
||||
/* Allocate a pool of free Queue Head (QH) structures */
|
||||
|
||||
g_qhpool = kmm_memalign(32, CONFIG_IMXRT_EHCI_NQHS *
|
||||
g_qhpool = kmm_memalign(32, CONFIG_IMXRT_EHCI_USB1_NQHS *
|
||||
sizeof(struct imxrt_qh_s));
|
||||
if (!g_qhpool)
|
||||
{
|
||||
|
|
@ -5069,17 +5069,17 @@ struct usbhost_connection_s *imxrt_ehci_initialize(int controller)
|
|||
|
||||
/* Initialize the list of free Queue Head (QH) structures */
|
||||
|
||||
for (i = 0; i < CONFIG_IMXRT_EHCI_NQHS; i++)
|
||||
for (i = 0; i < CONFIG_IMXRT_EHCI_USB1_NQHS; i++)
|
||||
{
|
||||
/* Put the QH structure in a free list */
|
||||
|
||||
imxrt_qh_free(&g_qhpool[i]);
|
||||
}
|
||||
|
||||
# ifndef CONFIG_IMXRT_EHCI_PREALLOCATE
|
||||
# ifndef CONFIG_IMXRT_EHCI_USB1_PREALLOCATE
|
||||
/* Allocate a pool of free Transfer Descriptor (qTD) structures */
|
||||
|
||||
g_qtdpool = kmm_memalign(32, CONFIG_IMXRT_EHCI_NQTDS *
|
||||
g_qtdpool = kmm_memalign(32, CONFIG_IMXRT_EHCI_USB1_NQTDS *
|
||||
sizeof(struct imxrt_qtd_s));
|
||||
if (!g_qtdpool)
|
||||
{
|
||||
|
|
@ -5089,7 +5089,7 @@ struct usbhost_connection_s *imxrt_ehci_initialize(int controller)
|
|||
}
|
||||
# endif
|
||||
|
||||
# if !defined(CONFIG_IMXRT_EHCI_PREALLOCATE) && !defined(CONFIG_USBHOST_INT_DISABLE)
|
||||
# if !defined(CONFIG_IMXRT_EHCI_USB1_PREALLOCATE) && !defined(CONFIG_USBHOST_INT_DISABLE)
|
||||
/* Allocate the periodic framelist */
|
||||
|
||||
g_framelist = kmm_memalign(4096, FRAME_LIST_SIZE * sizeof(uint32_t));
|
||||
|
|
@ -5104,7 +5104,7 @@ struct usbhost_connection_s *imxrt_ehci_initialize(int controller)
|
|||
|
||||
/* Initialize the list of free Transfer Descriptor (qTD) structures */
|
||||
|
||||
for (i = 0; i < CONFIG_IMXRT_EHCI_NQTDS; i++)
|
||||
for (i = 0; i < CONFIG_IMXRT_EHCI_USB1_NQTDS; i++)
|
||||
{
|
||||
/* Put the TD in a free list */
|
||||
|
||||
|
|
@ -5127,7 +5127,7 @@ struct usbhost_connection_s *imxrt_ehci_initialize(int controller)
|
|||
* some performance.
|
||||
*/
|
||||
|
||||
# ifdef CONFIG_IMXRT_EHCI_SDIS
|
||||
# ifdef CONFIG_IMXRT_EHCI_USB1_SDIS
|
||||
putreg32(USBHOST_USBMODE_CM_HOST | USBHOST_USBMODE_SDIS |
|
||||
USBHOST_USBMODE_VBPS, IMXRT_USBDEV_USBMODE);
|
||||
# else
|
||||
|
|
@ -5149,7 +5149,7 @@ struct usbhost_connection_s *imxrt_ehci_initialize(int controller)
|
|||
* host configuration in the reset.
|
||||
*/
|
||||
|
||||
# ifdef CONFIG_IMXRT_EHCI_SDIS
|
||||
# ifdef CONFIG_IMXRT_EHCI_USB1_SDIS
|
||||
putreg32(USBHOST_USBMODE_CM_HOST | USBHOST_USBMODE_SDIS |
|
||||
USBHOST_USBMODE_VBPS, IMXRT_USBDEV_USBMODE);
|
||||
# else
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue