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arm64: Use the correct aff in up_affinity_irq function

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Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
This commit is contained in:
zhangyuan21 2023-07-11 09:51:02 +08:00 • committed by Xiang Xiao
parent 57bf3e1fea
commit 601202ee4a
2 changed files with 9 additions and 3 deletions
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2
arch/arm64/src/common/arm64_arch.h
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@ -184,7 +184,7 @@
({ \
uint64_t __mpidr = GET_MPIDR(); \
__mpidr &= ~(MPIDR_AFFLVL_MASK << MPIDR_AFF ## aff_level ## _SHIFT); \
__mpidr |= (cpu << MPIDR_AFF ## aff_level ## _SHIFT); \
__mpidr |= ((core) << MPIDR_AFF ## aff_level ## _SHIFT); \
__mpidr &= MPIDR_ID_MASK; \
__mpidr; \
})

10
arch/arm64/src/common/arm64_gicv3.c
View file

@ -53,6 +53,7 @@
* selects distributor base for SPI
* The macro translates to distributor base for GICv2 and GICv1
*/
#define GET_DIST_BASE(intid) ((intid < GIC_SPI_INT_BASE) ? \
(gic_get_rdist() + GICR_SGI_BASE_OFF) \
: GIC_DIST_BASE)
@ -245,7 +246,7 @@ void arm64_gic_irq_enable(unsigned int intid)
if (GIC_IS_SPI(intid))
{
arm64_gic_write_irouter(up_cpu_index(), intid);
arm64_gic_write_irouter((GET_MPIDR() & MPIDR_ID_MASK), intid);
}
}
@ -615,7 +616,12 @@ void up_affinity_irq(int irq, cpu_set_t cpuset)
{
if (GIC_IS_SPI(irq))
{
arm64_gic_write_irouter(cpuset, irq);
/* Only support interrupt routing mode 0,
* so routing to the first cpu in cpuset.
*/
uint64_t mpid = arm64_get_mpid(ffs(cpuset) - 1);
arm64_gic_write_irouter(mpid, irq);
}
}