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boards/arm/stm32f7: separate nucleo-144 board into individual boards

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nucleo-144 combines 3 different ST boards. This approach is inconsistent with
the support for the rest of the nucleo boards, where each board is in separate folders.
Also nucleo-144 is no longer reserved for STM32F7 chips but other families also use this format.

After this commit nucleo-144 is divided into 3 boards:

- nucleo-f746zg
- nucleo-f767zi
- nucleo-f722ze
This commit is contained in:
raiden00pl 2024-10-20 09:58:25 +02:00 • committed by Xiang Xiao
parent d73d34b1a0
commit 6657f2abb7
117 changed files with 11536 additions and 552 deletions
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16
Documentation/platforms/arm/stm32f7/boards/nucleo-f722/index.rst → Documentation/platforms/arm/stm32f7/boards/nucleo-f722ze/index.rst
View file

@ -272,8 +272,8 @@ and connect it as follows::
Configurations
==============
f7xx-nsh
--------
nsh
---
Configures the NuttShell (nsh) located at apps/examples/nsh for the
Nucleo-144 boards. The Configuration enables the serial interfaces
@ -290,11 +290,11 @@ NOTES:
b. If this is the initial configuration then execute::
./tools/configure.sh nucleo-144:nsh
./tools/configure.sh nucleo-f722ze:nsh
in nuttx/ in order to start configuration process.
Caution: Doing this step more than once will overwrite .config with
the contents of the nucleo-144/nsh/defconfig file.
the contents of the nucleo-f722ze/nsh/defconfig file.
c. Execute 'make oldconfig' in nuttx/ in order to refresh the
configuration.
@ -334,8 +334,8 @@ NOTES:
Default values for other settings associated with the select USART should
be correct.
f7xx-evalos:
------------
evalos:
-------
This configuration is designed to test the features of the board.
@ -358,11 +358,11 @@ NOTES:
b. If this is the initial configuration then execute::
./tools/configure.sh nucleo-144:evalos
./tools/configure.sh nucleo-f722ze:evalos
in nuttx/ in order to start configuration process.
Caution: Doing this step more than once will overwrite .config with
the contents of the nucleo-144/evalos/defconfig file.
the contents of the nucleo-f722ze/evalos/defconfig file.
c. Execute 'make oldconfig' in nuttx/ in order to refresh the
configuration.

14
Documentation/platforms/arm/stm32f7/boards/nucleo-f746/index.rst → Documentation/platforms/arm/stm32f7/boards/nucleo-f746zg/index.rst
View file

@ -314,8 +314,8 @@ and connect it as follows::
Configurations
==============
f7xx-nsh
--------
nsh
---
Configures the NuttShell (nsh) located at apps/examples/nsh for the
Nucleo-144 boards. The Configuration enables the serial interfaces
@ -332,11 +332,11 @@ NOTES:
b. If this is the initial configuration then execute::
./tools/configure.sh nucleo-144:nsh
./tools/configure.sh nucleo-f746zg:nsh
in nuttx/ in order to start configuration process.
Caution: Doing this step more than once will overwrite .config with
the contents of the nucleo-144/nsh/defconfig file.
the contents of the nucleo-f746zg/nsh/defconfig file.
c. Execute 'make oldconfig' in nuttx/ in order to refresh the
configuration.
@ -376,8 +376,8 @@ NOTES:
Default values for other settings associated with the select USART should
be correct.
f7xx-evalos:
------------
evalos:
-------
This configuration is designed to test the features of the board.
@ -404,7 +404,7 @@ NOTES:
in nuttx/ in order to start configuration process.
Caution: Doing this step more than once will overwrite .config with
the contents of the nucleo-144/evalos/defconfig file.
the contents of the nucleo-f746zg/evalos/defconfig file.
c. Execute 'make oldconfig' in nuttx/ in order to refresh the
configuration.

16
Documentation/platforms/arm/stm32f7/boards/nucleo-f767/index.rst → Documentation/platforms/arm/stm32f7/boards/nucleo-f767zi/index.rst
View file

@ -316,8 +316,8 @@ and connect it as follows::
Configurations
==============
f7xx-nsh
--------
nsh
---
Configures the NuttShell (nsh) located at apps/examples/nsh for the
Nucleo-144 boards. The Configuration enables the serial interfaces
@ -334,11 +334,11 @@ NOTES:
b. If this is the initial configuration then execute::
./tools/configure.sh nucleo-144:nsh
./tools/configure.sh nucleo-f767zi:nsh
in nuttx/ in order to start configuration process.
Caution: Doing this step more than once will overwrite .config with
the contents of the nucleo-144/nsh/defconfig file.
the contents of the nucleo-f767zi/nsh/defconfig file.
c. Execute 'make oldconfig' in nuttx/ in order to refresh the
configuration.
@ -378,8 +378,8 @@ NOTES:
Default values for other settings associated with the select USART should
be correct.
f7xx-evalos:
------------
evalos:
-------
This configuration is designed to test the features of the board.
@ -402,11 +402,11 @@ NOTES:
b. If this is the initial configuration then execute::
./tools/configure.sh nucleo-144:evalos
./tools/configure.sh nucleo-f767zi:evalos
in nuttx/ in order to start configuration process.
Caution: Doing this step more than once will overwrite .config with
the contents of the nucleo-144/evalos/defconfig file.
the contents of the nucleo-f767zi/evalos/defconfig file.
c. Execute 'make oldconfig' in nuttx/ in order to refresh the
configuration.

12
LICENSE
View file

@ -3355,8 +3355,12 @@ boards/arm/stm32/omnibusf4/src/stm32_romfs.h
boards/arm/stm32/omnibusf4/src/stm32_romfs_initialize.c
boards/arm/stm32/stm32f4discovery/src/stm32_romfs.h
boards/arm/stm32/stm32f4discovery/src/stm32_romfs_initialize.c
boards/arm/stm32f7/nucleo-144/src/stm32_romfs.h
boards/arm/stm32f7/nucleo-144/src/stm32_romfs_initialize.c
boards/arm/stm32f7/nucleo-f722ze/src/stm32_romfs.h
boards/arm/stm32f7/nucleo-f722ze/src/stm32_romfs_initialize.c
boards/arm/stm32f7/nucleo-f746zg/src/stm32_romfs.h
boards/arm/stm32f7/nucleo-f746zg/src/stm32_romfs_initialize.c
boards/arm/stm32f7/nucleo-f767zi/src/stm32_romfs.h
boards/arm/stm32f7/nucleo-f767zi/src/stm32_romfs_initialize.c
=============================================================
Copyright (C) 2017 Tomasz Wozniak. All rights reserved.
@ -3420,7 +3424,9 @@ LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
boards/arm/stm32f7/nucleo-144/src/stm32_dma_alloc.c
boards/arm/stm32f7/nucleo-f722ze/src/stm32_dma_alloc.c
boards/arm/stm32f7/nucleo-f746zg/src/stm32_dma_alloc.c
boards/arm/stm32f7/nucleo-f767zi/src/stm32_dma_alloc.c
boards/arm/stm32f7/stm32f746-ws/src/stm32_dma_alloc.c
boards/arm/stm32l4/nucleo-l496zg/src/stm32_dma_alloc.c
boards/arm/tms570/tms570ls31x-usb-kit/include/nsh_romfsimg.h

61
boards/Kconfig
View file

@ -1524,36 +1524,35 @@ config ARCH_BOARD_NUCLEO_F429ZI
---help---
STMicro Nucleo-F429zi board based on the STMicro STM32F429ZIT6 MCU.
config ARCH_BOARD_NUCLEO_144
bool "STMicro NUCLEO-144"
depends on ARCH_CHIP_STM32F722ZE || ARCH_CHIP_STM32F746ZG || ARCH_CHIP_STM32F767ZI
config ARCH_BOARD_NUCLEO_F722ZE
bool "STMicro NUCLEO-F722ZE"
depends on ARCH_CHIP_STM32F722ZE
select ARCH_HAVE_LEDS
select ARCH_HAVE_BUTTONS
select ARCH_HAVE_IRQBUTTONS
---help---
STMicro Nucleo-144 development board featuring STMicroelectronics
F2, F3, F4, F7 and L4 MCU families. The board is a "Hardware pattern"
that can be populated with the 144 pin package of the following MCUs:
STMicro Nucleo F722ZE board based on STM32F722ZET6,
a 216MHz Cortex-M7, w/FPU, 512KiB Flash memory and 256KiB SRAM.
Target STM32 Order code
STM32F207ZGT6 NUCLEO-F207ZG
STM32F303ZET6 NUCLEO-F303ZE
STM32F429ZIT6 NUCLEO-F429ZI
STM32F446ZET6 NUCLEO-F446ZE
STM32F722ZET6 NUCLEO-F722ZE
STM32F746ZGT6 NUCLEO-F746ZG
STM32F767ZIT6 NUCLEO-F767ZI
STM32L496ZGT6 NUCLEO-L496ZG
STM32L496ZGT6P NUCLEO-L496ZG-P
config ARCH_BOARD_NUCLEO_F746ZG
bool "STMicro NUCLEO-F746ZG"
depends on ARCH_CHIP_STM32F746ZG
select ARCH_HAVE_LEDS
select ARCH_HAVE_BUTTONS
select ARCH_HAVE_IRQBUTTONS
---help---
STMicro Nucleo F746ZG board based on STM32F746ZGT6
a 216MHz Cortex-M7, w/FPU, 1024KiB Flash memory and 320KiB SRAM.
Supported in this configuration are:
NUCLEO-F722ZE - STM32F722ZET6 a 216MHz Cortex-M7, w/FPU -
512KiB Flash memory and 256KiB SRAM.
NUCLEO-F746ZG - STM32F746ZGT6 a 216MHz Cortex-M7, w/FPU -
1024KiB Flash memory and 320KiB SRAM.
NUCLEO-F767ZI - STM32F767ZIT6 a 216MHz Cortex-M7, w/DPFPU -
2048KiB Flash memory and 512KiB SRAM.
config ARCH_BOARD_NUCLEO_F767ZI
bool "STMicro NUCLEO-F767ZI"
depends on ARCH_CHIP_STM32F767ZI
select ARCH_HAVE_LEDS
select ARCH_HAVE_BUTTONS
select ARCH_HAVE_IRQBUTTONS
---help---
STMicro Nucleo F767ZI board based on STM32F767ZIT6,
a 216MHz Cortex-M7, w/DPFPU 2048KiB Flash memory and 512KiB SRAM.
config ARCH_BOARD_NUCLEO_L073RZ
bool "STM32L073RZU6 Nucleo L073RZ"
@ -3356,7 +3355,9 @@ config ARCH_BOARD
default "thingy91-nrf52" if ARCH_BOARD_THINGY91_NRF52
default "nrf9160-dk-nrf52" if ARCH_BOARD_NRF9160_DK_NRF52
default "ntosd-dm320" if ARCH_BOARD_NTOSD_DM320
default "nucleo-144" if ARCH_BOARD_NUCLEO_144
default "nucleo-f722ze" if ARCH_BOARD_NUCLEO_F722ZE
default "nucleo-f746zg" if ARCH_BOARD_NUCLEO_F746ZG
default "nucleo-f767zi" if ARCH_BOARD_NUCLEO_F767ZI
default "nucleo-f072rb" if ARCH_BOARD_NUCLEO_F072RB
default "nucleo-f091rc" if ARCH_BOARD_NUCLEO_F091RC
default "nucleo-f103rb" if ARCH_BOARD_NUCLEO_F103RB
@ -4002,8 +4003,14 @@ endif
if ARCH_BOARD_STM32F072_DISCOVERY
source "boards/arm/stm32f0l0g0/stm32f072-discovery/Kconfig"
endif
if ARCH_BOARD_NUCLEO_144
source "boards/arm/stm32f7/nucleo-144/Kconfig"
if ARCH_BOARD_NUCLEO_F722ZE
source "boards/arm/stm32f7/nucleo-f722ze/Kconfig"
endif
if ARCH_BOARD_NUCLEO_F746ZG
source "boards/arm/stm32f7/nucleo-f746zg/Kconfig"
endif
if ARCH_BOARD_NUCLEO_F767ZI
source "boards/arm/stm32f7/nucleo-f767zi/Kconfig"
endif
if ARCH_BOARD_STM32F746_WS
source "boards/arm/stm32f7/stm32f746-ws/Kconfig"

39
boards/arm/stm32f7/nucleo-144/configs/f722-cansock/Make.defs
View file

@ -1,39 +0,0 @@
############################################################################
# boards/arm/stm32f7/nucleo-144/configs/f722-cansock/Make.defs
#
# Licensed to the Apache Software Foundation (ASF) under one or more
# contributor license agreements. See the NOTICE file distributed with
# this work for additional information regarding copyright ownership. The
# ASF licenses this file to you under the Apache License, Version 2.0 (the
# "License"); you may not use this file except in compliance with the
# License. You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
# License for the specific language governing permissions and limitations
# under the License.
#
############################################################################
include $(TOPDIR)/.config
include $(TOPDIR)/tools/Config.mk
include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs
LDSCRIPT = f722-flash.ld
ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT)
ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10
CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS)
CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS)
CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS)
CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS)
CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS)
AFLAGS := $(CFLAGS) -D__ASSEMBLY__
NXFLATLDFLAGS1 = -r -d -warn-common
NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections
LDNXFLATFLAGS = -e main -s 2048

39
boards/arm/stm32f7/nucleo-144/configs/f722-composite/Make.defs
View file

@ -1,39 +0,0 @@
############################################################################
# boards/arm/stm32f7/nucleo-144/configs/f722-composite/Make.defs
#
# Licensed to the Apache Software Foundation (ASF) under one or more
# contributor license agreements. See the NOTICE file distributed with
# this work for additional information regarding copyright ownership. The
# ASF licenses this file to you under the Apache License, Version 2.0 (the
# "License"); you may not use this file except in compliance with the
# License. You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
# License for the specific language governing permissions and limitations
# under the License.
#
############################################################################
include $(TOPDIR)/.config
include $(TOPDIR)/tools/Config.mk
include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs
LDSCRIPT = f722-flash.ld
ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT)
ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10
CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS)
CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS)
CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS)
CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS)
CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS)
AFLAGS := $(CFLAGS) -D__ASSEMBLY__
NXFLATLDFLAGS1 = -r -d -warn-common
NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections
LDNXFLATFLAGS = -e main -s 2048

39
boards/arm/stm32f7/nucleo-144/configs/f722-nsh/Make.defs
View file

@ -1,39 +0,0 @@
############################################################################
# boards/arm/stm32f7/nucleo-144/configs/f722-nsh/Make.defs
#
# Licensed to the Apache Software Foundation (ASF) under one or more
# contributor license agreements. See the NOTICE file distributed with
# this work for additional information regarding copyright ownership. The
# ASF licenses this file to you under the Apache License, Version 2.0 (the
# "License"); you may not use this file except in compliance with the
# License. You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
# License for the specific language governing permissions and limitations
# under the License.
#
############################################################################
include $(TOPDIR)/.config
include $(TOPDIR)/tools/Config.mk
include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs
LDSCRIPT = f722-flash.ld
ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT)
ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10
CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS)
CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS)
CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS)
CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS)
CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS)
AFLAGS := $(CFLAGS) -D__ASSEMBLY__
NXFLATLDFLAGS1 = -r -d -warn-common
NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections
LDNXFLATFLAGS = -e main -s 2048

39
boards/arm/stm32f7/nucleo-144/configs/f746-evalos/Make.defs
View file

@ -1,39 +0,0 @@
############################################################################
# boards/arm/stm32f7/nucleo-144/configs/f746-evalos/Make.defs
#
# Licensed to the Apache Software Foundation (ASF) under one or more
# contributor license agreements. See the NOTICE file distributed with
# this work for additional information regarding copyright ownership. The
# ASF licenses this file to you under the Apache License, Version 2.0 (the
# "License"); you may not use this file except in compliance with the
# License. You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
# License for the specific language governing permissions and limitations
# under the License.
#
############################################################################
include $(TOPDIR)/.config
include $(TOPDIR)/tools/Config.mk
include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs
LDSCRIPT = f746-flash.ld
ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT)
ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10
CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS)
CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS)
CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS)
CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS)
CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS)
AFLAGS := $(CFLAGS) -D__ASSEMBLY__
NXFLATLDFLAGS1 = -r -d -warn-common
NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections
LDNXFLATFLAGS = -e main -s 2048

39
boards/arm/stm32f7/nucleo-144/configs/f746-pysim/Make.defs
View file

@ -1,39 +0,0 @@
############################################################################
# boards/arm/stm32f7/nucleo-144/configs/f746-pysim/Make.defs
#
# Licensed to the Apache Software Foundation (ASF) under one or more
# contributor license agreements. See the NOTICE file distributed with
# this work for additional information regarding copyright ownership. The
# ASF licenses this file to you under the Apache License, Version 2.0 (the
# "License"); you may not use this file except in compliance with the
# License. You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
# License for the specific language governing permissions and limitations
# under the License.
#
############################################################################
include $(TOPDIR)/.config
include $(TOPDIR)/tools/Config.mk
include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs
LDSCRIPT = f746-flash.ld
ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT)
ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10
CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS)
CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS)
CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS)
CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS)
CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS)
AFLAGS := $(CFLAGS) -D__ASSEMBLY__
NXFLATLDFLAGS1 = -r -d -warn-common
NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections
LDNXFLATFLAGS = -e main -s 2048

39
boards/arm/stm32f7/nucleo-144/configs/f767-evalos/Make.defs
View file

@ -1,39 +0,0 @@
############################################################################
# boards/arm/stm32f7/nucleo-144/configs/f767-evalos/Make.defs
#
# Licensed to the Apache Software Foundation (ASF) under one or more
# contributor license agreements. See the NOTICE file distributed with
# this work for additional information regarding copyright ownership. The
# ASF licenses this file to you under the Apache License, Version 2.0 (the
# "License"); you may not use this file except in compliance with the
# License. You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
# License for the specific language governing permissions and limitations
# under the License.
#
############################################################################
include $(TOPDIR)/.config
include $(TOPDIR)/tools/Config.mk
include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs
LDSCRIPT = f767-flash.ld
ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT)
ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10
CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS)
CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS)
CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS)
CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS)
CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS)
AFLAGS := $(CFLAGS) -D__ASSEMBLY__
NXFLATLDFLAGS1 = -r -d -warn-common
NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections
LDNXFLATFLAGS = -e main -s 2048

39
boards/arm/stm32f7/nucleo-144/configs/f767-netnsh/Make.defs
View file

@ -1,39 +0,0 @@
############################################################################
# boards/arm/stm32f7/nucleo-144/configs/f767-netnsh/Make.defs
#
# Licensed to the Apache Software Foundation (ASF) under one or more
# contributor license agreements. See the NOTICE file distributed with
# this work for additional information regarding copyright ownership. The
# ASF licenses this file to you under the Apache License, Version 2.0 (the
# "License"); you may not use this file except in compliance with the
# License. You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
# License for the specific language governing permissions and limitations
# under the License.
#
############################################################################
include $(TOPDIR)/.config
include $(TOPDIR)/tools/Config.mk
include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs
LDSCRIPT = f767-flash.ld
ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT)
ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10
CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS)
CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS)
CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS)
CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS)
CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS)
AFLAGS := $(CFLAGS) -D__ASSEMBLY__
NXFLATLDFLAGS1 = -r -d -warn-common
NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections
LDNXFLATFLAGS = -e main -s 2048

2
boards/arm/stm32f7/nucleo-144/CMakeLists.txt → boards/arm/stm32f7/nucleo-f722ze/CMakeLists.txt
View file

@ -1,5 +1,5 @@
# ##############################################################################
# boards/arm/stm32f7/nucleo-144/CMakeLists.txt
# boards/arm/stm32f7/nucleo-f722ze/CMakeLists.txt
#
# Licensed to the Apache Software Foundation (ASF) under one or more contributor
# license agreements. See the NOTICE file distributed with this work for

112
boards/arm/stm32f7/nucleo-144/Kconfig → boards/arm/stm32f7/nucleo-f722ze/Kconfig
View file

@ -3,7 +3,7 @@
# see the file kconfig-language.txt in the NuttX tools repository.
#
if ARCH_BOARD_NUCLEO_144
if ARCH_BOARD_NUCLEO_F722ZE
config STM32_ROMFS
bool "Automount baked-in ROMFS image"
@ -29,7 +29,7 @@ config STM32_ROMFS_IMAGEFILE
choice
prompt "Select Console wiring."
default NUCLEO_CONSOLE_ARDUINO
default NUCLEO_F722ZE_CONSOLE_ARDUINO
---help---
Select where you will connect the console.
@ -77,196 +77,196 @@ choice
-------- --------- -----
Note: SB13 must be removed to disable Ethernet.
config NUCLEO_CONSOLE_ARDUINO
config NUCLEO_F722ZE_CONSOLE_ARDUINO
bool "Arduino Connector"
select STM32F7_USART6
select USART6_SERIALDRIVER
config NUCLEO_CONSOLE_VIRTUAL
config NUCLEO_F722ZE_CONSOLE_VIRTUAL
bool "Virtual Comport"
select STM32F7_USART3
select USART3_SERIALDRIVER
config NUCLEO_CONSOLE_MORPHO
config NUCLEO_F722ZE_CONSOLE_MORPHO
bool "Morpho Connector"
select STM32F7_UART8
select UART8_SERIALDRIVER
config NUCLEO_CONSOLE_MORPHO_UART4
config NUCLEO_F722ZE_CONSOLE_MORPHO_UART4
bool "Morpho Connector UART4"
select STM32F7_UART4
select UART4_SERIALDRIVER
config NUCLEO_CONSOLE_NONE
config NUCLEO_F722ZE_CONSOLE_NONE
bool "No Console"
endchoice # "Select Console wiring"
config NUCLEO_SPI_TEST
config NUCLEO_F722ZE_SPI_TEST
bool "Enable SPI test"
default n
---help---
Enable Spi test - initialize and configure SPI to send
NUCLEO_SPI_TEST_MESSAGE text. The text is sent on the
NUCLEO_F722ZE_SPI_TEST_MESSAGE text. The text is sent on the
selected SPI Buses with the configured parameters.
Note the CS lines will not be asserted.
if NUCLEO_SPI_TEST
if NUCLEO_F722ZE_SPI_TEST
config NUCLEO_SPI_TEST_MESSAGE
config NUCLEO_F722ZE_SPI_TEST_MESSAGE
string "Text to Send on SPI Bus(es)"
default "Hello World"
depends on NUCLEO_SPI_TEST
depends on NUCLEO_F722ZE_SPI_TEST
---help---
Text to sent on SPI bus(es)
config NUCLEO_SPI1_TEST
config NUCLEO_F722ZE_SPI1_TEST
bool "Test SPI bus 1"
default n
depends on NUCLEO_SPI_TEST
depends on NUCLEO_F722ZE_SPI_TEST
---help---
Enable Spi test - on SPI BUS 1
if NUCLEO_SPI1_TEST
if NUCLEO_F722ZE_SPI1_TEST
config NUCLEO_SPI1_TEST_FREQ
config NUCLEO_F722ZE_SPI1_TEST_FREQ
int "SPI 1 Clock Freq in Hz"
default 1000000
depends on NUCLEO_SPI1_TEST
depends on NUCLEO_F722ZE_SPI1_TEST
---help---
Sets SPI 1 Clock Freq
config NUCLEO_SPI1_TEST_BITS
config NUCLEO_F722ZE_SPI1_TEST_BITS
int "SPI 1 number of bits"
default 8
depends on NUCLEO_SPI1_TEST
depends on NUCLEO_F722ZE_SPI1_TEST
---help---
Sets SPI 1 bit length
choice
prompt "SPI BUS 1 Clock Mode"
default NUCLEO_SPI1_TEST_MODE3
default NUCLEO_F722ZE_SPI1_TEST_MODE3
---help---
Sets SPI 1 clock mode
config NUCLEO_SPI1_TEST_MODE0
config NUCLEO_F722ZE_SPI1_TEST_MODE0
bool "CPOL=0 CPHA=0"
config NUCLEO_SPI1_TEST_MODE1
config NUCLEO_F722ZE_SPI1_TEST_MODE1
bool "CPOL=0 CPHA=1"
config NUCLEO_SPI1_TEST_MODE2
config NUCLEO_F722ZE_SPI1_TEST_MODE2
bool "CPOL=1 CPHA=0"
config NUCLEO_SPI1_TEST_MODE3
config NUCLEO_F722ZE_SPI1_TEST_MODE3
bool "CPOL=1 CPHA=1"
endchoice # "SPI BUS 1 Clock Mode"
endif # NUCLEO_SPI1_TEST
endif # NUCLEO_F722ZE_SPI1_TEST
config NUCLEO_SPI2_TEST
config NUCLEO_F722ZE_SPI2_TEST
bool "Test SPI bus 2"
default n
depends on NUCLEO_SPI_TEST
depends on NUCLEO_F722ZE_SPI_TEST
---help---
Enable Spi test - on SPI BUS 2
if NUCLEO_SPI2_TEST
if NUCLEO_F722ZE_SPI2_TEST
config NUCLEO_SPI2_TEST_FREQ
config NUCLEO_F722ZE_SPI2_TEST_FREQ
int "SPI 2 Clock Freq in Hz"
default 12000000
depends on NUCLEO_SPI2_TEST
depends on NUCLEO_F722ZE_SPI2_TEST
---help---
Sets SPI 2 Clock Freq
config NUCLEO_SPI2_TEST_BITS
config NUCLEO_F722ZE_SPI2_TEST_BITS
int "SPI 2 number of bits"
default 8
depends on NUCLEO_SPI2_TEST
depends on NUCLEO_F722ZE_SPI2_TEST
---help---
Sets SPI 2 bit length
choice
prompt "SPI BUS 2 Clock Mode"
default NUCLEO_SPI2_TEST_MODE3
default NUCLEO_F722ZE_SPI2_TEST_MODE3
---help---
Sets SPI 2 clock mode
config NUCLEO_SPI2_TEST_MODE0
config NUCLEO_F722ZE_SPI2_TEST_MODE0
bool "CPOL=0 CPHA=0"
config NUCLEO_SPI2_TEST_MODE1
config NUCLEO_F722ZE_SPI2_TEST_MODE1
bool "CPOL=0 CPHA=1"
config NUCLEO_SPI2_TEST_MODE2
config NUCLEO_F722ZE_SPI2_TEST_MODE2
bool "CPOL=1 CPHA=0"
config NUCLEO_SPI2_TEST_MODE3
config NUCLEO_F722ZE_SPI2_TEST_MODE3
bool "CPOL=1 CPHA=1"
endchoice # "SPI BUS 2 Clock Mode"
endif # NUCLEO_SPI2_TEST
endif # NUCLEO_F722ZE_SPI2_TEST
config NUCLEO_SPI3_TEST
config NUCLEO_F722ZE_SPI3_TEST
bool "Test SPI bus 3"
default n
depends on NUCLEO_SPI_TEST
depends on NUCLEO_F722ZE_SPI_TEST
---help---
Enable Spi test - on SPI BUS 3
if NUCLEO_SPI3_TEST
if NUCLEO_F722ZE_SPI3_TEST
config NUCLEO_SPI3_TEST_FREQ
config NUCLEO_F722ZE_SPI3_TEST_FREQ
int "SPI 3 Clock Freq in Hz"
default 40000000
depends on NUCLEO_SPI3_TEST
depends on NUCLEO_F722ZE_SPI3_TEST
---help---
Sets SPI 3 Clock Freq
config NUCLEO_SPI3_TEST_BITS
config NUCLEO_F722ZE_SPI3_TEST_BITS
int "SPI 3 number of bits"
default 8
depends on NUCLEO_SPI3_TEST
depends on NUCLEO_F722ZE_SPI3_TEST
---help---
Sets SPI 3 bit length
choice
prompt "SPI BUS 3 Clock Mode"
default NUCLEO_SPI3_TEST_MODE3
default NUCLEO_F722ZE_SPI3_TEST_MODE3
---help---
Sets SPI 3 clock mode
config NUCLEO_SPI3_TEST_MODE0
config NUCLEO_F722ZE_SPI3_TEST_MODE0
bool "CPOL=0 CPHA=0"
config NUCLEO_SPI3_TEST_MODE1
config NUCLEO_F722ZE_SPI3_TEST_MODE1
bool "CPOL=0 CPHA=1"
config NUCLEO_SPI3_TEST_MODE2
config NUCLEO_F722ZE_SPI3_TEST_MODE2
bool "CPOL=1 CPHA=0"
config NUCLEO_SPI3_TEST_MODE3
config NUCLEO_F722ZE_SPI3_TEST_MODE3
bool "CPOL=1 CPHA=1"
endchoice # "SPI BUS 3 Clock Mode"
endif # NUCLEO_SPI3_TEST
endif # NUCLEO_SPI_TEST
endif # NUCLEO_F722ZE_SPI3_TEST
endif # NUCLEO_F722ZE_SPI_TEST
choice
prompt "CAN1 pins selection"
default NUCLEO_CAN1_MAP_PD0PD1
default NUCLEO_F722ZE_CAN1_MAP_PD0PD1
depends on STM32F7_CAN1
config NUCLEO_144_CAN1_MAP_D14D15
config NUCLEO_F722ZE_F722ZE_CAN1_MAP_D14D15
bool "CAN1_TX=D14 CAN1_RX=D15"
config NUCLEO_CAN1_MAP_PD0PD1
config NUCLEO_F722ZE_CAN1_MAP_PD0PD1
bool "CAN1_RX=PD0 CAN1_TX=PD1"
endchoice # CAN1 pins selection
endif # ARCH_BOARD_NUCLEO_144
endif # ARCH_BOARD_NUCLEO_F722ZE

8
boards/arm/stm32f7/nucleo-144/configs/f722-can/defconfig → boards/arm/stm32f7/nucleo-f722ze/configs/can/defconfig
View file

@ -8,8 +8,8 @@
# CONFIG_ARCH_FPU is not set
# CONFIG_STM32F7_USE_LEGACY_PINMAP is not set
CONFIG_ARCH="arm"
CONFIG_ARCH_BOARD="nucleo-144"
CONFIG_ARCH_BOARD_NUCLEO_144=y
CONFIG_ARCH_BOARD="nucleo-f722ze"
CONFIG_ARCH_BOARD_NUCLEO_F722ZE=y
CONFIG_ARCH_BUTTONS=y
CONFIG_ARCH_CHIP="stm32f7"
CONFIG_ARCH_CHIP_STM32F722ZE=y
@ -35,8 +35,8 @@ CONFIG_NSH_BUILTIN_APPS=y
CONFIG_NSH_FILEIOSIZE=512
CONFIG_NSH_LINELEN=64
CONFIG_NSH_READLINE=y
CONFIG_NUCLEO_144_CAN1_MAP_D14D15=y
CONFIG_NUCLEO_CONSOLE_VIRTUAL=y
CONFIG_NUCLEO_F722ZE_CAN1_MAP_D14D15=y
CONFIG_NUCLEO_F722ZE_CONSOLE_VIRTUAL=y
CONFIG_PREALLOC_TIMERS=4
CONFIG_RAM_SIZE=245760
CONFIG_RAM_START=0x20010000

8
boards/arm/stm32f7/nucleo-144/configs/f722-cansock/defconfig → boards/arm/stm32f7/nucleo-f722ze/configs/cansock/defconfig
View file

@ -10,8 +10,8 @@
# CONFIG_NET_IPv4 is not set
# CONFIG_STM32F7_USE_LEGACY_PINMAP is not set
CONFIG_ARCH="arm"
CONFIG_ARCH_BOARD="nucleo-144"
CONFIG_ARCH_BOARD_NUCLEO_144=y
CONFIG_ARCH_BOARD="nucleo-f722ze"
CONFIG_ARCH_BOARD_NUCLEO_F722ZE=y
CONFIG_ARCH_BUTTONS=y
CONFIG_ARCH_CHIP="stm32f7"
CONFIG_ARCH_CHIP_STM32F722ZE=y
@ -43,8 +43,8 @@ CONFIG_NSH_BUILTIN_APPS=y
CONFIG_NSH_FILEIOSIZE=512
CONFIG_NSH_LINELEN=64
CONFIG_NSH_READLINE=y
CONFIG_NUCLEO_144_CAN1_MAP_D14D15=y
CONFIG_NUCLEO_CONSOLE_VIRTUAL=y
CONFIG_NUCLEO_F722ZE_CAN1_MAP_D14D15=y
CONFIG_NUCLEO_F722ZE_CONSOLE_VIRTUAL=y
CONFIG_PREALLOC_TIMERS=4
CONFIG_RAM_SIZE=245760
CONFIG_RAM_START=0x20010000

6
boards/arm/stm32f7/nucleo-144/configs/f722-composite/defconfig → boards/arm/stm32f7/nucleo-f722ze/configs/composite/defconfig
View file

@ -8,8 +8,8 @@
# CONFIG_ARCH_FPU is not set
# CONFIG_STM32F7_USE_LEGACY_PINMAP is not set
CONFIG_ARCH="arm"
CONFIG_ARCH_BOARD="nucleo-144"
CONFIG_ARCH_BOARD_NUCLEO_144=y
CONFIG_ARCH_BOARD="nucleo-f722ze"
CONFIG_ARCH_BOARD_NUCLEO_F722ZE=y
CONFIG_ARCH_BUTTONS=y
CONFIG_ARCH_CHIP="stm32f7"
CONFIG_ARCH_CHIP_STM32F722ZE=y
@ -57,7 +57,7 @@ CONFIG_NSH_BUILTIN_APPS=y
CONFIG_NSH_FILEIOSIZE=512
CONFIG_NSH_LINELEN=64
CONFIG_NSH_READLINE=y
CONFIG_NUCLEO_CONSOLE_VIRTUAL=y
CONFIG_NUCLEO_F722ZE_CONSOLE_VIRTUAL=y
CONFIG_PREALLOC_TIMERS=4
CONFIG_RAM_SIZE=245760
CONFIG_RAM_START=0x20010000

4
boards/arm/stm32f7/nucleo-144/configs/f722-nsh/defconfig → boards/arm/stm32f7/nucleo-f722ze/configs/nsh/defconfig
View file

@ -10,8 +10,8 @@
# CONFIG_NSH_DISABLE_PS is not set
# CONFIG_STM32F7_USE_LEGACY_PINMAP is not set
CONFIG_ARCH="arm"
CONFIG_ARCH_BOARD="nucleo-144"
CONFIG_ARCH_BOARD_NUCLEO_144=y
CONFIG_ARCH_BOARD="nucleo-f722ze"
CONFIG_ARCH_BOARD_NUCLEO_F722ZE=y
CONFIG_ARCH_BUTTONS=y
CONFIG_ARCH_CHIP="stm32f7"
CONFIG_ARCH_CHIP_STM32F722ZE=y

22
boards/arm/stm32f7/nucleo-144/include/board.h → boards/arm/stm32f7/nucleo-f722ze/include/board.h
View file

@ -1,5 +1,5 @@
/****************************************************************************
* boards/arm/stm32f7/nucleo-144/include/board.h
* boards/arm/stm32f7/nucleo-f722ze/include/board.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
@ -18,8 +18,8 @@
*
****************************************************************************/
#ifndef __BOARDS_ARM_STM32F7_NUCLEO_144_INCLUDE_BOARD_H
#define __BOARDS_ARM_STM32F7_NUCLEO_144_INCLUDE_BOARD_H
#ifndef __BOARDS_ARM_STM32F7_NUCLEO_F722ZE_INCLUDE_BOARD_H
#define __BOARDS_ARM_STM32F7_NUCLEO_F722ZE_INCLUDE_BOARD_H
/****************************************************************************
* Included Files
@ -39,7 +39,7 @@
/* Clocking *****************************************************************/
/* The Nucleo-144 board provides the following clock sources:
/* The Nucleo-f722ze board provides the following clock sources:
*
* MCO: 8 MHz from MCO output of ST-LINK is used as input clock
* X2: 32.768 KHz crystal for LSE
@ -256,7 +256,7 @@
/* LED definitions **********************************************************/
/* The Nucleo-144 board has numerous LEDs but only three, LD1 a Green LED,
/* The Nucleo-f722ze board has numerous LEDs but only three, LD1 a Green LED,
* LD2 a Blue LED and LD3 a Red LED, that can be controlled by software.
* The following definitions assume the default Solder Bridges are installed.
*
@ -384,7 +384,7 @@
#define GPIO_TIM3_CH3OUT (GPIO_TIM3_CH3OUT_2|GPIO_SPEED_50MHz)
#define GPIO_TIM3_CH4OUT (GPIO_TIM3_CH4OUT_1|GPIO_SPEED_50MHz)
#if defined(CONFIG_NUCLEO_CONSOLE_ARDUINO)
#if defined(CONFIG_NUCLEO_F722ZE_CONSOLE_ARDUINO)
/* USART6:
*
@ -408,12 +408,12 @@
* Use USART3 and the USB virtual COM port
*/
#if defined(CONFIG_NUCLEO_CONSOLE_VIRTUAL)
#if defined(CONFIG_NUCLEO_F722ZE_CONSOLE_VIRTUAL)
# define GPIO_USART3_RX (GPIO_USART3_RX_3|GPIO_SPEED_100MHz)
# define GPIO_USART3_TX (GPIO_USART3_TX_3|GPIO_SPEED_100MHz)
#endif
#if defined(CONFIG_NUCLEO_CONSOLE_MORPHO_UART4)
#if defined(CONFIG_NUCLEO_F722ZE_CONSOLE_MORPHO_UART4)
/* UART4:
*
@ -538,10 +538,10 @@
/* CAN Bus */
#ifdef CONFIG_NUCLEO_CAN1_MAP_PD0PD1
#ifdef CONFIG_NUCLEO_F722ZE_CAN1_MAP_PD0PD1
# define GPIO_CAN1_TX (GPIO_CAN1_TX_3|GPIO_SPEED_50MHz) /* PD1 */
# define GPIO_CAN1_RX (GPIO_CAN1_RX_3|GPIO_SPEED_50MHz) /* PD0 */
#elif CONFIG_NUCLEO_144_CAN1_MAP_D14D15
#elif CONFIG_NUCLEO_F722ZE_CAN1_MAP_D14D15
# define GPIO_CAN1_TX (GPIO_CAN1_TX_2|GPIO_SPEED_50MHz) /* PB9 */
# define GPIO_CAN1_RX (GPIO_CAN1_RX_2|GPIO_SPEED_50MHz) /* PB8 */
#endif
@ -565,4 +565,4 @@
#define GPIO_OTGFS_DP (GPIO_OTGFS_DP_0|GPIO_SPEED_100MHz)
#define GPIO_OTGFS_ID (GPIO_OTGFS_ID_0|GPIO_SPEED_100MHz)
#endif /* __BOARDS_ARM_STM32F7_NUCLEO_144_INCLUDE_BOARD_H */
#endif /* __BOARDS_ARM_STM32F7_NUCLEO_F722ZE_INCLUDE_BOARD_H */

4
boards/arm/stm32f7/nucleo-144/configs/f722-can/Make.defs → boards/arm/stm32f7/nucleo-f722ze/scripts/Make.defs
View file

@ -1,5 +1,5 @@
############################################################################
# boards/arm/stm32f7/nucleo-144/configs/f722-can/Make.defs
# boards/arm/stm32f7/nucleo-f722ze/scriptsMake.defs
#
# Licensed to the Apache Software Foundation (ASF) under one or more
# contributor license agreements. See the NOTICE file distributed with
@ -22,7 +22,7 @@ include $(TOPDIR)/.config
include $(TOPDIR)/tools/Config.mk
include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs
LDSCRIPT = f722-flash.ld
LDSCRIPT = flash.ld
ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT)
ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10

2
boards/arm/stm32f7/nucleo-144/scripts/f722-flash.ld → boards/arm/stm32f7/nucleo-f722ze/scripts/flash.ld
View file

@ -1,5 +1,5 @@
/****************************************************************************
* boards/arm/stm32f7/nucleo-144/scripts/f722-flash.ld
* boards/arm/stm32f7/nucleo-f722ze/scripts/flash.ld
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with

2
boards/arm/stm32f7/nucleo-144/scripts/kernel-space.ld → boards/arm/stm32f7/nucleo-f722ze/scripts/kernel-space.ld
View file

@ -1,5 +1,5 @@
/****************************************************************************
* boards/arm/stm32f7/nucleo-144/scripts/kernel-space.ld
* boards/arm/stm32f7/nucleo-f722ze/scripts/kernel-space.ld
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with

2
boards/arm/stm32f7/nucleo-144/scripts/user-space.ld → boards/arm/stm32f7/nucleo-f722ze/scripts/user-space.ld
View file

@ -1,5 +1,5 @@
/****************************************************************************
* boards/arm/stm32f7/nucleo-144/scripts/user-space.ld
* boards/arm/stm32f7/nucleo-f722ze/scripts/user-space.ld
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with

9
boards/arm/stm32f7/nucleo-144/src/CMakeLists.txt → boards/arm/stm32f7/nucleo-f722ze/src/CMakeLists.txt
View file

@ -1,5 +1,5 @@
# ##############################################################################
# boards/arm/stm32f7/nucleo-144/src/CMakeLists.txt
# boards/arm/stm32f7/nucleo-f722ze/src/CMakeLists.txt
#
# Licensed to the Apache Software Foundation (ASF) under one or more contributor
# license agreements. See the NOTICE file distributed with this work for
@ -89,10 +89,5 @@ endif()
target_sources(board PRIVATE ${SRCS})
if(CONFIG_ARCH_CHIP_STM32F722ZE)
set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/f722-flash.ld")
elseif(CONFIG_ARCH_CHIP_STM32F746ZG)
set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/f746-flash.ld")
elseif(CONFIG_ARCH_CHIP_STM32F767ZI)
set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/f767-flash.ld")
set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/flash.ld")
endif()

2
boards/arm/stm32f7/nucleo-144/src/Make.defs → boards/arm/stm32f7/nucleo-f722ze/src/Make.defs
View file

@ -1,5 +1,5 @@
############################################################################
# boards/arm/stm32f7/nucleo-144/src/Make.defs
# boards/arm/stm32f7/nucleo-f722ze/src/Make.defs
#
# Licensed to the Apache Software Foundation (ASF) under one or more
# contributor license agreements. See the NOTICE file distributed with

353
boards/arm/stm32f7/nucleo-f722ze/src/nucleo-f722ze.h Normal file
View file

@ -0,0 +1,353 @@
/****************************************************************************
* boards/arm/stm32f7/nucleo-f722ze/src/nucleo-f722ze.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __BOARDS_ARM_STM32F7_NUCLEO_F722ZE_SRC_NUCLEO_F722ZE_H
#define __BOARDS_ARM_STM32F7_NUCLEO_F722ZE_SRC_NUCLEO_F722ZE_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/compiler.h>
#include <stdint.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Configuration ************************************************************/
/* procfs File System */
#ifdef CONFIG_FS_PROCFS
# ifdef CONFIG_NSH_PROC_MOUNTPOINT
# define STM32_PROCFS_MOUNTPOINT CONFIG_NSH_PROC_MOUNTPOINT
# else
# define STM32_PROCFS_MOUNTPOINT "/proc"
# endif
#endif
/* nucleo-f722ze GPIO Pin Definitions ***************************************/
/* LED
*
* The nucleo-f722ze board has numerous LEDs but only three, LD1 a Green LED,
* LD2 a Blue LED and LD3 a Red LED, that can be controlled by software.
* The following definitions assume the default Solder Bridges are installed.
*/
#define GPIO_LD1 (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_50MHz | GPIO_OUTPUT_CLEAR | \
GPIO_PORTB | GPIO_PIN0)
#define GPIO_LD2 (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_50MHz | GPIO_OUTPUT_CLEAR | \
GPIO_PORTB | GPIO_PIN7)
#define GPIO_LD3 (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_50MHz | GPIO_OUTPUT_CLEAR | \
GPIO_PORTB | GPIO_PIN14)
#define GPIO_LED_GREEN GPIO_LD1
#define GPIO_LED_BLUE GPIO_LD2
#define GPIO_LED_RED GPIO_LD3
#define LED_DRIVER_PATH "/dev/userleds"
/* BUTTONS
*
* The Blue pushbutton B1, labeled "User", is connected to GPIO PC13.
* A high value will be sensed when the button is depressed.
* Note:
* 1) That the EXTI is included in the definition to enable an interrupt
* on this IO.
* 2) The following definitions assume the default Solder Bridges are
* installed.
*/
#define GPIO_BTN_USER (GPIO_INPUT | GPIO_FLOAT | GPIO_EXTI | GPIO_PORTC | GPIO_PIN13)
/* SPI **********************************************************************/
#define GPIO_SPI_CS (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_50MHz | \
GPIO_OUTPUT_SET)
#define GPIO_SPI1_CS0 (GPIO_SPI_CS | GPIO_PORTA | GPIO_PIN15)
#define GPIO_SPI1_CS1 (GPIO_SPI_CS | GPIO_PORTC | GPIO_PIN15)
#define GPIO_SPI1_CS2 (GPIO_SPI_CS | GPIO_PORTC | GPIO_PIN14)
#define GPIO_SPI1_CS3 (GPIO_SPI_CS | GPIO_PORTC | GPIO_PIN2)
#define GPIO_SPI2_CS0 (GPIO_SPI_CS | GPIO_PORTD | GPIO_PIN7)
#define GPIO_SPI2_CS1 (GPIO_SPI_CS | GPIO_PORTG | GPIO_PIN1)
#define GPIO_SPI2_CS2 (GPIO_SPI_CS | GPIO_PORTG | GPIO_PIN2)
#define GPIO_SPI2_CS3 (GPIO_SPI_CS | GPIO_PORTG | GPIO_PIN3)
#define GPIO_SPI3_CS0 (GPIO_SPI_CS | GPIO_PORTG | GPIO_PIN4)
#define GPIO_SPI3_CS1 (GPIO_SPI_CS | GPIO_PORTG | GPIO_PIN5)
#define GPIO_SPI3_CS2 (GPIO_SPI_CS | GPIO_PORTG | GPIO_PIN6)
#define GPIO_SPI3_CS3 (GPIO_SPI_CS | GPIO_PORTG | GPIO_PIN7)
#if defined(CONFIG_STM32F7_SDMMC1) || defined(CONFIG_STM32F7_SDMMC2)
# define HAVE_SDIO
#endif
#if defined(CONFIG_DISABLE_MOUNTPOINT) || !defined(CONFIG_MMCSD_SDIO)
# undef HAVE_SDIO
#endif
#define SDIO_SLOTNO 0 /* Only one slot */
#ifdef HAVE_SDIO
# if defined(CONFIG_STM32F7_SDMMC1)
# define GPIO_SDMMC1_NCD (GPIO_INPUT|GPIO_FLOAT|GPIO_EXTI | GPIO_PORTC | GPIO_PIN6)
# endif
# if defined(CONFIG_NSH_MMCSDSLOTNO) && (CONFIG_NSH_MMCSDSLOTNO != 0)
# warning "Only one MMC/SD slot, slot 0"
# define CONFIG_NSH_MMCSDSLOTNO SDIO_SLOTNO
# endif
# if defined(CONFIG_NSH_MMCSDMINOR)
# define SDIO_MINOR CONFIG_NSH_MMCSDMINOR
# else
# define SDIO_MINOR 0
# endif
#endif
/* USB OTG FS
*
* PA9 OTG_FS_VBUS VBUS sensing (also connected to the green LED)
* PC0 OTG_FS_PowerSwitchOn
* PD5 OTG_FS_Overcurrent
*/
#define GPIO_OTGFS_VBUS (GPIO_INPUT|GPIO_FLOAT|GPIO_SPEED_100MHz|\
GPIO_OPENDRAIN|GPIO_PORTA|GPIO_PIN9)
#define GPIO_OTGFS_PWRON (GPIO_OUTPUT|GPIO_FLOAT|GPIO_SPEED_100MHz|\
GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN6)
#ifdef CONFIG_USBHOST
# define GPIO_OTGFS_OVER (GPIO_INPUT|GPIO_EXTI|GPIO_FLOAT|\
GPIO_SPEED_100MHz|GPIO_PUSHPULL|\
GPIO_PORTG|GPIO_PIN7)
#else
# define GPIO_OTGFS_OVER (GPIO_INPUT|GPIO_FLOAT|GPIO_SPEED_100MHz|\
GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN7)
#endif
/* GPIO pins used by the GPIO Subsystem */
#define BOARD_NGPIOIN 4 /* Amount of GPIO Input pins */
#if defined(CONFIG_STM32F7_TIM1_CH1NOUT) && defined (CONFIG_STM32F7_TIM1_CH2NOUT)
#define BOARD_NGPIOOUT 8 /* Amount of GPIO Output pins */
#elif defined(CONFIG_STM32F7_TIM1_CH1NOUT) || defined (CONFIG_STM32F7_TIM1_CH2NOUT)
#define BOARD_NGPIOOUT 9 /* Amount of GPIO Output pins */
#else
#define BOARD_NGPIOOUT 10 /* Amount of GPIO Output pins */
#endif
#define BOARD_NGPIOINT 1 /* Amount of GPIO Input w/ Interruption pins */
#define GPIO_INT1 (GPIO_INPUT | GPIO_FLOAT | GPIO_PORTB | GPIO_PIN2)
#define GPIO_IN1 (GPIO_INPUT | GPIO_FLOAT | GPIO_PORTE | GPIO_PIN7)
#define GPIO_IN2 (GPIO_INPUT | GPIO_FLOAT | GPIO_PORTE | GPIO_PIN12)
#define GPIO_IN3 (GPIO_INPUT | GPIO_FLOAT | GPIO_PORTE | GPIO_PIN14)
#define GPIO_IN4 (GPIO_INPUT | GPIO_FLOAT | GPIO_PORTE | GPIO_PIN15)
#define GPIO_OUT1 (GPIO_OUTPUT | GPIO_SPEED_50MHz | \
GPIO_OUTPUT_SET | GPIO_PORTE | GPIO_PIN4)
#define GPIO_OUT2 (GPIO_OUTPUT | GPIO_SPEED_50MHz | \
GPIO_OUTPUT_SET | GPIO_PORTE | GPIO_PIN5)
#define GPIO_OUT3 (GPIO_OUTPUT | GPIO_SPEED_50MHz | \
GPIO_OUTPUT_SET | GPIO_PORTE | GPIO_PIN6)
#define GPIO_OUT4 (GPIO_OUTPUT | GPIO_SPEED_50MHz | \
GPIO_OUTPUT_SET | GPIO_PORTA |GPIO_PIN5)
#define GPIO_OUT5 (GPIO_OUTPUT | GPIO_SPEED_50MHz | \
GPIO_OUTPUT_SET | GPIO_PORTF | GPIO_PIN12)
#if !defined(CONFIG_STM32F7_TIM1_CH1NOUT)
#define GPIO_OUT6 (GPIO_OUTPUT | GPIO_SPEED_50MHz | \
GPIO_OUTPUT_SET | GPIO_PORTE | GPIO_PIN8)
#endif
#if !defined(CONFIG_STM32F7_TIM1_CH2NOUT)
#define GPIO_OUT7 (GPIO_OUTPUT | GPIO_SPEED_50MHz | \
GPIO_OUTPUT_SET | GPIO_PORTE | GPIO_PIN10)
#endif
/****************************************************************************
* Public Data
****************************************************************************/
#ifndef __ASSEMBLY__
/****************************************************************************
* Public Functions Definitions
****************************************************************************/
/****************************************************************************
* Name: stm32_bringup
*
* Description:
* Perform architecture specific initialization
*
* CONFIG_BOARDCTL=y:
* If CONFIG_NSH_ARCHINITIALIZE=y:
* Called from the NSH library (or other application)
* Otherwise, assumed to be called from some other application.
*
* Otherwise CONFIG_BOARD_LATE_INITIALIZE=y:
* Called from board_late_initialize().
*
* Otherwise, bad news: Never called
*
****************************************************************************/
int stm32_bringup(void);
/****************************************************************************
* Name: stm32_spidev_initialize
*
* Description:
* Called to configure SPI chip select GPIO pins for the nucleo-f722ze
* board.
*
****************************************************************************/
#if defined(CONFIG_SPI)
void stm32_spidev_initialize(void);
#endif
/****************************************************************************
* Name: stm32_spidev_bus_test
*
* Description:
* Called to create the defined SPI buses and test them by initializing
* them and sending the NUCLEO_SPI_TEST (no chip select).
*
****************************************************************************/
#if defined(CONFIG_NUCLEO_F722ZE_SPI_TEST)
int stm32_spidev_bus_test(void);
#endif
/****************************************************************************
* Name: stm32_dma_alloc_init
*
* Description:
* Called to create a FAT DMA allocator
*
* Returned Value:
* 0 on success or -ENOMEM
*
****************************************************************************/
void stm32_dma_alloc_init(void);
#if defined (CONFIG_FAT_DMAMEMORY)
int stm32_dma_alloc_init(void);
#endif
/****************************************************************************
* Name: stm32_sdio_initialize
*
* Description:
* Called at application startup time to initialize the SCMMC
* functionality.
*
****************************************************************************/
#ifdef CONFIG_MMCSD
int stm32_sdio_initialize(void);
#endif
/****************************************************************************
* Name: stm32_usbinitialize
*
* Description:
* Called from stm32_usbinitialize very early in inialization to setup
* USB-related GPIO pins for the nucleo-f722ze board.
*
****************************************************************************/
#ifdef CONFIG_STM32F7_OTGFS
void stm32_usbinitialize(void);
#endif
/****************************************************************************
* Name: stm32_pwm_setup
*
* Description:
* Initialize PWM and register the PWM device.
*
****************************************************************************/
#ifdef CONFIG_PWM
int stm32_pwm_setup(void);
#endif
/****************************************************************************
* Name: stm32_adc_setup
*
* Description:
* Initialize ADC and register the ADC driver.
*
****************************************************************************/
#ifdef CONFIG_ADC
int stm32_adc_setup(void);
#endif
/****************************************************************************
* Name: stm32_bbsram_int
****************************************************************************/
#ifdef CONFIG_STM32F7_BBSRAM
int stm32_bbsram_int(void);
#endif
/****************************************************************************
* Name: stm32_qencoder_initialize
****************************************************************************/
#ifdef CONFIG_SENSORS_QENCODER
int stm32_qencoder_initialize(const char *devpath, int timer);
#endif
/****************************************************************************
* Name: stm32_can_setup
****************************************************************************/
#ifdef CONFIG_STM32F7_CAN_CHARDRIVER
int stm32_can_setup(void);
#endif
/****************************************************************************
* Name: stm32_cansock_setup
****************************************************************************/
#ifdef CONFIG_STM32F7_CAN_SOCKET
int stm32_cansock_setup(void);
#endif
/****************************************************************************
* Name: stm32f7_gpio_initialize
****************************************************************************/
#ifdef CONFIG_DEV_GPIO
int stm32_gpio_initialize(void);
#endif
#endif /* __ASSEMBLY__ */
#endif /* __BOARDS_ARM_STM32F7_NUCLEO_F722ZE_SRC_NUCLEO_F722ZE_H */

4
boards/arm/stm32f7/nucleo-144/src/stm32_adc.c → boards/arm/stm32f7/nucleo-f722ze/src/stm32_adc.c
View file

@ -1,5 +1,5 @@
/****************************************************************************
* boards/arm/stm32f7/nucleo-144/src/stm32_adc.c
* boards/arm/stm32f7/nucleo-f722ze/src/stm32_adc.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
@ -34,7 +34,7 @@
#include "chip.h"
#include "stm32_gpio.h"
#include "stm32_adc.h"
#include "nucleo-144.h"
#include "nucleo-f722ze.h"
#ifdef CONFIG_ADC

4
boards/arm/stm32f7/nucleo-144/src/stm32_appinitialize.c → boards/arm/stm32f7/nucleo-f722ze/src/stm32_appinitialize.c
View file

@ -1,5 +1,5 @@
/****************************************************************************
* boards/arm/stm32f7/nucleo-144/src/stm32_appinitialize.c
* boards/arm/stm32f7/nucleo-f722ze/src/stm32_appinitialize.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
@ -25,7 +25,7 @@
#include <nuttx/config.h>
#include <sys/types.h>
#include "nucleo-144.h"
#include "nucleo-f722ze.h"
#ifdef CONFIG_BOARDCTL

4
boards/arm/stm32f7/nucleo-144/src/stm32_autoleds.c → boards/arm/stm32f7/nucleo-f722ze/src/stm32_autoleds.c
View file

@ -1,5 +1,5 @@
/****************************************************************************
* boards/arm/stm32f7/nucleo-144/src/stm32_autoleds.c
* boards/arm/stm32f7/nucleo-f722ze/src/stm32_autoleds.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
@ -33,7 +33,7 @@
#include <arch/board/board.h>
#include "stm32_gpio.h"
#include "nucleo-144.h"
#include "nucleo-f722ze.h"
#ifdef CONFIG_ARCH_LEDS
/****************************************************************************

4
boards/arm/stm32f7/nucleo-144/src/stm32_bbsram.c → boards/arm/stm32f7/nucleo-f722ze/src/stm32_bbsram.c
View file

@ -1,5 +1,5 @@
/****************************************************************************
* boards/arm/stm32f7/nucleo-144/src/stm32_bbsram.c
* boards/arm/stm32f7/nucleo-f722ze/src/stm32_bbsram.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
@ -43,7 +43,7 @@
#include "arm_internal.h"
#include "stm32_bbsram.h"
#include "nucleo-144.h"
#include "nucleo-f722ze.h"
#ifdef CONFIG_STM32F7_BBSRAM

4
boards/arm/stm32f7/nucleo-144/src/stm32_boot.c → boards/arm/stm32f7/nucleo-f722ze/src/stm32_boot.c
View file

@ -1,5 +1,5 @@
/****************************************************************************
* boards/arm/stm32f7/nucleo-144/src/stm32_boot.c
* boards/arm/stm32f7/nucleo-f722ze/src/stm32_boot.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
@ -30,7 +30,7 @@
#include <arch/board/board.h>
#include "arm_internal.h"
#include "nucleo-144.h"
#include "nucleo-f722ze.h"
/****************************************************************************
* Public Functions

6
boards/arm/stm32f7/nucleo-144/src/stm32_bringup.c → boards/arm/stm32f7/nucleo-f722ze/src/stm32_bringup.c
View file

@ -1,5 +1,5 @@
/****************************************************************************
* boards/arm/stm32f7/nucleo-144/src/stm32_bringup.c
* boards/arm/stm32f7/nucleo-f722ze/src/stm32_bringup.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
@ -29,7 +29,7 @@
#include <syslog.h>
#include <stdio.h>
#include "nucleo-144.h"
#include "nucleo-f722ze.h"
#include <nuttx/fs/fs.h>
#include <nuttx/i2c/i2c_master.h>
#include <nuttx/kmalloc.h>
@ -141,7 +141,7 @@ int stm32_bringup(void)
}
#endif
#if defined(CONFIG_NUCLEO_SPI_TEST)
#if defined(CONFIG_NUCLEO_F722ZE_SPI_TEST)
/* Create SPI interfaces */
ret = stm32_spidev_bus_test();

4
boards/arm/stm32f7/nucleo-144/src/stm32_buttons.c → boards/arm/stm32f7/nucleo-f722ze/src/stm32_buttons.c
View file

@ -1,5 +1,5 @@
/****************************************************************************
* boards/arm/stm32f7/nucleo-144/src/stm32_buttons.c
* boards/arm/stm32f7/nucleo-f722ze/src/stm32_buttons.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
@ -33,7 +33,7 @@
#include <arch/board/board.h>
#include "stm32_gpio.h"
#include "nucleo-144.h"
#include "nucleo-f722ze.h"
#ifdef CONFIG_ARCH_BUTTONS

4
boards/arm/stm32f7/nucleo-144/src/stm32_can.c → boards/arm/stm32f7/nucleo-f722ze/src/stm32_can.c
View file

@ -1,5 +1,5 @@
/****************************************************************************
* boards/arm/stm32f7/nucleo-144/src/stm32_can.c
* boards/arm/stm32f7/nucleo-f722ze/src/stm32_can.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
@ -31,7 +31,7 @@
#include <nuttx/can/can.h>
#include "stm32_can.h"
#include "nucleo-144.h"
#include "nucleo-f722ze.h"
#ifdef CONFIG_CAN

2
boards/arm/stm32f7/nucleo-144/src/stm32_cansock.c → boards/arm/stm32f7/nucleo-f722ze/src/stm32_cansock.c
View file

@ -1,5 +1,5 @@
/****************************************************************************
* boards/arm/stm32f7/nucleo-144/src/stm32_cansock.c
* boards/arm/stm32f7/nucleo-f722ze/src/stm32_cansock.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with

2
boards/arm/stm32f7/nucleo-144/src/stm32_composite.c → boards/arm/stm32f7/nucleo-f722ze/src/stm32_composite.c
View file

@ -1,5 +1,5 @@
/****************************************************************************
* boards/arm/stm32f7/nucleo-144/src/stm32_composite.c
* boards/arm/stm32f7/nucleo-f722ze/src/stm32_composite.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with

4
boards/arm/stm32f7/nucleo-144/src/stm32_dma_alloc.c → boards/arm/stm32f7/nucleo-f722ze/src/stm32_dma_alloc.c
View file

@ -1,5 +1,5 @@
/****************************************************************************
* boards/arm/stm32f7/nucleo-144/src/stm32_dma_alloc.c
* boards/arm/stm32f7/nucleo-f722ze/src/stm32_dma_alloc.c
*
* Copyright (C) 2016 PX4 Development Team. All rights reserved.
*
@ -42,7 +42,7 @@
#include <errno.h>
#include <nuttx/mm/gran.h>
#include "nucleo-144.h"
#include "nucleo-f722ze.h"
#if defined(CONFIG_FAT_DMAMEMORY)

6
boards/arm/stm32f7/nucleo-144/src/stm32_gpio.c → boards/arm/stm32f7/nucleo-f722ze/src/stm32_gpio.c
View file

@ -1,5 +1,5 @@
/****************************************************************************
* boards/arm/stm32f7/nucleo-144/src/stm32_gpio.c
* boards/arm/stm32f7/nucleo-f722ze/src/stm32_gpio.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
@ -36,7 +36,7 @@
#include "chip.h"
#include "stm32_gpio.h"
#include "nucleo-144.h"
#include "nucleo-f722ze.h"
#if defined(CONFIG_DEV_GPIO) && !defined(CONFIG_GPIO_LOWER_HALF)
@ -126,7 +126,7 @@ static const uint32_t g_gpiooutputs[BOARD_NGPIOOUT] =
#if !defined(CONFIG_STM32F7_TIM1_CH1NOUT)
GPIO_OUT6,
#endif
#if !defined(CONFIG_STM32F7_TIM1_CH2NOUT)
#if !defined(CONFIG_STM32F7_TIM1_CH2NOUT)
GPIO_OUT7,
#endif
};

4
boards/arm/stm32f7/nucleo-144/src/stm32_pwm.c → boards/arm/stm32f7/nucleo-f722ze/src/stm32_pwm.c
View file

@ -1,5 +1,5 @@
/****************************************************************************
* boards/arm/stm32f7/nucleo-144/src/stm32_pwm.c
* boards/arm/stm32f7/nucleo-f722ze/src/stm32_pwm.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
@ -35,7 +35,7 @@
#include "chip.h"
#include "arm_internal.h"
#include "stm32_pwm.h"
#include "nucleo-144.h"
#include "nucleo-f722ze.h"
/****************************************************************************
* Pre-processor Definitions

4
boards/arm/stm32f7/nucleo-144/src/stm32_qencoder.c → boards/arm/stm32f7/nucleo-f722ze/src/stm32_qencoder.c
View file

@ -1,5 +1,5 @@
/****************************************************************************
* boards/arm/stm32f7/nucleo-144/src/stm32_qencoder.c
* boards/arm/stm32f7/nucleo-f722ze/src/stm32_qencoder.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
@ -33,7 +33,7 @@
#include "chip.h"
#include "arm_internal.h"
#include "stm32_qencoder.h"
#include "nucleo-144.h"
#include "nucleo-f722ze.h"
/****************************************************************************
* Public Functions

2
boards/arm/stm32f7/nucleo-144/src/stm32_reset.c → boards/arm/stm32f7/nucleo-f722ze/src/stm32_reset.c
View file

@ -1,5 +1,5 @@
/****************************************************************************
* boards/arm/stm32f7/nucleo-144/src/stm32_reset.c
* boards/arm/stm32f7/nucleo-f722ze/src/stm32_reset.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with

2
boards/arm/stm32f7/nucleo-144/src/stm32_romfs.h → boards/arm/stm32f7/nucleo-f722ze/src/stm32_romfs.h
View file

@ -1,5 +1,5 @@
/****************************************************************************
* boards/arm/stm32f7/nucleo-144/src/stm32_romfs.h
* boards/arm/stm32f7/nucleo-f722ze/src/stm32_romfs.h
*
* Copyright (C) 2017 Tomasz Wozniak. All rights reserved.
* Author: Tomasz Wozniak <t.wozniak@samsung.com>

2
boards/arm/stm32f7/nucleo-144/src/stm32_romfs_initialize.c → boards/arm/stm32f7/nucleo-f722ze/src/stm32_romfs_initialize.c
View file

@ -1,5 +1,5 @@
/****************************************************************************
* boards/arm/stm32f7/nucleo-144/src/stm32_romfs_initialize.c
* boards/arm/stm32f7/nucleo-f722ze/src/stm32_romfs_initialize.c
* This file provides contents of an optional ROMFS volume, mounted at boot.
*
* Copyright (C) 2017 Tomasz Wozniak. All rights reserved.

4
boards/arm/stm32f7/nucleo-144/src/stm32_sdio.c → boards/arm/stm32f7/nucleo-f722ze/src/stm32_sdio.c
View file

@ -1,5 +1,5 @@
/****************************************************************************
* boards/arm/stm32f7/nucleo-144/src/stm32_sdio.c
* boards/arm/stm32f7/nucleo-f722ze/src/stm32_sdio.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
@ -33,7 +33,7 @@
#include <nuttx/mmcsd.h>
#include "chip.h"
#include "nucleo-144.h"
#include "nucleo-f722ze.h"
#include "stm32_gpio.h"
#include "stm32_sdmmc.h"

106
boards/arm/stm32f7/nucleo-144/src/stm32_spi.c → boards/arm/stm32f7/nucleo-f722ze/src/stm32_spi.c
View file

@ -1,5 +1,5 @@
/****************************************************************************
* boards/arm/stm32f7/nucleo-144/src/stm32_spi.c
* boards/arm/stm32f7/nucleo-f722ze/src/stm32_spi.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
@ -39,7 +39,7 @@
#include "stm32_gpio.h"
#include "stm32_spi.h"
#include "nucleo-144.h"
#include "nucleo-f722ze.h"
#if defined(CONFIG_SPI)
@ -47,45 +47,45 @@
* Pre-processor Definitions
****************************************************************************/
#if defined(CONFIG_NUCLEO_SPI1_TEST)
# if defined(CONFIG_NUCLEO_SPI1_TEST_MODE0)
# define CONFIG_NUCLEO_SPI1_TEST_MODE SPIDEV_MODE0
# elif defined(CONFIG_NUCLEO_SPI1_TEST_MODE1)
# define CONFIG_NUCLEO_SPI1_TEST_MODE SPIDEV_MODE1
# elif defined(CONFIG_NUCLEO_SPI1_TEST_MODE2)
# define CONFIG_NUCLEO_SPI1_TEST_MODE SPIDEV_MODE2
# elif defined(CONFIG_NUCLEO_SPI1_TEST_MODE3)
# define CONFIG_NUCLEO_SPI1_TEST_MODE SPIDEV_MODE3
#if defined(CONFIG_NUCLEO_F722ZE_SPI1_TEST)
# if defined(CONFIG_NUCLEO_F722ZE_SPI1_TEST_MODE0)
# define CONFIG_NUCLEO_F722ZE_SPI1_TEST_MODE SPIDEV_MODE0
# elif defined(CONFIG_NUCLEO_F722ZE_SPI1_TEST_MODE1)
# define CONFIG_NUCLEO_F722ZE_SPI1_TEST_MODE SPIDEV_MODE1
# elif defined(CONFIG_NUCLEO_F722ZE_SPI1_TEST_MODE2)
# define CONFIG_NUCLEO_F722ZE_SPI1_TEST_MODE SPIDEV_MODE2
# elif defined(CONFIG_NUCLEO_F722ZE_SPI1_TEST_MODE3)
# define CONFIG_NUCLEO_F722ZE_SPI1_TEST_MODE SPIDEV_MODE3
# else
# error "No CONFIG_NUCLEO_SPI1_TEST_MODEx defined"
# error "No CONFIG_NUCLEO_F722ZE_SPI1_TEST_MODEx defined"
# endif
#endif
#if defined(CONFIG_NUCLEO_SPI2_TEST)
# if defined(CONFIG_NUCLEO_SPI2_TEST_MODE0)
# define CONFIG_NUCLEO_SPI2_TEST_MODE SPIDEV_MODE0
# elif defined(CONFIG_NUCLEO_SPI2_TEST_MODE1)
# define CONFIG_NUCLEO_SPI2_TEST_MODE SPIDEV_MODE1
# elif defined(CONFIG_NUCLEO_SPI2_TEST_MODE2)
# define CONFIG_NUCLEO_SPI2_TEST_MODE SPIDEV_MODE2
# elif defined(CONFIG_NUCLEO_SPI2_TEST_MODE3)
# define CONFIG_NUCLEO_SPI2_TEST_MODE SPIDEV_MODE3
#if defined(CONFIG_NUCLEO_F722ZE_SPI2_TEST)
# if defined(CONFIG_NUCLEO_F722ZE_SPI2_TEST_MODE0)
# define CONFIG_NUCLEO_F722ZE_SPI2_TEST_MODE SPIDEV_MODE0
# elif defined(CONFIG_NUCLEO_F722ZE_SPI2_TEST_MODE1)
# define CONFIG_NUCLEO_F722ZE_SPI2_TEST_MODE SPIDEV_MODE1
# elif defined(CONFIG_NUCLEO_F722ZE_SPI2_TEST_MODE2)
# define CONFIG_NUCLEO_F722ZE_SPI2_TEST_MODE SPIDEV_MODE2
# elif defined(CONFIG_NUCLEO_F722ZE_SPI2_TEST_MODE3)
# define CONFIG_NUCLEO_F722ZE_SPI2_TEST_MODE SPIDEV_MODE3
# else
# error "No CONFIG_NUCLEO_SPI2_TEST_MODEx defined"
# error "No CONFIG_NUCLEO_F722ZE_SPI2_TEST_MODEx defined"
# endif
#endif
#if defined(CONFIG_NUCLEO_SPI3_TEST)
# if defined(CONFIG_NUCLEO_SPI3_TEST_MODE0)
# define CONFIG_NUCLEO_SPI3_TEST_MODE SPIDEV_MODE0
# elif defined(CONFIG_NUCLEO_SPI3_TEST_MODE1)
# define CONFIG_NUCLEO_SPI3_TEST_MODE SPIDEV_MODE1
# elif defined(CONFIG_NUCLEO_SPI3_TEST_MODE2)
# define CONFIG_NUCLEO_SPI3_TEST_MODE SPIDEV_MODE2
# elif defined(CONFIG_NUCLEO_SPI3_TEST_MODE3)
# define CONFIG_NUCLEO_SPI3_TEST_MODE SPIDEV_MODE3
#if defined(CONFIG_NUCLEO_F722ZE_SPI3_TEST)
# if defined(CONFIG_NUCLEO_F722ZE_SPI3_TEST_MODE0)
# define CONFIG_NUCLEO_F722ZE_SPI3_TEST_MODE SPIDEV_MODE0
# elif defined(CONFIG_NUCLEO_F722ZE_SPI3_TEST_MODE1)
# define CONFIG_NUCLEO_F722ZE_SPI3_TEST_MODE SPIDEV_MODE1
# elif defined(CONFIG_NUCLEO_F722ZE_SPI3_TEST_MODE2)
# define CONFIG_NUCLEO_F722ZE_SPI3_TEST_MODE SPIDEV_MODE2
# elif defined(CONFIG_NUCLEO_F722ZE_SPI3_TEST_MODE3)
# define CONFIG_NUCLEO_F722ZE_SPI3_TEST_MODE SPIDEV_MODE3
# else
# error "No CONFIG_NUCLEO_SPI3_TEST_MODEx defined"
# error "No CONFIG_NUCLEO_F722ZE_SPI3_TEST_MODEx defined"
# endif
#endif
@ -171,7 +171,7 @@ static const uint32_t g_spi3gpio[] =
};
#endif
#if defined(CONFIG_NUCLEO_SPI_TEST)
#if defined(CONFIG_NUCLEO_F722ZE_SPI_TEST)
# if defined(CONFIG_STM32F7_SPI1)
struct spi_dev_s *spi1;
# endif
@ -191,7 +191,8 @@ struct spi_dev_s *spi3;
* Name: stm32_spidev_initialize
*
* Description:
* Called to configure SPI chip select GPIO pins for the Nucleo-144 board.
* Called to configure SPI chip select GPIO pins for the nucleo-f722ze
* board.
*
****************************************************************************/
@ -430,14 +431,14 @@ int stm32_spi6cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd)
#endif /* CONFIG_SPI_CMDDATA */
#if defined(CONFIG_NUCLEO_SPI_TEST)
#if defined(CONFIG_NUCLEO_F722ZE_SPI_TEST)
int stm32_spidev_bus_test(void)
{
/* Configure and test SPI- */
uint8_t *tx = (uint8_t *)CONFIG_NUCLEO_SPI_TEST_MESSAGE;
uint8_t *tx = (uint8_t *)CONFIG_NUCLEO_F722ZE_SPI_TEST_MESSAGE;
#if defined(CONFIG_NUCLEO_SPI1_TEST)
#if defined(CONFIG_NUCLEO_F722ZE_SPI1_TEST)
spi1 = stm32_spibus_initialize(1);
if (!spi1)
@ -448,13 +449,14 @@ int stm32_spidev_bus_test(void)
/* Default SPI1 to NUCLEO_SPI1_FREQ and mode */
SPI_SETFREQUENCY(spi1, CONFIG_NUCLEO_SPI1_TEST_FREQ);
SPI_SETBITS(spi1, CONFIG_NUCLEO_SPI1_TEST_BITS);
SPI_SETMODE(spi1, CONFIG_NUCLEO_SPI1_TEST_MODE);
SPI_EXCHANGE(spi1, tx, NULL, nitems(CONFIG_NUCLEO_SPI_TEST_MESSAGE));
SPI_SETFREQUENCY(spi1, CONFIG_NUCLEO_F722ZE_SPI1_TEST_FREQ);
SPI_SETBITS(spi1, CONFIG_NUCLEO_F722ZE_SPI1_TEST_BITS);
SPI_SETMODE(spi1, CONFIG_NUCLEO_F722ZE_SPI1_TEST_MODE);
SPI_EXCHANGE(spi1, tx, NULL,
nitems(CONFIG_NUCLEO_F722ZE_SPI_TEST_MESSAGE));
#endif
#if defined(CONFIG_NUCLEO_SPI2_TEST)
#if defined(CONFIG_NUCLEO_F722ZE_SPI2_TEST)
spi2 = stm32_spibus_initialize(2);
if (!spi2)
@ -465,13 +467,14 @@ int stm32_spidev_bus_test(void)
/* Default SPI2 to NUCLEO_SPI2_FREQ and mode */
SPI_SETFREQUENCY(spi2, CONFIG_NUCLEO_SPI2_TEST_FREQ);
SPI_SETBITS(spi2, CONFIG_NUCLEO_SPI2_TEST_BITS);
SPI_SETMODE(spi2, CONFIG_NUCLEO_SPI2_TEST_MODE);
SPI_EXCHANGE(spi2, tx, NULL, nitems(CONFIG_NUCLEO_SPI_TEST_MESSAGE));
SPI_SETFREQUENCY(spi2, CONFIG_NUCLEO_F722ZE_SPI2_TEST_FREQ);
SPI_SETBITS(spi2, CONFIG_NUCLEO_F722ZE_SPI2_TEST_BITS);
SPI_SETMODE(spi2, CONFIG_NUCLEO_F722ZE_SPI2_TEST_MODE);
SPI_EXCHANGE(spi2, tx, NULL,
nitems(CONFIG_NUCLEO_F722ZE_SPI_TEST_MESSAGE));
#endif
#if defined(CONFIG_NUCLEO_SPI3_TEST)
#if defined(CONFIG_NUCLEO_F722ZE_SPI3_TEST)
spi3 = stm32_spibus_initialize(3);
if (!spi3)
@ -482,10 +485,11 @@ int stm32_spidev_bus_test(void)
/* Default SPI3 to NUCLEO_SPI3_FREQ and mode */
SPI_SETFREQUENCY(spi3, CONFIG_NUCLEO_SPI3_TEST_FREQ);
SPI_SETBITS(spi3, CONFIG_NUCLEO_SPI3_TEST_BITS);
SPI_SETMODE(spi3, CONFIG_NUCLEO_SPI3_TEST_MODE);
SPI_EXCHANGE(spi3, tx, NULL, nitems(CONFIG_NUCLEO_SPI_TEST_MESSAGE));
SPI_SETFREQUENCY(spi3, CONFIG_NUCLEO_F722ZE_SPI3_TEST_FREQ);
SPI_SETBITS(spi3, CONFIG_NUCLEO_F722ZE_SPI3_TEST_BITS);
SPI_SETMODE(spi3, CONFIG_NUCLEO_F722ZE_SPI3_TEST_MODE);
SPI_EXCHANGE(spi3, tx, NULL,
nitems(CONFIG_NUCLEO_F722ZE_SPI_TEST_MESSAGE));
#endif
return OK;

6
boards/arm/stm32f7/nucleo-144/src/stm32_usb.c → boards/arm/stm32f7/nucleo-f722ze/src/stm32_usb.c
View file

@ -1,5 +1,5 @@
/****************************************************************************
* boards/arm/stm32f7/nucleo-144/src/stm32_usb.c
* boards/arm/stm32f7/nucleo-f722ze/src/stm32_usb.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
@ -41,7 +41,7 @@
#include "chip.h"
#include "stm32_gpio.h"
#include "stm32_otg.h"
#include "nucleo-144.h"
#include "nucleo-f722ze.h"
#ifdef CONFIG_STM32F7_OTGFS
@ -122,7 +122,7 @@ static int usbhost_waiter(int argc, char *argv[])
*
* Description:
* Called from stm32_usbinitialize very early in inialization to setup
* USB-related GPIO pins for the nucleo-144 board.
* USB-related GPIO pins for the nucleo-f722ze board.
*
****************************************************************************/

4
boards/arm/stm32f7/nucleo-144/src/stm32_userleds.c → boards/arm/stm32f7/nucleo-f722ze/src/stm32_userleds.c
View file

@ -1,5 +1,5 @@
/****************************************************************************
* boards/arm/stm32f7/nucleo-144/src/stm32_userleds.c
* boards/arm/stm32f7/nucleo-f722ze/src/stm32_userleds.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
@ -33,7 +33,7 @@
#include <arch/board/board.h>
#include "stm32_gpio.h"
#include "nucleo-144.h"
#include "nucleo-f722ze.h"
#ifndef CONFIG_ARCH_LEDS

21
boards/arm/stm32f7/nucleo-f746zg/CMakeLists.txt Normal file
View file

@ -0,0 +1,21 @@
# ##############################################################################
# boards/arm/stm32f7/nucleo-f746zg/CMakeLists.txt
#
# Licensed to the Apache Software Foundation (ASF) under one or more contributor
# license agreements. See the NOTICE file distributed with this work for
# additional information regarding copyright ownership. The ASF licenses this
# file to you under the Apache License, Version 2.0 (the "License"); you may not
# use this file except in compliance with the License. You may obtain a copy of
# the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
# License for the specific language governing permissions and limitations under
# the License.
#
# ##############################################################################
add_subdirectory(src)

272
boards/arm/stm32f7/nucleo-f746zg/Kconfig Normal file
View file

@ -0,0 +1,272 @@
#
# For a description of the syntax of this configuration file,
# see the file kconfig-language.txt in the NuttX tools repository.
#
if ARCH_BOARD_NUCLEO_F746ZG
config STM32_ROMFS
bool "Automount baked-in ROMFS image"
default n
depends on FS_ROMFS
---help---
Select STM32_ROMFS_IMAGEFILE, STM32_ROMFS_DEV_MINOR, STM32_ROMFS_MOUNTPOINT
config STM32_ROMFS_DEV_MINOR
int "Minor for the block device backing the data"
depends on STM32_ROMFS
default 64
config STM32_ROMFS_MOUNTPOINT
string "Mountpoint of the custom romfs image"
depends on STM32_ROMFS
default "/rom"
config STM32_ROMFS_IMAGEFILE
string "ROMFS image file to include into build"
depends on STM32_ROMFS
default "../../../rom.img"
choice
prompt "Select Console wiring."
default NUCLEO_F746ZG_CONSOLE_ARDUINO
---help---
Select where you will connect the console.
Virtual COM Port:
Advantage: Use the ST-Link as a console. No Extra wiring
needed.
Disadvantage: Not the best choice for initial bring up.
ARDUINO Connector:
Advantage: You have a shield so it is easy.
Disadvantage: You loose the use of the
other functions on PC6, PC7
STM32F7
ARDUINO FUNCTION GPIO
-- ----- --------- ----
DO RX USART6_RX PG9
D1 TX USART6_TX PG14
-- ----- --------- ---
OR
Morpho Connector:
STM32F7
MORPHO FUNCTION GPIO
-------- --------- -----
CN12-64 UART8_RX PE0
CN11-61 UART8_TX PE1
-------- --------- -----
OR
Morpho Connector UART4:
STM32F7
MORPHO FUNCTION GPIO
-------- --------- -----
CN11-30 UART4_RX PA0
CN11-28 UART4_TX PA1
-------- --------- -----
Note: SB13 must be removed to disable Ethernet.
config NUCLEO_F746ZG_CONSOLE_ARDUINO
bool "Arduino Connector"
select STM32F7_USART6
select USART6_SERIALDRIVER
config NUCLEO_F746ZG_CONSOLE_VIRTUAL
bool "Virtual Comport"
select STM32F7_USART3
select USART3_SERIALDRIVER
config NUCLEO_F746ZG_CONSOLE_MORPHO
bool "Morpho Connector"
select STM32F7_UART8
select UART8_SERIALDRIVER
config NUCLEO_F746ZG_CONSOLE_MORPHO_UART4
bool "Morpho Connector UART4"
select STM32F7_UART4
select UART4_SERIALDRIVER
config NUCLEO_F746ZG_CONSOLE_NONE
bool "No Console"
endchoice # "Select Console wiring"
config NUCLEO_F746ZG_SPI_TEST
bool "Enable SPI test"
default n
---help---
Enable Spi test - initialize and configure SPI to send
NUCLEO_F746ZG_SPI_TEST_MESSAGE text. The text is sent on the
selected SPI Buses with the configured parameters.
Note the CS lines will not be asserted.
if NUCLEO_F746ZG_SPI_TEST
config NUCLEO_F746ZG_SPI_TEST_MESSAGE
string "Text to Send on SPI Bus(es)"
default "Hello World"
depends on NUCLEO_F746ZG_SPI_TEST
---help---
Text to sent on SPI bus(es)
config NUCLEO_F746ZG_SPI1_TEST
bool "Test SPI bus 1"
default n
depends on NUCLEO_F746ZG_SPI_TEST
---help---
Enable Spi test - on SPI BUS 1
if NUCLEO_F746ZG_SPI1_TEST
config NUCLEO_F746ZG_SPI1_TEST_FREQ
int "SPI 1 Clock Freq in Hz"
default 1000000
depends on NUCLEO_F746ZG_SPI1_TEST
---help---
Sets SPI 1 Clock Freq
config NUCLEO_F746ZG_SPI1_TEST_BITS
int "SPI 1 number of bits"
default 8
depends on NUCLEO_F746ZG_SPI1_TEST
---help---
Sets SPI 1 bit length
choice
prompt "SPI BUS 1 Clock Mode"
default NUCLEO_F746ZG_SPI1_TEST_MODE3
---help---
Sets SPI 1 clock mode
config NUCLEO_F746ZG_SPI1_TEST_MODE0
bool "CPOL=0 CPHA=0"
config NUCLEO_F746ZG_SPI1_TEST_MODE1
bool "CPOL=0 CPHA=1"
config NUCLEO_F746ZG_SPI1_TEST_MODE2
bool "CPOL=1 CPHA=0"
config NUCLEO_F746ZG_SPI1_TEST_MODE3
bool "CPOL=1 CPHA=1"
endchoice # "SPI BUS 1 Clock Mode"
endif # NUCLEO_F746ZG_SPI1_TEST
config NUCLEO_F746ZG_SPI2_TEST
bool "Test SPI bus 2"
default n
depends on NUCLEO_F746ZG_SPI_TEST
---help---
Enable Spi test - on SPI BUS 2
if NUCLEO_F746ZG_SPI2_TEST
config NUCLEO_F746ZG_SPI2_TEST_FREQ
int "SPI 2 Clock Freq in Hz"
default 12000000
depends on NUCLEO_F746ZG_SPI2_TEST
---help---
Sets SPI 2 Clock Freq
config NUCLEO_F746ZG_SPI2_TEST_BITS
int "SPI 2 number of bits"
default 8
depends on NUCLEO_F746ZG_SPI2_TEST
---help---
Sets SPI 2 bit length
choice
prompt "SPI BUS 2 Clock Mode"
default NUCLEO_F746ZG_SPI2_TEST_MODE3
---help---
Sets SPI 2 clock mode
config NUCLEO_F746ZG_SPI2_TEST_MODE0
bool "CPOL=0 CPHA=0"
config NUCLEO_F746ZG_SPI2_TEST_MODE1
bool "CPOL=0 CPHA=1"
config NUCLEO_F746ZG_SPI2_TEST_MODE2
bool "CPOL=1 CPHA=0"
config NUCLEO_F746ZG_SPI2_TEST_MODE3
bool "CPOL=1 CPHA=1"
endchoice # "SPI BUS 2 Clock Mode"
endif # NUCLEO_F746ZG_SPI2_TEST
config NUCLEO_F746ZG_SPI3_TEST
bool "Test SPI bus 3"
default n
depends on NUCLEO_F746ZG_SPI_TEST
---help---
Enable Spi test - on SPI BUS 3
if NUCLEO_F746ZG_SPI3_TEST
config NUCLEO_F746ZG_SPI3_TEST_FREQ
int "SPI 3 Clock Freq in Hz"
default 40000000
depends on NUCLEO_F746ZG_SPI3_TEST
---help---
Sets SPI 3 Clock Freq
config NUCLEO_F746ZG_SPI3_TEST_BITS
int "SPI 3 number of bits"
default 8
depends on NUCLEO_F746ZG_SPI3_TEST
---help---
Sets SPI 3 bit length
choice
prompt "SPI BUS 3 Clock Mode"
default NUCLEO_F746ZG_SPI3_TEST_MODE3
---help---
Sets SPI 3 clock mode
config NUCLEO_F746ZG_SPI3_TEST_MODE0
bool "CPOL=0 CPHA=0"
config NUCLEO_F746ZG_SPI3_TEST_MODE1
bool "CPOL=0 CPHA=1"
config NUCLEO_F746ZG_SPI3_TEST_MODE2
bool "CPOL=1 CPHA=0"
config NUCLEO_F746ZG_SPI3_TEST_MODE3
bool "CPOL=1 CPHA=1"
endchoice # "SPI BUS 3 Clock Mode"
endif # NUCLEO_F746ZG_SPI3_TEST
endif # NUCLEO_F746ZG_SPI_TEST
choice
prompt "CAN1 pins selection"
default NUCLEO_F746ZG_CAN1_MAP_PD0PD1
depends on STM32F7_CAN1
config NUCLEO_F746ZG_F746ZG_CAN1_MAP_D14D15
bool "CAN1_TX=D14 CAN1_RX=D15"
config NUCLEO_F746ZG_CAN1_MAP_PD0PD1
bool "CAN1_RX=PD0 CAN1_TX=PD1"
endchoice # CAN1 pins selection
endif # ARCH_BOARD_NUCLEO_F746ZG

6
boards/arm/stm32f7/nucleo-144/configs/f746-evalos/defconfig → boards/arm/stm32f7/nucleo-f746zg/configs/evalos/defconfig
View file

@ -12,8 +12,8 @@
# CONFIG_NSH_DISABLE_PS is not set
# CONFIG_STM32F7_USE_LEGACY_PINMAP is not set
CONFIG_ARCH="arm"
CONFIG_ARCH_BOARD="nucleo-144"
CONFIG_ARCH_BOARD_NUCLEO_144=y
CONFIG_ARCH_BOARD="nucleo-f746zg"
CONFIG_ARCH_BOARD_NUCLEO_F746ZG=y
CONFIG_ARCH_BUTTONS=y
CONFIG_ARCH_CHIP="stm32f7"
CONFIG_ARCH_CHIP_STM32F746ZG=y
@ -37,7 +37,7 @@ CONFIG_NSH_BUILTIN_APPS=y
CONFIG_NSH_FILEIOSIZE=512
CONFIG_NSH_LINELEN=64
CONFIG_NSH_READLINE=y
CONFIG_NUCLEO_CONSOLE_VIRTUAL=y
CONFIG_NUCLEO_F746ZG_CONSOLE_VIRTUAL=y
CONFIG_PREALLOC_TIMERS=4
CONFIG_PRIORITY_INHERITANCE=y
CONFIG_PTHREAD_MUTEX_DEFAULT_PRIO_INHERIT=y

6
boards/arm/stm32f7/nucleo-144/configs/f746-nsh/defconfig → boards/arm/stm32f7/nucleo-f746zg/configs/nsh/defconfig
View file

@ -10,8 +10,8 @@
# CONFIG_NSH_DISABLE_PS is not set
# CONFIG_STM32F7_USE_LEGACY_PINMAP is not set
CONFIG_ARCH="arm"
CONFIG_ARCH_BOARD="nucleo-144"
CONFIG_ARCH_BOARD_NUCLEO_144=y
CONFIG_ARCH_BOARD="nucleo-f746zg"
CONFIG_ARCH_BOARD_NUCLEO_F746ZG=y
CONFIG_ARCH_BUTTONS=y
CONFIG_ARCH_CHIP="stm32f7"
CONFIG_ARCH_CHIP_STM32F746ZG=y
@ -32,7 +32,7 @@ CONFIG_NSH_BUILTIN_APPS=y
CONFIG_NSH_FILEIOSIZE=512
CONFIG_NSH_LINELEN=64
CONFIG_NSH_READLINE=y
CONFIG_NUCLEO_CONSOLE_VIRTUAL=y
CONFIG_NUCLEO_F746ZG_CONSOLE_VIRTUAL=y
CONFIG_PREALLOC_TIMERS=4
CONFIG_RAM_SIZE=245760
CONFIG_RAM_START=0x20010000

6
boards/arm/stm32f7/nucleo-144/configs/f746-pysim/defconfig → boards/arm/stm32f7/nucleo-f746zg/configs/pysim/defconfig
View file

@ -12,8 +12,8 @@ CONFIG_ADC=y
CONFIG_ADC_FIFOSIZE=16
CONFIG_ANALOG=y
CONFIG_ARCH="arm"
CONFIG_ARCH_BOARD="nucleo-144"
CONFIG_ARCH_BOARD_NUCLEO_144=y
CONFIG_ARCH_BOARD="nucleo-f746zg"
CONFIG_ARCH_BOARD_NUCLEO_F746ZG=y
CONFIG_ARCH_BUTTONS=y
CONFIG_ARCH_CHIP="stm32f7"
CONFIG_ARCH_CHIP_STM32F746ZG=y
@ -67,7 +67,7 @@ CONFIG_NSH_DISABLE_IFUPDOWN=y
CONFIG_NSH_FILEIOSIZE=512
CONFIG_NSH_LINELEN=64
CONFIG_NSH_READLINE=y
CONFIG_NUCLEO_CONSOLE_VIRTUAL=y
CONFIG_NUCLEO_F746ZG_CONSOLE_VIRTUAL=y
CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=4098
CONFIG_PREALLOC_TIMERS=4
CONFIG_PRIORITY_INHERITANCE=y

568
boards/arm/stm32f7/nucleo-f746zg/include/board.h Normal file
View file

@ -0,0 +1,568 @@
/****************************************************************************
* boards/arm/stm32f7/nucleo-f746zg/include/board.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __BOARDS_ARM_STM32F7_NUCLEO_F746ZG_INCLUDE_BOARD_H
#define __BOARDS_ARM_STM32F7_NUCLEO_F746ZG_INCLUDE_BOARD_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#ifndef __ASSEMBLY__
# include <stdint.h>
#endif
/* Do not include STM32 F7 header files here */
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Clocking *****************************************************************/
/* The Nucleo-f746zg board provides the following clock sources:
*
* MCO: 8 MHz from MCO output of ST-LINK is used as input clock
* X2: 32.768 KHz crystal for LSE
* X3: HSE crystal oscillator (not provided)
*
* So we have these clock source available within the STM32
*
* HSI: 16 MHz RC factory-trimmed
* LSI: 32 KHz RC
* HSE: 8 MHz from MCO output of ST-LINK
* LSE: 32.768 kHz
*/
#define STM32_BOARD_XTAL 8000000ul
#define STM32_HSI_FREQUENCY 16000000ul
#define STM32_LSI_FREQUENCY 32000
#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL
#define STM32_LSE_FREQUENCY 32768
/* Main PLL Configuration.
*
* PLL source is HSE = 8,000,000
*
* PLL_VCO = (STM32_HSE_FREQUENCY / PLLM) * PLLN
* Subject to:
*
* 2 <= PLLM <= 63
* 192 <= PLLN <= 432
* 192 MHz <= PLL_VCO <= 432MHz
*
* SYSCLK = PLL_VCO / PLLP
* Subject to
*
* PLLP = {2, 4, 6, 8}
* SYSCLK <= 216 MHz
*
* USB OTG FS, SDMMC and RNG Clock = PLL_VCO / PLLQ
* Subject to
* The USB OTG FS requires a 48 MHz clock to work correctly. The SDMMC
* and the random number generator need a frequency lower than or equal
* to 48 MHz to work correctly.
*
* 2 <= PLLQ <= 15
*/
/* Highest SYSCLK with USB OTG FS clock = 48 MHz
*
* PLL_VCO = (8,000,000 / 4) * 216 = 432 MHz
* SYSCLK = 432 MHz / 2 = 216 MHz
* USB OTG FS, SDMMC and RNG Clock = 432 MHz / 9 = 48 MHz
*/
#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(4)
#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(216)
#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_2
#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(9)
#define STM32_VCO_FREQUENCY ((STM32_HSE_FREQUENCY / 4) * 216)
#define STM32_SYSCLK_FREQUENCY (STM32_VCO_FREQUENCY / 2)
#define STM32_OTGFS_FREQUENCY (STM32_VCO_FREQUENCY / 9)
/* Configure factors for PLLSAI clock */
#define CONFIG_STM32F7_PLLSAI 1
#define STM32_RCC_PLLSAICFGR_PLLSAIN RCC_PLLSAICFGR_PLLSAIN(192)
#define STM32_RCC_PLLSAICFGR_PLLSAIP RCC_PLLSAICFGR_PLLSAIP(8)
#define STM32_RCC_PLLSAICFGR_PLLSAIQ RCC_PLLSAICFGR_PLLSAIQ(4)
#define STM32_RCC_PLLSAICFGR_PLLSAIR RCC_PLLSAICFGR_PLLSAIR(2)
/* Configure Dedicated Clock Configuration Register */
#define STM32_RCC_DCKCFGR1_PLLI2SDIVQ RCC_DCKCFGR1_PLLI2SDIVQ(1)
#define STM32_RCC_DCKCFGR1_PLLSAIDIVQ RCC_DCKCFGR1_PLLSAIDIVQ(1)
#define STM32_RCC_DCKCFGR1_PLLSAIDIVR RCC_DCKCFGR1_PLLSAIDIVR(0)
#define STM32_RCC_DCKCFGR1_SAI1SRC RCC_DCKCFGR1_SAI1SEL(0)
#define STM32_RCC_DCKCFGR1_SAI2SRC RCC_DCKCFGR1_SAI2SEL(0)
#define STM32_RCC_DCKCFGR1_TIMPRESRC 0
#define STM32_RCC_DCKCFGR1_DFSDM1SRC 0
#define STM32_RCC_DCKCFGR1_ADFSDM1SRC 0
/* Configure factors for PLLI2S clock */
#define CONFIG_STM32F7_PLLI2S 1
#define STM32_RCC_PLLI2SCFGR_PLLI2SN RCC_PLLI2SCFGR_PLLI2SN(192)
#define STM32_RCC_PLLI2SCFGR_PLLI2SP RCC_PLLI2SCFGR_PLLI2SP(2)
#define STM32_RCC_PLLI2SCFGR_PLLI2SQ RCC_PLLI2SCFGR_PLLI2SQ(2)
#define STM32_RCC_PLLI2SCFGR_PLLI2SR RCC_PLLI2SCFGR_PLLI2SR(2)
/* Configure Dedicated Clock Configuration Register 2 */
#define STM32_RCC_DCKCFGR2_USART1SRC RCC_DCKCFGR2_USART1SEL_APB
#define STM32_RCC_DCKCFGR2_USART2SRC RCC_DCKCFGR2_USART2SEL_APB
#define STM32_RCC_DCKCFGR2_UART4SRC RCC_DCKCFGR2_UART4SEL_APB
#define STM32_RCC_DCKCFGR2_UART5SRC RCC_DCKCFGR2_UART5SEL_APB
#define STM32_RCC_DCKCFGR2_USART6SRC RCC_DCKCFGR2_USART6SEL_APB
#define STM32_RCC_DCKCFGR2_UART7SRC RCC_DCKCFGR2_UART7SEL_APB
#define STM32_RCC_DCKCFGR2_UART8SRC RCC_DCKCFGR2_UART8SEL_APB
#define STM32_RCC_DCKCFGR2_I2C1SRC RCC_DCKCFGR2_I2C1SEL_HSI
#define STM32_RCC_DCKCFGR2_I2C2SRC RCC_DCKCFGR2_I2C2SEL_HSI
#define STM32_RCC_DCKCFGR2_I2C3SRC RCC_DCKCFGR2_I2C3SEL_HSI
#define STM32_RCC_DCKCFGR2_I2C4SRC RCC_DCKCFGR2_I2C4SEL_HSI
#define STM32_RCC_DCKCFGR2_LPTIM1SRC RCC_DCKCFGR2_LPTIM1SEL_APB
#define STM32_RCC_DCKCFGR2_CECSRC RCC_DCKCFGR2_CECSEL_HSI
#define STM32_RCC_DCKCFGR2_CK48MSRC RCC_DCKCFGR2_CK48MSEL_PLL
#define STM32_RCC_DCKCFGR2_SDMMCSRC RCC_DCKCFGR2_SDMMCSEL_48MHZ
#define STM32_RCC_DCKCFGR2_SDMMC2SRC RCC_DCKCFGR2_SDMMC2SEL_48MHZ
#define STM32_RCC_DCKCFGR2_DSISRC RCC_DCKCFGR2_DSISEL_PHY
/* Several prescalers allow the configuration of the two AHB buses, the
* high-speed APB (APB2) and the low-speed APB (APB1) domains. The maximum
* frequency of the two AHB buses is 216 MHz while the maximum frequency of
* the high-speed APB domains is 108 MHz. The maximum allowed frequency of
* the low-speed APB domain is 54 MHz.
*/
/* AHB clock (HCLK) is SYSCLK (216 MHz) */
#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */
#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY
/* APB1 clock (PCLK1) is HCLK/4 (54 MHz) */
#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd4 /* PCLK1 = HCLK / 4 */
#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/4)
/* Timers driven from APB1 will be twice PCLK1 */
#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY)
#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY)
#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY)
#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY)
#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY)
#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY)
#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY)
#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY)
#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY)
/* APB2 clock (PCLK2) is HCLK/2 (108MHz) */
#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLKd2 /* PCLK2 = HCLK / 2 */
#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/2)
/* Timers driven from APB2 will be twice PCLK2 */
#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY)
#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY)
#define STM32_APB2_TIM9_CLKIN (2*STM32_PCLK2_FREQUENCY)
#define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK2_FREQUENCY)
#define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK2_FREQUENCY)
/* SDMMC dividers. Note that slower clocking is required when DMA
* is disabledin order to avoid RX overrun/TX underrun errors due
* to delayed responses to service FIFOs in interrupt driven mode.
* These values have not been tuned!!!
*
* SDMMCCLK=48MHz, SDMMC_CK=SDMMCCLK/(118+2)=400 KHz
*/
#define STM32_SDMMC_INIT_CLKDIV (118 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT)
/* DMA ON: SDMMCCLK=48MHz, SDMMC_CK=SDMMCCLK/(1+2)=16 MHz
* DMA OFF: SDMMCCLK=48MHz, SDMMC_CK=SDMMCCLK/(2+2)=12 MHz
*/
#ifdef CONFIG_SDIO_DMA
# define STM32_SDMMC_MMCXFR_CLKDIV (1 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT)
#else
# define STM32_SDMMC_MMCXFR_CLKDIV (2 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT)
#endif
/* DMA ON: SDMMCCLK=48MHz, SDMMC_CK=SDMMCCLK/(1+2)=16 MHz
* DMA OFF: SDMMCCLK=48MHz, SDMMC_CK=SDMMCCLK/(2+2)=12 MHz
*/
#ifdef CONFIG_SDIO_DMA
# define STM32_SDMMC_SDXFR_CLKDIV (1 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT)
#else
# define STM32_SDMMC_SDXFR_CLKDIV (2 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT)
#endif
/* DMA Channel/Stream Selections ********************************************/
/* Stream selections are arbitrary for now but might become important in the
* future if we set aside more DMA channels/streams.
*
* SDMMC DMA is on DMA2
*
* SDMMC1 DMA
* DMAMAP_SDMMC1_1 = Channel 4, Stream 3
* DMAMAP_SDMMC1_2 = Channel 4, Stream 6
*
* SDMMC2 DMA
* DMAMAP_SDMMC2_1 = Channel 11, Stream 0
* DMAMAP_SDMMC3_2 = Channel 11, Stream 5
*/
#define DMAMAP_SDMMC1 DMAMAP_SDMMC1_1
#define DMAMAP_SDMMC2 DMAMAP_SDMMC2_1
/* FLASH wait states
*
* --------- ---------- -----------
* VDD MAX SYSCLK WAIT STATES
* --------- ---------- -----------
* 1.7-2.1 V 180 MHz 8
* 2.1-2.4 V 216 MHz 9
* 2.4-2.7 V 216 MHz 8
* 2.7-3.6 V 216 MHz 7
* --------- ---------- -----------
*/
#define BOARD_FLASH_WAITSTATES 7
/* LED definitions **********************************************************/
/* The Nucleo-f746zg board has numerous LEDs but only three, LD1 a Green LED,
* LD2 a Blue LED and LD3 a Red LED, that can be controlled by software.
* The following definitions assume the default Solder Bridges are installed.
*
* If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs
* in any way.
* The following definitions are used to access individual LEDs.
*/
/* LED index values for use with board_userled() */
#define BOARD_LED1 0
#define BOARD_LED2 1
#define BOARD_LED3 2
#define BOARD_NLEDS 3
#define BOARD_LED_GREEN BOARD_LED1
#define BOARD_LED_BLUE BOARD_LED2
#define BOARD_LED_RED BOARD_LED3
/* LED bits for use with board_userled_all() */
#define BOARD_LED1_BIT (1 << BOARD_LED1)
#define BOARD_LED2_BIT (1 << BOARD_LED2)
#define BOARD_LED3_BIT (1 << BOARD_LED3)
/* If CONFIG_ARCH_LEDS is defined, the usage by the board port is defined in
* include/board.h and src/stm32_leds.c. The LEDs are used to encode
* OS-relatedevents as follows:
*
*
* SYMBOL Meaning LED state
* Red Green Blue
* ---------------------- -------------------------- ------ ------ ----
*/
#define LED_STARTED 0 /* NuttX has been started OFF OFF OFF */
#define LED_HEAPALLOCATE 1 /* Heap has been allocated OFF OFF ON */
#define LED_IRQSENABLED 2 /* Interrupts enabled OFF ON OFF */
#define LED_STACKCREATED 3 /* Idle stack created OFF ON ON */
#define LED_INIRQ 4 /* In an interrupt N/C N/C GLOW */
#define LED_SIGNAL 5 /* In a signal handler N/C GLOW N/C */
#define LED_ASSERTION 6 /* An assertion failed GLOW N/C GLOW */
#define LED_PANIC 7 /* The system has crashed Blink OFF N/C */
#define LED_IDLE 8 /* MCU is is sleep mode ON OFF OFF */
/* Thus if the Green LED is statically on, NuttX has successfully booted and
* is, apparently, running normally. If the Red LED is flashing at
* approximately 2Hz, then a fatal error has been detected and the system
* has halted.
*/
/* Button definitions *******************************************************/
/* The STM32F7 Discovery supports one button: Pushbutton B1, labeled "User",
* is connected to GPIO PI11.
* A high value will be sensed when the button is depressed.
*/
#define BUTTON_USER 0
#define NUM_BUTTONS 1
#define BUTTON_USER_BIT (1 << BUTTON_USER)
/* DMA channels *************************************************************/
/* ADC */
#define ADC1_DMA_CHAN DMAMAP_ADC1_1
#define ADC2_DMA_CHAN DMAMAP_ADC2_1
#define ADC3_DMA_CHAN DMAMAP_ADC3_1
/* Alternate function pin selections ****************************************/
/* ADC1 */
#define GPIO_ADC1_IN0 GPIO_ADC1_IN0_0 /* PA0 */
#define GPIO_ADC1_IN1 GPIO_ADC1_IN1_0 /* PA1 */
#define GPIO_ADC1_IN2 GPIO_ADC1_IN2_0 /* PA2 */
#define GPIO_ADC1_IN3 GPIO_ADC1_IN3_0 /* PA3 */
#define GPIO_ADC1_IN4 GPIO_ADC1_IN4_0 /* PA4 */
#define GPIO_ADC1_IN5 GPIO_ADC1_IN5_0 /* PA5 */
#define GPIO_ADC1_IN6 GPIO_ADC1_IN6_0 /* PA6 */
#define GPIO_ADC1_IN7 GPIO_ADC1_IN7_0 /* PA7 */
#define GPIO_ADC1_IN8 GPIO_ADC1_IN8_0 /* PB0 */
#define GPIO_ADC1_IN9 GPIO_ADC1_IN9_0 /* PB1 */
#define GPIO_ADC1_IN10 GPIO_ADC1_IN10_0 /* PC0 */
#define GPIO_ADC1_IN11 GPIO_ADC1_IN11_0 /* PC1 */
#define GPIO_ADC1_IN12 GPIO_ADC1_IN12_0 /* PC2 */
#define GPIO_ADC1_IN13 GPIO_ADC1_IN13_0 /* PC3 */
#define GPIO_ADC1_IN14 GPIO_ADC1_IN14_0 /* PC4 */
#define GPIO_ADC1_IN15 GPIO_ADC1_IN15_0 /* PC5 */
/* TIM */
/* Quadrature encoder
* Default is to use timer 8 (16-bit) and encoder on PC6/PC7
* We use here TIM2 with a 32-bit counter on PA15/PB3
*/
#define GPIO_TIM1_CH1IN (GPIO_TIM1_CH1IN_2|GPIO_SPEED_50MHz)
#define GPIO_TIM1_CH2IN (GPIO_TIM1_CH2IN_2|GPIO_SPEED_50MHz)
#define GPIO_TIM2_CH1IN (GPIO_TIM2_CH1IN_2|GPIO_SPEED_50MHz)
#define GPIO_TIM2_CH2IN (GPIO_TIM2_CH2IN_2|GPIO_SPEED_50MHz)
#define GPIO_TIM3_CH1IN (GPIO_TIM3_CH1IN_2|GPIO_SPEED_50MHz)
#define GPIO_TIM3_CH2IN (GPIO_TIM3_CH2IN_2|GPIO_SPEED_50MHz)
#define GPIO_TIM4_CH1IN (GPIO_TIM4_CH1IN_2|GPIO_SPEED_50MHz)
#define GPIO_TIM4_CH2IN (GPIO_TIM4_CH2IN_2|GPIO_SPEED_50MHz)
#define GPIO_TIM8_CH1IN (GPIO_TIM8_CH1IN_1|GPIO_SPEED_50MHz)
#define GPIO_TIM8_CH2IN (GPIO_TIM8_CH2IN_1|GPIO_SPEED_50MHz)
/* PWM
* Use Timer 1 or 3
*/
#define GPIO_TIM1_CH1OUT (GPIO_TIM1_CH1OUT_2|GPIO_SPEED_50MHz)
#define GPIO_TIM1_CH1NOUT (GPIO_TIM1_CH1NOUT_3|GPIO_SPEED_50MHz)
#define GPIO_TIM1_CH2OUT (GPIO_TIM1_CH2OUT_2|GPIO_SPEED_50MHz)
#define GPIO_TIM1_CH2NOUT (GPIO_TIM1_CH2NOUT_3|GPIO_SPEED_50MHz)
#define GPIO_TIM3_CH1OUT (GPIO_TIM3_CH1OUT_2|GPIO_SPEED_50MHz)
#define GPIO_TIM3_CH2OUT (GPIO_TIM3_CH2OUT_2|GPIO_SPEED_50MHz)
#define GPIO_TIM3_CH3OUT (GPIO_TIM3_CH3OUT_2|GPIO_SPEED_50MHz)
#define GPIO_TIM3_CH4OUT (GPIO_TIM3_CH4OUT_1|GPIO_SPEED_50MHz)
#if defined(CONFIG_NUCLEO_F746ZG_CONSOLE_ARDUINO)
/* USART6:
*
* These configurations assume that you are using a standard Arduio RS-232
* shield with the serial interface with RX on pin D0 and TX on pin D1:
*
* -------- ---------------
* STM32F7
* ARDUIONO FUNCTION GPIO
* -- ----- --------- -----
* DO RX USART6_RX PG9
* D1 TX USART6_TX PG14
* -- ----- --------- -----
*/
# define GPIO_USART6_RX (GPIO_USART6_RX_2|GPIO_SPEED_100MHz)
# define GPIO_USART6_TX (GPIO_USART6_TX_2|GPIO_SPEED_100MHz)
#endif
/* USART3:
* Use USART3 and the USB virtual COM port
*/
#if defined(CONFIG_NUCLEO_F746ZG_CONSOLE_VIRTUAL)
# define GPIO_USART3_RX (GPIO_USART3_RX_3|GPIO_SPEED_100MHz)
# define GPIO_USART3_TX (GPIO_USART3_TX_3|GPIO_SPEED_100MHz)
#endif
#if defined(CONFIG_NUCLEO_F746ZG_CONSOLE_MORPHO_UART4)
/* UART4:
*
* This configuration assumes that you disabled Ethernet MII clocking
* by removing SB13 to free PA1.
*
* -------- ---------------
* STM32F7
* Pin FUNCTION GPIO
* ------- --------- -----
* CN11 30 UART4_RX PA1
* CN11 28 UART4_TX PA0
* ------- --------- -----
*/
# define GPIO_UART4_RX (GPIO_UART4_RX_1|GPIO_SPEED_100MHz)
# define GPIO_UART4_TX (GPIO_UART4_TX_1|GPIO_SPEED_100MHz)
/* USART3 seems to be forced selected by the Nucleo-F746ZG kconfig - bug */
# define GPIO_USART3_RX (GPIO_USART3_RX_1|GPIO_SPEED_100MHz)
# define GPIO_USART3_TX (GPIO_USART3_TX_1|GPIO_SPEED_100MHz)
/* USART6 seems to be forced selected by the Nucleo-F722E kconfig - bug */
# define GPIO_USART6_RX (GPIO_USART6_RX_2|GPIO_SPEED_100MHz)
# define GPIO_USART6_TX (GPIO_USART6_TX_2|GPIO_SPEED_100MHz)
#endif
/* USART8:
*
* This configurations assume that you are connecting to the Morpho connector
* with the serial interface with the adaptor's RX on pin CN11 pin 64 and
* TX on pin CN11 pin 61
*
* USART8: has no remap
*/
/* SPI
*
*
* PA6 SPI1_MISO CN12-13
* PA7 SPI1_MOSI CN12-15
* PA5 SPI1_SCK CN12-11
*
* PB14 SPI2_MISO CN12-28
* PB15 SPI2_MOSI CN12-26
* PB13 SPI2_SCK CN12-30
*
* PB4 SPI3_MISO CN12-27
* PB5 SPI3_MOSI CN12-29
* PB3 SPI3_SCK CN12-31
*/
#define GPIO_SPI1_MISO (GPIO_SPI1_MISO_1|GPIO_SPEED_50MHz)
#define GPIO_SPI1_MOSI (GPIO_SPI1_MOSI_1|GPIO_SPEED_50MHz)
#define GPIO_SPI1_SCK (GPIO_SPI1_SCK_1|GPIO_SPEED_50MHz)
#define GPIO_SPI2_MISO (GPIO_SPI2_MISO_1|GPIO_SPEED_50MHz)
#define GPIO_SPI2_MOSI (GPIO_SPI2_MOSI_1|GPIO_SPEED_50MHz)
#define GPIO_SPI2_SCK (GPIO_SPI2_SCK_3|GPIO_SPEED_50MHz)
#define GPIO_SPI3_MISO (GPIO_SPI3_MISO_1|GPIO_SPEED_50MHz)
#define GPIO_SPI3_MOSI (GPIO_SPI3_MOSI_2|GPIO_SPEED_50MHz)
#define GPIO_SPI3_SCK (GPIO_SPI3_SCK_1|GPIO_SPEED_50MHz)
/* I2C
*
*
* PB8 I2C1_SCL CN12-3
* PB9 I2C1_SDA CN12-5
* PB10 I2C2_SCL CN11-51
* PB11 I2C2_SDA CN12-18
*
* PA8 I2C3_SCL CN12-23
* PC9 I2C3_SDA CN12-1
*
*/
#define GPIO_I2C1_SCL (GPIO_I2C1_SCL_2|GPIO_SPEED_50MHz)
#define GPIO_I2C1_SDA (GPIO_I2C1_SDA_2|GPIO_SPEED_50MHz)
#define GPIO_I2C2_SCL (GPIO_I2C2_SCL_1|GPIO_SPEED_50MHz)
#define GPIO_I2C2_SDA (GPIO_I2C2_SDA_1|GPIO_SPEED_50MHz)
#define GPIO_I2C3_SCL (GPIO_I2C3_SCL_1|GPIO_SPEED_50MHz)
#define GPIO_I2C3_SDA (GPIO_I2C3_SDA_1|GPIO_SPEED_50MHz)
/* The STM32 F7 connects to a SMSC LAN8742A PHY using these pins:
*
* STM32 F7 BOARD LAN8742A
* GPIO SIGNAL PIN NAME
* -------- ------------ -------------
* PG11 RMII_TX_EN TXEN
* PG13 RMII_TXD0 TXD0
* PB13 RMII_TXD1 TXD1
* PC4 RMII_RXD0 RXD0/MODE0
* PC5 RMII_RXD1 RXD1/MODE1
* PG2 RMII_RXER RXER/PHYAD0 -- Not used
* PA7 RMII_CRS_DV CRS_DV/MODE2
* PC1 RMII_MDC MDC
* PA2 RMII_MDIO MDIO
* N/A NRST nRST
* PA1 RMII_REF_CLK nINT/REFCLK0
* N/A OSC_25M XTAL1/CLKIN
*
* The PHY address is either 0 or 1, depending on the state of PG2 on reset.
* PG2 is not controlled but appears to result in a PHY address of 0.
*/
#define GPIO_ETH_MDC (GPIO_ETH_MDC_0|GPIO_SPEED_100MHz)
#define GPIO_ETH_MDIO (GPIO_ETH_MDIO_0|GPIO_SPEED_100MHz)
#define GPIO_ETH_RMII_CRS_DV (GPIO_ETH_RMII_CRS_DV_0|GPIO_SPEED_100MHz)
#define GPIO_ETH_RMII_REF_CLK (GPIO_ETH_RMII_REF_CLK_0|GPIO_SPEED_100MHz)
#define GPIO_ETH_RMII_RXD0 (GPIO_ETH_RMII_RXD0_0|GPIO_SPEED_100MHz)
#define GPIO_ETH_RMII_RXD1 (GPIO_ETH_RMII_RXD1_0|GPIO_SPEED_100MHz)
#define GPIO_ETH_RMII_TX_EN (GPIO_ETH_RMII_TX_EN_2|GPIO_SPEED_100MHz)
#define GPIO_ETH_RMII_TXD0 (GPIO_ETH_RMII_TXD0_2|GPIO_SPEED_100MHz)
#define GPIO_ETH_RMII_TXD1 (GPIO_ETH_RMII_TXD1_1|GPIO_SPEED_100MHz)
/* CAN Bus */
#ifdef CONFIG_NUCLEO_F746ZG_CAN1_MAP_PD0PD1
# define GPIO_CAN1_TX (GPIO_CAN1_TX_3|GPIO_SPEED_50MHz) /* PD1 */
# define GPIO_CAN1_RX (GPIO_CAN1_RX_3|GPIO_SPEED_50MHz) /* PD0 */
#elif CONFIG_NUCLEO_F746ZG_CAN1_MAP_D14D15
# define GPIO_CAN1_TX (GPIO_CAN1_TX_2|GPIO_SPEED_50MHz) /* PB9 */
# define GPIO_CAN1_RX (GPIO_CAN1_RX_2|GPIO_SPEED_50MHz) /* PB8 */
#endif
/* SDMMC2 */
#define GPIO_SDMMC2_CK (GPIO_SDMMC2_CK_0|GPIO_SPEED_50MHz)
#define GPIO_SDMMC2_CMD (GPIO_SDMMC2_CMD_0|GPIO_SPEED_50MHz)
#define GPIO_SDMMC2_D0 (GPIO_SDMMC2_D0_0|GPIO_SPEED_50MHz)
#define GPIO_SDMMC2_D1 (GPIO_SDMMC2_D1_0|GPIO_SPEED_50MHz)
#define GPIO_SDMMC2_D2 (GPIO_SDMMC2_D2_0|GPIO_SPEED_50MHz)
#define GPIO_SDMMC2_D3 (GPIO_SDMMC2_D3_0|GPIO_SPEED_50MHz)
#define GPIO_SDMMC2_D4 (GPIO_SDMMC2_D4_0|GPIO_SPEED_50MHz)
#define GPIO_SDMMC2_D5 (GPIO_SDMMC2_D5_0|GPIO_SPEED_50MHz)
#define GPIO_SDMMC2_D6 (GPIO_SDMMC2_D6_0|GPIO_SPEED_50MHz)
#define GPIO_SDMMC2_D7 (GPIO_SDMMC2_D7_0|GPIO_SPEED_50MHz)
/* OTGFS */
#define GPIO_OTGFS_DM (GPIO_OTGFS_DM_0|GPIO_SPEED_100MHz)
#define GPIO_OTGFS_DP (GPIO_OTGFS_DP_0|GPIO_SPEED_100MHz)
#define GPIO_OTGFS_ID (GPIO_OTGFS_ID_0|GPIO_SPEED_100MHz)
#endif /* __BOARDS_ARM_STM32F7_NUCLEO_F746ZG_INCLUDE_BOARD_H */

4
boards/arm/stm32f7/nucleo-144/configs/f767-nsh/Make.defs → boards/arm/stm32f7/nucleo-f746zg/scripts/Make.defs
View file

@ -1,5 +1,5 @@
############################################################################
# boards/arm/stm32f7/nucleo-144/configs/f767-nsh/Make.defs
# boards/arm/stm32f7/nucleo-f746zg/scripts/Make.defs
#
# Licensed to the Apache Software Foundation (ASF) under one or more
# contributor license agreements. See the NOTICE file distributed with
@ -22,7 +22,7 @@ include $(TOPDIR)/.config
include $(TOPDIR)/tools/Config.mk
include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs
LDSCRIPT = f767-flash.ld
LDSCRIPT = flash.ld
ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT)
ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10

2
boards/arm/stm32f7/nucleo-144/scripts/f746-flash.ld → boards/arm/stm32f7/nucleo-f746zg/scripts/flash.ld
View file

@ -1,5 +1,5 @@
/****************************************************************************
* boards/arm/stm32f7/nucleo-144/scripts/f746-flash.ld
* boards/arm/stm32f7/nucleo-f746zg/scripts/flash.ld
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with

97
boards/arm/stm32f7/nucleo-f746zg/scripts/kernel-space.ld Normal file
View file

@ -0,0 +1,97 @@
/****************************************************************************
* boards/arm/stm32f7/nucleo-f746zg/scripts/kernel-space.ld
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* NOTE: This depends on the memory.ld script having been included prior to
* this script.
*/
OUTPUT_ARCH(arm)
ENTRY(_stext)
SECTIONS
{
.text : {
_stext = ABSOLUTE(.);
*(.vectors)
*(.text .text.*)
*(.fixup)
*(.gnu.warning)
*(.rodata .rodata.*)
*(.gnu.linkonce.t.*)
*(.glue_7)
*(.glue_7t)
*(.got)
*(.gcc_except_table)
*(.gnu.linkonce.r.*)
_etext = ABSOLUTE(.);
} > kflash
.init_section : {
_sinit = ABSOLUTE(.);
KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors))
_einit = ABSOLUTE(.);
} > kflash
.ARM.extab : {
*(.ARM.extab*)
} > kflash
__exidx_start = ABSOLUTE(.);
.ARM.exidx : {
*(.ARM.exidx*)
} > kflash
__exidx_end = ABSOLUTE(.);
_eronly = ABSOLUTE(.);
.data : {
_sdata = ABSOLUTE(.);
*(.data .data.*)
*(.gnu.linkonce.d.*)
CONSTRUCTORS
. = ALIGN(4);
_edata = ABSOLUTE(.);
} > ksram AT > kflash
.bss : {
_sbss = ABSOLUTE(.);
*(.bss .bss.*)
*(.gnu.linkonce.b.*)
*(COMMON)
. = ALIGN(4);
_ebss = ABSOLUTE(.);
} > ksram
/* Stabs debugging sections */
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.stab.excl 0 : { *(.stab.excl) }
.stab.exclstr 0 : { *(.stab.exclstr) }
.stab.index 0 : { *(.stab.index) }
.stab.indexstr 0 : { *(.stab.indexstr) }
.comment 0 : { *(.comment) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_info 0 : { *(.debug_info) }
.debug_line 0 : { *(.debug_line) }
.debug_pubnames 0 : { *(.debug_pubnames) }
.debug_aranges 0 : { *(.debug_aranges) }
}

2
boards/arm/stm32f7/nucleo-144/scripts/memory.ld → boards/arm/stm32f7/nucleo-f746zg/scripts/memory.ld
View file

@ -1,5 +1,5 @@
/****************************************************************************
* boards/arm/stm32f7/nucleo-144/scripts/memory.ld
* boards/arm/stm32f7/nucleo-f746zg/scripts/memory.ld
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with

99
boards/arm/stm32f7/nucleo-f746zg/scripts/user-space.ld Normal file
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@ -0,0 +1,99 @@
/****************************************************************************
* boards/arm/stm32f7/nucleo-f746zg/scripts/user-space.ld
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* NOTE: This depends on the memory.ld script having been included prior to
* this script.
*/
OUTPUT_ARCH(arm)
SECTIONS
{
.userspace : {
*(.userspace)
} > uflash
.text : {
_stext = ABSOLUTE(.);
*(.text .text.*)
*(.fixup)
*(.gnu.warning)
*(.rodata .rodata.*)
*(.gnu.linkonce.t.*)
*(.glue_7)
*(.glue_7t)
*(.got)
*(.gcc_except_table)
*(.gnu.linkonce.r.*)
_etext = ABSOLUTE(.);
} > uflash
.init_section : {
_sinit = ABSOLUTE(.);
KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors))
_einit = ABSOLUTE(.);
} > uflash
.ARM.extab : {
*(.ARM.extab*)
} > uflash
__exidx_start = ABSOLUTE(.);
.ARM.exidx : {
*(.ARM.exidx*)
} > uflash
__exidx_end = ABSOLUTE(.);
_eronly = ABSOLUTE(.);
.data : {
_sdata = ABSOLUTE(.);
*(.data .data.*)
*(.gnu.linkonce.d.*)
CONSTRUCTORS
. = ALIGN(4);
_edata = ABSOLUTE(.);
} > usram AT > uflash
.bss : {
_sbss = ABSOLUTE(.);
*(.bss .bss.*)
*(.gnu.linkonce.b.*)
*(COMMON)
. = ALIGN(4);
_ebss = ABSOLUTE(.);
} > usram
/* Stabs debugging sections */
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.stab.excl 0 : { *(.stab.excl) }
.stab.exclstr 0 : { *(.stab.exclstr) }
.stab.index 0 : { *(.stab.index) }
.stab.indexstr 0 : { *(.stab.indexstr) }
.comment 0 : { *(.comment) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_info 0 : { *(.debug_info) }
.debug_line 0 : { *(.debug_line) }
.debug_pubnames 0 : { *(.debug_pubnames) }
.debug_aranges 0 : { *(.debug_aranges) }
}

93
boards/arm/stm32f7/nucleo-f746zg/src/CMakeLists.txt Normal file
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@ -0,0 +1,93 @@
# ##############################################################################
# boards/arm/stm32f7/nucleo-f746zg/src/CMakeLists.txt
#
# Licensed to the Apache Software Foundation (ASF) under one or more contributor
# license agreements. See the NOTICE file distributed with this work for
# additional information regarding copyright ownership. The ASF licenses this
# file to you under the Apache License, Version 2.0 (the "License"); you may not
# use this file except in compliance with the License. You may obtain a copy of
# the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
# License for the specific language governing permissions and limitations under
# the License.
#
# ##############################################################################
set(SRCS stm32_boot.c stm32_bringup.c)
if(CONFIG_ARCH_LEDS)
list(APPEND SRCS stm32_autoleds.c)
else()
list(APPEND SRCS stm32_userleds.c)
endif()
if(CONFIG_ARCH_BUTTONS)
list(APPEND SRCS stm32_buttons.c)
endif()
if(CONFIG_BOARDCTL)
list(APPEND SRCS stm32_appinitialize.c)
endif()
if(CONFIG_DEV_GPIO)
list(APPEND SRCS stm32_gpio.c)
endif()
if(CONFIG_SPI)
list(APPEND SRCS stm32_spi.c)
endif()
if(CONFIG_ADC)
list(APPEND SRCS stm32_adc.c)
endif()
if(CONFIG_PWM)
list(APPEND SRCS stm32_pwm.c)
endif()
if(CONFIG_MMCSD)
list(APPEND SRCS stm32_sdio.c)
endif()
if(CONFIG_STM32F7_OTGFS)
list(APPEND SRCS stm32_usb.c)
endif()
if(CONFIG_STM32F7_BBSRAM)
list(APPEND SRCS stm32_bbsram.c)
endif()
if(CONFIG_BOARDCTL_RESET)
list(APPEND SRCS stm32_reset.c)
endif()
if(CONFIG_STM32_ROMFS)
list(APPEND SRCS stm32_romfs_initialize.c)
endif()
if(CONFIG_SENSORS_QENCODER)
list(APPEND SRCS stm32_qencoder.c)
endif()
if(CONFIG_STM32F7_CAN)
if(CONFIG_STM32F7_CAN_CHARDRIVER)
list(APPEND SRCS stm32_can.c)
endif()
if(CONFIG_STM32F7_CAN_SOCKET)
list(APPEND SRCS stm32_cansock.c)
endif()
endif()
if(CONFIG_USBDEV_COMPOSITE)
list(APPEND SRCS stm32_composite.c)
endif()
target_sources(board PRIVATE ${SRCS})
set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/flash.ld")
endif()

94
boards/arm/stm32f7/nucleo-f746zg/src/Make.defs Normal file
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@ -0,0 +1,94 @@
############################################################################
# boards/arm/stm32f7/nucleo-f746zg/src/Make.defs
#
# Licensed to the Apache Software Foundation (ASF) under one or more
# contributor license agreements. See the NOTICE file distributed with
# this work for additional information regarding copyright ownership. The
# ASF licenses this file to you under the Apache License, Version 2.0 (the
# "License"); you may not use this file except in compliance with the
# License. You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
# License for the specific language governing permissions and limitations
# under the License.
#
############################################################################
include $(TOPDIR)/Make.defs
CSRCS = stm32_boot.c stm32_bringup.c
ifeq ($(CONFIG_ARCH_LEDS),y)
CSRCS += stm32_autoleds.c
else
CSRCS += stm32_userleds.c
endif
ifeq ($(CONFIG_ARCH_BUTTONS),y)
CSRCS += stm32_buttons.c
endif
ifeq ($(CONFIG_BOARDCTL),y)
CSRCS += stm32_appinitialize.c
endif
ifeq ($(CONFIG_DEV_GPIO),y)
CSRCS += stm32_gpio.c
endif
ifeq ($(CONFIG_SPI),y)
CSRCS += stm32_spi.c
endif
ifeq ($(CONFIG_ADC),y)
CSRCS += stm32_adc.c
endif
ifeq ($(CONFIG_PWM),y)
CSRCS += stm32_pwm.c
endif
ifeq ($(CONFIG_MMCSD),y)
CSRCS += stm32_sdio.c
endif
ifeq ($(CONFIG_STM32F7_OTGFS),y)
CSRCS += stm32_usb.c
endif
ifeq ($(CONFIG_STM32F7_BBSRAM),y)
CSRCS += stm32_bbsram.c
endif
ifeq ($(CONFIG_BOARDCTL_RESET),y)
CSRCS += stm32_reset.c
endif
ifeq ($(CONFIG_STM32_ROMFS),y)
CSRCS += stm32_romfs_initialize.c
endif
ifeq ($(CONFIG_SENSORS_QENCODER),y)
CSRCS += stm32_qencoder.c
endif
ifeq ($(CONFIG_STM32F7_CAN),y)
ifeq ($(CONFIG_STM32F7_CAN_CHARDRIVER),y)
CSRCS += stm32_can.c
endif
ifeq ($(CONFIG_STM32F7_CAN_SOCKET),y)
CSRCS += stm32_cansock.c
endif
endif
ifeq ($(CONFIG_USBDEV_COMPOSITE),y)
CSRCS += stm32_composite.c
endif
DEPPATH += --dep-path board
VPATH += :board
CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board

353
boards/arm/stm32f7/nucleo-f746zg/src/nucleo-f746zg.h Normal file
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@ -0,0 +1,353 @@
/****************************************************************************
* boards/arm/stm32f7/nucleo-f746zg/src/nucleo-f746zg.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __BOARDS_ARM_STM32F7_NUCLEO_F746ZG_SRC_NUCLEO_F746ZG_H
#define __BOARDS_ARM_STM32F7_NUCLEO_F746ZG_SRC_NUCLEO_F746ZG_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/compiler.h>
#include <stdint.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Configuration ************************************************************/
/* procfs File System */
#ifdef CONFIG_FS_PROCFS
# ifdef CONFIG_NSH_PROC_MOUNTPOINT
# define STM32_PROCFS_MOUNTPOINT CONFIG_NSH_PROC_MOUNTPOINT
# else
# define STM32_PROCFS_MOUNTPOINT "/proc"
# endif
#endif
/* nucleo-f746zg GPIO Pin Definitions ***************************************/
/* LED
*
* The nucleo-f746zg board has numerous LEDs but only three, LD1 a Green LED,
* LD2 a Blue LED and LD3 a Red LED, that can be controlled by software.
* The following definitions assume the default Solder Bridges are installed.
*/
#define GPIO_LD1 (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_50MHz | GPIO_OUTPUT_CLEAR | \
GPIO_PORTB | GPIO_PIN0)
#define GPIO_LD2 (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_50MHz | GPIO_OUTPUT_CLEAR | \
GPIO_PORTB | GPIO_PIN7)
#define GPIO_LD3 (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_50MHz | GPIO_OUTPUT_CLEAR | \
GPIO_PORTB | GPIO_PIN14)
#define GPIO_LED_GREEN GPIO_LD1
#define GPIO_LED_BLUE GPIO_LD2
#define GPIO_LED_RED GPIO_LD3
#define LED_DRIVER_PATH "/dev/userleds"
/* BUTTONS
*
* The Blue pushbutton B1, labeled "User", is connected to GPIO PC13.
* A high value will be sensed when the button is depressed.
* Note:
* 1) That the EXTI is included in the definition to enable an interrupt
* on this IO.
* 2) The following definitions assume the default Solder Bridges are
* installed.
*/
#define GPIO_BTN_USER (GPIO_INPUT | GPIO_FLOAT | GPIO_EXTI | GPIO_PORTC | GPIO_PIN13)
/* SPI **********************************************************************/
#define GPIO_SPI_CS (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_50MHz | \
GPIO_OUTPUT_SET)
#define GPIO_SPI1_CS0 (GPIO_SPI_CS | GPIO_PORTA | GPIO_PIN15)
#define GPIO_SPI1_CS1 (GPIO_SPI_CS | GPIO_PORTC | GPIO_PIN15)
#define GPIO_SPI1_CS2 (GPIO_SPI_CS | GPIO_PORTC | GPIO_PIN14)
#define GPIO_SPI1_CS3 (GPIO_SPI_CS | GPIO_PORTC | GPIO_PIN2)
#define GPIO_SPI2_CS0 (GPIO_SPI_CS | GPIO_PORTD | GPIO_PIN7)
#define GPIO_SPI2_CS1 (GPIO_SPI_CS | GPIO_PORTG | GPIO_PIN1)
#define GPIO_SPI2_CS2 (GPIO_SPI_CS | GPIO_PORTG | GPIO_PIN2)
#define GPIO_SPI2_CS3 (GPIO_SPI_CS | GPIO_PORTG | GPIO_PIN3)
#define GPIO_SPI3_CS0 (GPIO_SPI_CS | GPIO_PORTG | GPIO_PIN4)
#define GPIO_SPI3_CS1 (GPIO_SPI_CS | GPIO_PORTG | GPIO_PIN5)
#define GPIO_SPI3_CS2 (GPIO_SPI_CS | GPIO_PORTG | GPIO_PIN6)
#define GPIO_SPI3_CS3 (GPIO_SPI_CS | GPIO_PORTG | GPIO_PIN7)
#if defined(CONFIG_STM32F7_SDMMC1) || defined(CONFIG_STM32F7_SDMMC2)
# define HAVE_SDIO
#endif
#if defined(CONFIG_DISABLE_MOUNTPOINT) || !defined(CONFIG_MMCSD_SDIO)
# undef HAVE_SDIO
#endif
#define SDIO_SLOTNO 0 /* Only one slot */
#ifdef HAVE_SDIO
# if defined(CONFIG_STM32F7_SDMMC1)
# define GPIO_SDMMC1_NCD (GPIO_INPUT|GPIO_FLOAT|GPIO_EXTI | GPIO_PORTC | GPIO_PIN6)
# endif
# if defined(CONFIG_NSH_MMCSDSLOTNO) && (CONFIG_NSH_MMCSDSLOTNO != 0)
# warning "Only one MMC/SD slot, slot 0"
# define CONFIG_NSH_MMCSDSLOTNO SDIO_SLOTNO
# endif
# if defined(CONFIG_NSH_MMCSDMINOR)
# define SDIO_MINOR CONFIG_NSH_MMCSDMINOR
# else
# define SDIO_MINOR 0
# endif
#endif
/* USB OTG FS
*
* PA9 OTG_FS_VBUS VBUS sensing (also connected to the green LED)
* PC0 OTG_FS_PowerSwitchOn
* PD5 OTG_FS_Overcurrent
*/
#define GPIO_OTGFS_VBUS (GPIO_INPUT|GPIO_FLOAT|GPIO_SPEED_100MHz|\
GPIO_OPENDRAIN|GPIO_PORTA|GPIO_PIN9)
#define GPIO_OTGFS_PWRON (GPIO_OUTPUT|GPIO_FLOAT|GPIO_SPEED_100MHz|\
GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN6)
#ifdef CONFIG_USBHOST
# define GPIO_OTGFS_OVER (GPIO_INPUT|GPIO_EXTI|GPIO_FLOAT|\
GPIO_SPEED_100MHz|GPIO_PUSHPULL|\
GPIO_PORTG|GPIO_PIN7)
#else
# define GPIO_OTGFS_OVER (GPIO_INPUT|GPIO_FLOAT|GPIO_SPEED_100MHz|\
GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN7)
#endif
/* GPIO pins used by the GPIO Subsystem */
#define BOARD_NGPIOIN 4 /* Amount of GPIO Input pins */
#if defined(CONFIG_STM32F7_TIM1_CH1NOUT) && defined (CONFIG_STM32F7_TIM1_CH2NOUT)
#define BOARD_NGPIOOUT 8 /* Amount of GPIO Output pins */
#elif defined(CONFIG_STM32F7_TIM1_CH1NOUT) || defined (CONFIG_STM32F7_TIM1_CH2NOUT)
#define BOARD_NGPIOOUT 9 /* Amount of GPIO Output pins */
#else
#define BOARD_NGPIOOUT 10 /* Amount of GPIO Output pins */
#endif
#define BOARD_NGPIOINT 1 /* Amount of GPIO Input w/ Interruption pins */
#define GPIO_INT1 (GPIO_INPUT | GPIO_FLOAT | GPIO_PORTB | GPIO_PIN2)
#define GPIO_IN1 (GPIO_INPUT | GPIO_FLOAT | GPIO_PORTE | GPIO_PIN7)
#define GPIO_IN2 (GPIO_INPUT | GPIO_FLOAT | GPIO_PORTE | GPIO_PIN12)
#define GPIO_IN3 (GPIO_INPUT | GPIO_FLOAT | GPIO_PORTE | GPIO_PIN14)
#define GPIO_IN4 (GPIO_INPUT | GPIO_FLOAT | GPIO_PORTE | GPIO_PIN15)
#define GPIO_OUT1 (GPIO_OUTPUT | GPIO_SPEED_50MHz | \
GPIO_OUTPUT_SET | GPIO_PORTE | GPIO_PIN4)
#define GPIO_OUT2 (GPIO_OUTPUT | GPIO_SPEED_50MHz | \
GPIO_OUTPUT_SET | GPIO_PORTE | GPIO_PIN5)
#define GPIO_OUT3 (GPIO_OUTPUT | GPIO_SPEED_50MHz | \
GPIO_OUTPUT_SET | GPIO_PORTE | GPIO_PIN6)
#define GPIO_OUT4 (GPIO_OUTPUT | GPIO_SPEED_50MHz | \
GPIO_OUTPUT_SET | GPIO_PORTA |GPIO_PIN5)
#define GPIO_OUT5 (GPIO_OUTPUT | GPIO_SPEED_50MHz | \
GPIO_OUTPUT_SET | GPIO_PORTF | GPIO_PIN12)
#if !defined(CONFIG_STM32F7_TIM1_CH1NOUT)
#define GPIO_OUT6 (GPIO_OUTPUT | GPIO_SPEED_50MHz | \
GPIO_OUTPUT_SET | GPIO_PORTE | GPIO_PIN8)
#endif
#if !defined(CONFIG_STM32F7_TIM1_CH2NOUT)
#define GPIO_OUT7 (GPIO_OUTPUT | GPIO_SPEED_50MHz | \
GPIO_OUTPUT_SET | GPIO_PORTE | GPIO_PIN10)
#endif
/****************************************************************************
* Public Data
****************************************************************************/
#ifndef __ASSEMBLY__
/****************************************************************************
* Public Functions Definitions
****************************************************************************/
/****************************************************************************
* Name: stm32_bringup
*
* Description:
* Perform architecture specific initialization
*
* CONFIG_BOARDCTL=y:
* If CONFIG_NSH_ARCHINITIALIZE=y:
* Called from the NSH library (or other application)
* Otherwise, assumed to be called from some other application.
*
* Otherwise CONFIG_BOARD_LATE_INITIALIZE=y:
* Called from board_late_initialize().
*
* Otherwise, bad news: Never called
*
****************************************************************************/
int stm32_bringup(void);
/****************************************************************************
* Name: stm32_spidev_initialize
*
* Description:
* Called to configure SPI chip select GPIO pins for the nucleo-f746zg
* board.
*
****************************************************************************/
#if defined(CONFIG_SPI)
void stm32_spidev_initialize(void);
#endif
/****************************************************************************
* Name: stm32_spidev_bus_test
*
* Description:
* Called to create the defined SPI buses and test them by initializing
* them and sending the NUCLEO_SPI_TEST (no chip select).
*
****************************************************************************/
#if defined(CONFIG_NUCLEO_F722ZE_SPI_TEST)
int stm32_spidev_bus_test(void);
#endif
/****************************************************************************
* Name: stm32_dma_alloc_init
*
* Description:
* Called to create a FAT DMA allocator
*
* Returned Value:
* 0 on success or -ENOMEM
*
****************************************************************************/
void stm32_dma_alloc_init(void);
#if defined (CONFIG_FAT_DMAMEMORY)
int stm32_dma_alloc_init(void);
#endif
/****************************************************************************
* Name: stm32_sdio_initialize
*
* Description:
* Called at application startup time to initialize the SCMMC
* functionality.
*
****************************************************************************/
#ifdef CONFIG_MMCSD
int stm32_sdio_initialize(void);
#endif
/****************************************************************************
* Name: stm32_usbinitialize
*
* Description:
* Called from stm32_usbinitialize very early in inialization to setup
* USB-related GPIO pins for the nucleo-f746zg board.
*
****************************************************************************/
#ifdef CONFIG_STM32F7_OTGFS
void stm32_usbinitialize(void);
#endif
/****************************************************************************
* Name: stm32_pwm_setup
*
* Description:
* Initialize PWM and register the PWM device.
*
****************************************************************************/
#ifdef CONFIG_PWM
int stm32_pwm_setup(void);
#endif
/****************************************************************************
* Name: stm32_adc_setup
*
* Description:
* Initialize ADC and register the ADC driver.
*
****************************************************************************/
#ifdef CONFIG_ADC
int stm32_adc_setup(void);
#endif
/****************************************************************************
* Name: stm32_bbsram_int
****************************************************************************/
#ifdef CONFIG_STM32F7_BBSRAM
int stm32_bbsram_int(void);
#endif
/****************************************************************************
* Name: stm32_qencoder_initialize
****************************************************************************/
#ifdef CONFIG_SENSORS_QENCODER
int stm32_qencoder_initialize(const char *devpath, int timer);
#endif
/****************************************************************************
* Name: stm32_can_setup
****************************************************************************/
#ifdef CONFIG_STM32F7_CAN_CHARDRIVER
int stm32_can_setup(void);
#endif
/****************************************************************************
* Name: stm32_cansock_setup
****************************************************************************/
#ifdef CONFIG_STM32F7_CAN_SOCKET
int stm32_cansock_setup(void);
#endif
/****************************************************************************
* Name: stm32f7_gpio_initialize
****************************************************************************/
#ifdef CONFIG_DEV_GPIO
int stm32_gpio_initialize(void);
#endif
#endif /* __ASSEMBLY__ */
#endif /* __BOARDS_ARM_STM32F7_NUCLEO_F746ZG_SRC_NUCLEO_F746ZG_H */

169
boards/arm/stm32f7/nucleo-f746zg/src/stm32_adc.c Normal file
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/****************************************************************************
* boards/arm/stm32f7/nucleo-f746zg/src/stm32_adc.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <errno.h>
#include <debug.h>
#include <nuttx/board.h>
#include <nuttx/analog/adc.h>
#include <arch/board/board.h>
#include "chip.h"
#include "stm32_gpio.h"
#include "stm32_adc.h"
#include "nucleo-f746zg.h"
#ifdef CONFIG_ADC
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Configuration ************************************************************/
/* Up to 3 ADC interfaces are supported */
#if STM32F7_NADC < 3
# undef CONFIG_STM32F7_ADC3
#endif
#if STM32F7_NADC < 2
# undef CONFIG_STM32F7_ADC2
#endif
#if STM32F7_NADC < 1
# undef CONFIG_STM32F7_ADC1
#endif
#if defined(CONFIG_STM32F7_ADC1) || defined(CONFIG_STM32F7_ADC2) || defined(CONFIG_STM32F7_ADC3)
#ifndef CONFIG_STM32F7_ADC1
# warning "Channel information only available for ADC1"
#endif
/* The number of ADC channels in the conversion list */
/* #define ADC1_NCHANNELS 14 */
#define ADC1_NCHANNELS 4
/****************************************************************************
* Private Data
****************************************************************************/
/* Identifying number of each ADC channel: Variable Resistor.
*
* {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 15};
*/
#ifdef CONFIG_STM32F7_ADC1
static const uint8_t g_chanlist[ADC1_NCHANNELS] =
{
3, 4, 10, 13
};
/* Configurations of pins used byte each ADC channels
*
* {GPIO_ADC1_IN1, GPIO_ADC1_IN2, GPIO_ADC1_IN3,
* GPIO_ADC1_IN4, GPIO_ADC1_IN5, GPIO_ADC1_IN6,
* GPIO_ADC1_IN7, GPIO_ADC1_IN8, GPIO_ADC1_IN9,
* GPIO_ADC1_IN10, GPIO_ADC1_IN11, GPIO_ADC1_IN12,
* GPIO_ADC1_IN13, GPIO_ADC1_IN15};
*/
static const uint32_t g_pinlist[ADC1_NCHANNELS] =
{
GPIO_ADC1_IN3, GPIO_ADC1_IN4, GPIO_ADC1_IN10, GPIO_ADC1_IN13
};
#endif
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: stm32_adc_setup
*
* Description:
* Initialize ADC and register the ADC driver.
*
****************************************************************************/
int stm32_adc_setup(void)
{
#ifdef CONFIG_STM32F7_ADC1
static bool initialized = false;
struct adc_dev_s *adc;
int ret;
int i;
/* Check if we have already initialized */
if (!initialized)
{
/* Configure the pins as analog inputs for the selected channels */
for (i = 0; i < ADC1_NCHANNELS; i++)
{
if (g_pinlist[i] != 0)
{
stm32_configgpio(g_pinlist[i]);
}
}
/* Call stm32_adcinitialize() to get an instance of the ADC interface */
adc = stm32_adc_initialize(1, g_chanlist, ADC1_NCHANNELS);
if (adc == NULL)
{
aerr("ERROR: Failed to get ADC interface\n");
return -ENODEV;
}
/* Register the ADC driver at "/dev/adc0" */
ret = adc_register("/dev/adc0", adc);
if (ret < 0)
{
aerr("ERROR: adc_register failed: %d\n", ret);
return ret;
}
/* Now we are initialized */
initialized = true;
}
return OK;
#else
return -ENOSYS;
#endif
}
#endif /* CONFIG_STM32F7_ADC1 || CONFIG_STM32F7_ADC2 || CONFIG_STM32F7_ADC3 */
#endif /* CONFIG_ADC */

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boards/arm/stm32f7/nucleo-f746zg/src/stm32_appinitialize.c Normal file
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/****************************************************************************
* boards/arm/stm32f7/nucleo-f746zg/src/stm32_appinitialize.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <sys/types.h>
#include "nucleo-f746zg.h"
#ifdef CONFIG_BOARDCTL
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: board_app_initialize
*
* Description:
* Perform application specific initialization. This function is never
* called directly from application code, but only indirectly via the
* (non-standard) boardctl() interface using the command BOARDIOC_INIT.
*
* Input Parameters:
* arg - The boardctl() argument is passed to the board_app_initialize()
* implementation without modification. The argument has no
* meaning to NuttX; the meaning of the argument is a contract
* between the board-specific initialization logic and the
* matching application logic. The value could be such things as a
* mode enumeration value, a set of DIP switch switch settings, a
* pointer to configuration data read from a file or serial FLASH,
* or whatever you would like to do with it. Every implementation
* should accept zero/NULL as a default configuration.
*
* Returned Value:
* Zero (OK) is returned on success; a negated errno value is returned on
* any failure to indicate the nature of the failure.
*
****************************************************************************/
int board_app_initialize(uintptr_t arg)
{
#ifndef CONFIG_BOARD_LATE_INITIALIZE
/* Perform board-specific initialization */
return stm32_bringup();
#else
return OK;
#endif
}
#endif

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/****************************************************************************
* boards/arm/stm32f7/nucleo-f746zg/src/stm32_autoleds.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdbool.h>
#include <debug.h>
#include <sys/param.h>
#include <nuttx/board.h>
#include <arch/board/board.h>
#include "stm32_gpio.h"
#include "nucleo-f746zg.h"
#ifdef CONFIG_ARCH_LEDS
/****************************************************************************
* Private Data
****************************************************************************/
/* Indexed by BOARD_LED_<color> */
static const uint32_t g_ledmap[BOARD_NLEDS] =
{
GPIO_LED_GREEN,
GPIO_LED_BLUE,
GPIO_LED_RED,
};
static bool g_initialized;
/****************************************************************************
* Private Functions
****************************************************************************/
static void phy_set_led(int led, bool state)
{
/* Active High */
stm32_gpiowrite(g_ledmap[led], state);
}
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: board_autoled_initialize
****************************************************************************/
void board_autoled_initialize(void)
{
int i;
/* Configure the LD1 GPIO for output. Initial state is OFF */
for (i = 0; i < nitems(g_ledmap); i++)
{
stm32_configgpio(g_ledmap[i]);
}
}
/****************************************************************************
* Name: board_autoled_on
****************************************************************************/
void board_autoled_on(int led)
{
switch (led)
{
default:
break;
case LED_HEAPALLOCATE:
phy_set_led(BOARD_LED_BLUE, true);
break;
case LED_IRQSENABLED:
phy_set_led(BOARD_LED_BLUE, false);
phy_set_led(BOARD_LED_GREEN, true);
break;
case LED_STACKCREATED:
phy_set_led(BOARD_LED_GREEN, true);
phy_set_led(BOARD_LED_BLUE, true);
g_initialized = true;
break;
case LED_INIRQ:
phy_set_led(BOARD_LED_BLUE, true);
break;
case LED_SIGNAL:
phy_set_led(BOARD_LED_GREEN, true);
break;
case LED_ASSERTION:
phy_set_led(BOARD_LED_RED, true);
phy_set_led(BOARD_LED_BLUE, true);
break;
case LED_PANIC:
phy_set_led(BOARD_LED_RED, true);
break;
case LED_IDLE : /* IDLE */
phy_set_led(BOARD_LED_RED, true);
break;
}
}
/****************************************************************************
* Name: board_autoled_off
****************************************************************************/
void board_autoled_off(int led)
{
switch (led)
{
default:
break;
case LED_SIGNAL:
phy_set_led(BOARD_LED_GREEN, false);
break;
case LED_INIRQ:
phy_set_led(BOARD_LED_BLUE, false);
break;
case LED_ASSERTION:
phy_set_led(BOARD_LED_RED, false);
phy_set_led(BOARD_LED_BLUE, false);
break;
case LED_PANIC:
phy_set_led(BOARD_LED_RED, false);
break;
case LED_IDLE : /* IDLE */
phy_set_led(BOARD_LED_RED, false);
break;
}
}
#endif /* CONFIG_ARCH_LEDS */

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/****************************************************************************
* boards/arm/stm32f7/nucleo-f746zg/src/stm32_bbsram.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <sys/ioctl.h>
#include <stdint.h>
#include <stddef.h>
#include <stdlib.h>
#include <fcntl.h>
#include <string.h>
#include <assert.h>
#include <errno.h>
#include <debug.h>
#include <syslog.h>
#include <sys/param.h>
#include <nuttx/fs/fs.h>
#include "arm_internal.h"
#include "stm32_bbsram.h"
#include "nucleo-f746zg.h"
#ifdef CONFIG_STM32F7_BBSRAM
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Configuration ************************************************************/
#define FREEZE_STR(s) #s
#define STRINGIFY(s) FREEZE_STR(s)
#define HARDFAULT_FILENO 3
#define HARDFAULT_PATH BBSRAM_PATH""STRINGIFY(HARDFAULT_FILENO)
#define HARDFAULT_REBOOT_ FILENO 0
#define HARDFAULT_REBOOT_PATH BBSRAM_PATH""STRINGIFY(HARDFAULT_REBOOT_FILENO)
#define BBSRAM_SIZE_FN0 (sizeof(int))
#define BBSRAM_SIZE_FN1 384
#define BBSRAM_SIZE_FN2 384
#define BBSRAM_SIZE_FN3 - 1
/* The following guides in the amount of the user and interrupt stack
* data we can save. The amount of storage left will dictate the actual
* number of entries of the user stack data saved. If it is too big
* It will be truncated by the call to stm32_bbsram_savepanic
*/
#define BBSRAM_HEADER_SIZE 20 /* This is an assumption */
#define BBSRAM_USED ((4*BBSRAM_HEADER_SIZE)+ \
(BBSRAM_SIZE_FN0+BBSRAM_SIZE_FN1+ \
BBSRAM_SIZE_FN2))
#define BBSRAM_REAMINING (STM32F7_BBSRAM_SIZE-BBSRAM_USED)
#if CONFIG_ARCH_INTERRUPTSTACK <= 3
# define BBSRAM_NUMBER_STACKS 1
#else
# define BBSRAM_NUMBER_STACKS 2
#endif
#define BBSRAM_FIXED_ELEMENTS_SIZE (sizeof(info_t))
#define BBSRAM_LEFTOVER (BBSRAM_REAMINING-\
BBSRAM_FIXED_ELEMENTS_SIZE)
#define CONFIG_ISTACK_SIZE (BBSRAM_LEFTOVER/BBSRAM_NUMBER_STACKS/ \
sizeof(stack_word_t))
#define CONFIG_USTACK_SIZE (BBSRAM_LEFTOVER/BBSRAM_NUMBER_STACKS/ \
sizeof(stack_word_t))
/* The path to the Battery Backed up SRAM */
#define BBSRAM_PATH "/fs/bbr"
/* The sizes of the files to create (-1) use rest of BBSRAM memory */
#define BSRAM_FILE_SIZES \
{ \
BBSRAM_SIZE_FN0, \
BBSRAM_SIZE_FN1, \
BBSRAM_SIZE_FN2, \
BBSRAM_SIZE_FN3, \
0 \
}
/* For Assert keep this much of the file name */
#define MAX_FILE_PATH_LENGTH 40
#define HEADER_TIME_FMT "%Y-%m-%d-%H:%M:%S"
#define HEADER_TIME_FMT_NUM (2+ 0+ 0+ 0+ 0+ 0)
#define HEADER_TIME_FMT_LEN (((nitems(HEADER_TIME_FMT)-1) + \
HEADER_TIME_FMT_NUM))
/****************************************************************************
* Private Data
****************************************************************************/
/* Used for stack frame storage */
typedef uint32_t stack_word_t;
/* Stack related data */
typedef struct
{
uint32_t sp;
uint32_t top;
uint32_t size;
} _stack_t;
typedef struct
{
_stack_t user;
#if CONFIG_ARCH_INTERRUPTSTACK > 3
_stack_t interrupt;
#endif
} stacks_t;
/* Not Used for reference only */
typedef struct
{
uint32_t r0;
uint32_t r1;
uint32_t r2;
uint32_t r3;
uint32_t r4;
uint32_t r5;
uint32_t r6;
uint32_t r7;
uint32_t r8;
uint32_t r9;
uint32_t r10;
uint32_t r11;
uint32_t r12;
uint32_t sp;
uint32_t lr;
uint32_t pc;
uint32_t xpsr;
uint32_t d0;
uint32_t d1;
uint32_t d2;
uint32_t d3;
uint32_t d4;
uint32_t d5;
uint32_t d6;
uint32_t d7;
uint32_t d8;
uint32_t d9;
uint32_t d10;
uint32_t d11;
uint32_t d12;
uint32_t d13;
uint32_t d14;
uint32_t d15;
uint32_t fpscr;
uint32_t sp_main;
uint32_t sp_process;
uint32_t apsr;
uint32_t ipsr;
uint32_t epsr;
uint32_t primask;
uint32_t basepri;
uint32_t faultmask;
uint32_t control;
uint32_t s0;
uint32_t s1;
uint32_t s2;
uint32_t s3;
uint32_t s4;
uint32_t s5;
uint32_t s6;
uint32_t s7;
uint32_t s8;
uint32_t s9;
uint32_t s10;
uint32_t s11;
uint32_t s12;
uint32_t s13;
uint32_t s14;
uint32_t s15;
uint32_t s16;
uint32_t s17;
uint32_t s18;
uint32_t s19;
uint32_t s20;
uint32_t s21;
uint32_t s22;
uint32_t s23;
uint32_t s24;
uint32_t s25;
uint32_t s26;
uint32_t s27;
uint32_t s28;
uint32_t s29;
uint32_t s30;
uint32_t s31;
} proc_regs_t;
/* Flags to identify what is in the dump */
typedef enum
{
REGS_PRESENT = 0x01,
USERSTACK_PRESENT = 0x02,
INTSTACK_PRESENT = 0x04,
INVALID_USERSTACK_PTR = 0x20,
INVALID_INTSTACK_PTR = 0x40,
} fault_flags_t;
typedef struct
{
fault_flags_t flags; /* What is in the dump */
uintptr_t current_regs; /* Used to validate the dump */
int lineno; /* __LINE__ to up_assert */
int pid; /* Process ID */
uint32_t regs[XCPTCONTEXT_REGS]; /* Interrupt register save area */
stack_t stacks; /* Stack info */
char name[CONFIG_TASK_NAME_SIZE + 1]; /* Task name (with NULL
* terminator) */
char filename[MAX_FILE_PATH_LENGTH]; /* the Last of chars in
* __FILE__ to up_assert */
} info_t;
typedef struct
{
info_t info; /* The info */
#if CONFIG_ARCH_INTERRUPTSTACK > 3
/* The amount of stack data is compile time
* sized backed on what is left after the
* other BBSRAM files are defined
* The order is such that only the
* ustack should be truncated
*/
stack_word_t istack[CONFIG_USTACK_SIZE];
#endif
stack_word_t ustack[CONFIG_ISTACK_SIZE];
} fullcontext_t;
/****************************************************************************
* Private Data
****************************************************************************/
static uint8_t g_sdata[STM32F7_BBSRAM_SIZE];
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: hardfault_get_desc
****************************************************************************/
static int hardfault_get_desc(struct bbsramd_s *desc)
{
struct file filestruct;
int ret;
ret = file_open(&filestruct, HARDFAULT_PATH, O_RDONLY);
if (ret < 0)
{
syslog(LOG_INFO, "stm32 bbsram: Failed to open Fault Log file [%s] "
"(%d)\n", HARDFAULT_PATH, ret);
}
else
{
ret = file_ioctl(&filestruct, STM32F7_BBSRAM_GETDESC_IOCTL,
(unsigned long)((uintptr_t)desc));
file_close(&filestruct);
if (ret < 0)
{
syslog(LOG_INFO, "stm32 bbsram: Failed to get Fault Log "
"descriptor (%d)\n", ret);
}
}
return ret;
}
/****************************************************************************
* Name: copy_reverse
****************************************************************************/
#if defined(CONFIG_STM32F7_SAVE_CRASHDUMP)
static void copy_reverse(stack_word_t *dest, stack_word_t *src, int size)
{
while (size--)
{
*dest++ = *src--;
}
}
#endif /* CONFIG_STM32F7_SAVE_CRASHDUMP */
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: stm32_bbsram_int
****************************************************************************/
int stm32_bbsram_int(void)
{
int filesizes[CONFIG_STM32F7_BBSRAM_FILES + 1] = BSRAM_FILE_SIZES;
char buf[HEADER_TIME_FMT_LEN + 1];
struct bbsramd_s desc;
int rv;
int state;
struct tm tt;
time_t time_sec;
/* Using Battery Backed Up SRAM */
stm32_bbsraminitialize(BBSRAM_PATH, filesizes);
#if defined(CONFIG_STM32F7_SAVE_CRASHDUMP)
/* Panic Logging in Battery Backed Up Files */
/* Do we have an hard fault in BBSRAM? */
rv = hardfault_get_desc(&desc);
if (rv >= OK)
{
syslog(LOG_EMERG, "There is a hard fault logged.\n");
state = (desc.lastwrite.tv_sec || desc.lastwrite.tv_nsec) ? OK : 1;
syslog(LOG_INFO, "Fault Log info File No %d Length %d flags:0x%02x "
"state:%d\n", (unsigned int)desc.fileno, (unsigned int)desc.len,
(unsigned int)desc.flags, state);
if (state == OK)
{
time_sec = desc.lastwrite.tv_sec + (desc.lastwrite.tv_nsec / 1e9);
gmtime_r(&time_sec, &tt);
strftime(buf, HEADER_TIME_FMT_LEN , HEADER_TIME_FMT , &tt);
syslog(LOG_INFO, "Fault Logged on %s - Valid\n", buf);
}
rv = nx_unlink(HARDFAULT_PATH);
if (rv < 0)
{
syslog(LOG_INFO, "stm32 bbsram: Failed to unlink Fault Log file"
" [%s] (%d)\n", HARDFAULT_PATH, rv);
}
}
#endif /* CONFIG_STM32F7_SAVE_CRASHDUMP */
return rv;
}
/****************************************************************************
* Name: board_crashdump
****************************************************************************/
#if defined(CONFIG_STM32F7_SAVE_CRASHDUMP)
void board_crashdump(uintptr_t sp, struct tcb_s *tcb,
const char *filename, int lineno,
const char *msg, void *regs)
{
fullcontext_t *pdump = (fullcontext_t *)&g_sdata;
int rv;
enter_critical_section();
/* Zero out everything */
memset(pdump, 0, sizeof(fullcontext_t));
/* Save Info */
pdump->info.lineno = lineno;
if (filename)
{
int offset = 0;
unsigned int len = strlen((char *)filename) + 1;
if (len > sizeof(pdump->info.filename))
{
offset = len - sizeof(pdump->info.filename);
}
strlcpy(pdump->info.filename, (char *)&filename[offset],
sizeof(pdump->info.filename));
}
/* Save the value of the pointer for current_regs as debugging info.
* It should be NULL in case of an ASSERT and will aid in cross
* checking the validity of system memory at the time of the
* fault.
*/
pdump->info.current_regs = (uintptr_t)up_current_regs();
/* Save Context */
strlcpy(pdump->info.name, get_task_name(tcb), sizeof(pdump->info.name));
pdump->info.pid = tcb->pid;
if (up_interrupt_context())
{
pdump->info.stacks.interrupt.sp = sp;
pdump->info.flags |= (REGS_PRESENT | USERSTACK_PRESENT |
INTSTACK_PRESENT);
memcpy(pdump->info.regs, up_current_regs(),
sizeof(pdump->info.regs));
pdump->info.stacks.user.sp = pdump->info.regs[REG_R13];
}
else
{
/* users context */
pdump->info.flags |= USERSTACK_PRESENT;
pdump->info.stacks.user.sp = sp;
}
pdump->info.stacks.user.top = (uint32_t)tcb->stack_base_ptr +
tcb->adj_stack_size;
pdump->info.stacks.user.size = (uint32_t)tcb->adj_stack_size;
#if CONFIG_ARCH_INTERRUPTSTACK > 3
/* Get the limits on the interrupt stack memory */
pdump->info.stacks.interrupt.top = (uint32_t)g_intstacktop;
pdump->info.stacks.interrupt.size = (CONFIG_ARCH_INTERRUPTSTACK & ~3);
/* If In interrupt Context save the interrupt stack data centered
* about the interrupt stack pointer
*/
if ((pdump->info.flags & INTSTACK_PRESENT) != 0)
{
stack_word_t *ps = (stack_word_t *) pdump->info.stacks.interrupt.sp;
copy_reverse(pdump->istack, &ps[nitems(pdump->istack) / 2],
nitems(pdump->istack));
}
/* Is it Invalid? */
if (!(pdump->info.stacks.interrupt.sp <=
pdump->info.stacks.interrupt.top &&
pdump->info.stacks.interrupt.sp > pdump->info.stacks.interrupt.top -
pdump->info.stacks.interrupt.size))
{
pdump->info.flags |= INVALID_INTSTACK_PTR;
}
#endif
/* If In interrupt context or User save the user stack data centered
* about the user stack pointer
*/
if ((pdump->info.flags & USERSTACK_PRESENT) != 0)
{
stack_word_t *ps = (stack_word_t *) pdump->info.stacks.user.sp;
copy_reverse(pdump->ustack, &ps[nitems(pdump->ustack) / 2],
nitems(pdump->ustack));
}
/* Is it Invalid? */
if (!(pdump->info.stacks.user.sp <= pdump->info.stacks.user.top &&
pdump->info.stacks.user.sp > pdump->info.stacks.user.top -
pdump->info.stacks.user.size))
{
pdump->info.flags |= INVALID_USERSTACK_PTR;
}
rv = stm32_bbsram_savepanic(HARDFAULT_FILENO, (uint8_t *)pdump,
sizeof(fullcontext_t));
/* Test if memory got wiped because of using _sdata */
if (rv == -ENXIO)
{
char *dead = "Memory wiped - dump not saved!";
while (*dead)
{
arm_lowputc(*dead++);
}
}
else if (rv == -ENOSPC)
{
/* hard fault again */
arm_lowputc('!');
}
}
#endif /* CONFIG_STM32F7_SAVE_CRASHDUMP */
#endif /* CONFIG_STM32_BBSRAM */

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/****************************************************************************
* boards/arm/stm32f7/nucleo-f746zg/src/stm32_boot.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <debug.h>
#include <nuttx/board.h>
#include <arch/board/board.h>
#include "arm_internal.h"
#include "nucleo-f746zg.h"
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: stm32_boardinitialize
*
* Description:
* All STM32 architectures must provide the following entry point.
* This entry point is called early in the initialization -- after all
* memory has been configured and mapped but before any devices have been
* initialized.
*
****************************************************************************/
void stm32_boardinitialize(void)
{
#ifdef CONFIG_ARCH_LEDS
/* Configure on-board LEDs if LED support has been selected. */
board_autoled_initialize();
#endif
#if defined(CONFIG_STM32F7_OTGFS) || defined(CONFIG_STM32F7_HOST)
stm32_usbinitialize();
#endif
#if defined(CONFIG_SPI)
/* Configure SPI chip selects */
stm32_spidev_initialize();
#endif
}
/****************************************************************************
* Name: board_late_initialize
*
* Description:
* If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional
* initialization call will be performed in the boot-up sequence to a
* function called board_late_initialize(). board_late_initialize() will
* be called immediately after up_initialize() is called and just before
* the initial application is started. This additional initialization
* phase may be used, for example, to initialize board-specific device
* drivers.
*
****************************************************************************/
#ifdef CONFIG_BOARD_LATE_INITIALIZE
void board_late_initialize(void)
{
/* Perform board-specific initialization */
stm32_bringup();
}
#endif

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boards/arm/stm32f7/nucleo-f746zg/src/stm32_bringup.c Normal file
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/****************************************************************************
* boards/arm/stm32f7/nucleo-f746zg/src/stm32_bringup.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <sys/types.h>
#include <debug.h>
#include <syslog.h>
#include <stdio.h>
#include "nucleo-f746zg.h"
#include <nuttx/fs/fs.h>
#include <nuttx/i2c/i2c_master.h>
#include <nuttx/kmalloc.h>
#include <nuttx/leds/userled.h>
#include <nuttx/sensors/mpu60x0.h>
#include "stm32_i2c.h"
#ifdef CONFIG_STM32_ROMFS
#include "stm32_romfs.h"
#endif
#ifdef CONFIG_SYSTEMTICK_HOOK
#include <semaphore.h>
#endif
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: stm32_bringup
*
* Description:
* Perform architecture-specific initialization
*
* CONFIG_BOARD_LATE_INITIALIZE=y :
* Called from board_late_initialize().
*
* CONFIG_BOARD_LATE_INITIALIZE=n && CONFIG_BOARDCTL=y :
* Called from the NSH library
*
****************************************************************************/
int stm32_bringup(void)
{
int ret;
#ifdef CONFIG_I2C
int i2c_bus;
struct i2c_master_s *i2c;
#ifdef CONFIG_MPU60X0_I2C
struct mpu_config_s *mpu_config;
#endif
#endif
#ifdef CONFIG_FS_PROCFS
/* Mount the procfs file system */
ret = nx_mount(NULL, STM32_PROCFS_MOUNTPOINT, "procfs", 0, NULL);
if (ret < 0)
{
syslog(LOG_ERR, "ERROR: Failed to mount procfs at %s: %d\n",
STM32_PROCFS_MOUNTPOINT, ret);
}
#endif
#ifdef CONFIG_STM32_ROMFS
/* Mount the romfs partition */
ret = stm32_romfs_initialize();
if (ret < 0)
{
syslog(LOG_ERR, "ERROR: Failed to mount romfs at %s: %d\n",
CONFIG_STM32_ROMFS_MOUNTPOINT, ret);
}
#endif
#ifdef CONFIG_DEV_GPIO
/* Register the GPIO driver */
ret = stm32_gpio_initialize();
if (ret < 0)
{
syslog(LOG_ERR, "Failed to initialize GPIO Driver: %d\n", ret);
return ret;
}
#endif
#if !defined(CONFIG_ARCH_LEDS) && defined(CONFIG_USERLED_LOWER)
/* Register the LED driver */
ret = userled_lower_initialize(LED_DRIVER_PATH);
if (ret < 0)
{
syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", ret);
}
#endif
#ifdef CONFIG_ADC
/* Initialize ADC and register the ADC driver. */
ret = stm32_adc_setup();
if (ret < 0)
{
syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret);
}
#endif
#ifdef CONFIG_STM32F7_BBSRAM
/* Initialize battery-backed RAM */
stm32_bbsram_int();
#endif
#if defined(CONFIG_FAT_DMAMEMORY)
if (stm32_dma_alloc_init() < 0)
{
syslog(LOG_ERR, "DMA alloc FAILED");
}
#endif
#if defined(CONFIG_NUCLEO_F746ZG_SPI_TEST)
/* Create SPI interfaces */
ret = stm32_spidev_bus_test();
if (ret != OK)
{
syslog(LOG_ERR, "ERROR: Failed to initialize SPI interfaces: %d\n",
ret);
return ret;
}
#endif
#if defined(CONFIG_MMCSD)
/* Initialize the SDIO block driver */
ret = stm32_sdio_initialize();
if (ret != OK)
{
ferr("ERROR: Failed to initialize MMC/SD driver: %d\n", ret);
return ret;
}
#endif
#if defined(CONFIG_PWM)
/* Initialize PWM and register the PWM device */
ret = stm32_pwm_setup();
if (ret < 0)
{
syslog(LOG_ERR, "ERROR: stm32_pwm_setup() failed: %d\n", ret);
}
#endif
#ifdef CONFIG_SENSORS_QENCODER
char buf[9];
#ifdef CONFIG_STM32F7_TIM1_QE
snprintf(buf, sizeof(buf), "/dev/qe0");
ret = stm32_qencoder_initialize(buf, 1);
if (ret < 0)
{
syslog(LOG_ERR,
"ERROR: Failed to register the qencoder: %d\n",
ret);
return ret;
}
#endif
#ifdef CONFIG_STM32F7_TIM3_QE
snprintf(buf, sizeof(buf), "/dev/qe2");
ret = stm32_qencoder_initialize(buf, 3);
if (ret < 0)
{
syslog(LOG_ERR,
"ERROR: Failed to register the qencoder: %d\n",
ret);
return ret;
}
#endif
#ifdef CONFIG_STM32F7_TIM4_QE
snprintf(buf, sizeof(buf), "/dev/qe3");
ret = stm32_qencoder_initialize(buf, 4);
if (ret < 0)
{
syslog(LOG_ERR,
"ERROR: Failed to register the qencoder: %d\n",
ret);
return ret;
}
#endif
#ifdef CONFIG_STM32F7_TIM8_QE
snprintf(buf, sizeof(buf), "/dev/qe4");
ret = stm32_qencoder_initialize(buf, 8);
if (ret < 0)
{
syslog(LOG_ERR,
"ERROR: Failed to register the qencoder: %d\n",
ret);
return ret;
}
#endif
#endif
#ifdef CONFIG_STM32F7_CAN_CHARDRIVER
ret = stm32_can_setup();
if (ret < 0)
{
syslog(LOG_ERR, "ERROR: stm32f7_can_setup failed: %d\n", ret);
return ret;
}
#endif
#ifdef CONFIG_STM32F7_CAN_SOCKET
ret = stm32_cansock_setup();
if (ret < 0)
{
syslog(LOG_ERR, "ERROR: stm32_cansock_setup failed: %d\n", ret);
}
#endif
#if defined(CONFIG_I2C) && defined(CONFIG_STM32F7_I2C1)
i2c_bus = 1;
i2c = stm32_i2cbus_initialize(i2c_bus);
if (i2c == NULL)
{
syslog(LOG_ERR, "ERROR: Failed to get I2C%d interface\n", i2c_bus);
}
else
{
#if defined(CONFIG_SYSTEM_I2CTOOL)
ret = i2c_register(i2c, i2c_bus);
if (ret < 0)
{
syslog(LOG_ERR, "ERROR: Failed to register I2C%d driver: %d\n",
i2c_bus, ret);
}
#endif
#ifdef CONFIG_MPU60X0_I2C
mpu_config = kmm_zalloc(sizeof(struct mpu_config_s));
if (mpu_config == NULL)
{
syslog(LOG_ERR, "ERROR: Failed to allocate mpu60x0 driver\n");
}
else
{
mpu_config->i2c = i2c;
mpu_config->addr = 0x68;
mpu60x0_register("/dev/imu0", mpu_config);
}
#endif
}
#endif
UNUSED(ret);
return OK;
}
#ifdef CONFIG_SYSTEMTICK_HOOK
sem_t g_waitsem;
void board_timerhook(void)
{
(void)sem_post(&g_waitsem);
}
#endif

106
boards/arm/stm32f7/nucleo-f746zg/src/stm32_buttons.c Normal file
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/****************************************************************************
* boards/arm/stm32f7/nucleo-f746zg/src/stm32_buttons.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stddef.h>
#include <errno.h>
#include <nuttx/irq.h>
#include <nuttx/board.h>
#include <arch/board/board.h>
#include "stm32_gpio.h"
#include "nucleo-f746zg.h"
#ifdef CONFIG_ARCH_BUTTONS
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: board_button_initialize
*
* Description:
* board_button_initialize() must be called to initialize button resources.
* After that, board_buttons() may be called to collect the current state
* of all buttons or board_button_irq() may be called to register button
* interrupt handlers.
*
****************************************************************************/
uint32_t board_button_initialize(void)
{
stm32_configgpio(GPIO_BTN_USER);
return NUM_BUTTONS;
}
/****************************************************************************
* Name: board_buttons
****************************************************************************/
uint32_t board_buttons(void)
{
return stm32_gpioread(GPIO_BTN_USER) ? 1 : 0;
}
/****************************************************************************
* Button support.
*
* Description:
* board_button_initialize() must be called to initialize button resources.
* After that, board_buttons() may be called to collect the current state
* of all buttons or board_button_irq() may be called to register button
* interrupt handlers.
*
* After board_button_initialize() has been called, board_buttons() may be
* called to collect the state of all buttons. board_buttons() returns an
* 32-bit bit set with each bit associated with a button. See the
* BUTTON_*_BIT definitions in board.h for the meaning of each bit.
*
* board_button_irq() may be called to register an interrupt handler that
* will be called when a button is depressed or released. The ID value is a
* button enumeration value that uniquely identifies a button resource. See
* the BUTTON_* definitions in board.h for the meaning of enumeration
* value.
*
****************************************************************************/
#ifdef CONFIG_ARCH_IRQBUTTONS
int board_button_irq(int id, xcpt_t irqhandler, void *arg)
{
int ret = -EINVAL;
if (id == BUTTON_USER)
{
ret = stm32_gpiosetevent(GPIO_BTN_USER, true, true, true,
irqhandler, arg);
}
return ret;
}
#endif
#endif /* CONFIG_ARCH_BUTTONS */

115
boards/arm/stm32f7/nucleo-f746zg/src/stm32_can.c Normal file
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/****************************************************************************
* boards/arm/stm32f7/nucleo-f746zg/src/stm32_can.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdbool.h>
#include <errno.h>
#include <debug.h>
#include <nuttx/can/can.h>
#include "stm32_can.h"
#include "nucleo-f746zg.h"
#ifdef CONFIG_CAN
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#ifdef CONFIG_STM32F7_CAN1
# define CAN_PORT 1
#else
# define CAN_PORT 2
#endif
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: stm32_can_setup
*
* Description:
* Initialize CAN and register the CAN device
*
****************************************************************************/
int stm32_can_setup(void)
{
#if defined(CONFIG_STM32F7_CAN1)
struct can_dev_s *can;
int ret;
/* Call stm32f7can_initialize() to get an instance of the CAN interface */
can = stm32_caninitialize(CAN_PORT);
if (can == NULL)
{
canerr("ERROR: Failed to get CAN interface\n");
return -ENODEV;
}
/* Register the CAN driver at "/dev/can0" */
ret = can_register("/dev/can0", can);
if (ret < 0)
{
canerr("ERROR: can_register failed: %d\n", ret);
return ret;
}
return OK;
#endif
#if defined(CONFIG_STM32F7_CAN2)
struct can_dev_s *can;
int ret;
/* Call stm32f7can_initialize() to get an instance of the CAN interface */
can = stm32_caninitialize(CAN_PORT);
if (can == NULL)
{
canerr("ERROR: Failed to get CAN interface\n");
return -ENODEV;
}
/* Register the CAN driver at "/dev/can1" */
ret = can_register("/dev/can1", can);
if (ret < 0)
{
canerr("ERROR: can_register failed: %d\n", ret);
return ret;
}
return OK;
#else
return -ENODEV;
#endif
}
#endif /* CONFIG_CAN */

83
boards/arm/stm32f7/nucleo-f746zg/src/stm32_cansock.c Normal file
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/****************************************************************************
* boards/arm/stm32f7/nucleo-f746zg/src/stm32_cansock.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <debug.h>
#include "stm32_can.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Configuration ************************************************************/
#if !defined(CONFIG_STM32F7_CAN1) && !defined(CONFIG_STM32F7_CAN2)
# error "No CAN is enable. Please eneable at least one CAN device"
#endif
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: stm32_cansock_setup
*
* Description:
* Initialize CAN socket interface
*
****************************************************************************/
int stm32_cansock_setup(void)
{
int ret = OK;
UNUSED(ret);
#ifdef CONFIG_STM32F7_CAN1
/* Call stm32_caninitialize() to get an instance of the CAN interface */
ret = stm32_cansockinitialize(1);
if (ret < 0)
{
canerr("ERROR: Failed to get CAN interface %d\n", ret);
goto errout;
}
#endif
#ifdef CONFIG_STM32F7_CAN2
/* Call stm32_caninitialize() to get an instance of the CAN interface */
ret = stm32_cansockinitialize(2);
if (ret < 0)
{
canerr("ERROR: Failed to get CAN interface %d\n", ret);
goto errout;
}
#endif
errout:
return ret;
}

347
boards/arm/stm32f7/nucleo-f746zg/src/stm32_composite.c Normal file
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/****************************************************************************
* boards/arm/stm32f7/nucleo-f746zg/src/stm32_composite.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <sys/types.h>
#include <debug.h>
#include <assert.h>
#include <nuttx/usb/usbdev.h>
#include <nuttx/usb/rndis.h>
#include <nuttx/usb/cdcacm.h>
#include <nuttx/usb/usbmsc.h>
#include <nuttx/usb/composite.h>
#include "stm32_otg.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#define COMPOSITE0_DEV (3)
/****************************************************************************
* Private Data
****************************************************************************/
#ifdef CONFIG_USBMSC_COMPOSITE
static void *g_mschandle;
#endif
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: board_mscclassobject
*
* Description:
* If the mass storage class driver is part of composite device, then
* its instantiation and configuration is a multi-step, board-specific,
* process (See comments for usbmsc_configure below). In this case,
* board-specific logic must provide board_mscclassobject().
*
* board_mscclassobject() is called from the composite driver. It must
* encapsulate the instantiation and configuration of the mass storage
* class and the return the mass storage device's class driver instance
* to the composite driver.
*
* Input Parameters:
* classdev - The location to return the mass storage class' device
* instance.
*
* Returned Value:
* 0 on success; a negated errno on failure
*
****************************************************************************/
#ifdef CONFIG_USBMSC_COMPOSITE
static int board_mscclassobject(int minor,
struct usbdev_devinfo_s *devinfo,
struct usbdevclass_driver_s **classdev)
{
int ret;
DEBUGASSERT(g_mschandle == NULL);
/* Configure the mass storage device */
uinfo("Configuring with NLUNS=1\n");
ret = usbmsc_configure(1, &g_mschandle);
if (ret < 0)
{
uerr("ERROR: usbmsc_configure failed: %d\n", -ret);
return ret;
}
uinfo("MSC handle=%p\n", g_mschandle);
/* Bind the LUN(s) */
uinfo("Bind LUN=0 to /dev/mmcsd0\n");
ret = usbmsc_bindlun(g_mschandle, "/dev/mmcsd0", 0, 0, 0, false);
if (ret < 0)
{
uerr("ERROR: usbmsc_bindlun failed for LUN 1 at /dev/mmcsd0: %d\n",
ret);
usbmsc_uninitialize(g_mschandle);
g_mschandle = NULL;
return ret;
}
/* Get the mass storage device's class object */
ret = usbmsc_classobject(g_mschandle, devinfo, classdev);
if (ret < 0)
{
uerr("ERROR: usbmsc_classobject failed: %d\n", -ret);
usbmsc_uninitialize(g_mschandle);
g_mschandle = NULL;
}
return ret;
}
#endif
/****************************************************************************
* Name: board_mscuninitialize
*
* Description:
* Un-initialize the USB storage class driver.
* This is just an application specific wrapper for usbmsc_unitialize()
* that is called form the composite device logic.
*
* Input Parameters:
* classdev - The class driver instrance previously give to the composite
* driver by board_mscclassobject().
*
* Returned Value:
* None
*
****************************************************************************/
#ifdef CONFIG_USBMSC_COMPOSITE
static void board_mscuninitialize(struct usbdevclass_driver_s *classdev)
{
if (g_mschandle)
{
usbmsc_uninitialize(g_mschandle);
}
g_mschandle = NULL;
}
#endif
/****************************************************************************
* Name: board_composite_connect
*
* Description:
* Connect the USB composite device on the specified USB device port for
* configuration 0.
*
* Input Parameters:
* port - The USB device port.
*
* Returned Value:
* A non-NULL handle value is returned on success. NULL is returned on
* any failure.
*
****************************************************************************/
static void *board_composite0_connect(int port)
{
struct composite_devdesc_s dev[COMPOSITE0_DEV];
int ifnobase = 0;
int strbase = COMPOSITE_NSTRIDS;
int dev_idx = 0;
int epin = 1;
int epout = 1;
#ifdef CONFIG_RNDIS_COMPOSITE
/* Configure the RNDIS USB device */
/* Ask the rndis driver to fill in the constants we didn't
* know here.
*/
usbdev_rndis_get_composite_devdesc(&dev[dev_idx]);
/* Interfaces */
dev[dev_idx].devinfo.ifnobase = ifnobase;
dev[dev_idx].minor = 0;
/* Strings */
dev[dev_idx].devinfo.strbase = strbase;
/* Endpoints */
dev[dev_idx].devinfo.epno[RNDIS_EP_INTIN_IDX] = epin++;
dev[dev_idx].devinfo.epno[RNDIS_EP_BULKIN_IDX] = epin++;
dev[dev_idx].devinfo.epno[RNDIS_EP_BULKOUT_IDX] = epout++;
/* Count up the base numbers */
ifnobase += dev[dev_idx].devinfo.ninterfaces;
strbase += dev[dev_idx].devinfo.nstrings;
dev_idx += 1;
#endif
#ifdef CONFIG_CDCACM_COMPOSITE
/* Configure the CDC/ACM device */
/* Ask the cdcacm driver to fill in the constants we didn't
* know here.
*/
cdcacm_get_composite_devdesc(&dev[dev_idx]);
/* Overwrite and correct some values... */
/* The callback functions for the CDC/ACM class */
dev[dev_idx].classobject = cdcacm_classobject;
dev[dev_idx].uninitialize = cdcacm_uninitialize;
/* Interfaces */
dev[dev_idx].devinfo.ifnobase = ifnobase; /* Offset to Interface-IDs */
dev[dev_idx].minor = 0; /* The minor interface number */
/* Strings */
dev[dev_idx].devinfo.strbase = strbase; /* Offset to String Numbers */
/* Endpoints */
dev[dev_idx].devinfo.epno[CDCACM_EP_INTIN_IDX] = epin++;
dev[dev_idx].devinfo.epno[CDCACM_EP_BULKIN_IDX] = epin++;
dev[dev_idx].devinfo.epno[CDCACM_EP_BULKOUT_IDX] = epout++;
/* Count up the base numbers */
ifnobase += dev[dev_idx].devinfo.ninterfaces;
strbase += dev[dev_idx].devinfo.nstrings;
dev_idx += 1;
#endif
#ifdef CONFIG_USBMSC_COMPOSITE
/* Configure the mass storage device device */
/* Ask the usbmsc driver to fill in the constants we didn't
* know here.
*/
usbmsc_get_composite_devdesc(&dev[dev_idx]);
/* Overwrite and correct some values... */
/* The callback functions for the USBMSC class */
dev[dev_idx].classobject = board_mscclassobject;
dev[dev_idx].uninitialize = board_mscuninitialize;
/* Interfaces */
dev[dev_idx].devinfo.ifnobase = ifnobase; /* Offset to Interface-IDs */
dev[dev_idx].minor = 0; /* The minor interface number */
/* Strings */
dev[dev_idx].devinfo.strbase = strbase; /* Offset to String Numbers */
/* Endpoints */
dev[dev_idx].devinfo.epno[USBMSC_EP_BULKIN_IDX] = epin++;
dev[dev_idx].devinfo.epno[USBMSC_EP_BULKOUT_IDX] = epout++;
/* Count up the base numbers */
ifnobase += dev[dev_idx].devinfo.ninterfaces;
strbase += dev[dev_idx].devinfo.nstrings;
dev_idx += 1;
#endif
/* Sanity checks */
DEBUGASSERT(epin < STM32_NENDPOINTS);
DEBUGASSERT(epout < STM32_NENDPOINTS);
return composite_initialize(composite_getdevdescs(), dev, dev_idx);
}
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: board_composite_initialize
*
* Description:
* Perform architecture specific initialization of a composite USB device.
*
****************************************************************************/
int board_composite_initialize(int port)
{
return OK;
}
/****************************************************************************
* Name: board_composite_connect
*
* Description:
* Connect the USB composite device on the specified USB device port using
* the specified configuration. The interpretation of the configid is
* board specific.
*
* Input Parameters:
* port - The USB device port.
* configid - The USB composite configuration
*
* Returned Value:
* A non-NULL handle value is returned on success. NULL is returned on
* any failure.
*
****************************************************************************/
void *board_composite_connect(int port, int configid)
{
if (configid == 0)
{
return board_composite0_connect(port);
}
else
{
return NULL;
}
}

119
boards/arm/stm32f7/nucleo-f746zg/src/stm32_dma_alloc.c Normal file
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/****************************************************************************
* boards/arm/stm32f7/nucleo-f746zg/src/stm32_dma_alloc.c
*
* Copyright (C) 2016 PX4 Development Team. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name PX4 nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <syslog.h>
#include <stdint.h>
#include <errno.h>
#include <nuttx/mm/gran.h>
#include "nucleo-f746zg.h"
#if defined(CONFIG_FAT_DMAMEMORY)
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#if !defined(CONFIG_GRAN)
# error microSD DMA support requires CONFIG_GRAN
#endif
#define BOARD_DMA_ALLOC_POOL_SIZE (8*512)
/****************************************************************************
* Private Data
****************************************************************************/
static GRAN_HANDLE dma_allocator;
/* The DMA heap size constrains the total number of things that can be
* ready to do DMA at a time.
*
* For example, FAT DMA depends on one sector-sized buffer per filesystem
* plus one sector-sized buffer per file.
*
* We use a fundamental alignment / granule size of 64B; this is sufficient
* to guarantee alignment for the largest STM32 DMA burst
* (16 beats x 32bits).
*/
static
uint8_t g_dma_heap[BOARD_DMA_ALLOC_POOL_SIZE] aligned_data(64);
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: stm32_dma_alloc_init
*
* Description:
* All boards may optionally provide this API to instantiate a pool of
* memory for uses with FAST FS DMA operations.
*
****************************************************************************/
int stm32_dma_alloc_init(void)
{
dma_allocator = gran_initialize(g_dma_heap,
sizeof(g_dma_heap),
7, /* 128B granule - must be > alignment (XXX bug?) */
6); /* 64B alignment */
if (dma_allocator == NULL)
{
return -ENOMEM;
}
return OK;
}
/* DMA-aware allocator stubs for the FAT filesystem. */
void *fat_dma_alloc(size_t size)
{
return gran_alloc(dma_allocator, size);
}
void fat_dma_free(void *memory, size_t size)
{
gran_free(dma_allocator, memory, size);
}
#endif /* CONFIG_FAT_DMAMEMORY */

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/****************************************************************************
* boards/arm/stm32f7/nucleo-f746zg/src/stm32_gpio.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdbool.h>
#include <assert.h>
#include <debug.h>
#include <nuttx/clock.h>
#include <nuttx/wdog.h>
#include <nuttx/ioexpander/gpio.h>
#include <arch/board/board.h>
#include "chip.h"
#include "stm32_gpio.h"
#include "nucleo-f746zg.h"
#if defined(CONFIG_DEV_GPIO) && !defined(CONFIG_GPIO_LOWER_HALF)
/****************************************************************************
* Private Types
****************************************************************************/
struct stm32gpio_dev_s
{
struct gpio_dev_s gpio;
uint8_t id;
};
struct stm32gpint_dev_s
{
struct stm32gpio_dev_s stm32gpio;
pin_interrupt_t callback;
};
/****************************************************************************
* Private Function Prototypes
****************************************************************************/
static int gpin_read(struct gpio_dev_s *dev, bool *value);
static int gpout_read(struct gpio_dev_s *dev, bool *value);
static int gpout_write(struct gpio_dev_s *dev, bool value);
static int gpint_read(struct gpio_dev_s *dev, bool *value);
static int gpint_attach(struct gpio_dev_s *dev,
pin_interrupt_t callback);
static int gpint_enable(struct gpio_dev_s *dev, bool enable);
/****************************************************************************
* Private Data
****************************************************************************/
static const struct gpio_operations_s gpin_ops =
{
.go_read = gpin_read,
.go_write = NULL,
.go_attach = NULL,
.go_enable = NULL,
};
static const struct gpio_operations_s gpout_ops =
{
.go_read = gpout_read,
.go_write = gpout_write,
.go_attach = NULL,
.go_enable = NULL,
};
static const struct gpio_operations_s gpint_ops =
{
.go_read = gpint_read,
.go_write = NULL,
.go_attach = gpint_attach,
.go_enable = gpint_enable,
};
#if BOARD_NGPIOIN > 0
/* This array maps the GPIO pins used as INPUT */
static const uint32_t g_gpioinputs[BOARD_NGPIOIN] =
{
GPIO_IN1,
GPIO_IN2,
GPIO_IN3,
GPIO_IN4,
};
static struct stm32gpio_dev_s g_gpin[BOARD_NGPIOIN];
#endif
#if BOARD_NGPIOOUT
/* This array maps the GPIO pins used as OUTPUT */
static const uint32_t g_gpiooutputs[BOARD_NGPIOOUT] =
{
GPIO_LD1,
GPIO_LD2,
GPIO_LD3,
GPIO_OUT1,
GPIO_OUT2,
GPIO_OUT3,
GPIO_OUT4,
GPIO_OUT5,
#if !defined(CONFIG_STM32F7_TIM1_CH1NOUT)
GPIO_OUT6,
#endif
#if !defined(CONFIG_STM32F7_TIM1_CH2NOUT)
GPIO_OUT7,
#endif
};
static struct stm32gpio_dev_s g_gpout[BOARD_NGPIOOUT];
#endif
#if BOARD_NGPIOINT > 0
/* This array maps the GPIO pins used as INTERRUPT INPUTS */
static const uint32_t g_gpiointinputs[BOARD_NGPIOINT] =
{
GPIO_INT1,
};
static struct stm32gpint_dev_s g_gpint[BOARD_NGPIOINT];
#endif
/****************************************************************************
* Private Functions
****************************************************************************/
static int stm32gpio_interrupt(int irq, void *context, void *arg)
{
struct stm32gpint_dev_s *stm32gpint =
(struct stm32gpint_dev_s *)arg;
DEBUGASSERT(stm32gpint != NULL && stm32gpint->callback != NULL);
gpioinfo("Interrupt! callback=%p\n", stm32gpint->callback);
stm32gpint->callback(&stm32gpint->stm32gpio.gpio,
stm32gpint->stm32gpio.id);
return OK;
}
static int gpin_read(struct gpio_dev_s *dev, bool *value)
{
struct stm32gpio_dev_s *stm32gpio =
(struct stm32gpio_dev_s *)dev;
DEBUGASSERT(stm32gpio != NULL && value != NULL);
DEBUGASSERT(stm32gpio->id < BOARD_NGPIOIN);
gpioinfo("Reading...\n");
*value = stm32_gpioread(g_gpioinputs[stm32gpio->id]);
return OK;
}
static int gpout_read(struct gpio_dev_s *dev, bool *value)
{
struct stm32gpio_dev_s *stm32gpio =
(struct stm32gpio_dev_s *)dev;
DEBUGASSERT(stm32gpio != NULL && value != NULL);
DEBUGASSERT(stm32gpio->id < BOARD_NGPIOOUT);
gpioinfo("Reading...\n");
*value = stm32_gpioread(g_gpiooutputs[stm32gpio->id]);
return OK;
}
static int gpout_write(struct gpio_dev_s *dev, bool value)
{
struct stm32gpio_dev_s *stm32gpio =
(struct stm32gpio_dev_s *)dev;
DEBUGASSERT(stm32gpio != NULL);
DEBUGASSERT(stm32gpio->id < BOARD_NGPIOOUT);
gpioinfo("Writing %d\n", (int)value);
stm32_gpiowrite(g_gpiooutputs[stm32gpio->id], value);
return OK;
}
static int gpint_read(struct gpio_dev_s *dev, bool *value)
{
struct stm32gpint_dev_s *stm32gpint =
(struct stm32gpint_dev_s *)dev;
DEBUGASSERT(stm32gpint != NULL && value != NULL);
DEBUGASSERT(stm32gpint->stm32gpio.id < BOARD_NGPIOINT);
gpioinfo("Reading int pin...\n");
*value = stm32_gpioread(g_gpiointinputs[stm32gpint->stm32gpio.id]);
return OK;
}
static int gpint_attach(struct gpio_dev_s *dev,
pin_interrupt_t callback)
{
struct stm32gpint_dev_s *stm32gpint =
(struct stm32gpint_dev_s *)dev;
gpioinfo("Attaching the callback\n");
/* Make sure the interrupt is disabled */
stm32_gpiosetevent(g_gpiointinputs[stm32gpint->stm32gpio.id], false,
false, false, NULL, NULL);
gpioinfo("Attach %p\n", callback);
stm32gpint->callback = callback;
return OK;
}
static int gpint_enable(struct gpio_dev_s *dev, bool enable)
{
struct stm32gpint_dev_s *stm32gpint =
(struct stm32gpint_dev_s *)dev;
if (enable)
{
if (stm32gpint->callback != NULL)
{
gpioinfo("Enabling the interrupt\n");
/* Configure the interrupt for rising edge */
stm32_gpiosetevent(g_gpiointinputs[stm32gpint->stm32gpio.id],
true, false, false, stm32gpio_interrupt,
&g_gpint[stm32gpint->stm32gpio.id]);
}
}
else
{
gpioinfo("Disable the interrupt\n");
stm32_gpiosetevent(g_gpiointinputs[stm32gpint->stm32gpio.id],
false, false, false, NULL, NULL);
}
return OK;
}
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: stm32_gpio_initialize
*
* Description:
* Initialize GPIO drivers for use with /apps/examples/gpio
*
****************************************************************************/
int stm32_gpio_initialize(void)
{
int i;
int pincount = 0;
#if BOARD_NGPIOIN > 0
for (i = 0; i < BOARD_NGPIOIN; i++)
{
/* Setup and register the GPIO pin */
g_gpin[i].gpio.gp_pintype = GPIO_INPUT_PIN;
g_gpin[i].gpio.gp_ops = &gpin_ops;
g_gpin[i].id = i;
gpio_pin_register(&g_gpin[i].gpio, pincount);
/* Configure the pin that will be used as input */
stm32_configgpio(g_gpioinputs[i]);
pincount++;
}
#endif
#if BOARD_NGPIOOUT > 0
for (i = 0; i < BOARD_NGPIOOUT; i++)
{
/* Setup and register the GPIO pin */
g_gpout[i].gpio.gp_pintype = GPIO_OUTPUT_PIN;
g_gpout[i].gpio.gp_ops = &gpout_ops;
g_gpout[i].id = i;
gpio_pin_register(&g_gpout[i].gpio, pincount);
/* Configure the pin that will be used as output */
stm32_gpiowrite(g_gpiooutputs[i], 0);
stm32_configgpio(g_gpiooutputs[i]);
pincount++;
}
#endif
#if BOARD_NGPIOINT > 0
for (i = 0; i < BOARD_NGPIOINT; i++)
{
/* Setup and register the GPIO pin */
g_gpint[i].stm32gpio.gpio.gp_pintype = GPIO_INTERRUPT_PIN;
g_gpint[i].stm32gpio.gpio.gp_ops = &gpint_ops;
g_gpint[i].stm32gpio.id = i;
gpio_pin_register(&g_gpint[i].stm32gpio.gpio, pincount);
/* Configure the pin that will be used as interrupt input */
stm32_configgpio(g_gpiointinputs[i]);
pincount++;
}
#endif
return 0;
}
#endif /* CONFIG_DEV_GPIO && !CONFIG_GPIO_LOWER_HALF */

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/****************************************************************************
* boards/arm/stm32f7/nucleo-f746zg/src/stm32_pwm.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <errno.h>
#include <debug.h>
#include <sys/types.h>
#include <nuttx/board.h>
#include <nuttx/timers/pwm.h>
#include <arch/board/board.h>
#include "chip.h"
#include "arm_internal.h"
#include "stm32_pwm.h"
#include "nucleo-f746zg.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#define HAVE_PWM 1
#ifndef CONFIG_PWM
# undef HAVE_PWM
#endif
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: stm32_pwm_setup
*
* Description:
* Initialize PWM and register the PWM device.
*
****************************************************************************/
int stm32_pwm_setup(void)
{
#ifdef HAVE_PWM
static bool initialized = false;
struct pwm_lowerhalf_s *pwm;
int ret;
/* Have we already initialized? */
if (!initialized)
{
/* Call stm32_pwminitialize() to get an instance of the PWM interface */
#if defined(CONFIG_STM32F7_TIM1_PWM)
pwm = stm32_pwminitialize(1);
if (!pwm)
{
aerr("ERROR: Failed to get the STM32F7 PWM lower half\n");
return -ENODEV;
}
ret = pwm_register("/dev/pwm0", pwm);
if (ret < 0)
{
aerr("ERROR: pwm_register failed: %d\n", ret);
return ret;
}
#endif
#if defined(CONFIG_STM32F7_TIM2_PWM)
pwm = stm32_pwminitialize(2);
if (!pwm)
{
aerr("ERROR: Failed to get the STM32F7 PWM lower half\n");
return -ENODEV;
}
ret = pwm_register("/dev/pwm1", pwm);
if (ret < 0)
{
aerr("ERROR: pwm_register failed: %d\n", ret);
return ret;
}
#endif
#if defined(CONFIG_STM32F7_TIM3_PWM)
pwm = stm32_pwminitialize(3);
if (!pwm)
{
aerr("ERROR: Failed to get the STM32F7 PWM lower half\n");
return -ENODEV;
}
ret = pwm_register("/dev/pwm2", pwm);
if (ret < 0)
{
aerr("ERROR: pwm_register failed: %d\n", ret);
return ret;
}
#endif
#if defined(CONFIG_STM32F7_TIM4_PWM)
pwm = stm32_pwminitialize(4);
if (!pwm)
{
aerr("ERROR: Failed to get the STM32F7 PWM lower half\n");
return -ENODEV;
}
ret = pwm_register("/dev/pwm3", pwm);
if (ret < 0)
{
aerr("ERROR: pwm_register failed: %d\n", ret);
return ret;
}
#endif
/* Now we are initialized */
initialized = true;
}
return OK;
#else
return -ENODEV;
#endif
}

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boards/arm/stm32f7/nucleo-f746zg/src/stm32_qencoder.c Normal file
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/****************************************************************************
* boards/arm/stm32f7/nucleo-f746zg/src/stm32_qencoder.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <errno.h>
#include <debug.h>
#include <nuttx/sensors/qencoder.h>
#include <arch/board/board.h>
#include "chip.h"
#include "arm_internal.h"
#include "stm32_qencoder.h"
#include "nucleo-f746zg.h"
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: stm32_qencoder_initialize
*
* Description:
* All STM32F7 architectures must provide the following interface to work
* with examples/qencoder.
*
****************************************************************************/
int stm32_qencoder_initialize(const char *devpath, int timer)
{
int ret = 0;
/* Initialize a quadrature encoder interface. */
sninfo("Initializing the quadrature encoder using TIM%d\n", timer);
ret = stm32_qeinitialize(devpath, timer);
if (ret < 0)
{
snerr("ERROR: stm32_qeinitialize failed: %d\n", ret);
}
return ret;
}

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boards/arm/stm32f7/nucleo-f746zg/src/stm32_reset.c Normal file
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/****************************************************************************
* boards/arm/stm32f7/nucleo-f746zg/src/stm32_reset.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/arch.h>
#include <nuttx/board.h>
#ifdef CONFIG_BOARDCTL_RESET
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: board_reset
*
* Description:
* Reset board. Support for this function is required by board-level
* logic if CONFIG_BOARDCTL_RESET is selected.
*
* Input Parameters:
* status - Status information provided with the reset event. This
* meaning of this status information is board-specific. If not
* used by a board, the value zero may be provided in calls to
* board_reset().
*
* Returned Value:
* If this function returns, then it was not possible to power-off the
* board due to some constraints. The return value int this case is a
* board-specific reason for the failure to shutdown.
*
****************************************************************************/
int board_reset(int status)
{
up_systemreset();
return 0;
}
#endif /* CONFIG_BOARDCTL_RESET */

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boards/arm/stm32f7/nucleo-f746zg/src/stm32_romfs.h Normal file
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/****************************************************************************
* boards/arm/stm32f7/nucleo-f746zg/src/stm32_romfs.h
*
* Copyright (C) 2017 Tomasz Wozniak. All rights reserved.
* Author: Tomasz Wozniak <t.wozniak@samsung.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
#ifndef __BOARDS_ARM_STM32F7_NUCLEO144_SRC_STM32_ROMFS_H
#define __BOARDS_ARM_STM32F7_NUCLEO144_SRC_STM32_ROMFS_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#ifdef CONFIG_STM32_ROMFS
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#define ROMFS_SECTOR_SIZE 64
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: stm32_romfs_initialize
*
* Description:
* Registers built-in ROMFS image as block device and mounts it.
*
* Returned Value:
* Zero (OK) on success, a negated errno value on error.
*
* Assumptions/Limitations:
* Memory addresses [romfs_data_begin .. romfs_data_end) should contain
* ROMFS volume data, as included in the assembly snippet above (l. 84).
*
****************************************************************************/
int stm32_romfs_initialize(void);
#endif /* CONFIG_STM32_ROMFS */
#endif /* __BOARDS_ARM_STM32F7_NUCLEO144_SRC_STM32_ROMFS_H */

153
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/****************************************************************************
* boards/arm/stm32f7/nucleo-f746zg/src/stm32_romfs_initialize.c
* This file provides contents of an optional ROMFS volume, mounted at boot.
*
* Copyright (C) 2017 Tomasz Wozniak. All rights reserved.
* Author: Tomasz Wozniak <t.wozniak@samsung.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <sys/mount.h>
#include <sys/types.h>
#include <stdint.h>
#include <debug.h>
#include <errno.h>
#include <nuttx/fs/fs.h>
#include <nuttx/drivers/ramdisk.h>
#include "stm32_romfs.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#ifndef CONFIG_STM32_ROMFS
# error "CONFIG_STM32_ROMFS must be defined"
#else
#ifndef CONFIG_STM32_ROMFS_IMAGEFILE
# error "CONFIG_STM32_ROMFS_IMAGEFILE must be defined"
#endif
#ifndef CONFIG_STM32_ROMFS_DEV_MINOR
# error "CONFIG_STM32_ROMFS_DEV_MINOR must be defined"
#endif
#ifndef CONFIG_STM32_ROMFS_MOUNTPOINT
# error "CONFIG_STM32_ROMFS_MOUNTPOINT must be defined"
#endif
#define NSECTORS(size) (((size) + ROMFS_SECTOR_SIZE - 1)/ROMFS_SECTOR_SIZE)
#define STR2(m) #m
#define STR(m) STR2(m)
#define MKMOUNT_DEVNAME(m) "/dev/ram" STR(m)
#define MOUNT_DEVNAME MKMOUNT_DEVNAME(CONFIG_STM32_ROMFS_DEV_MINOR)
/****************************************************************************
* Private Data
****************************************************************************/
__asm__ (
".section .rodata\n"
".balign 16\n"
".globl romfs_data_begin\n"
"romfs_data_begin:\n"
".incbin " STR(CONFIG_STM32_ROMFS_IMAGEFILE) "\n"\
\
".balign " STR(ROMFS_SECTOR_SIZE) "\n"
".globl romfs_data_end\n"
"romfs_data_end:\n");
extern const uint8_t romfs_data_begin[];
extern const uint8_t romfs_data_end[];
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: stm32_romfs_initialize
*
* Description:
* Registers the aboveincluded binary file as block device.
* Then mounts the block device as ROMFS filesystems.
*
* Returned Value:
* Zero (OK) on success, a negated errno value on error.
*
* Assumptions/Limitations:
* Memory addresses [romfs_data_begin .. romfs_data_end) should contain
* ROMFS volume data, as included in the assembly snippet above (l. 84).
*
****************************************************************************/
int stm32_romfs_initialize(void)
{
size_t romfs_data_len;
int ret;
/* Create a ROM disk for the /etc filesystem */
romfs_data_len = romfs_data_end - romfs_data_begin;
ret = romdisk_register(CONFIG_STM32_ROMFS_DEV_MINOR, romfs_data_begin,
NSECTORS(romfs_data_len), ROMFS_SECTOR_SIZE);
if (ret < 0)
{
ferr("ERROR: romdisk_register failed: %d\n", -ret);
return ret;
}
/* Mount the file system */
finfo("Mounting ROMFS filesystem at target=%s with source=%s\n",
CONFIG_STM32_ROMFS_MOUNTPOINT, MOUNT_DEVNAME);
ret = nx_mount(MOUNT_DEVNAME, CONFIG_STM32_ROMFS_MOUNTPOINT,
"romfs", MS_RDONLY, NULL);
if (ret < 0)
{
ferr("ERROR: nx_mount(%s,%s,romfs) failed: %d\n",
MOUNT_DEVNAME, CONFIG_STM32_ROMFS_MOUNTPOINT, ret);
return ret;
}
return OK;
}
#endif /* CONFIG_STM32_ROMFS */

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/****************************************************************************
* boards/arm/stm32f7/nucleo-f746zg/src/stm32_sdio.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdbool.h>
#include <stdio.h>
#include <debug.h>
#include <errno.h>
#include <nuttx/sdio.h>
#include <nuttx/mmcsd.h>
#include "chip.h"
#include "nucleo-f746zg.h"
#include "stm32_gpio.h"
#include "stm32_sdmmc.h"
#ifdef CONFIG_MMCSD
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Configuration ************************************************************/
/* Card detections requires card support and a card detection GPIO */
#define HAVE_NCD 1
#if !defined(GPIO_SDMMC1_NCD)
# undef HAVE_NCD
#endif
/****************************************************************************
* Private Data
****************************************************************************/
static struct sdio_dev_s *g_sdio_dev;
#ifdef HAVE_NCD
static bool g_sd_inserted;
#endif
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: stm32_ncd_interrupt
*
* Description:
* Card detect interrupt handler.
*
****************************************************************************/
#ifdef HAVE_NCD
static int stm32_ncd_interrupt(int irq, void *context)
{
bool present;
present = !stm32_gpioread(GPIO_SDMMC1_NCD);
if (g_sdio_dev && present != g_sd_inserted)
{
sdio_mediachange(g_sdio_dev, present);
g_sd_inserted = present;
}
return OK;
}
#endif
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: stm32_sdio_initialize
*
* Description:
* Initialize SDIO-based MMC/SD card support
*
****************************************************************************/
int stm32_sdio_initialize(void)
{
int ret;
#ifdef HAVE_NCD
/* Configure the card detect GPIO */
stm32_configgpio(GPIO_SDMMC1_NCD);
/* Register an interrupt handler for the card detect pin */
stm32_gpiosetevent(GPIO_SDMMC1_NCD, true, true, true,
stm32_ncd_interrupt, NULL);
#endif
/* Mount the SDIO-based MMC/SD block driver */
/* First, get an instance of the SDIO interface */
finfo("Initializing SDIO slot %d\n", SDIO_SLOTNO);
g_sdio_dev = sdio_initialize(SDIO_SLOTNO);
if (!g_sdio_dev)
{
ferr("ERROR: Failed to initialize SDIO slot %d\n", SDIO_SLOTNO);
return -ENODEV;
}
/* Now bind the SDIO interface to the MMC/SD driver */
finfo("Bind SDIO to the MMC/SD driver, minor=%d\n", SDIO_MINOR);
ret = mmcsd_slotinitialize(SDIO_MINOR, g_sdio_dev);
if (ret != OK)
{
ferr("ERROR: Failed to bind SDIO to the MMC/SD driver: %d\n", ret);
return ret;
}
finfo("Successfully bound SDIO to the MMC/SD driver\n");
#ifdef HAVE_NCD
/* Use SD card detect pin to check if a card is g_sd_inserted */
g_sd_inserted = !stm32_gpioread(GPIO_SDMMC1_NCD);
finfo("Card detect : %d\n", g_sd_inserted);
sdio_mediachange(g_sdio_dev, g_sd_inserted);
#else
/* Assume that the SD card is inserted. What choice do we have? */
sdio_mediachange(g_sdio_dev, true);
#endif
return OK;
}
#endif /* HAVE_SDIO */

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/****************************************************************************
* boards/arm/stm32f7/nucleo-f746zg/src/stm32_spi.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <stdbool.h>
#include <errno.h>
#include <debug.h>
#include <sys/param.h>
#include <nuttx/spi/spi.h>
#include <arch/board/board.h>
#include "arm_internal.h"
#include "chip.h"
#include "stm32_gpio.h"
#include "stm32_spi.h"
#include "nucleo-f746zg.h"
#if defined(CONFIG_SPI)
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#if defined(CONFIG_NUCLEO_F746ZG_SPI1_TEST)
# if defined(CONFIG_NUCLEO_F746ZG_SPI1_TEST_MODE0)
# define CONFIG_NUCLEO_F746ZG_SPI1_TEST_MODE SPIDEV_MODE0
# elif defined(CONFIG_NUCLEO_F746ZG_SPI1_TEST_MODE1)
# define CONFIG_NUCLEO_F746ZG_SPI1_TEST_MODE SPIDEV_MODE1
# elif defined(CONFIG_NUCLEO_F746ZG_SPI1_TEST_MODE2)
# define CONFIG_NUCLEO_F746ZG_SPI1_TEST_MODE SPIDEV_MODE2
# elif defined(CONFIG_NUCLEO_F746ZG_SPI1_TEST_MODE3)
# define CONFIG_NUCLEO_F746ZG_SPI1_TEST_MODE SPIDEV_MODE3
# else
# error "No CONFIG_NUCLEO_F746ZG_SPI1_TEST_MODEx defined"
# endif
#endif
#if defined(CONFIG_NUCLEO_F746ZG_SPI2_TEST)
# if defined(CONFIG_NUCLEO_F746ZG_SPI2_TEST_MODE0)
# define CONFIG_NUCLEO_F746ZG_SPI2_TEST_MODE SPIDEV_MODE0
# elif defined(CONFIG_NUCLEO_F746ZG_SPI2_TEST_MODE1)
# define CONFIG_NUCLEO_F746ZG_SPI2_TEST_MODE SPIDEV_MODE1
# elif defined(CONFIG_NUCLEO_F746ZG_SPI2_TEST_MODE2)
# define CONFIG_NUCLEO_F746ZG_SPI2_TEST_MODE SPIDEV_MODE2
# elif defined(CONFIG_NUCLEO_F746ZG_SPI2_TEST_MODE3)
# define CONFIG_NUCLEO_F746ZG_SPI2_TEST_MODE SPIDEV_MODE3
# else
# error "No CONFIG_NUCLEO_F746ZG_SPI2_TEST_MODEx defined"
# endif
#endif
#if defined(CONFIG_NUCLEO_F746ZG_SPI3_TEST)
# if defined(CONFIG_NUCLEO_F746ZG_SPI3_TEST_MODE0)
# define CONFIG_NUCLEO_F746ZG_SPI3_TEST_MODE SPIDEV_MODE0
# elif defined(CONFIG_NUCLEO_F746ZG_SPI3_TEST_MODE1)
# define CONFIG_NUCLEO_F746ZG_SPI3_TEST_MODE SPIDEV_MODE1
# elif defined(CONFIG_NUCLEO_F746ZG_SPI3_TEST_MODE2)
# define CONFIG_NUCLEO_F746ZG_SPI3_TEST_MODE SPIDEV_MODE2
# elif defined(CONFIG_NUCLEO_F746ZG_SPI3_TEST_MODE3)
# define CONFIG_NUCLEO_F746ZG_SPI3_TEST_MODE SPIDEV_MODE3
# else
# error "No CONFIG_NUCLEO_F746ZG_SPI3_TEST_MODEx defined"
# endif
#endif
/****************************************************************************
* Private Data
****************************************************************************/
#if defined(CONFIG_STM32F7_SPI1)
static const uint32_t g_spi1gpio[] =
{
# if defined(GPIO_SPI1_CS0)
GPIO_SPI1_CS0,
# else
0,
# endif
# if defined(GPIO_SPI1_CS1)
GPIO_SPI1_CS1,
# else
0,
# endif
# if defined(GPIO_SPI1_CS2)
GPIO_SPI1_CS2,
# else
0,
# endif
# if defined(GPIO_SPI1_CS3)
GPIO_SPI1_CS3
# else
0
# endif
};
#endif
#if defined(CONFIG_STM32F7_SPI2)
static const uint32_t g_spi2gpio[] =
{
# if defined(GPIO_SPI2_CS0)
GPIO_SPI2_CS0,
# else
0,
# endif
# if defined(GPIO_SPI2_CS1)
GPIO_SPI2_CS1,
# else
0,
# endif
# if defined(GPIO_SPI2_CS2)
GPIO_SPI2_CS2,
# else
0,
# endif
# if defined(GPIO_SPI2_CS3)
GPIO_SPI2_CS3
# else
0
# endif
};
#endif
#if defined(CONFIG_STM32F7_SPI3)
static const uint32_t g_spi3gpio[] =
{
# if defined(GPIO_SPI3_CS0)
GPIO_SPI3_CS0,
# else
0,
# endif
# if defined(GPIO_SPI3_CS1)
GPIO_SPI3_CS1,
# else
0,
# endif
# if defined(GPIO_SPI3_CS2)
GPIO_SPI3_CS2,
# else
0,
# endif
# if defined(GPIO_SPI3_CS3)
GPIO_SPI3_CS3
# else
0
# endif
};
#endif
#if defined(CONFIG_NUCLEO_F746ZG_SPI_TEST)
# if defined(CONFIG_STM32F7_SPI1)
struct spi_dev_s *spi1;
# endif
# if defined(CONFIG_STM32F7_SPI2)
struct spi_dev_s *spi2;
# endif
# if defined(CONFIG_STM32F7_SPI3)
struct spi_dev_s *spi3;
# endif
#endif
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: stm32_spidev_initialize
*
* Description:
* Called to configure SPI chip select GPIO pins for the nucleo-f746zg
* board.
*
****************************************************************************/
void weak_function stm32_spidev_initialize(void)
{
/* Configure SPI CS GPIO for output */
#if defined(CONFIG_STM32F7_SPI1)
for (int i = 0; i < nitems(g_spi1gpio); i++)
{
if (g_spi1gpio[i] != 0)
{
stm32_configgpio(g_spi1gpio[i]);
}
}
#endif
#if defined(CONFIG_STM32F7_SPI2)
for (int i = 0; i < nitems(g_spi2gpio); i++)
{
if (g_spi2gpio[i] != 0)
{
stm32_configgpio(g_spi2gpio[i]);
}
}
#endif
#if defined(CONFIG_STM32F7_SPI3)
for (int i = 0; i < nitems(g_spi3gpio); i++)
{
if (g_spi3gpio[i] != 0)
{
stm32_configgpio(g_spi3gpio[i]);
}
}
#endif
}
/****************************************************************************
* Name: stm32_spi1/2/3/4/5/6select and stm32_spi1/2/3/4/5/6status
*
* Description:
* The external functions, stm32_spi1/2/3/4/5/6select and
* stm32_spi1/2/3/4/5/6status must be provided by board-specific logic.
* They are implementations of the select and status methods of the SPI
* interface defined by struct spi_ops_s (see include/nuttx/spi/spi.h).
* All other methods (including stm32_spibus_initialize())
* are provided by common STM32 logic. To use this common SPI logic on
* your board:
*
* 1. Provide logic in stm32_boardinitialize() to configure SPI chip select
* pins.
* 2. Provide stm32_spi1/2/3/4/5/6select() and stm32_spi1/2/3/4/5/6status()
* functions in your board-specific logic. These functions will perform
* chip selection and status operations using GPIOs in the way your
* board is configured.
* 3. Add a calls to stm32_spibus_initialize() in your low level
* application initialization logic
* 4. The handle returned by stm32_spibus_initialize() may then be used to
* bind the SPI driver to higher level logic (e.g., calling
* mmcsd_spislotinitialize(), for example, will bind the SPI driver to
* the SPI MMC/SD driver).
*
****************************************************************************/
#ifdef CONFIG_STM32F7_SPI1
void stm32_spi1select(struct spi_dev_s *dev,
uint32_t devid, bool selected)
{
uint32_t index = SPIDEVID_INDEX(devid);
spiinfo("devid: %d CS: %s\n",
(int)devid, selected ? "assert" : "de-assert");
if (g_spi1gpio[index] != 0)
{
stm32_gpiowrite(g_spi1gpio[index], !selected);
}
}
uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid)
{
return 0;
}
#endif
#ifdef CONFIG_STM32F7_SPI2
void stm32_spi2select(struct spi_dev_s *dev,
uint32_t devid, bool selected)
{
uint32_t index = SPIDEVID_INDEX(devid);
spiinfo("devid: %d CS: %s\n",
(int)devid, selected ? "assert" : "de-assert");
if (g_spi2gpio[index] != 0)
{
stm32_gpiowrite(g_spi2gpio[index], !selected);
}
}
uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid)
{
return 0;
}
#endif
#ifdef CONFIG_STM32F7_SPI3
void stm32_spi3select(struct spi_dev_s *dev,
uint32_t devid, bool selected)
{
uint32_t index = SPIDEVID_INDEX(devid);
spiinfo("devid: %d CS: %s\n",
(int)devid, selected ? "assert" : "de-assert");
if (g_spi3gpio[index] != 0)
{
stm32_gpiowrite(g_spi3gpio[index], !selected);
}
}
uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid)
{
return 0;
}
#endif
#ifdef CONFIG_STM32F7_SPI4
void stm32_spi4select(struct spi_dev_s *dev,
uint32_t devid, bool selected)
{
spiinfo("devid: %d CS: %s\n",
(int)devid, selected ? "assert" : "de-assert");
}
uint8_t stm32_spi4status(struct spi_dev_s *dev, uint32_t devid)
{
return 0;
}
#endif
#ifdef CONFIG_STM32F7_SPI5
void stm32_spi5select(struct spi_dev_s *dev,
uint32_t devid, bool selected)
{
spiinfo("devid: %d CS: %s\n",
(int)devid, selected ? "assert" : "de-assert");
}
uint8_t stm32_spi5status(struct spi_dev_s *dev, uint32_t devid)
{
return 0;
}
#endif
#ifdef CONFIG_STM32F7_SPI6
void stm32_spi6select(struct spi_dev_s *dev,
uint32_t devid, bool selected)
{
spiinfo("devid: %d CS: %s\n",
(int)devid, selected ? "assert" : "de-assert");
}
uint8_t stm32_spi6status(struct spi_dev_s *dev, uint32_t devid)
{
return 0;
}
#endif
/****************************************************************************
* Name: stm32_spi1/2/3/4/5/6cmddata
*
* Description:
* Set or clear the SH1101A A0 or SD1306 D/C n bit to select data (true)
* or command (false). This function must be provided by platform-specific
* logic. This is an implementation of the cmddata method of the SPI
* interface defined by struct spi_ops_s (see include/nuttx/spi/spi.h).
*
* Input Parameters:
*
* spi - SPI device that controls the bus the device that requires the CMD/
* DATA selection.
* devid - If there are multiple devices on the bus, this selects which one
* to select cmd or data. NOTE: This design restricts, for example,
* one one SPI display per SPI bus.
* cmd - true: select command; false: select data
*
* Returned Value:
* None
*
****************************************************************************/
#ifdef CONFIG_SPI_CMDDATA
#ifdef CONFIG_STM32F7_SPI1
int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd)
{
return -ENODEV;
}
#endif
#ifdef CONFIG_STM32F7_SPI2
int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd)
{
return -ENODEV;
}
#endif
#ifdef CONFIG_STM32F7_SPI3
int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd)
{
return -ENODEV;
}
#endif
#ifdef CONFIG_STM32F7_SPI4
int stm32_spi4cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd)
{
return -ENODEV;
}
#endif
#ifdef CONFIG_STM32F7_SPI5
int stm32_spi5cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd)
{
return -ENODEV;
}
#endif
#ifdef CONFIG_STM32F7_SPI6
int stm32_spi6cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd)
{
return -ENODEV;
}
#endif
#endif /* CONFIG_SPI_CMDDATA */
#if defined(CONFIG_NUCLEO_F746ZG_SPI_TEST)
int stm32_spidev_bus_test(void)
{
/* Configure and test SPI- */
uint8_t *tx = (uint8_t *)CONFIG_NUCLEO_F746ZG_SPI_TEST_MESSAGE;
#if defined(CONFIG_NUCLEO_F746ZG_SPI1_TEST)
spi1 = stm32_spibus_initialize(1);
if (!spi1)
{
syslog(LOG_ERR, "ERROR Failed to initialize SPI port 1\n");
return -ENODEV;
}
/* Default SPI1 to NUCLEO_F746ZG_SPI1_FREQ and mode */
SPI_SETFREQUENCY(spi1, CONFIG_NUCLEO_F746ZG_SPI1_TEST_FREQ);
SPI_SETBITS(spi1, CONFIG_NUCLEO_F746ZG_SPI1_TEST_BITS);
SPI_SETMODE(spi1, CONFIG_NUCLEO_F746ZG_SPI1_TEST_MODE);
SPI_EXCHANGE(spi1, tx, NULL,
nitems(CONFIG_NUCLEO_F746ZG_SPI_TEST_MESSAGE));
#endif
#if defined(CONFIG_NUCLEO_F746ZG_SPI2_TEST)
spi2 = stm32_spibus_initialize(2);
if (!spi2)
{
syslog(LOG_ERR, "ERROR Failed to initialize SPI port 2\n");
return -ENODEV;
}
/* Default SPI2 to NUCLEO_F746ZG_SPI2_FREQ and mode */
SPI_SETFREQUENCY(spi2, CONFIG_NUCLEO_F746ZG_SPI2_TEST_FREQ);
SPI_SETBITS(spi2, CONFIG_NUCLEO_F746ZG_SPI2_TEST_BITS);
SPI_SETMODE(spi2, CONFIG_NUCLEO_F746ZG_SPI2_TEST_MODE);
SPI_EXCHANGE(spi2, tx, NULL,
nitems(CONFIG_NUCLEO_F746ZG_SPI_TEST_MESSAGE));
#endif
#if defined(CONFIG_NUCLEO_F746ZG_SPI3_TEST)
spi3 = stm32_spibus_initialize(3);
if (!spi3)
{
syslog(LOG_ERR, "ERROR Failed to initialize SPI port 2\n");
return -ENODEV;
}
/* Default SPI3 to NUCLEO_F746ZG_SPI3_FREQ and mode */
SPI_SETFREQUENCY(spi3, CONFIG_NUCLEO_F746ZG_SPI3_TEST_FREQ);
SPI_SETBITS(spi3, CONFIG_NUCLEO_F746ZG_SPI3_TEST_BITS);
SPI_SETMODE(spi3, CONFIG_NUCLEO_F746ZG_SPI3_TEST_MODE);
SPI_EXCHANGE(spi3, tx, NULL,
nitems(CONFIG_NUCLEO_F746ZG_SPI_TEST_MESSAGE));
#endif
return OK;
}
#endif /* NUCLEO_F746ZG_SPI_TEST */
#endif /* defined(CONFIG_SPI) */

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/****************************************************************************
* boards/arm/stm32f7/nucleo-f746zg/src/stm32_usb.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <sys/types.h>
#include <stdint.h>
#include <stdbool.h>
#include <sched.h>
#include <errno.h>
#include <assert.h>
#include <debug.h>
#include <nuttx/kthread.h>
#include <nuttx/usb/usbdev.h>
#include <nuttx/usb/usbhost.h>
#include <nuttx/usb/usbdev_trace.h>
#include "arm_internal.h"
#include "chip.h"
#include "stm32_gpio.h"
#include "stm32_otg.h"
#include "nucleo-f746zg.h"
#ifdef CONFIG_STM32F7_OTGFS
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#if defined(CONFIG_USBDEV) || defined(CONFIG_USBHOST)
# define HAVE_USB 1
#else
# warning "CONFIG_STM32_OTGFS is enabled but neither CONFIG_USBDEV nor CONFIG_USBHOST"
# undef HAVE_USB
#endif
#ifndef CONFIG_NUCLEO144_USBHOST_PRIO
# define CONFIG_NUCLEO144_USBHOST_PRIO 100
#endif
#ifndef CONFIG_NUCLEO_USBHOST_STACKSIZE
# define CONFIG_NUCLEO_USBHOST_STACKSIZE 1024
#endif
/****************************************************************************
* Private Data
****************************************************************************/
#ifdef CONFIG_USBHOST
static struct usbhost_connection_s *g_usbconn;
#endif
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: usbhost_waiter
*
* Description:
* Wait for USB devices to be connected.
*
****************************************************************************/
#ifdef CONFIG_USBHOST
static int usbhost_waiter(int argc, char *argv[])
{
struct usbhost_hubport_s *hport;
uinfo("Running\n");
for (; ; )
{
/* Wait for the device to change state */
DEBUGVERIFY(CONN_WAIT(g_usbconn, &hport));
uinfo("%s\n", hport->connected ? "connected" : "disconnected");
/* Did we just become connected? */
if (hport->connected)
{
/* Yes.. enumerate the newly connected device */
CONN_ENUMERATE(g_usbconn, hport);
}
}
/* Keep the compiler from complaining */
return 0;
}
#endif
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: stm32_usbinitialize
*
* Description:
* Called from stm32_usbinitialize very early in inialization to setup
* USB-related GPIO pins for the nucleo-f746zg board.
*
****************************************************************************/
void stm32_usbinitialize(void)
{
/* The OTG FS has an internal soft pull-up.
* No GPIO configuration is required
*/
/* Configure the OTG FS VBUS sensing GPIO,
* Power On, and Overcurrent GPIOs
*/
#ifdef CONFIG_STM32F7_OTGFS
stm32_configgpio(GPIO_OTGFS_VBUS);
stm32_configgpio(GPIO_OTGFS_PWRON);
stm32_configgpio(GPIO_OTGFS_OVER);
#endif
}
/****************************************************************************
* Name: stm32_usbhost_initialize
*
* Description:
* Called at application startup time to initialize the USB host
* functionality.
* This function will start a thread that will monitor for device
* connection/disconnection events.
*
****************************************************************************/
#ifdef CONFIG_USBHOST
int stm32_usbhost_initialize(void)
{
int ret;
/* First, register all of the class drivers needed to support the drivers
* that we care about:
*/
uinfo("Register class drivers\n");
#ifdef CONFIG_USBHOST_HUB
/* Initialize USB hub class support */
ret = usbhost_hub_initialize();
if (ret < 0)
{
uerr("ERROR: usbhost_hub_initialize failed: %d\n", ret);
}
#endif
#ifdef CONFIG_USBHOST_MSC
/* Register the USB mass storage class class */
ret = usbhost_msc_initialize();
if (ret != OK)
{
uerr("ERROR: Failed to register the mass storage class: %d\n", ret);
}
#endif
#ifdef CONFIG_USBHOST_CDCACM
/* Register the CDC/ACM serial class */
ret = usbhost_cdcacm_initialize();
if (ret != OK)
{
uerr("ERROR: Failed to register the CDC/ACM serial class: %d\n", ret);
}
#endif
#ifdef CONFIG_USBHOST_HIDKBD
/* Initialize the HID keyboard class */
ret = usbhost_kbdinit();
if (ret != OK)
{
uerr("ERROR: Failed to register the HID keyboard class\n");
}
#endif
#ifdef CONFIG_USBHOST_HIDMOUSE
/* Initialize the HID mouse class */
ret = usbhost_mouse_init();
if (ret != OK)
{
uerr("ERROR: Failed to register the HID mouse class\n");
}
#endif
/* Then get an instance of the USB host interface */
uinfo("Initialize USB host\n");
g_usbconn = stm32_otgfshost_initialize(0);
if (g_usbconn)
{
/* Start a thread to handle device connection. */
uinfo("Start usbhost_waiter\n");
ret = kthread_create("usbhost", CONFIG_NUCLEO144_USBHOST_PRIO,
CONFIG_NUCLEO_USBHOST_STACKSIZE,
usbhost_waiter, NULL);
return ret < 0 ? -ENOEXEC : OK;
}
return -ENODEV;
}
#endif
/****************************************************************************
* Name: stm32_usbhost_vbusdrive
*
* Description:
* Enable/disable driving of VBUS 5V output. This function must be
* provided be each platform that implements the STM32 OTG FS host
* interface
*
* "On-chip 5 V VBUS generation is not supported. For this reason, a
* charge pump or, if 5 V are available on the application board, a
* basic power switch, must be added externally to drive the 5 V VBUS
* line. The external charge pump can be driven by any GPIO output.
* When the application decides to power on VBUS using the chosen GPIO,
* it must also set the port power bit in the host port control and
* status register (PPWR bit in OTG_FS_HPRT).
*
* "The application uses this field to control power to this port,
* and the core clears this bit on an overcurrent condition."
*
* Input Parameters:
* iface - For future growth to handle multiple USB host interface.
* Should be zero.
* enable - true: enable VBUS power; false: disable VBUS power
*
* Returned Value:
* None
*
****************************************************************************/
#ifdef CONFIG_USBHOST
void stm32_usbhost_vbusdrive(int iface, bool enable)
{
DEBUGASSERT(iface == 0);
/* Set the Power Switch by driving the active low enable pin */
stm32_gpiowrite(GPIO_OTGFS_PWRON, !enable);
}
#endif
/****************************************************************************
* Name: stm32_setup_overcurrent
*
* Description:
* Setup to receive an interrupt-level callback if an overcurrent
* condition is detected.
*
* Input Parameters:
* handler - New overcurrent interrupt handler
* arg - The argument provided for the interrupt handler
*
* Returned Value:
* Zero (OK) is returned on success. Otherwise, a negated errno value
* is returned to indicate the nature of the failure.
*
****************************************************************************/
#ifdef CONFIG_USBHOST
int stm32_setup_overcurrent(xcpt_t handler, void *arg)
{
return stm32_gpiosetevent(GPIO_OTGFS_OVER, true, true, true, handler, arg);
}
#endif
/****************************************************************************
* Name: stm32_usbsuspend
*
* Description:
* Board logic must provide the stm32_usbsuspend logic if the USBDEV
* driver is used. This function is called whenever the USB enters or
* leaves suspend mode. This is an opportunity for the board logic to
* shutdown clocks, power, etc. while the USB is suspended.
*
****************************************************************************/
#ifdef CONFIG_USBDEV
void stm32_usbsuspend(struct usbdev_s *dev, bool resume)
{
uinfo("resume: %d\n", resume);
}
#endif
#endif /* CONFIG_STM32_OTGFS */

125
boards/arm/stm32f7/nucleo-f746zg/src/stm32_userleds.c Normal file
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@ -0,0 +1,125 @@
/****************************************************************************
* boards/arm/stm32f7/nucleo-f746zg/src/stm32_userleds.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdbool.h>
#include <debug.h>
#include <sys/param.h>
#include <nuttx/board.h>
#include <arch/board/board.h>
#include "stm32_gpio.h"
#include "nucleo-f746zg.h"
#ifndef CONFIG_ARCH_LEDS
/****************************************************************************
* Private Data
****************************************************************************/
/* This array maps an LED number to GPIO pin configuration and is indexed by
* BOARD_LED_<color>
*/
static const uint32_t g_ledcfg[BOARD_NLEDS] =
{
GPIO_LED_GREEN,
GPIO_LED_BLUE,
GPIO_LED_RED,
};
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: board_userled_initialize
*
* Description:
* If CONFIG_ARCH_LEDS is defined, then NuttX will control the on-board
* LEDs. If CONFIG_ARCH_LEDS is not defined, then the
* board_userled_initialize() is available to initialize the LED from user
* application logic.
*
****************************************************************************/
uint32_t board_userled_initialize(void)
{
int i;
/* Configure LED1-3 GPIOs for output */
for (i = 0; i < nitems(g_ledcfg); i++)
{
stm32_configgpio(g_ledcfg[i]);
}
return BOARD_NLEDS;
}
/****************************************************************************
* Name: board_userled
*
* Description:
* If CONFIG_ARCH_LEDS is defined, then NuttX will control the on-board
* LEDs. If CONFIG_ARCH_LEDS is not defined, then the board_userled() is
* available to control the LED from user application logic.
*
****************************************************************************/
void board_userled(int led, bool ledon)
{
if ((unsigned)led < nitems(g_ledcfg))
{
stm32_gpiowrite(g_ledcfg[led], ledon);
}
}
/****************************************************************************
* Name: board_userled_all
*
* Description:
* If CONFIG_ARCH_LEDS is defined, then NuttX will control the on-board
* LEDs. If CONFIG_ARCH_LEDS is not defined, then the board_userled_all()
* is available to control the LED from user application logic. NOTE: since
* there is only a single LED on-board, this is function is not very useful.
*
****************************************************************************/
void board_userled_all(uint32_t ledset)
{
int i;
/* Configure LED1-3 GPIOs for output */
for (i = 0; i < nitems(g_ledcfg); i++)
{
stm32_gpiowrite(g_ledcfg[i], (ledset & (1 << i)) != 0);
}
}
#endif /* !CONFIG_ARCH_LEDS */

21
boards/arm/stm32f7/nucleo-f767zi/CMakeLists.txt Normal file
View file

@ -0,0 +1,21 @@
# ##############################################################################
# boards/arm/stm32f7/nucleo-f767zi/CMakeLists.txt
#
# Licensed to the Apache Software Foundation (ASF) under one or more contributor
# license agreements. See the NOTICE file distributed with this work for
# additional information regarding copyright ownership. The ASF licenses this
# file to you under the Apache License, Version 2.0 (the "License"); you may not
# use this file except in compliance with the License. You may obtain a copy of
# the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
# License for the specific language governing permissions and limitations under
# the License.
#
# ##############################################################################
add_subdirectory(src)

272
boards/arm/stm32f7/nucleo-f767zi/Kconfig Normal file
View file

@ -0,0 +1,272 @@
#
# For a description of the syntax of this configuration file,
# see the file kconfig-language.txt in the NuttX tools repository.
#
if ARCH_BOARD_NUCLEO_F767ZI
config STM32_ROMFS
bool "Automount baked-in ROMFS image"
default n
depends on FS_ROMFS
---help---
Select STM32_ROMFS_IMAGEFILE, STM32_ROMFS_DEV_MINOR, STM32_ROMFS_MOUNTPOINT
config STM32_ROMFS_DEV_MINOR
int "Minor for the block device backing the data"
depends on STM32_ROMFS
default 64
config STM32_ROMFS_MOUNTPOINT
string "Mountpoint of the custom romfs image"
depends on STM32_ROMFS
default "/rom"
config STM32_ROMFS_IMAGEFILE
string "ROMFS image file to include into build"
depends on STM32_ROMFS
default "../../../rom.img"
choice
prompt "Select Console wiring."
default NUCLEO_F767ZI_CONSOLE_ARDUINO
---help---
Select where you will connect the console.
Virtual COM Port:
Advantage: Use the ST-Link as a console. No Extra wiring
needed.
Disadvantage: Not the best choice for initial bring up.
ARDUINO Connector:
Advantage: You have a shield so it is easy.
Disadvantage: You loose the use of the
other functions on PC6, PC7
STM32F7
ARDUINO FUNCTION GPIO
-- ----- --------- ----
DO RX USART6_RX PG9
D1 TX USART6_TX PG14
-- ----- --------- ---
OR
Morpho Connector:
STM32F7
MORPHO FUNCTION GPIO
-------- --------- -----
CN12-64 UART8_RX PE0
CN11-61 UART8_TX PE1
-------- --------- -----
OR
Morpho Connector UART4:
STM32F7
MORPHO FUNCTION GPIO
-------- --------- -----
CN11-30 UART4_RX PA0
CN11-28 UART4_TX PA1
-------- --------- -----
Note: SB13 must be removed to disable Ethernet.
config NUCLEO_F767ZI_CONSOLE_ARDUINO
bool "Arduino Connector"
select STM32F7_USART6
select USART6_SERIALDRIVER
config NUCLEO_F767ZI_CONSOLE_VIRTUAL
bool "Virtual Comport"
select STM32F7_USART3
select USART3_SERIALDRIVER
config NUCLEO_F767ZI_CONSOLE_MORPHO
bool "Morpho Connector"
select STM32F7_UART8
select UART8_SERIALDRIVER
config NUCLEO_F767ZI_CONSOLE_MORPHO_UART4
bool "Morpho Connector UART4"
select STM32F7_UART4
select UART4_SERIALDRIVER
config NUCLEO_F767ZI_CONSOLE_NONE
bool "No Console"
endchoice # "Select Console wiring"
config NUCLEO_F767ZI_SPI_TEST
bool "Enable SPI test"
default n
---help---
Enable Spi test - initialize and configure SPI to send
NUCLEO_F767ZI_SPI_TEST_MESSAGE text. The text is sent on the
selected SPI Buses with the configured parameters.
Note the CS lines will not be asserted.
if NUCLEO_F767ZI_SPI_TEST
config NUCLEO_F767ZI_SPI_TEST_MESSAGE
string "Text to Send on SPI Bus(es)"
default "Hello World"
depends on NUCLEO_F767ZI_SPI_TEST
---help---
Text to sent on SPI bus(es)
config NUCLEO_F767ZI_SPI1_TEST
bool "Test SPI bus 1"
default n
depends on NUCLEO_F767ZI_SPI_TEST
---help---
Enable Spi test - on SPI BUS 1
if NUCLEO_F767ZI_SPI1_TEST
config NUCLEO_F767ZI_SPI1_TEST_FREQ
int "SPI 1 Clock Freq in Hz"
default 1000000
depends on NUCLEO_F767ZI_SPI1_TEST
---help---
Sets SPI 1 Clock Freq
config NUCLEO_F767ZI_SPI1_TEST_BITS
int "SPI 1 number of bits"
default 8
depends on NUCLEO_F767ZI_SPI1_TEST
---help---
Sets SPI 1 bit length
choice
prompt "SPI BUS 1 Clock Mode"
default NUCLEO_F767ZI_SPI1_TEST_MODE3
---help---
Sets SPI 1 clock mode
config NUCLEO_F767ZI_SPI1_TEST_MODE0
bool "CPOL=0 CPHA=0"
config NUCLEO_F767ZI_SPI1_TEST_MODE1
bool "CPOL=0 CPHA=1"
config NUCLEO_F767ZI_SPI1_TEST_MODE2
bool "CPOL=1 CPHA=0"
config NUCLEO_F767ZI_SPI1_TEST_MODE3
bool "CPOL=1 CPHA=1"
endchoice # "SPI BUS 1 Clock Mode"
endif # NUCLEO_F767ZI_SPI1_TEST
config NUCLEO_F767ZI_SPI2_TEST
bool "Test SPI bus 2"
default n
depends on NUCLEO_F767ZI_SPI_TEST
---help---
Enable Spi test - on SPI BUS 2
if NUCLEO_F767ZI_SPI2_TEST
config NUCLEO_F767ZI_SPI2_TEST_FREQ
int "SPI 2 Clock Freq in Hz"
default 12000000
depends on NUCLEO_F767ZI_SPI2_TEST
---help---
Sets SPI 2 Clock Freq
config NUCLEO_F767ZI_SPI2_TEST_BITS
int "SPI 2 number of bits"
default 8
depends on NUCLEO_F767ZI_SPI2_TEST
---help---
Sets SPI 2 bit length
choice
prompt "SPI BUS 2 Clock Mode"
default NUCLEO_F767ZI_SPI2_TEST_MODE3
---help---
Sets SPI 2 clock mode
config NUCLEO_F767ZI_SPI2_TEST_MODE0
bool "CPOL=0 CPHA=0"
config NUCLEO_F767ZI_SPI2_TEST_MODE1
bool "CPOL=0 CPHA=1"
config NUCLEO_F767ZI_SPI2_TEST_MODE2
bool "CPOL=1 CPHA=0"
config NUCLEO_F767ZI_SPI2_TEST_MODE3
bool "CPOL=1 CPHA=1"
endchoice # "SPI BUS 2 Clock Mode"
endif # NUCLEO_F767ZI_SPI2_TEST
config NUCLEO_F767ZI_SPI3_TEST
bool "Test SPI bus 3"
default n
depends on NUCLEO_F767ZI_SPI_TEST
---help---
Enable Spi test - on SPI BUS 3
if NUCLEO_F767ZI_SPI3_TEST
config NUCLEO_F767ZI_SPI3_TEST_FREQ
int "SPI 3 Clock Freq in Hz"
default 40000000
depends on NUCLEO_F767ZI_SPI3_TEST
---help---
Sets SPI 3 Clock Freq
config NUCLEO_F767ZI_SPI3_TEST_BITS
int "SPI 3 number of bits"
default 8
depends on NUCLEO_F767ZI_SPI3_TEST
---help---
Sets SPI 3 bit length
choice
prompt "SPI BUS 3 Clock Mode"
default NUCLEO_F767ZI_SPI3_TEST_MODE3
---help---
Sets SPI 3 clock mode
config NUCLEO_F767ZI_SPI3_TEST_MODE0
bool "CPOL=0 CPHA=0"
config NUCLEO_F767ZI_SPI3_TEST_MODE1
bool "CPOL=0 CPHA=1"
config NUCLEO_F767ZI_SPI3_TEST_MODE2
bool "CPOL=1 CPHA=0"
config NUCLEO_F767ZI_SPI3_TEST_MODE3
bool "CPOL=1 CPHA=1"
endchoice # "SPI BUS 3 Clock Mode"
endif # NUCLEO_F767ZI_SPI3_TEST
endif # NUCLEO_F767ZI_SPI_TEST
choice
prompt "CAN1 pins selection"
default NUCLEO_F767ZI_CAN1_MAP_PD0PD1
depends on STM32F7_CAN1
config NUCLEO_F767ZI_F767ZI_CAN1_MAP_D14D15
bool "CAN1_TX=D14 CAN1_RX=D15"
config NUCLEO_F767ZI_CAN1_MAP_PD0PD1
bool "CAN1_RX=PD0 CAN1_TX=PD1"
endchoice # CAN1 pins selection
endif # ARCH_BOARD_NUCLEO_F767ZI

6
boards/arm/stm32f7/nucleo-144/configs/f767-evalos/defconfig → boards/arm/stm32f7/nucleo-f767zi/configs/evalos/defconfig
View file

@ -12,8 +12,8 @@
# CONFIG_NSH_DISABLE_PS is not set
# CONFIG_STM32F7_USE_LEGACY_PINMAP is not set
CONFIG_ARCH="arm"
CONFIG_ARCH_BOARD="nucleo-144"
CONFIG_ARCH_BOARD_NUCLEO_144=y
CONFIG_ARCH_BOARD="nucleo-f767zi"
CONFIG_ARCH_BOARD_NUCLEO_F767ZI=y
CONFIG_ARCH_BUTTONS=y
CONFIG_ARCH_CHIP="stm32f7"
CONFIG_ARCH_CHIP_STM32F767ZI=y
@ -38,7 +38,7 @@ CONFIG_NSH_BUILTIN_APPS=y
CONFIG_NSH_FILEIOSIZE=512
CONFIG_NSH_LINELEN=64
CONFIG_NSH_READLINE=y
CONFIG_NUCLEO_CONSOLE_VIRTUAL=y
CONFIG_NUCLEO_F767ZI_CONSOLE_VIRTUAL=y
CONFIG_PREALLOC_TIMERS=4
CONFIG_PRIORITY_INHERITANCE=y
CONFIG_PTHREAD_MUTEX_DEFAULT_PRIO_INHERIT=y

6
boards/arm/stm32f7/nucleo-144/configs/f767-netnsh/defconfig → boards/arm/stm32f7/nucleo-f767zi/configs/netnsh/defconfig
View file

@ -7,8 +7,8 @@
#
# CONFIG_STM32F7_USE_LEGACY_PINMAP is not set
CONFIG_ARCH="arm"
CONFIG_ARCH_BOARD="nucleo-144"
CONFIG_ARCH_BOARD_NUCLEO_144=y
CONFIG_ARCH_BOARD="nucleo-f767zi"
CONFIG_ARCH_BOARD_NUCLEO_F767ZI=y
CONFIG_ARCH_BUTTONS=y
CONFIG_ARCH_CHIP="stm32f7"
CONFIG_ARCH_CHIP_STM32F767ZI=y
@ -50,7 +50,7 @@ CONFIG_NSH_BUILTIN_APPS=y
CONFIG_NSH_FILEIOSIZE=512
CONFIG_NSH_LINELEN=64
CONFIG_NSH_READLINE=y
CONFIG_NUCLEO_CONSOLE_VIRTUAL=y
CONFIG_NUCLEO_F767ZI_CONSOLE_VIRTUAL=y
CONFIG_PREALLOC_TIMERS=4
CONFIG_RAM_SIZE=245760
CONFIG_RAM_START=0x20010000

6
boards/arm/stm32f7/nucleo-144/configs/f767-nsh/defconfig → boards/arm/stm32f7/nucleo-f767zi/configs/nsh/defconfig
View file

@ -10,8 +10,8 @@
# CONFIG_NSH_DISABLE_PS is not set
# CONFIG_STM32F7_USE_LEGACY_PINMAP is not set
CONFIG_ARCH="arm"
CONFIG_ARCH_BOARD="nucleo-144"
CONFIG_ARCH_BOARD_NUCLEO_144=y
CONFIG_ARCH_BOARD="nucleo-f767zi"
CONFIG_ARCH_BOARD_NUCLEO_F767ZI=y
CONFIG_ARCH_BUTTONS=y
CONFIG_ARCH_CHIP="stm32f7"
CONFIG_ARCH_CHIP_STM32F767ZI=y
@ -32,7 +32,7 @@ CONFIG_NSH_BUILTIN_APPS=y
CONFIG_NSH_FILEIOSIZE=512
CONFIG_NSH_LINELEN=64
CONFIG_NSH_READLINE=y
CONFIG_NUCLEO_CONSOLE_VIRTUAL=y
CONFIG_NUCLEO_F767ZI_CONSOLE_VIRTUAL=y
CONFIG_PREALLOC_TIMERS=4
CONFIG_RAM_SIZE=245760
CONFIG_RAM_START=0x20010000

568
boards/arm/stm32f7/nucleo-f767zi/include/board.h Normal file
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@ -0,0 +1,568 @@
/****************************************************************************
* boards/arm/stm32f7/nucleo-f767zi/include/board.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __BOARDS_ARM_STM32F7_NUCLEO_F767ZI_INCLUDE_BOARD_H
#define __BOARDS_ARM_STM32F7_NUCLEO_F767ZI_INCLUDE_BOARD_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#ifndef __ASSEMBLY__
# include <stdint.h>
#endif
/* Do not include STM32 F7 header files here */
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Clocking *****************************************************************/
/* The Nucleo-f767zi board provides the following clock sources:
*
* MCO: 8 MHz from MCO output of ST-LINK is used as input clock
* X2: 32.768 KHz crystal for LSE
* X3: HSE crystal oscillator (not provided)
*
* So we have these clock source available within the STM32
*
* HSI: 16 MHz RC factory-trimmed
* LSI: 32 KHz RC
* HSE: 8 MHz from MCO output of ST-LINK
* LSE: 32.768 kHz
*/
#define STM32_BOARD_XTAL 8000000ul
#define STM32_HSI_FREQUENCY 16000000ul
#define STM32_LSI_FREQUENCY 32000
#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL
#define STM32_LSE_FREQUENCY 32768
/* Main PLL Configuration.
*
* PLL source is HSE = 8,000,000
*
* PLL_VCO = (STM32_HSE_FREQUENCY / PLLM) * PLLN
* Subject to:
*
* 2 <= PLLM <= 63
* 192 <= PLLN <= 432
* 192 MHz <= PLL_VCO <= 432MHz
*
* SYSCLK = PLL_VCO / PLLP
* Subject to
*
* PLLP = {2, 4, 6, 8}
* SYSCLK <= 216 MHz
*
* USB OTG FS, SDMMC and RNG Clock = PLL_VCO / PLLQ
* Subject to
* The USB OTG FS requires a 48 MHz clock to work correctly. The SDMMC
* and the random number generator need a frequency lower than or equal
* to 48 MHz to work correctly.
*
* 2 <= PLLQ <= 15
*/
/* Highest SYSCLK with USB OTG FS clock = 48 MHz
*
* PLL_VCO = (8,000,000 / 4) * 216 = 432 MHz
* SYSCLK = 432 MHz / 2 = 216 MHz
* USB OTG FS, SDMMC and RNG Clock = 432 MHz / 9 = 48 MHz
*/
#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(4)
#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(216)
#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_2
#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(9)
#define STM32_VCO_FREQUENCY ((STM32_HSE_FREQUENCY / 4) * 216)
#define STM32_SYSCLK_FREQUENCY (STM32_VCO_FREQUENCY / 2)
#define STM32_OTGFS_FREQUENCY (STM32_VCO_FREQUENCY / 9)
/* Configure factors for PLLSAI clock */
#define CONFIG_STM32F7_PLLSAI 1
#define STM32_RCC_PLLSAICFGR_PLLSAIN RCC_PLLSAICFGR_PLLSAIN(192)
#define STM32_RCC_PLLSAICFGR_PLLSAIP RCC_PLLSAICFGR_PLLSAIP(8)
#define STM32_RCC_PLLSAICFGR_PLLSAIQ RCC_PLLSAICFGR_PLLSAIQ(4)
#define STM32_RCC_PLLSAICFGR_PLLSAIR RCC_PLLSAICFGR_PLLSAIR(2)
/* Configure Dedicated Clock Configuration Register */
#define STM32_RCC_DCKCFGR1_PLLI2SDIVQ RCC_DCKCFGR1_PLLI2SDIVQ(1)
#define STM32_RCC_DCKCFGR1_PLLSAIDIVQ RCC_DCKCFGR1_PLLSAIDIVQ(1)
#define STM32_RCC_DCKCFGR1_PLLSAIDIVR RCC_DCKCFGR1_PLLSAIDIVR(0)
#define STM32_RCC_DCKCFGR1_SAI1SRC RCC_DCKCFGR1_SAI1SEL(0)
#define STM32_RCC_DCKCFGR1_SAI2SRC RCC_DCKCFGR1_SAI2SEL(0)
#define STM32_RCC_DCKCFGR1_TIMPRESRC 0
#define STM32_RCC_DCKCFGR1_DFSDM1SRC 0
#define STM32_RCC_DCKCFGR1_ADFSDM1SRC 0
/* Configure factors for PLLI2S clock */
#define CONFIG_STM32F7_PLLI2S 1
#define STM32_RCC_PLLI2SCFGR_PLLI2SN RCC_PLLI2SCFGR_PLLI2SN(192)
#define STM32_RCC_PLLI2SCFGR_PLLI2SP RCC_PLLI2SCFGR_PLLI2SP(2)
#define STM32_RCC_PLLI2SCFGR_PLLI2SQ RCC_PLLI2SCFGR_PLLI2SQ(2)
#define STM32_RCC_PLLI2SCFGR_PLLI2SR RCC_PLLI2SCFGR_PLLI2SR(2)
/* Configure Dedicated Clock Configuration Register 2 */
#define STM32_RCC_DCKCFGR2_USART1SRC RCC_DCKCFGR2_USART1SEL_APB
#define STM32_RCC_DCKCFGR2_USART2SRC RCC_DCKCFGR2_USART2SEL_APB
#define STM32_RCC_DCKCFGR2_UART4SRC RCC_DCKCFGR2_UART4SEL_APB
#define STM32_RCC_DCKCFGR2_UART5SRC RCC_DCKCFGR2_UART5SEL_APB
#define STM32_RCC_DCKCFGR2_USART6SRC RCC_DCKCFGR2_USART6SEL_APB
#define STM32_RCC_DCKCFGR2_UART7SRC RCC_DCKCFGR2_UART7SEL_APB
#define STM32_RCC_DCKCFGR2_UART8SRC RCC_DCKCFGR2_UART8SEL_APB
#define STM32_RCC_DCKCFGR2_I2C1SRC RCC_DCKCFGR2_I2C1SEL_HSI
#define STM32_RCC_DCKCFGR2_I2C2SRC RCC_DCKCFGR2_I2C2SEL_HSI
#define STM32_RCC_DCKCFGR2_I2C3SRC RCC_DCKCFGR2_I2C3SEL_HSI
#define STM32_RCC_DCKCFGR2_I2C4SRC RCC_DCKCFGR2_I2C4SEL_HSI
#define STM32_RCC_DCKCFGR2_LPTIM1SRC RCC_DCKCFGR2_LPTIM1SEL_APB
#define STM32_RCC_DCKCFGR2_CECSRC RCC_DCKCFGR2_CECSEL_HSI
#define STM32_RCC_DCKCFGR2_CK48MSRC RCC_DCKCFGR2_CK48MSEL_PLL
#define STM32_RCC_DCKCFGR2_SDMMCSRC RCC_DCKCFGR2_SDMMCSEL_48MHZ
#define STM32_RCC_DCKCFGR2_SDMMC2SRC RCC_DCKCFGR2_SDMMC2SEL_48MHZ
#define STM32_RCC_DCKCFGR2_DSISRC RCC_DCKCFGR2_DSISEL_PHY
/* Several prescalers allow the configuration of the two AHB buses, the
* high-speed APB (APB2) and the low-speed APB (APB1) domains. The maximum
* frequency of the two AHB buses is 216 MHz while the maximum frequency of
* the high-speed APB domains is 108 MHz. The maximum allowed frequency of
* the low-speed APB domain is 54 MHz.
*/
/* AHB clock (HCLK) is SYSCLK (216 MHz) */
#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */
#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY
/* APB1 clock (PCLK1) is HCLK/4 (54 MHz) */
#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd4 /* PCLK1 = HCLK / 4 */
#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/4)
/* Timers driven from APB1 will be twice PCLK1 */
#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY)
#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY)
#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY)
#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY)
#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY)
#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY)
#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY)
#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY)
#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY)
/* APB2 clock (PCLK2) is HCLK/2 (108MHz) */
#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLKd2 /* PCLK2 = HCLK / 2 */
#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/2)
/* Timers driven from APB2 will be twice PCLK2 */
#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY)
#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY)
#define STM32_APB2_TIM9_CLKIN (2*STM32_PCLK2_FREQUENCY)
#define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK2_FREQUENCY)
#define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK2_FREQUENCY)
/* SDMMC dividers. Note that slower clocking is required when DMA
* is disabledin order to avoid RX overrun/TX underrun errors due
* to delayed responses to service FIFOs in interrupt driven mode.
* These values have not been tuned!!!
*
* SDMMCCLK=48MHz, SDMMC_CK=SDMMCCLK/(118+2)=400 KHz
*/
#define STM32_SDMMC_INIT_CLKDIV (118 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT)
/* DMA ON: SDMMCCLK=48MHz, SDMMC_CK=SDMMCCLK/(1+2)=16 MHz
* DMA OFF: SDMMCCLK=48MHz, SDMMC_CK=SDMMCCLK/(2+2)=12 MHz
*/
#ifdef CONFIG_SDIO_DMA
# define STM32_SDMMC_MMCXFR_CLKDIV (1 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT)
#else
# define STM32_SDMMC_MMCXFR_CLKDIV (2 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT)
#endif
/* DMA ON: SDMMCCLK=48MHz, SDMMC_CK=SDMMCCLK/(1+2)=16 MHz
* DMA OFF: SDMMCCLK=48MHz, SDMMC_CK=SDMMCCLK/(2+2)=12 MHz
*/
#ifdef CONFIG_SDIO_DMA
# define STM32_SDMMC_SDXFR_CLKDIV (1 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT)
#else
# define STM32_SDMMC_SDXFR_CLKDIV (2 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT)
#endif
/* DMA Channel/Stream Selections ********************************************/
/* Stream selections are arbitrary for now but might become important in the
* future if we set aside more DMA channels/streams.
*
* SDMMC DMA is on DMA2
*
* SDMMC1 DMA
* DMAMAP_SDMMC1_1 = Channel 4, Stream 3
* DMAMAP_SDMMC1_2 = Channel 4, Stream 6
*
* SDMMC2 DMA
* DMAMAP_SDMMC2_1 = Channel 11, Stream 0
* DMAMAP_SDMMC3_2 = Channel 11, Stream 5
*/
#define DMAMAP_SDMMC1 DMAMAP_SDMMC1_1
#define DMAMAP_SDMMC2 DMAMAP_SDMMC2_1
/* FLASH wait states
*
* --------- ---------- -----------
* VDD MAX SYSCLK WAIT STATES
* --------- ---------- -----------
* 1.7-2.1 V 180 MHz 8
* 2.1-2.4 V 216 MHz 9
* 2.4-2.7 V 216 MHz 8
* 2.7-3.6 V 216 MHz 7
* --------- ---------- -----------
*/
#define BOARD_FLASH_WAITSTATES 7
/* LED definitions **********************************************************/
/* The Nucleo-f767zi board has numerous LEDs but only three, LD1 a Green LED,
* LD2 a Blue LED and LD3 a Red LED, that can be controlled by software.
* The following definitions assume the default Solder Bridges are installed.
*
* If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs
* in any way.
* The following definitions are used to access individual LEDs.
*/
/* LED index values for use with board_userled() */
#define BOARD_LED1 0
#define BOARD_LED2 1
#define BOARD_LED3 2
#define BOARD_NLEDS 3
#define BOARD_LED_GREEN BOARD_LED1
#define BOARD_LED_BLUE BOARD_LED2
#define BOARD_LED_RED BOARD_LED3
/* LED bits for use with board_userled_all() */
#define BOARD_LED1_BIT (1 << BOARD_LED1)
#define BOARD_LED2_BIT (1 << BOARD_LED2)
#define BOARD_LED3_BIT (1 << BOARD_LED3)
/* If CONFIG_ARCH_LEDS is defined, the usage by the board port is defined in
* include/board.h and src/stm32_leds.c. The LEDs are used to encode
* OS-relatedevents as follows:
*
*
* SYMBOL Meaning LED state
* Red Green Blue
* ---------------------- -------------------------- ------ ------ ----
*/
#define LED_STARTED 0 /* NuttX has been started OFF OFF OFF */
#define LED_HEAPALLOCATE 1 /* Heap has been allocated OFF OFF ON */
#define LED_IRQSENABLED 2 /* Interrupts enabled OFF ON OFF */
#define LED_STACKCREATED 3 /* Idle stack created OFF ON ON */
#define LED_INIRQ 4 /* In an interrupt N/C N/C GLOW */
#define LED_SIGNAL 5 /* In a signal handler N/C GLOW N/C */
#define LED_ASSERTION 6 /* An assertion failed GLOW N/C GLOW */
#define LED_PANIC 7 /* The system has crashed Blink OFF N/C */
#define LED_IDLE 8 /* MCU is is sleep mode ON OFF OFF */
/* Thus if the Green LED is statically on, NuttX has successfully booted and
* is, apparently, running normally. If the Red LED is flashing at
* approximately 2Hz, then a fatal error has been detected and the system
* has halted.
*/
/* Button definitions *******************************************************/
/* The STM32F7 Discovery supports one button: Pushbutton B1, labeled "User",
* is connected to GPIO PI11.
* A high value will be sensed when the button is depressed.
*/
#define BUTTON_USER 0
#define NUM_BUTTONS 1
#define BUTTON_USER_BIT (1 << BUTTON_USER)
/* DMA channels *************************************************************/
/* ADC */
#define ADC1_DMA_CHAN DMAMAP_ADC1_1
#define ADC2_DMA_CHAN DMAMAP_ADC2_1
#define ADC3_DMA_CHAN DMAMAP_ADC3_1
/* Alternate function pin selections ****************************************/
/* ADC1 */
#define GPIO_ADC1_IN0 GPIO_ADC1_IN0_0 /* PA0 */
#define GPIO_ADC1_IN1 GPIO_ADC1_IN1_0 /* PA1 */
#define GPIO_ADC1_IN2 GPIO_ADC1_IN2_0 /* PA2 */
#define GPIO_ADC1_IN3 GPIO_ADC1_IN3_0 /* PA3 */
#define GPIO_ADC1_IN4 GPIO_ADC1_IN4_0 /* PA4 */
#define GPIO_ADC1_IN5 GPIO_ADC1_IN5_0 /* PA5 */
#define GPIO_ADC1_IN6 GPIO_ADC1_IN6_0 /* PA6 */
#define GPIO_ADC1_IN7 GPIO_ADC1_IN7_0 /* PA7 */
#define GPIO_ADC1_IN8 GPIO_ADC1_IN8_0 /* PB0 */
#define GPIO_ADC1_IN9 GPIO_ADC1_IN9_0 /* PB1 */
#define GPIO_ADC1_IN10 GPIO_ADC1_IN10_0 /* PC0 */
#define GPIO_ADC1_IN11 GPIO_ADC1_IN11_0 /* PC1 */
#define GPIO_ADC1_IN12 GPIO_ADC1_IN12_0 /* PC2 */
#define GPIO_ADC1_IN13 GPIO_ADC1_IN13_0 /* PC3 */
#define GPIO_ADC1_IN14 GPIO_ADC1_IN14_0 /* PC4 */
#define GPIO_ADC1_IN15 GPIO_ADC1_IN15_0 /* PC5 */
/* TIM */
/* Quadrature encoder
* Default is to use timer 8 (16-bit) and encoder on PC6/PC7
* We use here TIM2 with a 32-bit counter on PA15/PB3
*/
#define GPIO_TIM1_CH1IN (GPIO_TIM1_CH1IN_2|GPIO_SPEED_50MHz)
#define GPIO_TIM1_CH2IN (GPIO_TIM1_CH2IN_2|GPIO_SPEED_50MHz)
#define GPIO_TIM2_CH1IN (GPIO_TIM2_CH1IN_2|GPIO_SPEED_50MHz)
#define GPIO_TIM2_CH2IN (GPIO_TIM2_CH2IN_2|GPIO_SPEED_50MHz)
#define GPIO_TIM3_CH1IN (GPIO_TIM3_CH1IN_2|GPIO_SPEED_50MHz)
#define GPIO_TIM3_CH2IN (GPIO_TIM3_CH2IN_2|GPIO_SPEED_50MHz)
#define GPIO_TIM4_CH1IN (GPIO_TIM4_CH1IN_2|GPIO_SPEED_50MHz)
#define GPIO_TIM4_CH2IN (GPIO_TIM4_CH2IN_2|GPIO_SPEED_50MHz)
#define GPIO_TIM8_CH1IN (GPIO_TIM8_CH1IN_1|GPIO_SPEED_50MHz)
#define GPIO_TIM8_CH2IN (GPIO_TIM8_CH2IN_1|GPIO_SPEED_50MHz)
/* PWM
* Use Timer 1 or 3
*/
#define GPIO_TIM1_CH1OUT (GPIO_TIM1_CH1OUT_2|GPIO_SPEED_50MHz)
#define GPIO_TIM1_CH1NOUT (GPIO_TIM1_CH1NOUT_3|GPIO_SPEED_50MHz)
#define GPIO_TIM1_CH2OUT (GPIO_TIM1_CH2OUT_2|GPIO_SPEED_50MHz)
#define GPIO_TIM1_CH2NOUT (GPIO_TIM1_CH2NOUT_3|GPIO_SPEED_50MHz)
#define GPIO_TIM3_CH1OUT (GPIO_TIM3_CH1OUT_2|GPIO_SPEED_50MHz)
#define GPIO_TIM3_CH2OUT (GPIO_TIM3_CH2OUT_2|GPIO_SPEED_50MHz)
#define GPIO_TIM3_CH3OUT (GPIO_TIM3_CH3OUT_2|GPIO_SPEED_50MHz)
#define GPIO_TIM3_CH4OUT (GPIO_TIM3_CH4OUT_1|GPIO_SPEED_50MHz)
#if defined(CONFIG_NUCLEO_F767ZI_CONSOLE_ARDUINO)
/* USART6:
*
* These configurations assume that you are using a standard Arduio RS-232
* shield with the serial interface with RX on pin D0 and TX on pin D1:
*
* -------- ---------------
* STM32F7
* ARDUIONO FUNCTION GPIO
* -- ----- --------- -----
* DO RX USART6_RX PG9
* D1 TX USART6_TX PG14
* -- ----- --------- -----
*/
# define GPIO_USART6_RX (GPIO_USART6_RX_2|GPIO_SPEED_100MHz)
# define GPIO_USART6_TX (GPIO_USART6_TX_2|GPIO_SPEED_100MHz)
#endif
/* USART3:
* Use USART3 and the USB virtual COM port
*/
#if defined(CONFIG_NUCLEO_F767ZI_CONSOLE_VIRTUAL)
# define GPIO_USART3_RX (GPIO_USART3_RX_3|GPIO_SPEED_100MHz)
# define GPIO_USART3_TX (GPIO_USART3_TX_3|GPIO_SPEED_100MHz)
#endif
#if defined(CONFIG_NUCLEO_F767ZI_CONSOLE_MORPHO_UART4)
/* UART4:
*
* This configuration assumes that you disabled Ethernet MII clocking
* by removing SB13 to free PA1.
*
* -------- ---------------
* STM32F7
* Pin FUNCTION GPIO
* ------- --------- -----
* CN11 30 UART4_RX PA1
* CN11 28 UART4_TX PA0
* ------- --------- -----
*/
# define GPIO_UART4_RX (GPIO_UART4_RX_1|GPIO_SPEED_100MHz)
# define GPIO_UART4_TX (GPIO_UART4_TX_1|GPIO_SPEED_100MHz)
/* USART3 seems to be forced selected by the Nucleo-F746ZG kconfig - bug */
# define GPIO_USART3_RX (GPIO_USART3_RX_1|GPIO_SPEED_100MHz)
# define GPIO_USART3_TX (GPIO_USART3_TX_1|GPIO_SPEED_100MHz)
/* USART6 seems to be forced selected by the Nucleo-F722E kconfig - bug */
# define GPIO_USART6_RX (GPIO_USART6_RX_2|GPIO_SPEED_100MHz)
# define GPIO_USART6_TX (GPIO_USART6_TX_2|GPIO_SPEED_100MHz)
#endif
/* USART8:
*
* This configurations assume that you are connecting to the Morpho connector
* with the serial interface with the adaptor's RX on pin CN11 pin 64 and
* TX on pin CN11 pin 61
*
* USART8: has no remap
*/
/* SPI
*
*
* PA6 SPI1_MISO CN12-13
* PA7 SPI1_MOSI CN12-15
* PA5 SPI1_SCK CN12-11
*
* PB14 SPI2_MISO CN12-28
* PB15 SPI2_MOSI CN12-26
* PB13 SPI2_SCK CN12-30
*
* PB4 SPI3_MISO CN12-27
* PB5 SPI3_MOSI CN12-29
* PB3 SPI3_SCK CN12-31
*/
#define GPIO_SPI1_MISO (GPIO_SPI1_MISO_1|GPIO_SPEED_50MHz)
#define GPIO_SPI1_MOSI (GPIO_SPI1_MOSI_1|GPIO_SPEED_50MHz)
#define GPIO_SPI1_SCK (GPIO_SPI1_SCK_1|GPIO_SPEED_50MHz)
#define GPIO_SPI2_MISO (GPIO_SPI2_MISO_1|GPIO_SPEED_50MHz)
#define GPIO_SPI2_MOSI (GPIO_SPI2_MOSI_1|GPIO_SPEED_50MHz)
#define GPIO_SPI2_SCK (GPIO_SPI2_SCK_3|GPIO_SPEED_50MHz)
#define GPIO_SPI3_MISO (GPIO_SPI3_MISO_1|GPIO_SPEED_50MHz)
#define GPIO_SPI3_MOSI (GPIO_SPI3_MOSI_2|GPIO_SPEED_50MHz)
#define GPIO_SPI3_SCK (GPIO_SPI3_SCK_1|GPIO_SPEED_50MHz)
/* I2C
*
*
* PB8 I2C1_SCL CN12-3
* PB9 I2C1_SDA CN12-5
* PB10 I2C2_SCL CN11-51
* PB11 I2C2_SDA CN12-18
*
* PA8 I2C3_SCL CN12-23
* PC9 I2C3_SDA CN12-1
*
*/
#define GPIO_I2C1_SCL (GPIO_I2C1_SCL_2|GPIO_SPEED_50MHz)
#define GPIO_I2C1_SDA (GPIO_I2C1_SDA_2|GPIO_SPEED_50MHz)
#define GPIO_I2C2_SCL (GPIO_I2C2_SCL_1|GPIO_SPEED_50MHz)
#define GPIO_I2C2_SDA (GPIO_I2C2_SDA_1|GPIO_SPEED_50MHz)
#define GPIO_I2C3_SCL (GPIO_I2C3_SCL_1|GPIO_SPEED_50MHz)
#define GPIO_I2C3_SDA (GPIO_I2C3_SDA_1|GPIO_SPEED_50MHz)
/* The STM32 F7 connects to a SMSC LAN8742A PHY using these pins:
*
* STM32 F7 BOARD LAN8742A
* GPIO SIGNAL PIN NAME
* -------- ------------ -------------
* PG11 RMII_TX_EN TXEN
* PG13 RMII_TXD0 TXD0
* PB13 RMII_TXD1 TXD1
* PC4 RMII_RXD0 RXD0/MODE0
* PC5 RMII_RXD1 RXD1/MODE1
* PG2 RMII_RXER RXER/PHYAD0 -- Not used
* PA7 RMII_CRS_DV CRS_DV/MODE2
* PC1 RMII_MDC MDC
* PA2 RMII_MDIO MDIO
* N/A NRST nRST
* PA1 RMII_REF_CLK nINT/REFCLK0
* N/A OSC_25M XTAL1/CLKIN
*
* The PHY address is either 0 or 1, depending on the state of PG2 on reset.
* PG2 is not controlled but appears to result in a PHY address of 0.
*/
#define GPIO_ETH_MDC (GPIO_ETH_MDC_0|GPIO_SPEED_100MHz)
#define GPIO_ETH_MDIO (GPIO_ETH_MDIO_0|GPIO_SPEED_100MHz)
#define GPIO_ETH_RMII_CRS_DV (GPIO_ETH_RMII_CRS_DV_0|GPIO_SPEED_100MHz)
#define GPIO_ETH_RMII_REF_CLK (GPIO_ETH_RMII_REF_CLK_0|GPIO_SPEED_100MHz)
#define GPIO_ETH_RMII_RXD0 (GPIO_ETH_RMII_RXD0_0|GPIO_SPEED_100MHz)
#define GPIO_ETH_RMII_RXD1 (GPIO_ETH_RMII_RXD1_0|GPIO_SPEED_100MHz)
#define GPIO_ETH_RMII_TX_EN (GPIO_ETH_RMII_TX_EN_2|GPIO_SPEED_100MHz)
#define GPIO_ETH_RMII_TXD0 (GPIO_ETH_RMII_TXD0_2|GPIO_SPEED_100MHz)
#define GPIO_ETH_RMII_TXD1 (GPIO_ETH_RMII_TXD1_1|GPIO_SPEED_100MHz)
/* CAN Bus */
#ifdef CONFIG_NUCLEO_F767ZI_CAN1_MAP_PD0PD1
# define GPIO_CAN1_TX (GPIO_CAN1_TX_3|GPIO_SPEED_50MHz) /* PD1 */
# define GPIO_CAN1_RX (GPIO_CAN1_RX_3|GPIO_SPEED_50MHz) /* PD0 */
#elif CONFIG_NUCLEO_F767ZI_CAN1_MAP_D14D15
# define GPIO_CAN1_TX (GPIO_CAN1_TX_2|GPIO_SPEED_50MHz) /* PB9 */
# define GPIO_CAN1_RX (GPIO_CAN1_RX_2|GPIO_SPEED_50MHz) /* PB8 */
#endif
/* SDMMC2 */
#define GPIO_SDMMC2_CK (GPIO_SDMMC2_CK_0|GPIO_SPEED_50MHz)
#define GPIO_SDMMC2_CMD (GPIO_SDMMC2_CMD_0|GPIO_SPEED_50MHz)
#define GPIO_SDMMC2_D0 (GPIO_SDMMC2_D0_0|GPIO_SPEED_50MHz)
#define GPIO_SDMMC2_D1 (GPIO_SDMMC2_D1_0|GPIO_SPEED_50MHz)
#define GPIO_SDMMC2_D2 (GPIO_SDMMC2_D2_0|GPIO_SPEED_50MHz)
#define GPIO_SDMMC2_D3 (GPIO_SDMMC2_D3_0|GPIO_SPEED_50MHz)
#define GPIO_SDMMC2_D4 (GPIO_SDMMC2_D4_0|GPIO_SPEED_50MHz)
#define GPIO_SDMMC2_D5 (GPIO_SDMMC2_D5_0|GPIO_SPEED_50MHz)
#define GPIO_SDMMC2_D6 (GPIO_SDMMC2_D6_0|GPIO_SPEED_50MHz)
#define GPIO_SDMMC2_D7 (GPIO_SDMMC2_D7_0|GPIO_SPEED_50MHz)
/* OTGFS */
#define GPIO_OTGFS_DM (GPIO_OTGFS_DM_0|GPIO_SPEED_100MHz)
#define GPIO_OTGFS_DP (GPIO_OTGFS_DP_0|GPIO_SPEED_100MHz)
#define GPIO_OTGFS_ID (GPIO_OTGFS_ID_0|GPIO_SPEED_100MHz)
#endif /* __BOARDS_ARM_STM32F7_NUCLEO_F767ZI_INCLUDE_BOARD_H */

4
boards/arm/stm32f7/nucleo-144/configs/f746-nsh/Make.defs → boards/arm/stm32f7/nucleo-f767zi/scripts/Make.defs
View file

@ -1,5 +1,5 @@
############################################################################
# boards/arm/stm32f7/nucleo-144/configs/f746-nsh/Make.defs
# boards/arm/stm32f7/nucleo-f767/scriptsMake.defs
#
# Licensed to the Apache Software Foundation (ASF) under one or more
# contributor license agreements. See the NOTICE file distributed with
@ -22,7 +22,7 @@ include $(TOPDIR)/.config
include $(TOPDIR)/tools/Config.mk
include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs
LDSCRIPT = f746-flash.ld
LDSCRIPT = flash.ld
ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT)
ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10

2
boards/arm/stm32f7/nucleo-144/scripts/f767-flash.ld → boards/arm/stm32f7/nucleo-f767zi/scripts/flash.ld
View file

@ -1,5 +1,5 @@
/****************************************************************************
* boards/arm/stm32f7/nucleo-144/scripts/f767-flash.ld
* boards/arm/stm32f7/nucleo-f767zi/scripts/flash.ld
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with

97
boards/arm/stm32f7/nucleo-f767zi/scripts/kernel-space.ld Normal file
View file

@ -0,0 +1,97 @@
/****************************************************************************
* boards/arm/stm32f7/nucleo-f767zi/scripts/kernel-space.ld
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* NOTE: This depends on the memory.ld script having been included prior to
* this script.
*/
OUTPUT_ARCH(arm)
ENTRY(_stext)
SECTIONS
{
.text : {
_stext = ABSOLUTE(.);
*(.vectors)
*(.text .text.*)
*(.fixup)
*(.gnu.warning)
*(.rodata .rodata.*)
*(.gnu.linkonce.t.*)
*(.glue_7)
*(.glue_7t)
*(.got)
*(.gcc_except_table)
*(.gnu.linkonce.r.*)
_etext = ABSOLUTE(.);
} > kflash
.init_section : {
_sinit = ABSOLUTE(.);
KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors))
_einit = ABSOLUTE(.);
} > kflash
.ARM.extab : {
*(.ARM.extab*)
} > kflash
__exidx_start = ABSOLUTE(.);
.ARM.exidx : {
*(.ARM.exidx*)
} > kflash
__exidx_end = ABSOLUTE(.);
_eronly = ABSOLUTE(.);
.data : {
_sdata = ABSOLUTE(.);
*(.data .data.*)
*(.gnu.linkonce.d.*)
CONSTRUCTORS
. = ALIGN(4);
_edata = ABSOLUTE(.);
} > ksram AT > kflash
.bss : {
_sbss = ABSOLUTE(.);
*(.bss .bss.*)
*(.gnu.linkonce.b.*)
*(COMMON)
. = ALIGN(4);
_ebss = ABSOLUTE(.);
} > ksram
/* Stabs debugging sections */
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.stab.excl 0 : { *(.stab.excl) }
.stab.exclstr 0 : { *(.stab.exclstr) }
.stab.index 0 : { *(.stab.index) }
.stab.indexstr 0 : { *(.stab.indexstr) }
.comment 0 : { *(.comment) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_info 0 : { *(.debug_info) }
.debug_line 0 : { *(.debug_line) }
.debug_pubnames 0 : { *(.debug_pubnames) }
.debug_aranges 0 : { *(.debug_aranges) }
}

99
boards/arm/stm32f7/nucleo-f767zi/scripts/user-space.ld Normal file
View file

@ -0,0 +1,99 @@
/****************************************************************************
* boards/arm/stm32f7/nucleo-f767zi/scripts/user-space.ld
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* NOTE: This depends on the memory.ld script having been included prior to
* this script.
*/
OUTPUT_ARCH(arm)
SECTIONS
{
.userspace : {
*(.userspace)
} > uflash
.text : {
_stext = ABSOLUTE(.);
*(.text .text.*)
*(.fixup)
*(.gnu.warning)
*(.rodata .rodata.*)
*(.gnu.linkonce.t.*)
*(.glue_7)
*(.glue_7t)
*(.got)
*(.gcc_except_table)
*(.gnu.linkonce.r.*)
_etext = ABSOLUTE(.);
} > uflash
.init_section : {
_sinit = ABSOLUTE(.);
KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors))
_einit = ABSOLUTE(.);
} > uflash
.ARM.extab : {
*(.ARM.extab*)
} > uflash
__exidx_start = ABSOLUTE(.);
.ARM.exidx : {
*(.ARM.exidx*)
} > uflash
__exidx_end = ABSOLUTE(.);
_eronly = ABSOLUTE(.);
.data : {
_sdata = ABSOLUTE(.);
*(.data .data.*)
*(.gnu.linkonce.d.*)
CONSTRUCTORS
. = ALIGN(4);
_edata = ABSOLUTE(.);
} > usram AT > uflash
.bss : {
_sbss = ABSOLUTE(.);
*(.bss .bss.*)
*(.gnu.linkonce.b.*)
*(COMMON)
. = ALIGN(4);
_ebss = ABSOLUTE(.);
} > usram
/* Stabs debugging sections */
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.stab.excl 0 : { *(.stab.excl) }
.stab.exclstr 0 : { *(.stab.exclstr) }
.stab.index 0 : { *(.stab.index) }
.stab.indexstr 0 : { *(.stab.indexstr) }
.comment 0 : { *(.comment) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_info 0 : { *(.debug_info) }
.debug_line 0 : { *(.debug_line) }
.debug_pubnames 0 : { *(.debug_pubnames) }
.debug_aranges 0 : { *(.debug_aranges) }
}

93
boards/arm/stm32f7/nucleo-f767zi/src/CMakeLists.txt Normal file
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@ -0,0 +1,93 @@
# ##############################################################################
# boards/arm/stm32f7/nucleo-f767zi/src/CMakeLists.txt
#
# Licensed to the Apache Software Foundation (ASF) under one or more contributor
# license agreements. See the NOTICE file distributed with this work for
# additional information regarding copyright ownership. The ASF licenses this
# file to you under the Apache License, Version 2.0 (the "License"); you may not
# use this file except in compliance with the License. You may obtain a copy of
# the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
# License for the specific language governing permissions and limitations under
# the License.
#
# ##############################################################################
set(SRCS stm32_boot.c stm32_bringup.c)
if(CONFIG_ARCH_LEDS)
list(APPEND SRCS stm32_autoleds.c)
else()
list(APPEND SRCS stm32_userleds.c)
endif()
if(CONFIG_ARCH_BUTTONS)
list(APPEND SRCS stm32_buttons.c)
endif()
if(CONFIG_BOARDCTL)
list(APPEND SRCS stm32_appinitialize.c)
endif()
if(CONFIG_DEV_GPIO)
list(APPEND SRCS stm32_gpio.c)
endif()
if(CONFIG_SPI)
list(APPEND SRCS stm32_spi.c)
endif()
if(CONFIG_ADC)
list(APPEND SRCS stm32_adc.c)
endif()
if(CONFIG_PWM)
list(APPEND SRCS stm32_pwm.c)
endif()
if(CONFIG_MMCSD)
list(APPEND SRCS stm32_sdio.c)
endif()
if(CONFIG_STM32F7_OTGFS)
list(APPEND SRCS stm32_usb.c)
endif()
if(CONFIG_STM32F7_BBSRAM)
list(APPEND SRCS stm32_bbsram.c)
endif()
if(CONFIG_BOARDCTL_RESET)
list(APPEND SRCS stm32_reset.c)
endif()
if(CONFIG_STM32_ROMFS)
list(APPEND SRCS stm32_romfs_initialize.c)
endif()
if(CONFIG_SENSORS_QENCODER)
list(APPEND SRCS stm32_qencoder.c)
endif()
if(CONFIG_STM32F7_CAN)
if(CONFIG_STM32F7_CAN_CHARDRIVER)
list(APPEND SRCS stm32_can.c)
endif()
if(CONFIG_STM32F7_CAN_SOCKET)
list(APPEND SRCS stm32_cansock.c)
endif()
endif()
if(CONFIG_USBDEV_COMPOSITE)
list(APPEND SRCS stm32_composite.c)
endif()
target_sources(board PRIVATE ${SRCS})
set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/flash.ld")
endif()

94
boards/arm/stm32f7/nucleo-f767zi/src/Make.defs Normal file
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@ -0,0 +1,94 @@
############################################################################
# boards/arm/stm32f7/nucleo-f767zi/src/Make.defs
#
# Licensed to the Apache Software Foundation (ASF) under one or more
# contributor license agreements. See the NOTICE file distributed with
# this work for additional information regarding copyright ownership. The
# ASF licenses this file to you under the Apache License, Version 2.0 (the
# "License"); you may not use this file except in compliance with the
# License. You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
# License for the specific language governing permissions and limitations
# under the License.
#
############################################################################
include $(TOPDIR)/Make.defs
CSRCS = stm32_boot.c stm32_bringup.c
ifeq ($(CONFIG_ARCH_LEDS),y)
CSRCS += stm32_autoleds.c
else
CSRCS += stm32_userleds.c
endif
ifeq ($(CONFIG_ARCH_BUTTONS),y)
CSRCS += stm32_buttons.c
endif
ifeq ($(CONFIG_BOARDCTL),y)
CSRCS += stm32_appinitialize.c
endif
ifeq ($(CONFIG_DEV_GPIO),y)
CSRCS += stm32_gpio.c
endif
ifeq ($(CONFIG_SPI),y)
CSRCS += stm32_spi.c
endif
ifeq ($(CONFIG_ADC),y)
CSRCS += stm32_adc.c
endif
ifeq ($(CONFIG_PWM),y)
CSRCS += stm32_pwm.c
endif
ifeq ($(CONFIG_MMCSD),y)
CSRCS += stm32_sdio.c
endif
ifeq ($(CONFIG_STM32F7_OTGFS),y)
CSRCS += stm32_usb.c
endif
ifeq ($(CONFIG_STM32F7_BBSRAM),y)
CSRCS += stm32_bbsram.c
endif
ifeq ($(CONFIG_BOARDCTL_RESET),y)
CSRCS += stm32_reset.c
endif
ifeq ($(CONFIG_STM32_ROMFS),y)
CSRCS += stm32_romfs_initialize.c
endif
ifeq ($(CONFIG_SENSORS_QENCODER),y)
CSRCS += stm32_qencoder.c
endif
ifeq ($(CONFIG_STM32F7_CAN),y)
ifeq ($(CONFIG_STM32F7_CAN_CHARDRIVER),y)
CSRCS += stm32_can.c
endif
ifeq ($(CONFIG_STM32F7_CAN_SOCKET),y)
CSRCS += stm32_cansock.c
endif
endif
ifeq ($(CONFIG_USBDEV_COMPOSITE),y)
CSRCS += stm32_composite.c
endif
DEPPATH += --dep-path board
VPATH += :board
CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board

19
boards/arm/stm32f7/nucleo-144/src/nucleo-144.h → boards/arm/stm32f7/nucleo-f767zi/src/nucleo-f767zi.h
View file

@ -1,5 +1,5 @@
/****************************************************************************
* boards/arm/stm32f7/nucleo-144/src/nucleo-144.h
* boards/arm/stm32f7/nucleo-f767zi/src/nucleo-f767zi.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
@ -18,8 +18,8 @@
*
****************************************************************************/
#ifndef __BOARDS_ARM_STM32F7_NUCLEO_144_SRC_NUCLEO_144_H
#define __BOARDS_ARM_STM32F7_NUCLEO_144_SRC_NUCLEO_144_H
#ifndef __BOARDS_ARM_STM32F7_NUCLEO_767ZI_SRC_NUCLEO_767ZI_H
#define __BOARDS_ARM_STM32F7_NUCLEO_767ZI_SRC_NUCLEO_767ZI_H
/****************************************************************************
* Included Files
@ -45,11 +45,11 @@
# endif
#endif
/* Nucleo-144 GPIO Pin Definitions ******************************************/
/* nucleo-f767zi GPIO Pin Definitions ***************************************/
/* LED
*
* The Nucleo-144 board has numerous LEDs but only three, LD1 a Green LED,
* The nucleo-f767zi board has numerous LEDs but only three, LD1 a Green LED,
* LD2 a Blue LED and LD3 a Red LED, that can be controlled by software.
* The following definitions assume the default Solder Bridges are installed.
*/
@ -220,7 +220,8 @@ int stm32_bringup(void);
* Name: stm32_spidev_initialize
*
* Description:
* Called to configure SPI chip select GPIO pins for the Nucleo-144 board.
* Called to configure SPI chip select GPIO pins for the nucleo-f767zi
* board.
*
****************************************************************************/
@ -237,7 +238,7 @@ void stm32_spidev_initialize(void);
*
****************************************************************************/
#if defined(CONFIG_NUCLEO_SPI_TEST)
#if defined(CONFIG_NUCLEO_F722ZE_SPI_TEST)
int stm32_spidev_bus_test(void);
#endif
@ -276,7 +277,7 @@ int stm32_sdio_initialize(void);
*
* Description:
* Called from stm32_usbinitialize very early in inialization to setup
* USB-related GPIO pins for the nucleo-144 board.
* USB-related GPIO pins for the nucleo-f767zi board.
*
****************************************************************************/
@ -349,4 +350,4 @@ int stm32_gpio_initialize(void);
#endif
#endif /* __ASSEMBLY__ */
#endif /* __BOARDS_ARM_STM32F7_NUCLEO_144_SRC_NUCLEO_144_H */
#endif /* __BOARDS_ARM_STM32F7_NUCLEO_767ZI_SRC_NUCLEO_767ZI_H */

169
boards/arm/stm32f7/nucleo-f767zi/src/stm32_adc.c Normal file
View file

@ -0,0 +1,169 @@
/****************************************************************************
* boards/arm/stm32f7/nucleo-f767zi/src/stm32_adc.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <errno.h>
#include <debug.h>
#include <nuttx/board.h>
#include <nuttx/analog/adc.h>
#include <arch/board/board.h>
#include "chip.h"
#include "stm32_gpio.h"
#include "stm32_adc.h"
#include "nucleo-f767zi.h"
#ifdef CONFIG_ADC
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Configuration ************************************************************/
/* Up to 3 ADC interfaces are supported */
#if STM32F7_NADC < 3
# undef CONFIG_STM32F7_ADC3
#endif
#if STM32F7_NADC < 2
# undef CONFIG_STM32F7_ADC2
#endif
#if STM32F7_NADC < 1
# undef CONFIG_STM32F7_ADC1
#endif
#if defined(CONFIG_STM32F7_ADC1) || defined(CONFIG_STM32F7_ADC2) || defined(CONFIG_STM32F7_ADC3)
#ifndef CONFIG_STM32F7_ADC1
# warning "Channel information only available for ADC1"
#endif
/* The number of ADC channels in the conversion list */
/* #define ADC1_NCHANNELS 14 */
#define ADC1_NCHANNELS 4
/****************************************************************************
* Private Data
****************************************************************************/
/* Identifying number of each ADC channel: Variable Resistor.
*
* {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 15};
*/
#ifdef CONFIG_STM32F7_ADC1
static const uint8_t g_chanlist[ADC1_NCHANNELS] =
{
3, 4, 10, 13
};
/* Configurations of pins used byte each ADC channels
*
* {GPIO_ADC1_IN1, GPIO_ADC1_IN2, GPIO_ADC1_IN3,
* GPIO_ADC1_IN4, GPIO_ADC1_IN5, GPIO_ADC1_IN6,
* GPIO_ADC1_IN7, GPIO_ADC1_IN8, GPIO_ADC1_IN9,
* GPIO_ADC1_IN10, GPIO_ADC1_IN11, GPIO_ADC1_IN12,
* GPIO_ADC1_IN13, GPIO_ADC1_IN15};
*/
static const uint32_t g_pinlist[ADC1_NCHANNELS] =
{
GPIO_ADC1_IN3, GPIO_ADC1_IN4, GPIO_ADC1_IN10, GPIO_ADC1_IN13
};
#endif
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: stm32_adc_setup
*
* Description:
* Initialize ADC and register the ADC driver.
*
****************************************************************************/
int stm32_adc_setup(void)
{
#ifdef CONFIG_STM32F7_ADC1
static bool initialized = false;
struct adc_dev_s *adc;
int ret;
int i;
/* Check if we have already initialized */
if (!initialized)
{
/* Configure the pins as analog inputs for the selected channels */
for (i = 0; i < ADC1_NCHANNELS; i++)
{
if (g_pinlist[i] != 0)
{
stm32_configgpio(g_pinlist[i]);
}
}
/* Call stm32_adcinitialize() to get an instance of the ADC interface */
adc = stm32_adc_initialize(1, g_chanlist, ADC1_NCHANNELS);
if (adc == NULL)
{
aerr("ERROR: Failed to get ADC interface\n");
return -ENODEV;
}
/* Register the ADC driver at "/dev/adc0" */
ret = adc_register("/dev/adc0", adc);
if (ret < 0)
{
aerr("ERROR: adc_register failed: %d\n", ret);
return ret;
}
/* Now we are initialized */
initialized = true;
}
return OK;
#else
return -ENOSYS;
#endif
}
#endif /* CONFIG_STM32F7_ADC1 || CONFIG_STM32F7_ADC2 || CONFIG_STM32F7_ADC3 */
#endif /* CONFIG_ADC */

73
boards/arm/stm32f7/nucleo-f767zi/src/stm32_appinitialize.c Normal file
View file

@ -0,0 +1,73 @@
/****************************************************************************
* boards/arm/stm32f7/nucleo-f767zi/src/stm32_appinitialize.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <sys/types.h>
#include "nucleo-f767zi.h"
#ifdef CONFIG_BOARDCTL
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: board_app_initialize
*
* Description:
* Perform application specific initialization. This function is never
* called directly from application code, but only indirectly via the
* (non-standard) boardctl() interface using the command BOARDIOC_INIT.
*
* Input Parameters:
* arg - The boardctl() argument is passed to the board_app_initialize()
* implementation without modification. The argument has no
* meaning to NuttX; the meaning of the argument is a contract
* between the board-specific initialization logic and the
* matching application logic. The value could be such things as a
* mode enumeration value, a set of DIP switch switch settings, a
* pointer to configuration data read from a file or serial FLASH,
* or whatever you would like to do with it. Every implementation
* should accept zero/NULL as a default configuration.
*
* Returned Value:
* Zero (OK) is returned on success; a negated errno value is returned on
* any failure to indicate the nature of the failure.
*
****************************************************************************/
int board_app_initialize(uintptr_t arg)
{
#ifndef CONFIG_BOARD_LATE_INITIALIZE
/* Perform board-specific initialization */
return stm32_bringup();
#else
return OK;
#endif
}
#endif

168
boards/arm/stm32f7/nucleo-f767zi/src/stm32_autoleds.c Normal file
View file

@ -0,0 +1,168 @@
/****************************************************************************
* boards/arm/stm32f7/nucleo-f767zi/src/stm32_autoleds.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdbool.h>
#include <debug.h>
#include <sys/param.h>
#include <nuttx/board.h>
#include <arch/board/board.h>
#include "stm32_gpio.h"
#include "nucleo-f767zi.h"
#ifdef CONFIG_ARCH_LEDS
/****************************************************************************
* Private Data
****************************************************************************/
/* Indexed by BOARD_LED_<color> */
static const uint32_t g_ledmap[BOARD_NLEDS] =
{
GPIO_LED_GREEN,
GPIO_LED_BLUE,
GPIO_LED_RED,
};
static bool g_initialized;
/****************************************************************************
* Private Functions
****************************************************************************/
static void phy_set_led(int led, bool state)
{
/* Active High */
stm32_gpiowrite(g_ledmap[led], state);
}
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: board_autoled_initialize
****************************************************************************/
void board_autoled_initialize(void)
{
int i;
/* Configure the LD1 GPIO for output. Initial state is OFF */
for (i = 0; i < nitems(g_ledmap); i++)
{
stm32_configgpio(g_ledmap[i]);
}
}
/****************************************************************************
* Name: board_autoled_on
****************************************************************************/
void board_autoled_on(int led)
{
switch (led)
{
default:
break;
case LED_HEAPALLOCATE:
phy_set_led(BOARD_LED_BLUE, true);
break;
case LED_IRQSENABLED:
phy_set_led(BOARD_LED_BLUE, false);
phy_set_led(BOARD_LED_GREEN, true);
break;
case LED_STACKCREATED:
phy_set_led(BOARD_LED_GREEN, true);
phy_set_led(BOARD_LED_BLUE, true);
g_initialized = true;
break;
case LED_INIRQ:
phy_set_led(BOARD_LED_BLUE, true);
break;
case LED_SIGNAL:
phy_set_led(BOARD_LED_GREEN, true);
break;
case LED_ASSERTION:
phy_set_led(BOARD_LED_RED, true);
phy_set_led(BOARD_LED_BLUE, true);
break;
case LED_PANIC:
phy_set_led(BOARD_LED_RED, true);
break;
case LED_IDLE : /* IDLE */
phy_set_led(BOARD_LED_RED, true);
break;
}
}
/****************************************************************************
* Name: board_autoled_off
****************************************************************************/
void board_autoled_off(int led)
{
switch (led)
{
default:
break;
case LED_SIGNAL:
phy_set_led(BOARD_LED_GREEN, false);
break;
case LED_INIRQ:
phy_set_led(BOARD_LED_BLUE, false);
break;
case LED_ASSERTION:
phy_set_led(BOARD_LED_RED, false);
phy_set_led(BOARD_LED_BLUE, false);
break;
case LED_PANIC:
phy_set_led(BOARD_LED_RED, false);
break;
case LED_IDLE : /* IDLE */
phy_set_led(BOARD_LED_RED, false);
break;
}
}
#endif /* CONFIG_ARCH_LEDS */

517
boards/arm/stm32f7/nucleo-f767zi/src/stm32_bbsram.c Normal file
View file

@ -0,0 +1,517 @@
/****************************************************************************
* boards/arm/stm32f7/nucleo-f767zi/src/stm32_bbsram.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <sys/ioctl.h>
#include <stdint.h>
#include <stddef.h>
#include <stdlib.h>
#include <fcntl.h>
#include <string.h>
#include <assert.h>
#include <errno.h>
#include <debug.h>
#include <syslog.h>
#include <sys/param.h>
#include <nuttx/fs/fs.h>
#include "arm_internal.h"
#include "stm32_bbsram.h"
#include "nucleo-f767zi.h"
#ifdef CONFIG_STM32F7_BBSRAM
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Configuration ************************************************************/
#define FREEZE_STR(s) #s
#define STRINGIFY(s) FREEZE_STR(s)
#define HARDFAULT_FILENO 3
#define HARDFAULT_PATH BBSRAM_PATH""STRINGIFY(HARDFAULT_FILENO)
#define HARDFAULT_REBOOT_ FILENO 0
#define HARDFAULT_REBOOT_PATH BBSRAM_PATH""STRINGIFY(HARDFAULT_REBOOT_FILENO)
#define BBSRAM_SIZE_FN0 (sizeof(int))
#define BBSRAM_SIZE_FN1 384
#define BBSRAM_SIZE_FN2 384
#define BBSRAM_SIZE_FN3 - 1
/* The following guides in the amount of the user and interrupt stack
* data we can save. The amount of storage left will dictate the actual
* number of entries of the user stack data saved. If it is too big
* It will be truncated by the call to stm32_bbsram_savepanic
*/
#define BBSRAM_HEADER_SIZE 20 /* This is an assumption */
#define BBSRAM_USED ((4*BBSRAM_HEADER_SIZE)+ \
(BBSRAM_SIZE_FN0+BBSRAM_SIZE_FN1+ \
BBSRAM_SIZE_FN2))
#define BBSRAM_REAMINING (STM32F7_BBSRAM_SIZE-BBSRAM_USED)
#if CONFIG_ARCH_INTERRUPTSTACK <= 3
# define BBSRAM_NUMBER_STACKS 1
#else
# define BBSRAM_NUMBER_STACKS 2
#endif
#define BBSRAM_FIXED_ELEMENTS_SIZE (sizeof(info_t))
#define BBSRAM_LEFTOVER (BBSRAM_REAMINING-\
BBSRAM_FIXED_ELEMENTS_SIZE)
#define CONFIG_ISTACK_SIZE (BBSRAM_LEFTOVER/BBSRAM_NUMBER_STACKS/ \
sizeof(stack_word_t))
#define CONFIG_USTACK_SIZE (BBSRAM_LEFTOVER/BBSRAM_NUMBER_STACKS/ \
sizeof(stack_word_t))
/* The path to the Battery Backed up SRAM */
#define BBSRAM_PATH "/fs/bbr"
/* The sizes of the files to create (-1) use rest of BBSRAM memory */
#define BSRAM_FILE_SIZES \
{ \
BBSRAM_SIZE_FN0, \
BBSRAM_SIZE_FN1, \
BBSRAM_SIZE_FN2, \
BBSRAM_SIZE_FN3, \
0 \
}
/* For Assert keep this much of the file name */
#define MAX_FILE_PATH_LENGTH 40
#define HEADER_TIME_FMT "%Y-%m-%d-%H:%M:%S"
#define HEADER_TIME_FMT_NUM (2+ 0+ 0+ 0+ 0+ 0)
#define HEADER_TIME_FMT_LEN (((nitems(HEADER_TIME_FMT)-1) + \
HEADER_TIME_FMT_NUM))
/****************************************************************************
* Private Data
****************************************************************************/
/* Used for stack frame storage */
typedef uint32_t stack_word_t;
/* Stack related data */
typedef struct
{
uint32_t sp;
uint32_t top;
uint32_t size;
} _stack_t;
typedef struct
{
_stack_t user;
#if CONFIG_ARCH_INTERRUPTSTACK > 3
_stack_t interrupt;
#endif
} stacks_t;
/* Not Used for reference only */
typedef struct
{
uint32_t r0;
uint32_t r1;
uint32_t r2;
uint32_t r3;
uint32_t r4;
uint32_t r5;
uint32_t r6;
uint32_t r7;
uint32_t r8;
uint32_t r9;
uint32_t r10;
uint32_t r11;
uint32_t r12;
uint32_t sp;
uint32_t lr;
uint32_t pc;
uint32_t xpsr;
uint32_t d0;
uint32_t d1;
uint32_t d2;
uint32_t d3;
uint32_t d4;
uint32_t d5;
uint32_t d6;
uint32_t d7;
uint32_t d8;
uint32_t d9;
uint32_t d10;
uint32_t d11;
uint32_t d12;
uint32_t d13;
uint32_t d14;
uint32_t d15;
uint32_t fpscr;
uint32_t sp_main;
uint32_t sp_process;
uint32_t apsr;
uint32_t ipsr;
uint32_t epsr;
uint32_t primask;
uint32_t basepri;
uint32_t faultmask;
uint32_t control;
uint32_t s0;
uint32_t s1;
uint32_t s2;
uint32_t s3;
uint32_t s4;
uint32_t s5;
uint32_t s6;
uint32_t s7;
uint32_t s8;
uint32_t s9;
uint32_t s10;
uint32_t s11;
uint32_t s12;
uint32_t s13;
uint32_t s14;
uint32_t s15;
uint32_t s16;
uint32_t s17;
uint32_t s18;
uint32_t s19;
uint32_t s20;
uint32_t s21;
uint32_t s22;
uint32_t s23;
uint32_t s24;
uint32_t s25;
uint32_t s26;
uint32_t s27;
uint32_t s28;
uint32_t s29;
uint32_t s30;
uint32_t s31;
} proc_regs_t;
/* Flags to identify what is in the dump */
typedef enum
{
REGS_PRESENT = 0x01,
USERSTACK_PRESENT = 0x02,
INTSTACK_PRESENT = 0x04,
INVALID_USERSTACK_PTR = 0x20,
INVALID_INTSTACK_PTR = 0x40,
} fault_flags_t;
typedef struct
{
fault_flags_t flags; /* What is in the dump */
uintptr_t current_regs; /* Used to validate the dump */
int lineno; /* __LINE__ to up_assert */
int pid; /* Process ID */
uint32_t regs[XCPTCONTEXT_REGS]; /* Interrupt register save area */
stack_t stacks; /* Stack info */
char name[CONFIG_TASK_NAME_SIZE + 1]; /* Task name (with NULL
* terminator) */
char filename[MAX_FILE_PATH_LENGTH]; /* the Last of chars in
* __FILE__ to up_assert */
} info_t;
typedef struct
{
info_t info; /* The info */
#if CONFIG_ARCH_INTERRUPTSTACK > 3
/* The amount of stack data is compile time
* sized backed on what is left after the
* other BBSRAM files are defined
* The order is such that only the
* ustack should be truncated
*/
stack_word_t istack[CONFIG_USTACK_SIZE];
#endif
stack_word_t ustack[CONFIG_ISTACK_SIZE];
} fullcontext_t;
/****************************************************************************
* Private Data
****************************************************************************/
static uint8_t g_sdata[STM32F7_BBSRAM_SIZE];
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: hardfault_get_desc
****************************************************************************/
static int hardfault_get_desc(struct bbsramd_s *desc)
{
struct file filestruct;
int ret;
ret = file_open(&filestruct, HARDFAULT_PATH, O_RDONLY);
if (ret < 0)
{
syslog(LOG_INFO, "stm32 bbsram: Failed to open Fault Log file [%s] "
"(%d)\n", HARDFAULT_PATH, ret);
}
else
{
ret = file_ioctl(&filestruct, STM32F7_BBSRAM_GETDESC_IOCTL,
(unsigned long)((uintptr_t)desc));
file_close(&filestruct);
if (ret < 0)
{
syslog(LOG_INFO, "stm32 bbsram: Failed to get Fault Log "
"descriptor (%d)\n", ret);
}
}
return ret;
}
/****************************************************************************
* Name: copy_reverse
****************************************************************************/
#if defined(CONFIG_STM32F7_SAVE_CRASHDUMP)
static void copy_reverse(stack_word_t *dest, stack_word_t *src, int size)
{
while (size--)
{
*dest++ = *src--;
}
}
#endif /* CONFIG_STM32F7_SAVE_CRASHDUMP */
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: stm32_bbsram_int
****************************************************************************/
int stm32_bbsram_int(void)
{
int filesizes[CONFIG_STM32F7_BBSRAM_FILES + 1] = BSRAM_FILE_SIZES;
char buf[HEADER_TIME_FMT_LEN + 1];
struct bbsramd_s desc;
int rv;
int state;
struct tm tt;
time_t time_sec;
/* Using Battery Backed Up SRAM */
stm32_bbsraminitialize(BBSRAM_PATH, filesizes);
#if defined(CONFIG_STM32F7_SAVE_CRASHDUMP)
/* Panic Logging in Battery Backed Up Files */
/* Do we have an hard fault in BBSRAM? */
rv = hardfault_get_desc(&desc);
if (rv >= OK)
{
syslog(LOG_EMERG, "There is a hard fault logged.\n");
state = (desc.lastwrite.tv_sec || desc.lastwrite.tv_nsec) ? OK : 1;
syslog(LOG_INFO, "Fault Log info File No %d Length %d flags:0x%02x "
"state:%d\n", (unsigned int)desc.fileno, (unsigned int)desc.len,
(unsigned int)desc.flags, state);
if (state == OK)
{
time_sec = desc.lastwrite.tv_sec + (desc.lastwrite.tv_nsec / 1e9);
gmtime_r(&time_sec, &tt);
strftime(buf, HEADER_TIME_FMT_LEN , HEADER_TIME_FMT , &tt);
syslog(LOG_INFO, "Fault Logged on %s - Valid\n", buf);
}
rv = nx_unlink(HARDFAULT_PATH);
if (rv < 0)
{
syslog(LOG_INFO, "stm32 bbsram: Failed to unlink Fault Log file"
" [%s] (%d)\n", HARDFAULT_PATH, rv);
}
}
#endif /* CONFIG_STM32F7_SAVE_CRASHDUMP */
return rv;
}
/****************************************************************************
* Name: board_crashdump
****************************************************************************/
#if defined(CONFIG_STM32F7_SAVE_CRASHDUMP)
void board_crashdump(uintptr_t sp, struct tcb_s *tcb,
const char *filename, int lineno,
const char *msg, void *regs)
{
fullcontext_t *pdump = (fullcontext_t *)&g_sdata;
int rv;
enter_critical_section();
/* Zero out everything */
memset(pdump, 0, sizeof(fullcontext_t));
/* Save Info */
pdump->info.lineno = lineno;
if (filename)
{
int offset = 0;
unsigned int len = strlen((char *)filename) + 1;
if (len > sizeof(pdump->info.filename))
{
offset = len - sizeof(pdump->info.filename);
}
strlcpy(pdump->info.filename, (char *)&filename[offset],
sizeof(pdump->info.filename));
}
/* Save the value of the pointer for current_regs as debugging info.
* It should be NULL in case of an ASSERT and will aid in cross
* checking the validity of system memory at the time of the
* fault.
*/
pdump->info.current_regs = (uintptr_t)up_current_regs();
/* Save Context */
strlcpy(pdump->info.name, get_task_name(tcb), sizeof(pdump->info.name));
pdump->info.pid = tcb->pid;
if (up_interrupt_context())
{
pdump->info.stacks.interrupt.sp = sp;
pdump->info.flags |= (REGS_PRESENT | USERSTACK_PRESENT |
INTSTACK_PRESENT);
memcpy(pdump->info.regs, up_current_regs(),
sizeof(pdump->info.regs));
pdump->info.stacks.user.sp = pdump->info.regs[REG_R13];
}
else
{
/* users context */
pdump->info.flags |= USERSTACK_PRESENT;
pdump->info.stacks.user.sp = sp;
}
pdump->info.stacks.user.top = (uint32_t)tcb->stack_base_ptr +
tcb->adj_stack_size;
pdump->info.stacks.user.size = (uint32_t)tcb->adj_stack_size;
#if CONFIG_ARCH_INTERRUPTSTACK > 3
/* Get the limits on the interrupt stack memory */
pdump->info.stacks.interrupt.top = (uint32_t)g_intstacktop;
pdump->info.stacks.interrupt.size = (CONFIG_ARCH_INTERRUPTSTACK & ~3);
/* If In interrupt Context save the interrupt stack data centered
* about the interrupt stack pointer
*/
if ((pdump->info.flags & INTSTACK_PRESENT) != 0)
{
stack_word_t *ps = (stack_word_t *) pdump->info.stacks.interrupt.sp;
copy_reverse(pdump->istack, &ps[nitems(pdump->istack) / 2],
nitems(pdump->istack));
}
/* Is it Invalid? */
if (!(pdump->info.stacks.interrupt.sp <=
pdump->info.stacks.interrupt.top &&
pdump->info.stacks.interrupt.sp > pdump->info.stacks.interrupt.top -
pdump->info.stacks.interrupt.size))
{
pdump->info.flags |= INVALID_INTSTACK_PTR;
}
#endif
/* If In interrupt context or User save the user stack data centered
* about the user stack pointer
*/
if ((pdump->info.flags & USERSTACK_PRESENT) != 0)
{
stack_word_t *ps = (stack_word_t *) pdump->info.stacks.user.sp;
copy_reverse(pdump->ustack, &ps[nitems(pdump->ustack) / 2],
nitems(pdump->ustack));
}
/* Is it Invalid? */
if (!(pdump->info.stacks.user.sp <= pdump->info.stacks.user.top &&
pdump->info.stacks.user.sp > pdump->info.stacks.user.top -
pdump->info.stacks.user.size))
{
pdump->info.flags |= INVALID_USERSTACK_PTR;
}
rv = stm32_bbsram_savepanic(HARDFAULT_FILENO, (uint8_t *)pdump,
sizeof(fullcontext_t));
/* Test if memory got wiped because of using _sdata */
if (rv == -ENXIO)
{
char *dead = "Memory wiped - dump not saved!";
while (*dead)
{
arm_lowputc(*dead++);
}
}
else if (rv == -ENOSPC)
{
/* hard fault again */
arm_lowputc('!');
}
}
#endif /* CONFIG_STM32F7_SAVE_CRASHDUMP */
#endif /* CONFIG_STM32_BBSRAM */

90
boards/arm/stm32f7/nucleo-f767zi/src/stm32_boot.c Normal file
View file

@ -0,0 +1,90 @@
/****************************************************************************
* boards/arm/stm32f7/nucleo-f767zi/src/stm32_boot.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <debug.h>
#include <nuttx/board.h>
#include <arch/board/board.h>
#include "arm_internal.h"
#include "nucleo-f767zi.h"
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: stm32_boardinitialize
*
* Description:
* All STM32 architectures must provide the following entry point.
* This entry point is called early in the initialization -- after all
* memory has been configured and mapped but before any devices have been
* initialized.
*
****************************************************************************/
void stm32_boardinitialize(void)
{
#ifdef CONFIG_ARCH_LEDS
/* Configure on-board LEDs if LED support has been selected. */
board_autoled_initialize();
#endif
#if defined(CONFIG_STM32F7_OTGFS) || defined(CONFIG_STM32F7_HOST)
stm32_usbinitialize();
#endif
#if defined(CONFIG_SPI)
/* Configure SPI chip selects */
stm32_spidev_initialize();
#endif
}
/****************************************************************************
* Name: board_late_initialize
*
* Description:
* If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional
* initialization call will be performed in the boot-up sequence to a
* function called board_late_initialize(). board_late_initialize() will
* be called immediately after up_initialize() is called and just before
* the initial application is started. This additional initialization
* phase may be used, for example, to initialize board-specific device
* drivers.
*
****************************************************************************/
#ifdef CONFIG_BOARD_LATE_INITIALIZE
void board_late_initialize(void)
{
/* Perform board-specific initialization */
stm32_bringup();
}
#endif

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