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arch: z16: nxstyle fixes

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nxstyle fixes to pass CI

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
This commit is contained in:
Alin Jerpelea 2021-03-29 20:23:42 +02:00 • committed by David Sidrane
parent 7f19d910ef
commit 67bd7824e4
2 changed files with 37 additions and 28 deletions
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6
arch/z16/include/z16f/irq.h
View file

@ -37,7 +37,9 @@
* Pre-processor Definitions
****************************************************************************/
/* Interrupt Vectors (excluding reset and sysexec which are handled differently) */
/* Interrupt Vectors
* (excluding reset and sysexec which are handled differently)
*/
#define Z16F_IRQ_IRQ0 ( 0) /* First of 8 IRQs controlled by IRQ0 registers */
#define Z16F_IRQ_ADC ( 0) /* Vector: 0x2C IRQ0.0 ADC */
@ -228,7 +230,7 @@ extern "C"
intrinsic void EI(void);
intrinsic void DI(void);
intrinsic void RI(unsigned short);
intrinsic void SET_VECTOR(int,void (* func) (void));
intrinsic void SET_VECTOR(int, void (* func) (void));
intrinsic unsigned short TDI(void);
#ifndef __ZILOG__

59
arch/z16/src/z16f/z16f_clkinit.c
View file

@ -53,16 +53,17 @@ extern _Erom unsigned long SYS_CLK_FREQ;
* function allows the selection of internal 5.56 MHz, the 10 KHz Watch Dog
* timer or an external clock Source. ZNEO supports clock frequency division
* with the Clock Division Register. The clock division Register will divide
* by (a minimum of) 2 or more. An assumed clock value of 5.5 MHz internal or
* an external clock of 20 MHz was used as the crystal frequency to match the
* Demo Target. The User can enter a new frequency in the OTHER clock dialog
* Target Setting. The clock frequency is passed with the variable _DEFFREQ
* and the clock source is _DEFSRC.
* by (a minimum of) 2 or more. An assumed clock value of 5.5 MHz internal
* or an external clock of 20 MHz was used as the crystal frequency to match
* the Demo Target. The User can enter a new frequency in the OTHER clock
* dialog Target Setting. The clock frequency is passed with the variable
* _DEFFREQ and the clock source is _DEFSRC.
*
* NOTE: The UART output is designed to work with 5.56 MHz internal and 20 MHz
* NOTE:
* The UART output is designed to work with 5.56 MHz internal and 20 MHz
* External clock frequencies at the Default Baud rate of 57.6K Baud.
* Entering different clock frequencies may cause the UART to stop transmitting
* unless the user makes changes to the UART routines.
* Entering different clock frequencies may cause the UART to stop
* transmitting unless the user makes changes to the UART routines.
*
* Function Not Recommended for Release Code.
*
@ -79,11 +80,13 @@ static void z16f_sysclkinit(int clockid, uint32_t frequency)
{
switch (clockid)
{
/* 0: Internal precision oscillator functions as system clock at 5.6 MHz */
/* 0: Internal precision oscillator functions as system clock
* at 5.6 MHz
*/
case 0:
{
/* Enable 5.6 MHz clock RESET DEFAULT*/
/* Enable 5.6 MHz clock RESET DEFAULT */
putreg8(0xe7, Z16F_OSC_CTL); /* Unlock the crystal oscillator */
putreg8(0x18, Z16F_OSC_CTL);
@ -101,7 +104,9 @@ static void z16f_sysclkinit(int clockid, uint32_t frequency)
}
break;
/* 1: Crystal oscillator or external clock driver functions as system clock */
/* 1: Crystal oscillator or external clock driver functions as
* system clock
*/
case 1:
{
@ -161,16 +166,18 @@ static void z16f_sysclkinit(int clockid, uint32_t frequency)
}
/* Check SysClock Frequency.
* divide the clock if the user has selected the OTHER option for frequency.
* divide the clock if the user has selected the OTHER option for
* frequency.
*/
if (((clockid == 0) && (frequency < 3000000ul)) ||
((clockid == 1) && (frequency <= 10000000ul)))
{
if ( clockid == 0 )
if (clockid == 0)
{
temp_oscdiv = (5526000ul / (frequency + 1));
/* Example @ 32 KHz: 0xAC (172 decimal)*/
/* Example @ 32 KHz: 0xAC (172 decimal) */
}
else
{
@ -209,25 +216,25 @@ static void z16f_sysclkinit(int clockid, uint32_t frequency)
if ((getreg8(Z16F_OSC_CTL) & 0x03) != 1)
{
/* No divider for the oscillator */
/* No divider for the oscillator */
putreg8(0x00, Z16F_OSC_DIV);
putreg8(0x00, Z16F_OSC_DIV);
/* Enable external oscillator */
/* Enable external oscillator */
putreg8(0xe7, Z16F_OSC_CTL); /* Unlock the crystal oscillator */
putreg8(0x18, Z16F_OSC_CTL);
putreg8(0xe0, Z16F_OSC_CTL); /* INTEN+XTLEN+WDTEN */
putreg8(0xe7, Z16F_OSC_CTL); /* Unlock the crystal oscillator */
putreg8(0x18, Z16F_OSC_CTL);
putreg8(0xe0, Z16F_OSC_CTL); /* INTEN+XTLEN+WDTEN */
/* Wait for oscillator to stabilize */
/* Wait for oscillator to stabilize */
for (count = 0; count < 10000; count++);
for (count = 0; count < 10000; count++);
/* Select external oscillator (SCLKSEL=1) */
/* Select external oscillator (SCLKSEL=1) */
putreg8(0xe7, Z16F_OSC_CTL); /* Unlock the crystal oscillator */
putreg8(0x18, Z16F_OSC_CTL);
putreg8(0xe0 | 1, Z16F_OSC_CTL); /* Use the external osc/clock as system clock */
putreg8(0xe7, Z16F_OSC_CTL); /* Unlock the crystal oscillator */
putreg8(0x18, Z16F_OSC_CTL);
putreg8(0xe0 | 1, Z16F_OSC_CTL); /* Use the external osc/clock as system clock */
}
}
#endif /* CONFIG_DEBUG_FEATURES */