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stm32f76xx77xx_rcc: Fix PLLI2S factor divisors

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Value was set with PLLSAI factor divisors instead of
PLLI2S factor divisors.

Signed-off-by: Alan C Assis <acassis@gmail.com>
This commit is contained in:
Alan Carvalho de Assis 2024-04-08 17:42:48 -03:00 • committed by Xiang Xiao
parent a9bff735e7
commit 67dbdb18e3
1 changed files with 8 additions and 5 deletions
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13
arch/arm/src/stm32f7/stm32f76xx77xx_rcc.c
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@ -913,7 +913,10 @@ static void stm32_stdclockconfig(void)
{
}
#endif
#if defined(CONFIG_STM32F7_PLLI2S) || (STM32_RCC_DCKCFGR1_SAI1SRC == RCC_DCKCFGR1_SAI1SEL(1)) || (STM32_RCC_DCKCFGR1_SAI2SRC == RCC_DCKCFGR1_SAI2SEL(1))
#if defined(CONFIG_STM32F7_PLLI2S) || \
(STM32_RCC_DCKCFGR1_SAI1SRC == RCC_DCKCFGR1_SAI1SEL(1)) || \
(STM32_RCC_DCKCFGR1_SAI2SRC == RCC_DCKCFGR1_SAI2SEL(1))
/* Configure PLLI2S */
@ -922,10 +925,10 @@ static void stm32_stdclockconfig(void)
| RCC_PLLI2SCFGR_PLLI2SP_MASK
| RCC_PLLI2SCFGR_PLLI2SQ_MASK
| RCC_PLLI2SCFGR_PLLI2SR_MASK);
regval |= (STM32_RCC_PLLSAICFGR_PLLSAIN
| STM32_RCC_PLLSAICFGR_PLLSAIP
| STM32_RCC_PLLSAICFGR_PLLSAIQ
| STM32_RCC_PLLSAICFGR_PLLSAIR);
regval |= (STM32_RCC_PLLI2SCFGR_PLLI2SN
| STM32_RCC_PLLI2SCFGR_PLLI2SP
| STM32_RCC_PLLI2SCFGR_PLLI2SQ
| STM32_RCC_PLLI2SCFGR_PLLI2SR);
putreg32(regval, STM32_RCC_PLLI2SCFGR);
/* Enable PLLI2S */