From 68008aa9d73b8b734cb4e1541210ad72029f454b Mon Sep 17 00:00:00 2001
From: buxiasen <buxiasen@xiaomi.com>
Date: Wed, 30 Apr 2025 16:19:05 +0800
Subject: [PATCH] arch/arm/armv7-a: add mmu_l1_setpgtable

Decrease the direct access of cp15, use mmu interface replace

Signed-off-by: buxiasen <buxiasen@xiaomi.com>
---
 arch/arm/src/armv7-a/arm_mmu.c |  4 ++--
 arch/arm/src/armv7-a/mmu.h     | 43 ++++++++++++++++++++++++++++------
 2 files changed, 38 insertions(+), 9 deletions(-)

diff --git a/arch/arm/src/armv7-a/arm_mmu.c b/arch/arm/src/armv7-a/arm_mmu.c
index 20d95c70d1..61b042f589 100644
--- a/arch/arm/src/armv7-a/arm_mmu.c
+++ b/arch/arm/src/armv7-a/arm_mmu.c
@@ -54,7 +54,7 @@
 #ifndef CONFIG_ARCH_ROMPGTABLE
 void mmu_l1_setentry(uint32_t paddr, uint32_t vaddr, uint32_t mmuflags)
 {
-  uint32_t *l1table = mmu_l1_pgtable();
+  uint32_t *l1table = mmu_l1_getpgtable();
   uint32_t  index   = vaddr >> 20;
 
   /* Save the page table entry */
@@ -89,7 +89,7 @@ void mmu_l1_setentry(uint32_t paddr, uint32_t vaddr, uint32_t mmuflags)
 #if !defined(CONFIG_ARCH_ROMPGTABLE) && defined(CONFIG_ARCH_ADDRENV)
 void mmu_l1_restore(uintptr_t vaddr, uint32_t l1entry)
 {
-  uint32_t *l1table = mmu_l1_pgtable();
+  uint32_t *l1table = mmu_l1_getpgtable();
   uint32_t  index   = vaddr >> 20;
 
   /* Set the encoded page table entry */
diff --git a/arch/arm/src/armv7-a/mmu.h b/arch/arm/src/armv7-a/mmu.h
index 35b063a46b..a85a13700e 100644
--- a/arch/arm/src/armv7-a/mmu.h
+++ b/arch/arm/src/armv7-a/mmu.h
@@ -1296,7 +1296,7 @@ static inline void cp15_invalidate_tlb_bymva(uint32_t vaddr)
  *
  ****************************************************************************/
 
-static inline void cp15_wrdacr(unsigned int dacr)
+static inline void cp15_wrdacr(uint32_t dacr)
 {
   CP15_SET(DACR, dacr);
   UP_NOP();
@@ -1324,7 +1324,7 @@ static inline void cp15_wrdacr(unsigned int dacr)
  *
  ****************************************************************************/
 
-static inline void cp15_wrttb(unsigned int ttb)
+static inline void cp15_wrttb(uint32_t ttb)
 {
   CP15_SET(TTBR0, ttb);
   UP_NOP();
@@ -1339,7 +1339,7 @@ static inline void cp15_wrttb(unsigned int ttb)
 }
 
 /****************************************************************************
- * Name: mmu_l1_pgtable
+ * Name: mmu_l1_getpgtable
  *
  * Description:
  *   Return the value of the L1 page table base address.
@@ -1351,7 +1351,7 @@ static inline void cp15_wrttb(unsigned int ttb)
  ****************************************************************************/
 
 #ifndef CONFIG_ARCH_ROMPGTABLE
-static inline uint32_t *mmu_l1_pgtable(void)
+static inline uint32_t *mmu_l1_getpgtable(void)
 {
 #if defined(CONFIG_SMP) && defined(CONFIG_ARCH_ADDRENV)
   uint32_t ttbr0;
@@ -1366,6 +1366,30 @@ static inline uint32_t *mmu_l1_pgtable(void)
 }
 #endif
 
+/****************************************************************************
+ * Name: mmu_l1_setpgtable
+ *
+ * Description:
+ *   Update current L1 page table base address.
+ *   The TTBR0 register contains the phys address for each cpu.
+ *
+ * Input Parameters:
+ *   ttb - The new value of the TTBR0 register
+ *
+ ****************************************************************************/
+
+#ifndef CONFIG_ARCH_ROMPGTABLE
+#  ifdef CONFIG_ARCH_ADDRENV
+static inline void mmu_l1_setpgtable(uintptr_t *ttb)
+{
+  cp15_wrttb((uint32_t)ttb | TTBR0_RGN_WBWA | TTBR0_IRGN0);
+  cp15_invalidate_tlbs();
+}
+#  else
+#    define mmu_l1_setpgtable(ttb)
+#  endif
+#endif
+
 /****************************************************************************
  * Name: mmu_l1_getentry
  *
@@ -1379,15 +1403,20 @@ static inline uint32_t *mmu_l1_pgtable(void)
  ****************************************************************************/
 
 #ifndef CONFIG_ARCH_ROMPGTABLE
-static inline uint32_t mmu_l1_getentry(uint32_t vaddr)
+static inline
+uint32_t mmu_l1table_getentry(uint32_t *l1table, uint32_t vaddr)
 {
-  uint32_t *l1table = mmu_l1_pgtable();
-  uint32_t  index   = vaddr >> 20;
+  uint32_t index = vaddr >> 20;
 
   /* Return the address of the page table entry */
 
   return l1table[index];
 }
+
+static inline uint32_t mmu_l1_getentry(uint32_t vaddr)
+{
+  return mmu_l1table_getentry(mmu_l1_getpgtable(), vaddr);
+}
 #endif
 
 /****************************************************************************