Initial STM32H5 USB Commit
Progress in USB driver Nothing is working yet. But just getting this in here so it is saved. Minor changes with USB power enabled Serial over USB is working now. Removed stm32_usbdev.c, added stm32_usbfs.c. Still needs review before pull-request. Rewrote VDDUSB valid check to use register definitions. Wait for USB33RDY before moving on. Also style updates. Renamed stm32_usbdev files to stm32_usbfs. Renamed STM32H5 configuration options from STM32H5_USB to STM32H5_USBFS. Properly named REGDEBUG defines. Added STM32H5_USB_REGDEBUG to Kconfig and updated stm32_usbfs.c to use it. TRACE functionality still needs work. Updated REGDEBUG for 32-bit register accesses. More style updates. Added usbnsh defconfig to nucleo-h563zi Update to allow 16 buffers (max for 8 endpoints). Renamed lpinterrupt and lptransfer. Changed board.h to use SYNCSRC_USB only if USB is enabled. Buffer size is still set to max packet size of 64 bytes, because we are using a full-speed peripheral. It is unclear to me whether having a buffer larger than the max packet size has any benefit. Double buffering is a way to increase throughput, though that still needs to be implemented. Adapted USBFS Buffer table for 32-bit accesses. Style updates Build stm32_hsi48.c based on CONFIG_STM32H5_HAVE_HSI48. Change LPMODE CNTR bit to SUSPRDY.
This commit is contained in:
Kyle Wilson
Xiang Xiao
parent
044879e7a3
commit
689aa55e01
11 changed files with 4387 additions and 3 deletions
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@ -53,6 +53,8 @@ config STM32H5_STM32H56XXX
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select STM32H5_HAVE_SPI4
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select STM32H5_HAVE_SPI5
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select STM32H5_HAVE_SPI6
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select STM32H5_HAVE_USBFS
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select STM32H5_HAVE_HSI48
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config STM32H5_STM32H563XX
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# STM32H552 and STM32H562 devices documented in RM0439
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@ -220,6 +222,10 @@ config STM32H5_HAVE_FDCAN2
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bool
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default n
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config STM32H5_HAVE_HSI48
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bool
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default n
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config STM32H5_HAVE_LPUART1
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bool
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default n
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@ -280,6 +286,10 @@ config STM32H5_HAVE_UART12
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bool
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default n
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config STM32H5_HAVE_USBFS
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bool
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default n
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# These "hidden" settings are the OR of individual peripheral selections
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# indicating that the general capability is required.
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@ -555,6 +565,12 @@ config STM32H5_TIM17
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endmenu # STM32H5 Timer Selection
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config STM32H5_USBFS
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bool "USB Device"
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default n
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depends on STM32H5_HAVE_USBFS
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select USBDEV
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endmenu
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config STM32H5_FLASH_PREFETCH
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@ -3770,6 +3786,20 @@ endmenu #STM32 TIMx Outputs Configuration
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endmenu # Timer Configuration
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comment "USB Device Configuration"
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menu "USB Full Speed Debug Configuration"
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depends on STM32H5_USBFS
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config STM32H5_USBFS_REGDEBUG
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bool "Register-Level Debug"
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default n
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depends on STM32H5_USBFS && DEBUG_USB_INFO
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---help---
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Enable very low-level register access debug.
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endmenu
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config STM32H5_SERIALDRIVER
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bool
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@ -68,6 +68,14 @@ ifeq ($(CONFIG_STM32H5_TIM),y)
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CHIP_CSRCS += stm32_tim.c
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endif
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ifeq ($(CONFIG_STM32H5_HAVE_HSI48),y)
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CHIP_CSRCS += stm32_hsi48.c
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endif
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ifeq ($(CONFIG_STM32H5_USBFS),y)
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CHIP_CSRCS += stm32_usbfs.c
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endif
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# Required chip type specific files
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ifeq ($(CONFIG_STM32H5_STM32H5XXXX),y)
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228
arch/arm/src/stm32h5/hardware/stm32_usbfs.h
Normal file
228
arch/arm/src/stm32h5/hardware/stm32_usbfs.h
Normal file
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@ -0,0 +1,228 @@
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/****************************************************************************
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* arch/arm/src/stm32h5/hardware/stm32_usbfs.h
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32_USBFS_H
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#define __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32_USBFS_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <chip.h>
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#ifdef CONFIG_STM32H5_HAVE_USBFS
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Register Offsets *********************************************************/
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/* Endpoint Registers */
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#define STM32_USB_EPR_OFFSET(n) ((n) << 2) /* USB endpoint n register (32-bits) */
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#define STM32_USB_EP0R_OFFSET 0x0000 /* USB endpoint 0 register (32-bits) */
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#define STM32_USB_EP1R_OFFSET 0x0004 /* USB endpoint 1 register (32-bits) */
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#define STM32_USB_EP2R_OFFSET 0x0008 /* USB endpoint 2 register (32-bits) */
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#define STM32_USB_EP3R_OFFSET 0x000c /* USB endpoint 3 register (32-bits) */
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#define STM32_USB_EP4R_OFFSET 0x0010 /* USB endpoint 4 register (32-bits) */
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#define STM32_USB_EP5R_OFFSET 0x0014 /* USB endpoint 5 register (32-bits) */
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#define STM32_USB_EP6R_OFFSET 0x0018 /* USB endpoint 6 register (32-bits) */
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#define STM32_USB_EP7R_OFFSET 0x001c /* USB endpoint 7 register (32-bits) */
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/* Common Registers */
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#define STM32_USB_CNTR_OFFSET 0x0040 /* USB control register (32-bits) */
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#define STM32_USB_ISTR_OFFSET 0x0044 /* USB interrupt status register (32-bits) */
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#define STM32_USB_FNR_OFFSET 0x0048 /* USB frame number register (32-bits) */
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#define STM32_USB_DADDR_OFFSET 0x004c /* USB device address (32-bits) */
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#define STM32_USB_LPMCSR_OFFSET 0x0054 /* LPM control and status register (32-bits) */
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#define STM32_USB_BCDR_OFFSET 0x0058 /* Battery charging detector (32-bits) */
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/* Buffer Descriptor Table (Relatative to BTABLE address) */
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#define STM32_USB_TX_WOFFSET (0) /* Transmission buffer n (32-bits) */
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#define STM32_USB_RX_WOFFSET (4) /* Reception buffer address n (32-bits) */
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#define STM32_USB_BTABLE_RADDR(ep,o) ((((uint32_t)STM32_USB_FS_RAM_BASE + ((ep) << 3)) + (o)))
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/* Register Addresses *******************************************************/
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/* Endpoint Registers */
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#define STM32_USB_EPR(n) (STM32_USB_FS_BASE + STM32_USB_EPR_OFFSET(n))
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#define STM32_USB_EP0R (STM32_USB_FS_BASE + STM32_USB_EP0R_OFFSET)
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#define STM32_USB_EP1R (STM32_USB_FS_BASE + STM32_USB_EP1R_OFFSET)
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#define STM32_USB_EP2R (STM32_USB_FS_BASE + STM32_USB_EP2R_OFFSET)
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#define STM32_USB_EP3R (STM32_USB_FS_BASE + STM32_USB_EP3R_OFFSET)
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#define STM32_USB_EP4R (STM32_USB_FS_BASE + STM32_USB_EP4R_OFFSET)
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#define STM32_USB_EP5R (STM32_USB_FS_BASE + STM32_USB_EP5R_OFFSET)
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#define STM32_USB_EP6R (STM32_USB_FS_BASE + STM32_USB_EP6R_OFFSET)
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#define STM32_USB_EP7R (STM32_USB_FS_BASE + STM32_USB_EP7R_OFFSET)
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/* Common Registers */
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#define STM32_USB_CNTR (STM32_USB_FS_BASE + STM32_USB_CNTR_OFFSET)
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#define STM32_USB_ISTR (STM32_USB_FS_BASE + STM32_USB_ISTR_OFFSET)
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#define STM32_USB_FNR (STM32_USB_FS_BASE + STM32_USB_FNR_OFFSET)
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#define STM32_USB_DADDR (STM32_USB_FS_BASE + STM32_USB_DADDR_OFFSET)
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#define STM32_USB_LPMCSR (STM32_USB_FS_BASE + STM32_USB_LPMCSR_OFFSET)
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#define STM32_USB_BCDR (STM32_USB_FS_BASE + STM32_USB_BCDR_OFFSET)
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/* Buffer Descriptor Table (Relative to BTABLE address) */
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#define STM32_USB_BTABLE_ADDR(ep,o) (STM32_USB_BTABLE_RADDR(ep,o))
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#define STM32_USB_TX(ep) STM32_USB_BTABLE_RADDR(ep,STM32_USB_TX_WOFFSET)
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#define STM32_USB_RX(ep) STM32_USB_BTABLE_RADDR(ep,STM32_USB_RX_WOFFSET)
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/* Register Bitfield Definitions ********************************************/
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/* USB endpoint register */
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#define USB_EPR_EA_SHIFT (0) /* Bits 3:0 [3:0]: Endpoint Address */
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#define USB_EPR_EA_MASK (0X0f << USB_EPR_EA_SHIFT)
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#define USB_EPR_STATTX_SHIFT (4) /* Bits 5-4: Status bits, for transmission transfers */
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#define USB_EPR_STATTX_MASK (3 << USB_EPR_STATTX_SHIFT)
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# define USB_EPR_STATTX_DIS (0 << USB_EPR_STATTX_SHIFT) /* EndPoint TX DISabled */
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# define USB_EPR_STATTX_STALL (1 << USB_EPR_STATTX_SHIFT) /* EndPoint TX STALLed */
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# define USB_EPR_STATTX_NAK (2 << USB_EPR_STATTX_SHIFT) /* EndPoint TX NAKed */
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# define USB_EPR_STATTX_VALID (3 << USB_EPR_STATTX_SHIFT) /* EndPoint TX VALID */
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# define USB_EPR_STATTX_DTOG1 (1 << USB_EPR_STATTX_SHIFT) /* EndPoint TX Data Toggle bit1 */
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# define USB_EPR_STATTX_DTOG2 (2 << USB_EPR_STATTX_SHIFT) /* EndPoint TX Data Toggle bit2 */
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#define USB_EPR_DTOG_TX (1 << 6) /* Bit 6: Data Toggle, for transmission transfers */
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#define USB_EPR_CTR_TX (1 << 7) /* Bit 7: Correct Transfer for transmission */
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#define USB_EPR_EP_KIND (1 << 8) /* Bit 8: Endpoint Kind */
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#define USB_EPR_EPTYPE_SHIFT (9) /* Bits 10-9: Endpoint type */
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#define USB_EPR_EPTYPE_MASK (3 << USB_EPR_EPTYPE_SHIFT)
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# define USB_EPR_EPTYPE_BULK (0 << USB_EPR_EPTYPE_SHIFT) /* EndPoint BULK */
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# define USB_EPR_EPTYPE_CONTROL (1 << USB_EPR_EPTYPE_SHIFT) /* EndPoint CONTROL */
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# define USB_EPR_EPTYPE_ISOC (2 << USB_EPR_EPTYPE_SHIFT) /* EndPoint ISOCHRONOUS */
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# define USB_EPR_EPTYPE_INTERRUPT (3 << USB_EPR_EPTYPE_SHIFT) /* EndPoint INTERRUPT */
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#define USB_EPR_SETUP (1 << 11) /* Bit 11: Setup transaction completed */
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#define USB_EPR_STATRX_SHIFT (12) /* Bits 13-12: Status bits, for reception transfers */
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#define USB_EPR_STATRX_MASK (3 << USB_EPR_STATRX_SHIFT)
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# define USB_EPR_STATRX_DIS (0 << USB_EPR_STATRX_SHIFT) /* EndPoint RX DISabled */
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# define USB_EPR_STATRX_STALL (1 << USB_EPR_STATRX_SHIFT) /* EndPoint RX STALLed */
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# define USB_EPR_STATRX_NAK (2 << USB_EPR_STATRX_SHIFT) /* EndPoint RX NAKed */
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# define USB_EPR_STATRX_VALID (3 << USB_EPR_STATRX_SHIFT) /* EndPoint RX VALID */
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# define USB_EPR_STATRX_DTOG1 (1 << USB_EPR_STATRX_SHIFT) /* EndPoint RX Data TOGgle bit1 */
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# define USB_EPR_STATRX_DTOG2 (2 << USB_EPR_STATRX_SHIFT) /* EndPoint RX Data TOGgle bit1 */
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#define USB_EPR_DTOG_RX (1 << 14) /* Bit 14: Data Toggle, for reception transfers */
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#define USB_EPR_CTR_RX (1 << 15) /* Bit 15: Correct Transfer for reception */
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/* USB control register */
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#define USB_CNTR_FRES (1 << 0) /* Bit 0: Force USB Reset */
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#define USB_CNTR_PDWN (1 << 1) /* Bit 1: Power down */
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#define USB_CNTR_SUSPRDY (1 << 2) /* Bit 2: Suspend Ready */
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#define USB_CNTR_FSUSP (1 << 3) /* Bit 3: Force suspend */
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#define USB_CNTR_RESUME (1 << 4) /* Bit 4: Resume request */
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#define USB_CNTR_L1RESUME (1 << 5) /* Bit 5: LPM L1 Resume request */
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#define USB_CNTR_L1REQ (1 << 7) /* Bit 7: LPM L1 state request interrupt mask */
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#define USB_CNTR_ESOFM (1 << 8) /* Bit 8: Expected Start Of Frame Interrupt Mask */
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#define USB_CNTR_SOFM (1 << 9) /* Bit 9: Start Of Frame Interrupt Mask */
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#define USB_CNTR_RESETM (1 << 10) /* Bit 10: USB Reset Interrupt Mask */
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#define USB_CNTR_SUSPM (1 << 11) /* Bit 11: Suspend mode Interrupt Mask */
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#define USB_CNTR_WKUPM (1 << 12) /* Bit 12: Wakeup Interrupt Mask */
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#define USB_CNTR_ERRM (1 << 13) /* Bit 13: Error Interrupt Mask */
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#define USB_CNTR_PMAOVRN (1 << 14) /* Bit 14: Packet Memory Area Over / Underrun Interrupt Mask */
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#define USB_CNTR_CTRM (1 << 15) /* Bit 15: Correct Transfer Interrupt Mask */
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#define USB_CNTR_ALLINTS (USB_CNTR_L1REQ|USB_CNTR_ESOFM|USB_CNTR_SOFM|USB_CNTR_RESETM|\
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USB_CNTR_SUSPM|USB_CNTR_WKUPM|USB_CNTR_ERRM|USB_CNTR_PMAOVRN|\
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USB_CNTR_CTRM)
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/* USB interrupt status register */
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#define USB_ISTR_EPID_SHIFT (0) /* Bits 3-0: Endpoint Identifier */
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#define USB_ISTR_EPID_MASK (0x0f << USB_ISTR_EPID_SHIFT)
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#define USB_ISTR_DIR (1 << 4) /* Bit 4: Direction of transaction */
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#define USB_ISTR_L1REQ (1 << 7) /* Bit 7: LPM L1 state request */
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#define USB_ISTR_ESOF (1 << 8) /* Bit 8: Expected Start Of Frame */
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#define USB_ISTR_SOF (1 << 9) /* Bit 9: Start Of Frame */
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#define USB_ISTR_RESET (1 << 10) /* Bit 10: USB RESET request */
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#define USB_ISTR_SUSP (1 << 11) /* Bit 11: Suspend mode request */
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#define USB_ISTR_WKUP (1 << 12) /* Bit 12: Wake up */
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#define USB_ISTR_ERR (1 << 13) /* Bit 13: Error */
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#define USB_ISTR_PMAOVRN (1 << 14) /* Bit 14: Packet Memory Area Over / Underrun */
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#define USB_ISTR_CTR (1 << 15) /* Bit 15: Correct Transfer */
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#define USB_ISTR_ALLINTS (USB_ISTR_L1REQ|USB_ISTR_ESOF|USB_ISTR_SOF|USB_ISTR_RESET|\
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USB_ISTR_SUSP|USB_ISTR_WKUP|USB_ISTR_ERR|USB_ISTR_PMAOVRN|\
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USB_ISTR_CTR)
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/* USB frame number register */
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#define USB_FNR_FN_SHIFT (0) /* Bits 10-0: Frame Number */
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#define USB_FNR_FN_MASK (0x07ff << USB_FNR_FN_SHIFT)
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#define USB_FNR_LSOF_SHIFT (11) /* Bits 12-11: Lost SOF */
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#define USB_FNR_LSOF_MASK (3 << USB_FNR_LSOF_SHIFT)
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#define USB_FNR_LCK (1 << 13) /* Bit 13: Locked */
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#define USB_FNR_RXDM (1 << 14) /* Bit 14: Receive Data - Line Status */
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#define USB_FNR_RXDP (1 << 15) /* Bit 15: Receive Data + Line Status */
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/* USB device address */
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#define USB_DADDR_ADD_SHIFT (0) /* Bits 6-0: Device Address */
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#define USB_DADDR_ADD_MASK (0x7f << USB_DADDR_ADD_SHIFT)
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#define USB_DADDR_EF (1 << 7) /* Bit 7: Enable Function */
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/* LPM control and status register (32-bits) */
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#define USB_LPMCSR_LPMEN (1 << 0) /* Bit 0: LPM support enable */
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#define USB_LPMCSR_LPMACK (1 << 1) /* Bit 1: LPM Token acknowledge enable */
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#define USB_LPMCSR_REMWAKE (1 << 3) /* Bit 3: bRemoteWake value */
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#define USB_LPMCSR_BESL_SHIFT (4) /* Bits 4-7: BESL value */
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#define USB_LPMCSR_BESL_MASK (15 << USB_LPMCSR_BESL_SHIFT)
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/* Battery charging detector (32-bits) */
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#define USB_BCDR_BCDEN (1 << 0) /* Bit 0: Battery charging detector (BCD) enable */
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#define USB_BCDR_DCDEN (1 << 1) /* Bit 1: Data contact detection (DCD) mode enable */
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#define USB_BCDR_PDEN (1 << 2) /* Bit 2: Primary detection (PD) mode enable */
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#define USB_BCDR_SDEN (1 << 3) /* Bit 3: Secondary detection (SD) mode enable */
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#define USB_BCDR_DCDET (1 << 4) /* Bit 4: Data contact detection (DCD) status */
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#define USB_BCDR_PDET (1 << 5) /* Bit 5: Primary detection (PD) status */
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#define USB_BCDR_SDET (1 << 6) /* Bit 6: Secondary detection (SD) status */
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#define USB_BCDR_PS2DET (1 << 7) /* Bit 7: DM pull-up detection status */
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#define USB_BCDR_DPPU (1 << 15) /* Bit 15: DP pull-up control */
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/* Reception buffer address */
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#define USB_ADDR_RX_SHIFT (2) /* Bits 15:2 ADDRn_RX[15:2]: Reception Buffer Address */
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#define USB_ADDR_RX_MASK (0x3fff << USB_ADDR_RX_SHIFT)
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/* Reception byte count */
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#define USB_COUNT_RX_BL_SIZE (1 << 31) /* Bit 15: BLock SIZE. */
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#define USB_COUNT_RX_NUM_BLOCK_SHIFT (26) /* Bits 14-10: Number of blocks */
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#define USB_COUNT_RX_NUM_BLOCK_MASK (0x1f << USB_COUNT_RX_NUM_BLOCK_SHIFT)
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#define USB_COUNT_RX_SHIFT (16) /* Bits 9-0: Reception Byte Count */
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#define USB_COUNT_RX_MASK (0x3ff << USB_COUNT_RX_SHIFT)
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#endif /* CONFIG_STM32H5_HAVE_USBFS */
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#endif /* __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32_USBFS_H */
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#define GPIO_LPUART1_CTS_1 (GPIO_ALT|GPIO_AF3|GPIO_PORTA|GPIO_PIN11)
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#define GPIO_LPUART1_RTS_DE_1 (GPIO_ALT|GPIO_AF3|GPIO_PORTA|GPIO_PIN12)
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/* USB */
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#define GPIO_USB_DM (GPIO_ALT|GPIO_AF10|GPIO_PUSHPULL|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN11)
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#define GPIO_USB_DP (GPIO_ALT|GPIO_AF10|GPIO_PUSHPULL|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN12)
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#define GPIO_USB_SOF (GPIO_ALT|GPIO_AF10|GPIO_PUSHPULL|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN8)
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/* ADC1 */
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#define GPIO_ADC1_IN0_0 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN0)
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|
|||
#include "stm32_lowputc.h"
|
||||
#include "stm32_i2c.h"
|
||||
#include "stm32_adc.h"
|
||||
#include "stm32_usbfs.h"
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32H5_STM32_H */
|
||||
|
|
|
|||
|
|
@ -87,7 +87,7 @@ void stm32h5_enable_hsi48(enum syncsrc_e syncsrc)
|
|||
|
||||
/* Wait for the HSI48 clock to stabilize */
|
||||
|
||||
while ((getreg32(STM32_RCC_CRRCR) & RCC_CRRCR_HSI48RDY) == 0);
|
||||
while ((getreg32(STM32_RCC_CR) & RCC_CR_HSI48RDY) == 0);
|
||||
|
||||
/* Return if no synchronization */
|
||||
|
||||
|
|
|
|||
3951
arch/arm/src/stm32h5/stm32_usbfs.c
Normal file
3951
arch/arm/src/stm32h5/stm32_usbfs.c
Normal file
File diff suppressed because it is too large
Load diff
92
arch/arm/src/stm32h5/stm32_usbfs.h
Normal file
92
arch/arm/src/stm32h5/stm32_usbfs.h
Normal file
|
|
@ -0,0 +1,92 @@
|
|||
/****************************************************************************
|
||||
* arch/arm/src/stm32h5/stm32_usbfs.h
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32H5_STM32_USBFS_H
|
||||
#define __ARCH_ARM_SRC_STM32H5_STM32_USBFS_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include <nuttx/usb/usbdev.h>
|
||||
#include <stdint.h>
|
||||
|
||||
#include "chip.h"
|
||||
#include "hardware/stm32_usbfs.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/* Number of endpoints */
|
||||
|
||||
#define STM32_NENDPOINTS (8)
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
#define EXTERN extern "C"
|
||||
extern "C"
|
||||
{
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_usbpullup
|
||||
*
|
||||
* Description:
|
||||
* If USB is supported and the board supports a pullup via GPIO
|
||||
* (for USB software connect and disconnect), then the board software must
|
||||
* provide stm32_pullup.
|
||||
* See include/nuttx/usb/usbdev.h for additional description of this method.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
int stm32_usbpullup(struct usbdev_s *dev, bool enable);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_usbsuspend
|
||||
*
|
||||
* Description:
|
||||
* Board logic must provide the stm32_usbsuspend logic if the USBDEV driver
|
||||
* is used. This function is called whenever the USB enters or leaves
|
||||
* suspend mode. This is an opportunity for the board logic to shutdown
|
||||
* clocks, power, etc. while the USB is suspended.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void stm32_usbsuspend(struct usbdev_s *dev, bool resume);
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __ARCH_ARM_SRC_STM32H5_STM32_USBFS_H */
|
||||
|
|
@ -31,6 +31,7 @@
|
|||
#include "stm32_pwr.h"
|
||||
#include "stm32_flash.h"
|
||||
#include "stm32_rcc.h"
|
||||
#include "stm32_hsi48.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
|
|
@ -58,7 +59,7 @@
|
|||
|
||||
#if defined(CONFIG_STM32H5_HAVE_HSI48) && defined(STM32H5_USE_CLK48)
|
||||
# if STM32H5_CLKUSB_SEL == RCC_CCIPR4_USBSEL_HSI48KERCK
|
||||
# define STM32H5_USE_HSI48
|
||||
# define STM32H5_USE_HSI48 1
|
||||
# endif
|
||||
#endif
|
||||
|
||||
|
|
@ -567,7 +568,7 @@ static inline void rcc_enableapb2(void)
|
|||
regval |= RCC_APB2ENR_SAI2EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32H5_USB
|
||||
#ifdef CONFIG_STM32H5_USBFS
|
||||
/* USB clock enable */
|
||||
|
||||
regval |= RCC_APB2ENR_USBEN;
|
||||
|
|
@ -1180,6 +1181,13 @@ void stm32_stdclockconfig(void)
|
|||
regval |= STM32_RCC_CCIPR3_SPI6SEL;
|
||||
putreg32(regval, STM32_RCC_CCIPR3);
|
||||
#endif
|
||||
|
||||
#if defined(STM32H5_CLKUSB_SEL)
|
||||
regval = getreg32(STM32_RCC_CCIPR4);
|
||||
regval &= ~RCC_CCIPR4_USBSEL_MASK;
|
||||
regval |= STM32H5_CLKUSB_SEL;
|
||||
putreg32(regval, STM32_RCC_CCIPR4);
|
||||
#endif
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
|
|
|||
55
boards/arm/stm32h5/nucleo-h563zi/configs/usbnsh/defconfig
Normal file
55
boards/arm/stm32h5/nucleo-h563zi/configs/usbnsh/defconfig
Normal file
|
|
@ -0,0 +1,55 @@
|
|||
#
|
||||
# This file is autogenerated: PLEASE DO NOT EDIT IT.
|
||||
#
|
||||
# You can use "make menuconfig" to make any modifications to the installed .config file.
|
||||
# You can then do "make savedefconfig" to generate a new defconfig file that includes your
|
||||
# modifications.
|
||||
#
|
||||
# CONFIG_DEV_CONSOLE is not set
|
||||
# CONFIG_NSH_ARGCAT is not set
|
||||
# CONFIG_STANDARD_SERIAL is not set
|
||||
CONFIG_ARCH="arm"
|
||||
CONFIG_ARCH_BOARD="nucleo-h563zi"
|
||||
CONFIG_ARCH_BOARD_NUCLEO_H563ZI=y
|
||||
CONFIG_ARCH_BUTTONS=y
|
||||
CONFIG_ARCH_CHIP="stm32h5"
|
||||
CONFIG_ARCH_CHIP_STM32H563ZI=y
|
||||
CONFIG_ARCH_CHIP_STM32H5=y
|
||||
CONFIG_ARCH_INTERRUPTSTACK=4096
|
||||
CONFIG_ARCH_STACKDUMP=y
|
||||
CONFIG_ARMV8M_STACKCHECK=y
|
||||
CONFIG_BOARDCTL_USBDEVCTRL=y
|
||||
CONFIG_BOARD_LOOPSPERMSEC=9251
|
||||
CONFIG_BUILTIN=y
|
||||
CONFIG_CDCACM=y
|
||||
CONFIG_CDCACM_CONSOLE=y
|
||||
CONFIG_DEBUG_ASSERTIONS=y
|
||||
CONFIG_DEBUG_FEATURES=y
|
||||
CONFIG_DEBUG_SYMBOLS=y
|
||||
CONFIG_FS_PROCFS=y
|
||||
CONFIG_FS_PROCFS_REGISTER=y
|
||||
CONFIG_HAVE_CXX=y
|
||||
CONFIG_HAVE_CXXINITIALIZE=y
|
||||
CONFIG_IDLETHREAD_STACKSIZE=2048
|
||||
CONFIG_INIT_ENTRYPOINT="nsh_main"
|
||||
CONFIG_INIT_STACKSIZE=4096
|
||||
CONFIG_IRQ_WORK_STACKSIZE=4096
|
||||
CONFIG_LINE_MAX=64
|
||||
CONFIG_NSH_ARCHINIT=y
|
||||
CONFIG_NSH_BUILTIN_APPS=y
|
||||
CONFIG_NSH_DISABLE_IFUPDOWN=y
|
||||
CONFIG_NSH_FILEIOSIZE=512
|
||||
CONFIG_NSH_READLINE=y
|
||||
CONFIG_PREALLOC_TIMERS=4
|
||||
CONFIG_RAM_SIZE=655360
|
||||
CONFIG_RAM_START=0x20000000
|
||||
CONFIG_RAW_BINARY=y
|
||||
CONFIG_READLINE_CMD_HISTORY=y
|
||||
CONFIG_READLINE_TABCOMPLETION=y
|
||||
CONFIG_RR_INTERVAL=200
|
||||
CONFIG_SCHED_WAITPID=y
|
||||
CONFIG_STACK_COLORATION=y
|
||||
CONFIG_STM32H5_USART3=y
|
||||
CONFIG_STM32H5_USBFS=y
|
||||
CONFIG_SYSTEM_NSH=y
|
||||
CONFIG_TASK_NAME_SIZE=0
|
||||
|
|
@ -152,7 +152,12 @@
|
|||
|
||||
#if defined(CONFIG_STM32H5_USBFS) || defined(CONFIG_STM32H5_RNG)
|
||||
# define STM32H5_USE_CLK48 1
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_STM32H5_USBFS)
|
||||
# define STM32H5_CLKUSB_SEL RCC_CCIPR4_USBSEL_HSI48KERCK
|
||||
# define STM32H5_HSI48_SYNCSRC SYNCSRC_USB
|
||||
#else
|
||||
# define STM32H5_HSI48_SYNCSRC SYNCSRC_NONE
|
||||
#endif
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue