From 6949c823105aaa0e7ca02dfde384cde9537b7949 Mon Sep 17 00:00:00 2001 From: lipengfei28 Date: Wed, 11 Dec 2024 10:34:20 +0800 Subject: [PATCH] arch/arm:use UP_DSB, UP_DMB, UP_ISB as barrier standard API Signed-off-by: lipengfei28 --- arch/arm/{src => include}/armv6-m/barriers.h | 14 ++-- arch/arm/{src => include}/armv7-a/barriers.h | 18 ++--- arch/arm/{src => include}/armv7-m/barriers.h | 14 ++-- arch/arm/{src => include}/armv7-r/barriers.h | 18 ++--- arch/arm/{src => include}/armv8-m/barriers.h | 14 ++-- arch/arm/{src => include}/armv8-r/barriers.h | 18 ++--- arch/arm/include/barriers.h | 52 ++++++++++++++ arch/arm/include/spinlock.h | 2 + arch/arm/src/armv7-a/arm_cache.c | 2 +- arch/arm/src/armv7-a/arm_l2cc_pl310.c | 11 ++- arch/arm/src/armv7-a/arm_scu.c | 8 +-- arch/arm/src/armv7-a/arm_timer.c | 20 +++--- arch/arm/src/armv7-a/cp15_cacheops.c | 12 ++-- arch/arm/src/armv7-a/cp15_cacheops.h | 34 +++++----- arch/arm/src/armv7-a/mmu.h | 44 ++++++------ arch/arm/src/armv7-a/sctlr.h | 19 +++--- arch/arm/src/armv7-m/arm_cache.c | 67 +++++++------------ arch/arm/src/armv7-m/arm_mpu.c | 15 ++--- arch/arm/src/armv7-r/arm_cache.c | 2 +- arch/arm/src/armv7-r/arm_l2cc_pl310.c | 11 ++- arch/arm/src/armv7-r/arm_mpu.c | 3 +- arch/arm/src/armv7-r/arm_scu.c | 8 +-- arch/arm/src/armv7-r/arm_timer.c | 20 +++--- arch/arm/src/armv7-r/cp15_cacheops.c | 12 ++-- arch/arm/src/armv7-r/cp15_cacheops.h | 34 +++++----- arch/arm/src/armv7-r/sctlr.h | 19 +++--- arch/arm/src/armv8-m/arm_cache.c | 67 +++++++------------ arch/arm/src/armv8-m/arm_mpu.c | 14 ++-- arch/arm/src/armv8-r/arm_arch_timer.c | 2 +- arch/arm/src/armv8-r/arm_cache.c | 2 +- arch/arm/src/armv8-r/arm_gicv3.c | 10 +-- arch/arm/src/armv8-r/arm_l2cc_pl310.c | 11 ++- arch/arm/src/armv8-r/cp15_cacheops.c | 12 ++-- arch/arm/src/armv8-r/cp15_cacheops.h | 34 +++++----- arch/arm/src/armv8-r/sctlr.h | 19 +++--- arch/arm/src/fvp-v8r-aarch32/fvp_boot.c | 4 +- arch/arm/src/imx6/imx_cpuboot.c | 4 +- arch/arm/src/imx9/imx9_clockconfig.c | 13 +--- arch/arm/src/imx9/imx9_mpuinit.c | 5 +- arch/arm/src/imx9/imx9_start.c | 8 +-- arch/arm/src/imxrt/imxrt106x_flash.c | 3 +- arch/arm/src/imxrt/imxrt_enet.c | 8 +-- arch/arm/src/imxrt/imxrt_flexio.c | 2 +- arch/arm/src/imxrt/imxrt_flexspi.c | 2 +- arch/arm/src/imxrt/imxrt_mpuinit.c | 4 +- arch/arm/src/imxrt/imxrt_periphclks.c | 9 ++- arch/arm/src/imxrt/imxrt_start.c | 8 +-- arch/arm/src/mps/mps_start.c | 10 ++- arch/arm/src/mps/mps_userspace.c | 2 +- arch/arm/src/nrf52/nrf52_nvmc.c | 6 +- arch/arm/src/nrf52/nrf52_qspi.c | 4 -- arch/arm/src/nrf52/nrf52_spi.c | 5 +- arch/arm/src/nrf53/nrf53_flash.c | 12 ++-- arch/arm/src/nrf53/nrf53_qspi.c | 4 -- arch/arm/src/nrf53/nrf53_spi.c | 2 +- arch/arm/src/nrf91/nrf91_errata.c | 11 ++- arch/arm/src/nrf91/nrf91_flash.c | 12 ++-- arch/arm/src/nrf91/nrf91_spi.c | 2 +- arch/arm/src/rp2040/rp2040_cyw43439.c | 11 ++- arch/arm/src/rp23xx/rp23xx_testset.c | 2 +- arch/arm/src/s32k3xx/s32k3xx_emac.c | 6 +- arch/arm/src/s32k3xx/s32k3xx_mpuinit.c | 4 +- arch/arm/src/s32k3xx/s32k3xx_qspi.c | 12 ++-- arch/arm/src/sama5/sam_qspi.c | 14 ++-- arch/arm/src/samv7/sam_eefc.c | 3 +- arch/arm/src/samv7/sam_mpuinit.c | 4 +- arch/arm/src/samv7/sam_progmem.c | 4 +- arch/arm/src/samv7/sam_qspi.c | 14 ++-- arch/arm/src/samv7/sam_start.c | 8 +-- arch/arm/src/samv7/sam_us.c | 4 +- arch/arm/src/samv7/sam_usbdevhs.c | 16 ++--- arch/arm/src/stm32f7/stm32_ethernet.c | 8 +-- arch/arm/src/stm32f7/stm32_flash.c | 5 +- arch/arm/src/stm32f7/stm32_qspi.c | 18 ++--- arch/arm/src/stm32f7/stm32_start.c | 8 +-- arch/arm/src/stm32h5/stm32_ethernet.c | 9 +-- arch/arm/src/stm32h5/stm32_qspi.c | 19 +++--- arch/arm/src/stm32h7/stm32_ethernet.c | 8 +-- arch/arm/src/stm32h7/stm32_pwr.c | 6 +- arch/arm/src/stm32h7/stm32_qspi.c | 18 ++--- arch/arm/src/stm32h7/stm32_start.c | 8 +-- arch/arm/src/stm32h7/stm32h743xx_flash.c | 11 ++- arch/arm/src/stm32h7/stm32h7b3xx_flash.c | 11 ++- arch/arm/src/stm32l4/stm32l4_qspi.c | 18 ++--- .../imxrt1064-evk/src/imxrt_boot_image.c | 4 +- .../arm/nrf52/common/src/nrf52_boot_image.c | 4 +- .../arm/nrf53/common/src/nrf53_boot_image.c | 4 +- .../arm/nrf91/common/src/nrf91_boot_image.c | 6 +- boards/arm/samv7/common/src/sam_boot_image.c | 4 +- .../nucleo-h743zi/src/stm32_boot_image.c | 4 +- 90 files changed, 493 insertions(+), 584 deletions(-) rename arch/arm/{src => include}/armv6-m/barriers.h (85%) rename arch/arm/{src => include}/armv7-a/barriers.h (83%) rename arch/arm/{src => include}/armv7-m/barriers.h (85%) rename arch/arm/{src => include}/armv7-r/barriers.h (83%) rename arch/arm/{src => include}/armv8-m/barriers.h (85%) rename arch/arm/{src => include}/armv8-r/barriers.h (83%) create mode 100644 arch/arm/include/barriers.h diff --git a/arch/arm/src/armv6-m/barriers.h b/arch/arm/include/armv6-m/barriers.h similarity index 85% rename from arch/arm/src/armv6-m/barriers.h rename to arch/arm/include/armv6-m/barriers.h index 246815ca1a..b1b251fc29 100644 --- a/arch/arm/src/armv6-m/barriers.h +++ b/arch/arm/include/armv6-m/barriers.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/armv6-m/barriers.h + * arch/arm/include/armv6-m/barriers.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_ARMV6_M_BARRIERS_H -#define __ARCH_ARM_SRC_ARMV6_M_BARRIERS_H +#ifndef __ARCH_ARM_INCLUDE_ARMV6_M_BARRIERS_H +#define __ARCH_ARM_INCLUDE_ARMV6_M_BARRIERS_H /**************************************************************************** * Included Files @@ -37,8 +37,8 @@ #define arm_isb() __asm__ __volatile__ ("isb " : : : "memory") #define arm_dmb() __asm__ __volatile__ ("dmb " : : : "memory") -#define ARM_DSB() arm_dsb() -#define ARM_ISB() arm_isb() -#define ARM_DMB() arm_dmb() +#define UP_DSB() arm_dsb() +#define UP_ISB() arm_isb() +#define UP_DMB() arm_dmb() -#endif /* __ARCH_ARM_SRC_ARMV6_M_BARRIERS_H */ +#endif /* __ARCH_ARM_INCLUDE_ARMV6_M_BARRIERS_H */ diff --git a/arch/arm/src/armv7-a/barriers.h b/arch/arm/include/armv7-a/barriers.h similarity index 83% rename from arch/arm/src/armv7-a/barriers.h rename to arch/arm/include/armv7-a/barriers.h index 6de8e67c5b..9f94b8d477 100644 --- a/arch/arm/src/armv7-a/barriers.h +++ b/arch/arm/include/armv7-a/barriers.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/armv7-a/barriers.h + * arch/arm/include/armv7-a/barriers.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_ARMV7_A_BARRIERS_H -#define __ARCH_ARM_SRC_ARMV7_A_BARRIERS_H +#ifndef __ARCH_ARM_INCLUDE_ARMV7_A_BARRIERS_H +#define __ARCH_ARM_INCLUDE_ARMV7_A_BARRIERS_H /**************************************************************************** * Included Files @@ -39,10 +39,10 @@ #define arm_nop() __asm__ __volatile__ ("nop\n") #define arm_sev() __asm__ __volatile__ ("sev\n") -#define ARM_DSB() arm_dsb(15) -#define ARM_DMB() arm_dmb(15) -#define ARM_ISB() arm_isb() -#define ARM_NOP() arm_nop() -#define ARM_SEV() arm_sev() +#define UP_DSB() arm_dsb(15) +#define UP_DMB() arm_dmb(15) +#define UP_ISB() arm_isb() +#define UP_NOP() arm_nop() +#define UP_SEV() arm_sev() -#endif /* __ARCH_ARM_SRC_ARMV7_A_BARRIERS_H */ +#endif /* __ARCH_ARM_INCLUDE_ARMV7_A_BARRIERS_H */ diff --git a/arch/arm/src/armv7-m/barriers.h b/arch/arm/include/armv7-m/barriers.h similarity index 85% rename from arch/arm/src/armv7-m/barriers.h rename to arch/arm/include/armv7-m/barriers.h index 1ec6a62ec3..360844656e 100644 --- a/arch/arm/src/armv7-m/barriers.h +++ b/arch/arm/include/armv7-m/barriers.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/armv7-m/barriers.h + * arch/arm/include/armv7-m/barriers.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_ARMV7_M_BARRIERS_H -#define __ARCH_ARM_SRC_ARMV7_M_BARRIERS_H +#ifndef __ARCH_ARM_INCLUDE_ARMV7_M_BARRIERS_H +#define __ARCH_ARM_INCLUDE_ARMV7_M_BARRIERS_H /**************************************************************************** * Included Files @@ -37,8 +37,8 @@ #define arm_isb() __asm__ __volatile__ ("isb " : : : "memory") #define arm_dmb() __asm__ __volatile__ ("dmb " : : : "memory") -#define ARM_DSB() arm_dsb() -#define ARM_ISB() arm_isb() -#define ARM_DMB() arm_dmb() +#define UP_DSB() arm_dsb() +#define UP_ISB() arm_isb() +#define UP_DMB() arm_dmb() -#endif /* __ARCH_ARM_SRC_ARMV7_M_BARRIERS_H */ +#endif /* __ARCH_ARM_INCLUDE_ARMV7_M_BARRIERS_H */ diff --git a/arch/arm/src/armv7-r/barriers.h b/arch/arm/include/armv7-r/barriers.h similarity index 83% rename from arch/arm/src/armv7-r/barriers.h rename to arch/arm/include/armv7-r/barriers.h index 21c6457127..f396d427c6 100644 --- a/arch/arm/src/armv7-r/barriers.h +++ b/arch/arm/include/armv7-r/barriers.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/armv7-r/barriers.h + * arch/arm/include/armv7-r/barriers.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_ARMV7_R_BARRIERS_H -#define __ARCH_ARM_SRC_ARMV7_R_BARRIERS_H +#ifndef __ARCH_ARM_INCLUDE_ARMV7_R_BARRIERS_H +#define __ARCH_ARM_INCLUDE_ARMV7_R_BARRIERS_H /**************************************************************************** * Included Files @@ -39,10 +39,10 @@ #define arm_nop() __asm__ __volatile__ ("nop\n") #define arm_sev() __asm__ __volatile__ ("sev\n") -#define ARM_DSB() arm_dsb(15) -#define ARM_DMB() arm_dmb(15) -#define ARM_ISB() arm_isb() -#define ARM_NOP() arm_nop() -#define ARM_SEV() arm_sev() +#define UP_DSB() arm_dsb(15) +#define UP_DMB() arm_dmb(15) +#define UP_ISB() arm_isb() +#define UP_NOP() arm_nop() +#define UP_SEV() arm_sev() -#endif /* __ARCH_ARM_SRC_ARMV7_R_BARRIERS_H */ +#endif /* __ARCH_ARM_INCLUDE_ARMV7_R_BARRIERS_H */ diff --git a/arch/arm/src/armv8-m/barriers.h b/arch/arm/include/armv8-m/barriers.h similarity index 85% rename from arch/arm/src/armv8-m/barriers.h rename to arch/arm/include/armv8-m/barriers.h index 671c82ab99..f47a223a03 100644 --- a/arch/arm/src/armv8-m/barriers.h +++ b/arch/arm/include/armv8-m/barriers.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/armv8-m/barriers.h + * arch/arm/include/armv8-m/barriers.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_ARMV8_M_BARRIERS_H -#define __ARCH_ARM_SRC_ARMV8_M_BARRIERS_H +#ifndef __ARCH_ARM_INCLUDE_ARMV8_M_BARRIERS_H +#define __ARCH_ARM_INCLUDE_ARMV8_M_BARRIERS_H /**************************************************************************** * Included Files @@ -37,8 +37,8 @@ #define arm_dmb() __asm__ __volatile__ ("dmb " : : : "memory") #define arm_dsb(n) __asm__ __volatile__ ("dsb " #n : : : "memory") -#define ARM_ISB() arm_isb() -#define ARM_DMB() arm_dmb() -#define ARM_DSB() arm_dsb(15) +#define UP_ISB() arm_isb() +#define UP_DMB() arm_dmb() +#define UP_DSB() arm_dsb(15) -#endif /* __ARCH_ARM_SRC_ARMV8_M_BARRIERS_H */ +#endif /* __ARCH_ARM_INCLUDE_ARMV8_M_BARRIERS_H */ diff --git a/arch/arm/src/armv8-r/barriers.h b/arch/arm/include/armv8-r/barriers.h similarity index 83% rename from arch/arm/src/armv8-r/barriers.h rename to arch/arm/include/armv8-r/barriers.h index 1b32b88f07..df8f86480c 100644 --- a/arch/arm/src/armv8-r/barriers.h +++ b/arch/arm/include/armv8-r/barriers.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/armv8-r/barriers.h + * arch/arm/include/armv8-r/barriers.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_ARMV8_R_BARRIERS_H -#define __ARCH_ARM_SRC_ARMV8_R_BARRIERS_H +#ifndef __ARCH_ARM_INCLUDE_ARMV8_R_BARRIERS_H +#define __ARCH_ARM_INCLUDE_ARMV8_R_BARRIERS_H /**************************************************************************** * Included Files @@ -39,10 +39,10 @@ #define arm_nop() __asm__ __volatile__ ("nop\n") #define arm_sev() __asm__ __volatile__ ("sev\n") -#define ARM_DSB() arm_dsb(15) -#define ARM_DMB() arm_dmb(15) -#define ARM_ISB() arm_isb() -#define ARM_NOP() arm_nop() -#define ARM_SEV() arm_sev() +#define UP_DSB() arm_dsb(15) +#define UP_DMB() arm_dmb(15) +#define UP_ISB() arm_isb() +#define UP_NOP() arm_nop() +#define UP_SEV() arm_sev() -#endif /* __ARCH_ARM_SRC_ARMV8_R_BARRIERS_H */ +#endif /* __ARCH_ARM_INCLUDE_ARMV8_R_BARRIERS_H */ diff --git a/arch/arm/include/barriers.h b/arch/arm/include/barriers.h new file mode 100644 index 0000000000..b67c2695c2 --- /dev/null +++ b/arch/arm/include/barriers.h @@ -0,0 +1,52 @@ +/**************************************************************************** + * arch/arm/include/barriers.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_INCLUDE_BARRIERS_H +#define __ARCH_ARM_INCLUDE_BARRIERS_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#if defined(CONFIG_ARCH_ARMV7A) +# include +#elif defined(CONFIG_ARCH_ARMV7R) +# include +#elif defined(CONFIG_ARCH_ARMV8R) +# include +#elif defined(CONFIG_ARCH_ARMV7M) +# include +#elif defined(CONFIG_ARCH_ARMV8M) +# include +#elif defined(CONFIG_ARCH_ARMV6M) +# include +#else +# include +#endif + +#define UP_MB() \ + do \ + { \ + UP_DSB(); \ + UP_ISB(); \ + } \ + while (0) + +#endif /* __ARCH_ARM_INCLUDE_BARRIERS_H */ diff --git a/arch/arm/include/spinlock.h b/arch/arm/include/spinlock.h index 973c6e347f..4aa024bee8 100644 --- a/arch/arm/include/spinlock.h +++ b/arch/arm/include/spinlock.h @@ -31,6 +31,8 @@ # include #endif /* __ASSEMBLY__ */ +#include + /**************************************************************************** * Pre-processor Prototypes ****************************************************************************/ diff --git a/arch/arm/src/armv7-a/arm_cache.c b/arch/arm/src/armv7-a/arm_cache.c index 3dfe12aa43..b91f79b02d 100644 --- a/arch/arm/src/armv7-a/arm_cache.c +++ b/arch/arm/src/armv7-a/arm_cache.c @@ -28,9 +28,9 @@ #include #include #include +#include #include "cp15_cacheops.h" -#include "barriers.h" #include "l2cc.h" /**************************************************************************** diff --git a/arch/arm/src/armv7-a/arm_l2cc_pl310.c b/arch/arm/src/armv7-a/arm_l2cc_pl310.c index 0b36f2175f..a3d15baeae 100644 --- a/arch/arm/src/armv7-a/arm_l2cc_pl310.c +++ b/arch/arm/src/armv7-a/arm_l2cc_pl310.c @@ -40,8 +40,8 @@ #include #include +#include #include "arm_internal.h" -#include "barriers.h" #include "l2cc.h" #include "l2cc_pl310.h" @@ -292,8 +292,7 @@ static void l2cc_disable_nolock(void) /* Disable the L2CC-P310 L2 cache by clearing the Control Register (CR) */ putreg32(0, L2CC_CR); - ARM_DSB(); - ARM_ISB(); + UP_MB(); } /**************************************************************************** @@ -457,8 +456,7 @@ void arm_l2ccinitialize(void) l2cc_invalidate_all(); putreg32(L2CC_CR_L2CEN, L2CC_CR); - ARM_DSB(); - ARM_ISB(); + UP_MB(); } sinfo("(%d ways) * (%d bytes/way) = %d bytes\n", @@ -533,8 +531,7 @@ void l2cc_enable(void) l2cc_invalidate_all_nolock(); putreg32(L2CC_CR_L2CEN, L2CC_CR); - ARM_DSB(); - ARM_ISB(); + UP_MB(); spin_unlock_irqrestore(&g_l2cc_lock, flags); } diff --git a/arch/arm/src/armv7-a/arm_scu.c b/arch/arm/src/armv7-a/arm_scu.c index 78322f911e..b8058a1b57 100644 --- a/arch/arm/src/armv7-a/arm_scu.c +++ b/arch/arm/src/armv7-a/arm_scu.c @@ -28,12 +28,12 @@ #include +#include #include #include #include "arm_internal.h" #include "cp15_cacheops.h" -#include "barriers.h" #include "sctlr.h" #include "scu.h" @@ -83,7 +83,7 @@ void arm_enable_smp(int cpu) */ cp15_invalidate_dcache_all(); - ARM_DSB(); + UP_DSB(); /* Invalidate the L2C-310 -- Missing logic. */ @@ -95,7 +95,7 @@ void arm_enable_smp(int cpu) /* Initialize done, kick other cpus which waiting on __start */ - ARM_SEV(); + UP_SEV(); } /* Actions for other CPUs */ @@ -107,7 +107,7 @@ void arm_enable_smp(int cpu) */ cp15_dcache_op_level(0, CP15_CACHE_INVALIDATE); - ARM_DSB(); + UP_DSB(); /* Wait for the SCU to be enabled by the primary processor -- should * not be necessary. diff --git a/arch/arm/src/armv7-a/arm_timer.c b/arch/arm/src/armv7-a/arm_timer.c index 8ec7dcc996..65faafa8bd 100644 --- a/arch/arm/src/armv7-a/arm_timer.c +++ b/arch/arm/src/armv7-a/arm_timer.c @@ -29,10 +29,10 @@ #include #include +#include #include #include "arm_timer.h" -#include "barriers.h" #include "gic.h" /**************************************************************************** @@ -98,49 +98,49 @@ static const struct oneshot_operations_s g_arm_timer_ops = static inline void arm_timer_set_freq(uint32_t freq) { CP15_SET(CNTFRQ, freq); - ARM_ISB(); + UP_ISB(); } static inline uint64_t arm_timer_get_count(void) { - ARM_ISB(); + UP_ISB(); return CP15_GET64(CNTPCT); } static inline uint32_t arm_timer_get_ctrl(void) { - ARM_ISB(); + UP_ISB(); return CP15_GET(CNTP_CTL); } static inline void arm_timer_set_ctrl(uint32_t ctrl) { CP15_SET(CNTP_CTL, ctrl); - ARM_ISB(); + UP_ISB(); } static inline uint32_t arm_timer_get_tval(void) { - ARM_ISB(); + UP_ISB(); return CP15_GET(CNTP_TVAL); } static inline void arm_timer_set_tval(uint32_t tval) { CP15_SET(CNTP_TVAL, tval); - ARM_ISB(); + UP_ISB(); } static inline uint64_t arm_timer_get_cval(void) { - ARM_ISB(); + UP_ISB(); return CP15_GET64(CNTP_CVAL); } static inline void arm_timer_set_cval(uint64_t cval) { CP15_SET64(CNTP_CVAL, cval); - ARM_ISB(); + UP_ISB(); } static inline uint64_t nsec_from_count(uint64_t count, uint32_t freq) @@ -288,7 +288,7 @@ static int arm_timer_interrupt(int irq, void *context, void *arg) uint32_t arm_timer_get_freq(void) { - ARM_ISB(); + UP_ISB(); return CP15_GET(CNTFRQ); } diff --git a/arch/arm/src/armv7-a/cp15_cacheops.c b/arch/arm/src/armv7-a/cp15_cacheops.c index 15ec27a2c8..09b0df1ff8 100644 --- a/arch/arm/src/armv7-a/cp15_cacheops.c +++ b/arch/arm/src/armv7-a/cp15_cacheops.c @@ -113,7 +113,7 @@ static void cp15_dcache_op_mva(uintptr_t start, uintptr_t end, int op) line = cp15_dcache_linesize(); - ARM_DSB(); + UP_DSB(); if ((start & (line - 1)) != 0) { @@ -152,7 +152,7 @@ static void cp15_dcache_op_mva(uintptr_t start, uintptr_t end, int op) start += line; } - ARM_ISB(); + UP_ISB(); } /**************************************************************************** @@ -181,7 +181,7 @@ void cp15_dcache_op_level(uint32_t level, int op) way_shift = 32 - ilog2(ways); set_shift = ilog2(line); - ARM_DSB(); + UP_DSB(); /* A: Log2(ways) * B: L+S @@ -220,7 +220,7 @@ void cp15_dcache_op_level(uint32_t level, int op) } } - ARM_ISB(); + UP_ISB(); } void cp15_invalidate_icache(uintptr_t start, uintptr_t end) @@ -230,7 +230,7 @@ void cp15_invalidate_icache(uintptr_t start, uintptr_t end) line = cp15_icache_linesize(); start &= ~(line - 1); - ARM_DSB(); + UP_DSB(); while (start < end) { @@ -238,7 +238,7 @@ void cp15_invalidate_icache(uintptr_t start, uintptr_t end) start += line; } - ARM_ISB(); + UP_ISB(); } void cp15_coherent_dcache(uintptr_t start, uintptr_t end) diff --git a/arch/arm/src/armv7-a/cp15_cacheops.h b/arch/arm/src/armv7-a/cp15_cacheops.h index d20f907476..6f9aaf5354 100644 --- a/arch/arm/src/armv7-a/cp15_cacheops.h +++ b/arch/arm/src/armv7-a/cp15_cacheops.h @@ -587,7 +587,7 @@ static inline void cp15_enable_dcache(void) sctlr = CP15_GET(SCTLR); sctlr |= SCTLR_C; CP15_SET(SCTLR, sctlr); - ARM_ISB(); + UP_ISB(); } /**************************************************************************** @@ -611,7 +611,7 @@ static inline void cp15_disable_dcache(void) sctlr = CP15_GET(SCTLR); sctlr &= ~SCTLR_C; CP15_SET(SCTLR, sctlr); - ARM_ISB(); + UP_ISB(); } /**************************************************************************** @@ -635,7 +635,7 @@ static inline void cp15_enable_icache(void) sctlr = CP15_GET(SCTLR); sctlr |= SCTLR_I; CP15_SET(SCTLR, sctlr); - ARM_ISB(); + UP_ISB(); } /**************************************************************************** @@ -659,7 +659,7 @@ static inline void cp15_disable_icache(void) sctlr = CP15_GET(SCTLR); sctlr &= ~SCTLR_I; CP15_SET(SCTLR, sctlr); - ARM_ISB(); + UP_ISB(); } /**************************************************************************** @@ -679,7 +679,7 @@ static inline void cp15_disable_icache(void) static inline void cp15_invalidate_icache_inner_sharable(void) { CP15_SET(ICIALLUIS, 0); - ARM_ISB(); + UP_ISB(); } /**************************************************************************** @@ -699,7 +699,7 @@ static inline void cp15_invalidate_icache_inner_sharable(void) static inline void cp15_invalidate_btb_inner_sharable(void) { CP15_SET(BPIALLIS, 0); - ARM_ISB(); + UP_ISB(); } /**************************************************************************** @@ -720,7 +720,7 @@ static inline void cp15_invalidate_btb_inner_sharable(void) static inline void cp15_invalidate_icache_all(void) { CP15_SET(ICIALLU, 0); - ARM_ISB(); + UP_ISB(); } /**************************************************************************** @@ -740,7 +740,7 @@ static inline void cp15_invalidate_icache_all(void) static inline void cp15_invalidate_icache_bymva(unsigned int va) { CP15_SET(ICIMVAU, va); - ARM_ISB(); + UP_ISB(); } /**************************************************************************** @@ -760,7 +760,7 @@ static inline void cp15_invalidate_icache_bymva(unsigned int va) static inline void cp15_flush_btb(void) { CP15_SET(BPIALL, 0); - ARM_ISB(); + UP_ISB(); } /**************************************************************************** @@ -780,7 +780,7 @@ static inline void cp15_flush_btb(void) static inline void cp15_flush_btb_bymva(unsigned int va) { CP15_SET(BPIMVA, va); - ARM_ISB(); + UP_ISB(); } /**************************************************************************** @@ -802,7 +802,7 @@ static inline void cp15_flush_btb_bymva(unsigned int va) static inline void cp15_invalidate_dcacheline_bymva(unsigned int va) { CP15_SET(DCIMVAC, va); - ARM_ISB(); + UP_ISB(); } /**************************************************************************** @@ -824,7 +824,7 @@ static inline void cp15_invalidate_dcacheline_bymva(unsigned int va) static inline void cp15_invalidate_dcacheline_bysetway(unsigned int setway) { CP15_SET(DCISW, setway); - ARM_ISB(); + UP_ISB(); } /**************************************************************************** @@ -846,7 +846,7 @@ static inline void cp15_invalidate_dcacheline_bysetway(unsigned int setway) static inline void cp15_clean_dcache_bymva(unsigned int va) { CP15_SET(DCCMVAC, va); - ARM_ISB(); + UP_ISB(); } /**************************************************************************** @@ -866,7 +866,7 @@ static inline void cp15_clean_dcache_bymva(unsigned int va) static inline void cp15_clean_dcache_bysetway(unsigned int setway) { CP15_SET(DCCSW, setway); - ARM_ISB(); + UP_ISB(); } /**************************************************************************** @@ -886,7 +886,7 @@ static inline void cp15_clean_dcache_bysetway(unsigned int setway) static inline void cp15_clean_ucache_bymva(unsigned int va) { CP15_SET(DCCMVAU, va); - ARM_ISB(); + UP_ISB(); } /**************************************************************************** @@ -906,7 +906,7 @@ static inline void cp15_clean_ucache_bymva(unsigned int va) static inline void cp15_cleaninvalidate_dcacheline_bymva(unsigned int va) { CP15_SET(DCCIMVAC, va); - ARM_ISB(); + UP_ISB(); } /**************************************************************************** @@ -926,7 +926,7 @@ static inline void cp15_cleaninvalidate_dcacheline_bymva(unsigned int va) static inline void cp15_cleaninvalidate_dcacheline(unsigned int setway) { CP15_SET(DCCISW, setway); - ARM_ISB(); + UP_ISB(); } #endif /* __ASSEMBLY__ */ diff --git a/arch/arm/src/armv7-a/mmu.h b/arch/arm/src/armv7-a/mmu.h index 46da0e2c21..e794bd7cd0 100644 --- a/arch/arm/src/armv7-a/mmu.h +++ b/arch/arm/src/armv7-a/mmu.h @@ -37,12 +37,12 @@ #include #include +#include #include "sctlr.h" #ifndef __ASSEMBLY__ # include # include "chip.h" -# include "barriers.h" #endif /* __ASSEMBLY__ */ /**************************************************************************** @@ -1250,7 +1250,7 @@ static inline void cp15_disable_mmu(void) static inline void cp15_invalidate_tlbs(void) { - ARM_DSB(); + UP_DSB(); #ifdef CONFIG_ARM_HAVE_MPCORE CP15_SET(TLBIALLIS, 0); CP15_SET(BPIALLIS, 0); @@ -1258,8 +1258,7 @@ static inline void cp15_invalidate_tlbs(void) CP15_SET2(TLBIALL, c7, 0); CP15_SET(BPIALL, 0); #endif - ARM_DSB(); - ARM_ISB(); + UP_MB(); } /**************************************************************************** @@ -1275,7 +1274,7 @@ static inline void cp15_invalidate_tlbs(void) static inline void cp15_invalidate_tlb_bymva(uint32_t vaddr) { - ARM_DSB(); + UP_DSB(); #ifdef CONFIG_ARM_HAVE_MPCORE CP15_SET(TLBIMVAAIS, vaddr); CP15_SET(BPIALLIS, 0); @@ -1283,8 +1282,7 @@ static inline void cp15_invalidate_tlb_bymva(uint32_t vaddr) CP15_SET2(TLBIMVA, c7, vaddr); CP15_SET(BPIALL, 0); #endif - ARM_DSB(); - ARM_ISB(); + UP_MB(); } /**************************************************************************** @@ -1301,14 +1299,14 @@ static inline void cp15_invalidate_tlb_bymva(uint32_t vaddr) static inline void cp15_wrdacr(unsigned int dacr) { CP15_SET(DACR, dacr); - ARM_NOP(); - ARM_NOP(); - ARM_NOP(); - ARM_NOP(); - ARM_NOP(); - ARM_NOP(); - ARM_NOP(); - ARM_NOP(); + UP_NOP(); + UP_NOP(); + UP_NOP(); + UP_NOP(); + UP_NOP(); + UP_NOP(); + UP_NOP(); + UP_NOP(); } /**************************************************************************** @@ -1329,14 +1327,14 @@ static inline void cp15_wrdacr(unsigned int dacr) static inline void cp15_wrttb(unsigned int ttb) { CP15_SET(TTBR0, ttb); - ARM_NOP(); - ARM_NOP(); - ARM_NOP(); - ARM_NOP(); - ARM_NOP(); - ARM_NOP(); - ARM_NOP(); - ARM_NOP(); + UP_NOP(); + UP_NOP(); + UP_NOP(); + UP_NOP(); + UP_NOP(); + UP_NOP(); + UP_NOP(); + UP_NOP(); CP15_SET(TTBCR, 0); } diff --git a/arch/arm/src/armv7-a/sctlr.h b/arch/arm/src/armv7-a/sctlr.h index b244c817fb..acf6b642ef 100644 --- a/arch/arm/src/armv7-a/sctlr.h +++ b/arch/arm/src/armv7-a/sctlr.h @@ -36,10 +36,9 @@ * Included Files ****************************************************************************/ +#include #include -#include "barriers.h" - /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ @@ -460,14 +459,14 @@ static inline unsigned int cp15_rdsctlr(void) static inline void cp15_wrsctlr(unsigned int sctlr) { CP15_SET(SCTLR, sctlr); - ARM_NOP(); - ARM_NOP(); - ARM_NOP(); - ARM_NOP(); - ARM_NOP(); - ARM_NOP(); - ARM_NOP(); - ARM_NOP(); + UP_NOP(); + UP_NOP(); + UP_NOP(); + UP_NOP(); + UP_NOP(); + UP_NOP(); + UP_NOP(); + UP_NOP(); } /* Read/write the vector base address register (VBAR) */ diff --git a/arch/arm/src/armv7-m/arm_cache.c b/arch/arm/src/armv7-m/arm_cache.c index 37d6e82a81..254ad0b9e9 100644 --- a/arch/arm/src/armv7-m/arm_cache.c +++ b/arch/arm/src/armv7-m/arm_cache.c @@ -42,9 +42,9 @@ #include #include +#include #include "arm_internal.h" -#include "barriers.h" #include "nvic.h" /**************************************************************************** @@ -268,8 +268,7 @@ void up_enable_icache(void) { uint32_t regval; - ARM_DSB(); - ARM_ISB(); + UP_MB(); /* Invalidate the entire I-Cache */ @@ -281,8 +280,7 @@ void up_enable_icache(void) regval |= NVIC_CFGCON_IC; putreg32(regval, NVIC_CFGCON); - ARM_DSB(); - ARM_ISB(); + UP_MB(); } #endif @@ -305,8 +303,7 @@ void up_disable_icache(void) { uint32_t regval; - ARM_DSB(); - ARM_ISB(); + UP_MB(); /* Disable the I-Cache */ @@ -318,8 +315,7 @@ void up_disable_icache(void) putreg32(0, NVIC_ICIALLU); - ARM_DSB(); - ARM_ISB(); + UP_MB(); } #endif @@ -350,7 +346,7 @@ void up_invalidate_icache(uintptr_t start, uintptr_t end) * (ssize - 1) = 0x007f : Mask of the set field */ - ARM_DSB(); + UP_DSB(); if ((start & (ssize - 1)) != 0) { @@ -380,8 +376,7 @@ void up_invalidate_icache(uintptr_t start, uintptr_t end) putreg32(start, NVIC_ICIMVAU); } - ARM_DSB(); - ARM_ISB(); + UP_MB(); } #endif /* CONFIG_ARMV7M_ICACHE */ @@ -402,15 +397,13 @@ void up_invalidate_icache(uintptr_t start, uintptr_t end) #ifdef CONFIG_ARMV7M_ICACHE void up_invalidate_icache_all(void) { - ARM_DSB(); - ARM_ISB(); + UP_MB(); /* Invalidate the entire I-Cache */ putreg32(0, NVIC_ICIALLU); - ARM_DSB(); - ARM_ISB(); + UP_MB(); } #endif @@ -523,7 +516,7 @@ void up_enable_dcache(void) /* Invalidate the entire D-Cache */ - ARM_DSB(); + UP_DSB(); do { int32_t tmpways = ways; @@ -537,7 +530,7 @@ void up_enable_dcache(void) } while (sets--); - ARM_DSB(); + UP_DSB(); #ifdef CONFIG_ARMV7M_DCACHE_WRITETHROUGH ccr = getreg32(NVIC_CACR); @@ -551,8 +544,7 @@ void up_enable_dcache(void) ccr |= NVIC_CFGCON_DC; putreg32(ccr, NVIC_CFGCON); - ARM_DSB(); - ARM_ISB(); + UP_MB(); } #endif /* CONFIG_ARMV7M_DCACHE */ @@ -601,7 +593,7 @@ void up_disable_dcache(void) wshift = arm_clz(ways) & 0x1f; - ARM_DSB(); + UP_DSB(); /* Disable the D-Cache */ @@ -624,8 +616,7 @@ void up_disable_dcache(void) } while (sets--); - ARM_DSB(); - ARM_ISB(); + UP_MB(); } #endif /* CONFIG_ARMV7M_DCACHE */ @@ -665,7 +656,7 @@ void up_invalidate_dcache(uintptr_t start, uintptr_t end) * (ssize - 1) = 0x007f : Mask of the set field */ - ARM_DSB(); + UP_DSB(); if ((start & (ssize - 1)) != 0) { @@ -695,8 +686,7 @@ void up_invalidate_dcache(uintptr_t start, uintptr_t end) putreg32(start, NVIC_DCCIMVAC); } - ARM_DSB(); - ARM_ISB(); + UP_MB(); } #endif /* CONFIG_ARMV7M_DCACHE */ @@ -744,7 +734,7 @@ void up_invalidate_dcache_all(void) wshift = arm_clz(ways) & 0x1f; - ARM_DSB(); + UP_DSB(); /* Invalidate the entire D-Cache */ @@ -761,8 +751,7 @@ void up_invalidate_dcache_all(void) } while (sets--); - ARM_DSB(); - ARM_ISB(); + UP_MB(); } #endif /* CONFIG_ARMV7M_DCACHE */ @@ -819,7 +808,7 @@ void up_clean_dcache(uintptr_t start, uintptr_t end) #endif start &= ~(ssize - 1); - ARM_DSB(); + UP_DSB(); do { @@ -839,8 +828,7 @@ void up_clean_dcache(uintptr_t start, uintptr_t end) while (start < end); #endif /* !CONFIG_ARMV7M_DCACHE_WRITETHROUGH */ - ARM_DSB(); - ARM_ISB(); + UP_MB(); } #endif /* CONFIG_ARMV7M_DCACHE */ @@ -898,7 +886,7 @@ void up_clean_dcache_all(void) wshift = arm_clz(ways) & 0x1f; - ARM_DSB(); + UP_DSB(); /* Clean the entire D-Cache */ @@ -916,8 +904,7 @@ void up_clean_dcache_all(void) while (sets--); #endif /* !CONFIG_ARMV7M_DCACHE_WRITETHROUGH */ - ARM_DSB(); - ARM_ISB(); + UP_MB(); } #endif /* CONFIG_ARMV7M_DCACHE */ @@ -974,7 +961,7 @@ void up_flush_dcache(uintptr_t start, uintptr_t end) #endif start &= ~(ssize - 1); - ARM_DSB(); + UP_DSB(); do { @@ -993,8 +980,7 @@ void up_flush_dcache(uintptr_t start, uintptr_t end) } while (start < end); - ARM_DSB(); - ARM_ISB(); + UP_MB(); #else up_invalidate_dcache(start, end); #endif /* !CONFIG_ARMV7M_DCACHE_WRITETHROUGH */ @@ -1054,7 +1040,7 @@ void up_flush_dcache_all(void) wshift = arm_clz(ways) & 0x1f; - ARM_DSB(); + UP_DSB(); /* Clean and invalidate the entire D-Cache */ @@ -1071,8 +1057,7 @@ void up_flush_dcache_all(void) } while (sets--); - ARM_DSB(); - ARM_ISB(); + UP_MB(); #else up_invalidate_dcache_all(); #endif /* !CONFIG_ARMV7M_DCACHE_WRITETHROUGH */ diff --git a/arch/arm/src/armv7-m/arm_mpu.c b/arch/arm/src/armv7-m/arm_mpu.c index 85eec2e3c6..1d3646cd2c 100644 --- a/arch/arm/src/armv7-m/arm_mpu.c +++ b/arch/arm/src/armv7-m/arm_mpu.c @@ -30,9 +30,10 @@ #include #include +#include + #include "mpu.h" #include "arm_internal.h" -#include "barriers.h" /**************************************************************************** * Pre-processor Definitions @@ -226,8 +227,7 @@ static void mpu_reset_internal(void) putreg32(0, MPU_CTRL); - ARM_DSB(); - ARM_ISB(); + UP_MB(); } #endif @@ -284,8 +284,7 @@ void mpu_freeregion(unsigned int region) putreg32(0, MPU_RASR); putreg32(0, MPU_RBAR); g_mpu_region &= ~(1 << region); - ARM_DSB(); - ARM_ISB(); + UP_MB(); } /**************************************************************************** @@ -450,8 +449,7 @@ void mpu_control(bool enable, bool hfnmiena, bool privdefena) /* Ensure MPU setting take effects */ - ARM_DSB(); - ARM_ISB(); + UP_MB(); } /**************************************************************************** @@ -524,8 +522,7 @@ void mpu_modify_region(unsigned int region, uintptr_t base, size_t size, /* Ensure MPU setting take effects */ - ARM_DSB(); - ARM_ISB(); + UP_MB(); } /**************************************************************************** diff --git a/arch/arm/src/armv7-r/arm_cache.c b/arch/arm/src/armv7-r/arm_cache.c index c6dfade230..70304ecac2 100644 --- a/arch/arm/src/armv7-r/arm_cache.c +++ b/arch/arm/src/armv7-r/arm_cache.c @@ -28,9 +28,9 @@ #include #include #include +#include #include "cp15_cacheops.h" -#include "barriers.h" #include "l2cc.h" /**************************************************************************** diff --git a/arch/arm/src/armv7-r/arm_l2cc_pl310.c b/arch/arm/src/armv7-r/arm_l2cc_pl310.c index 33164ce526..a2c60e8332 100644 --- a/arch/arm/src/armv7-r/arm_l2cc_pl310.c +++ b/arch/arm/src/armv7-r/arm_l2cc_pl310.c @@ -39,9 +39,9 @@ #include #include +#include #include "arm_internal.h" -#include "barriers.h" #include "l2cc.h" #include "l2cc_pl310.h" @@ -292,8 +292,7 @@ static void l2cc_disable_nolock(void) /* Disable the L2CC-P310 L2 cache by clearing the Control Register (CR) */ putreg32(0, L2CC_CR); - ARM_DSB(); - ARM_ISB(); + UP_MB(); } /**************************************************************************** @@ -457,8 +456,7 @@ void arm_l2ccinitialize(void) l2cc_invalidate_all(); putreg32(L2CC_CR_L2CEN, L2CC_CR); - ARM_DSB(); - ARM_ISB(); + UP_MB(); } sinfo("(%d ways) * (%d bytes/way) = %d bytes\n", @@ -533,8 +531,7 @@ void l2cc_enable(void) l2cc_invalidate_all_nolock(); putreg32(L2CC_CR_L2CEN, L2CC_CR); - ARM_DSB(); - ARM_ISB(); + UP_MB(); spin_unlock_irqrestore(&g_l2cc_lock, flags); } diff --git a/arch/arm/src/armv7-r/arm_mpu.c b/arch/arm/src/armv7-r/arm_mpu.c index 2adb097f1c..cb5570a1bf 100644 --- a/arch/arm/src/armv7-r/arm_mpu.c +++ b/arch/arm/src/armv7-r/arm_mpu.c @@ -281,8 +281,7 @@ void mpu_freeregion(unsigned int region) mpu_set_dracr(0); mpu_set_drsr(0); g_mpu_region &= ~(1 << region); - ARM_DSB(); - ARM_ISB(); + UP_MB(); } /**************************************************************************** diff --git a/arch/arm/src/armv7-r/arm_scu.c b/arch/arm/src/armv7-r/arm_scu.c index 75913b445a..41c0a5aa4b 100644 --- a/arch/arm/src/armv7-r/arm_scu.c +++ b/arch/arm/src/armv7-r/arm_scu.c @@ -28,12 +28,12 @@ #include +#include #include #include #include "arm_internal.h" #include "cp15_cacheops.h" -#include "barriers.h" #include "sctlr.h" #include "scu.h" @@ -85,7 +85,7 @@ void arm_enable_smp(int cpu) */ cp15_invalidate_dcache_all(); - ARM_DSB(); + UP_DSB(); /* Invalidate the L2C-310 -- Missing logic. */ @@ -97,7 +97,7 @@ void arm_enable_smp(int cpu) /* Initialize done, kick other cpus which waiting on __start */ - ARM_SEV(); + UP_SEV(); } /* Actions for other CPUs */ @@ -109,7 +109,7 @@ void arm_enable_smp(int cpu) */ cp15_dcache_op_level(0, CP15_CACHE_INVALIDATE); - ARM_DSB(); + UP_DSB(); /* Wait for the SCU to be enabled by the primary processor -- should * not be necessary. diff --git a/arch/arm/src/armv7-r/arm_timer.c b/arch/arm/src/armv7-r/arm_timer.c index 449a245aac..2e69426cfa 100644 --- a/arch/arm/src/armv7-r/arm_timer.c +++ b/arch/arm/src/armv7-r/arm_timer.c @@ -28,9 +28,9 @@ #include #include #include +#include #include "arm_timer.h" -#include "barriers.h" #include "gic.h" /**************************************************************************** @@ -96,49 +96,49 @@ static const struct oneshot_operations_s g_arm_timer_ops = static inline void arm_timer_set_freq(uint32_t freq) { CP15_SET(CNTFRQ, freq); - ARM_ISB(); + UP_ISB(); } static inline uint64_t arm_timer_get_count(void) { - ARM_ISB(); + UP_ISB(); return CP15_GET64(CNTPCT); } static inline uint32_t arm_timer_get_ctrl(void) { - ARM_ISB(); + UP_ISB(); return CP15_GET(CNTP_CTL); } static inline void arm_timer_set_ctrl(uint32_t ctrl) { CP15_SET(CNTP_CTL, ctrl); - ARM_ISB(); + UP_ISB(); } static inline uint32_t arm_timer_get_tval(void) { - ARM_ISB(); + UP_ISB(); return CP15_GET(CNTP_TVAL); } static inline void arm_timer_set_tval(uint32_t tval) { CP15_SET(CNTP_TVAL, tval); - ARM_ISB(); + UP_ISB(); } static inline uint64_t arm_timer_get_cval(void) { - ARM_ISB(); + UP_ISB(); return CP15_GET64(CNTP_CVAL); } static inline void arm_timer_set_cval(uint64_t cval) { CP15_SET64(CNTP_CVAL, cval); - ARM_ISB(); + UP_ISB(); } static inline uint64_t nsec_from_count(uint64_t count, uint32_t freq) @@ -286,7 +286,7 @@ static int arm_timer_interrupt(int irq, void *context, void *arg) uint32_t arm_timer_get_freq(void) { - ARM_ISB(); + UP_ISB(); return CP15_GET(CNTFRQ); } diff --git a/arch/arm/src/armv7-r/cp15_cacheops.c b/arch/arm/src/armv7-r/cp15_cacheops.c index 7f347c8150..f7c8f33730 100644 --- a/arch/arm/src/armv7-r/cp15_cacheops.c +++ b/arch/arm/src/armv7-r/cp15_cacheops.c @@ -113,7 +113,7 @@ static void cp15_dcache_op_mva(uintptr_t start, uintptr_t end, int op) line = cp15_dcache_linesize(); - ARM_DSB(); + UP_DSB(); if ((start & (line - 1)) != 0) { @@ -152,7 +152,7 @@ static void cp15_dcache_op_mva(uintptr_t start, uintptr_t end, int op) start += line; } - ARM_ISB(); + UP_ISB(); } /**************************************************************************** @@ -181,7 +181,7 @@ void cp15_dcache_op_level(uint32_t level, int op) way_shift = 32 - ilog2(ways); set_shift = ilog2(line); - ARM_DSB(); + UP_DSB(); /* A: Log2(ways) * B: L+S @@ -220,7 +220,7 @@ void cp15_dcache_op_level(uint32_t level, int op) } } - ARM_ISB(); + UP_ISB(); } void cp15_invalidate_icache(uintptr_t start, uintptr_t end) @@ -230,7 +230,7 @@ void cp15_invalidate_icache(uintptr_t start, uintptr_t end) line = cp15_icache_linesize(); start &= ~(line - 1); - ARM_DSB(); + UP_DSB(); while (start < end) { @@ -238,7 +238,7 @@ void cp15_invalidate_icache(uintptr_t start, uintptr_t end) start += line; } - ARM_ISB(); + UP_ISB(); } void cp15_coherent_dcache(uintptr_t start, uintptr_t end) diff --git a/arch/arm/src/armv7-r/cp15_cacheops.h b/arch/arm/src/armv7-r/cp15_cacheops.h index 81e7ebe91d..3c8b1f4fef 100644 --- a/arch/arm/src/armv7-r/cp15_cacheops.h +++ b/arch/arm/src/armv7-r/cp15_cacheops.h @@ -594,7 +594,7 @@ static inline void cp15_enable_dcache(void) sctlr = CP15_GET(SCTLR); sctlr |= SCTLR_C; CP15_SET(SCTLR, sctlr); - ARM_ISB(); + UP_ISB(); } /**************************************************************************** @@ -618,7 +618,7 @@ static inline void cp15_disable_dcache(void) sctlr = CP15_GET(SCTLR); sctlr &= ~SCTLR_C; CP15_SET(SCTLR, sctlr); - ARM_ISB(); + UP_ISB(); } /**************************************************************************** @@ -642,7 +642,7 @@ static inline void cp15_enable_icache(void) sctlr = CP15_GET(SCTLR); sctlr |= SCTLR_I; CP15_SET(SCTLR, sctlr); - ARM_ISB(); + UP_ISB(); } /**************************************************************************** @@ -666,7 +666,7 @@ static inline void cp15_disable_icache(void) sctlr = CP15_GET(SCTLR); sctlr &= ~SCTLR_I; CP15_SET(SCTLR, sctlr); - ARM_ISB(); + UP_ISB(); } /**************************************************************************** @@ -686,7 +686,7 @@ static inline void cp15_disable_icache(void) static inline void cp15_invalidate_icache_inner_sharable(void) { CP15_SET(ICIALLUIS, 0); - ARM_ISB(); + UP_ISB(); } /**************************************************************************** @@ -706,7 +706,7 @@ static inline void cp15_invalidate_icache_inner_sharable(void) static inline void cp15_invalidate_btb_inner_sharable(void) { CP15_SET(BPIALLIS, 0); - ARM_ISB(); + UP_ISB(); } /**************************************************************************** @@ -727,7 +727,7 @@ static inline void cp15_invalidate_btb_inner_sharable(void) static inline void cp15_invalidate_icache_all(void) { CP15_SET(ICIALLU, 0); - ARM_ISB(); + UP_ISB(); } /**************************************************************************** @@ -747,7 +747,7 @@ static inline void cp15_invalidate_icache_all(void) static inline void cp15_invalidate_icache_bymva(unsigned int va) { CP15_SET(ICIMVAU, va); - ARM_ISB(); + UP_ISB(); } /**************************************************************************** @@ -767,7 +767,7 @@ static inline void cp15_invalidate_icache_bymva(unsigned int va) static inline void cp15_flush_btb(void) { CP15_SET(BPIALL, 0); - ARM_ISB(); + UP_ISB(); } /**************************************************************************** @@ -787,7 +787,7 @@ static inline void cp15_flush_btb(void) static inline void cp15_flush_btb_bymva(unsigned int va) { CP15_SET(BPIMVA, va); - ARM_ISB(); + UP_ISB(); } /**************************************************************************** @@ -809,7 +809,7 @@ static inline void cp15_flush_btb_bymva(unsigned int va) static inline void cp15_invalidate_dcacheline_bymva(unsigned int va) { CP15_SET(DCIMVAC, va); - ARM_ISB(); + UP_ISB(); } /**************************************************************************** @@ -831,7 +831,7 @@ static inline void cp15_invalidate_dcacheline_bymva(unsigned int va) static inline void cp15_invalidate_dcacheline_bysetway(unsigned int setway) { CP15_SET(DCISW, setway); - ARM_ISB(); + UP_ISB(); } /**************************************************************************** @@ -853,7 +853,7 @@ static inline void cp15_invalidate_dcacheline_bysetway(unsigned int setway) static inline void cp15_clean_dcache_bymva(unsigned int va) { CP15_SET(DCCMVAC, va); - ARM_ISB(); + UP_ISB(); } /**************************************************************************** @@ -873,7 +873,7 @@ static inline void cp15_clean_dcache_bymva(unsigned int va) static inline void cp15_clean_dcache_bysetway(unsigned int setway) { CP15_SET(DCCSW, setway); - ARM_ISB(); + UP_ISB(); } /**************************************************************************** @@ -893,7 +893,7 @@ static inline void cp15_clean_dcache_bysetway(unsigned int setway) static inline void cp15_clean_ucache_bymva(unsigned int va) { CP15_SET(DCCMVAU, va); - ARM_ISB(); + UP_ISB(); } /**************************************************************************** @@ -913,7 +913,7 @@ static inline void cp15_clean_ucache_bymva(unsigned int va) static inline void cp15_cleaninvalidate_dcacheline_bymva(unsigned int va) { CP15_SET(DCCIMVAC, va); - ARM_ISB(); + UP_ISB(); } /**************************************************************************** @@ -933,7 +933,7 @@ static inline void cp15_cleaninvalidate_dcacheline_bymva(unsigned int va) static inline void cp15_cleaninvalidate_dcacheline(unsigned int setway) { CP15_SET(DCCISW, setway); - ARM_ISB(); + UP_ISB(); } #endif /* __ASSEMBLY__ */ diff --git a/arch/arm/src/armv7-r/sctlr.h b/arch/arm/src/armv7-r/sctlr.h index 331d9375f7..11077e7ce0 100644 --- a/arch/arm/src/armv7-r/sctlr.h +++ b/arch/arm/src/armv7-r/sctlr.h @@ -34,10 +34,9 @@ * Included Files ****************************************************************************/ +#include #include -#include "barriers.h" - /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ @@ -524,14 +523,14 @@ static inline unsigned int cp15_rdsctlr(void) static inline void cp15_wrsctlr(unsigned int sctlr) { CP15_SET(SCTLR, sctlr); - ARM_NOP(); - ARM_NOP(); - ARM_NOP(); - ARM_NOP(); - ARM_NOP(); - ARM_NOP(); - ARM_NOP(); - ARM_NOP(); + UP_NOP(); + UP_NOP(); + UP_NOP(); + UP_NOP(); + UP_NOP(); + UP_NOP(); + UP_NOP(); + UP_NOP(); } /* Read/write the vector base address register (VBAR) */ diff --git a/arch/arm/src/armv8-m/arm_cache.c b/arch/arm/src/armv8-m/arm_cache.c index f3f07c4b59..c5229d65aa 100644 --- a/arch/arm/src/armv8-m/arm_cache.c +++ b/arch/arm/src/armv8-m/arm_cache.c @@ -42,9 +42,9 @@ #include #include +#include #include "arm_internal.h" -#include "barriers.h" #include "nvic.h" /**************************************************************************** @@ -268,8 +268,7 @@ void up_enable_icache(void) { uint32_t regval; - ARM_DSB(); - ARM_ISB(); + UP_MB(); /* Invalidate the entire I-Cache */ @@ -281,8 +280,7 @@ void up_enable_icache(void) regval |= NVIC_CFGCON_IC; putreg32(regval, NVIC_CFGCON); - ARM_DSB(); - ARM_ISB(); + UP_MB(); } #endif @@ -305,8 +303,7 @@ void up_disable_icache(void) { uint32_t regval; - ARM_DSB(); - ARM_ISB(); + UP_MB(); /* Disable the I-Cache */ @@ -318,8 +315,7 @@ void up_disable_icache(void) putreg32(0, NVIC_ICIALLU); - ARM_DSB(); - ARM_ISB(); + UP_MB(); } #endif @@ -350,7 +346,7 @@ void up_invalidate_icache(uintptr_t start, uintptr_t end) * (ssize - 1) = 0x007f : Mask of the set field */ - ARM_DSB(); + UP_DSB(); if ((start & (ssize - 1)) != 0) { @@ -380,8 +376,7 @@ void up_invalidate_icache(uintptr_t start, uintptr_t end) putreg32(start, NVIC_ICIMVAU); } - ARM_DSB(); - ARM_ISB(); + UP_MB(); } #endif /* CONFIG_ARMV8M_ICACHE */ @@ -402,15 +397,13 @@ void up_invalidate_icache(uintptr_t start, uintptr_t end) #ifdef CONFIG_ARMV8M_ICACHE void up_invalidate_icache_all(void) { - ARM_DSB(); - ARM_ISB(); + UP_MB(); /* Invalidate the entire I-Cache */ putreg32(0, NVIC_ICIALLU); - ARM_DSB(); - ARM_ISB(); + UP_MB(); } #endif @@ -523,7 +516,7 @@ void up_enable_dcache(void) /* Invalidate the entire D-Cache */ - ARM_DSB(); + UP_DSB(); do { int32_t tmpways = ways; @@ -537,7 +530,7 @@ void up_enable_dcache(void) } while (sets--); - ARM_DSB(); + UP_DSB(); #ifdef CONFIG_ARMV8M_DCACHE_WRITETHROUGH ccr = getreg32(NVIC_CACR); @@ -551,8 +544,7 @@ void up_enable_dcache(void) ccr |= NVIC_CFGCON_DC; putreg32(ccr, NVIC_CFGCON); - ARM_DSB(); - ARM_ISB(); + UP_MB(); } #endif /* CONFIG_ARMV8M_DCACHE */ @@ -601,7 +593,7 @@ void up_disable_dcache(void) wshift = arm_clz(ways) & 0x1f; - ARM_DSB(); + UP_DSB(); /* Disable the D-Cache */ @@ -624,8 +616,7 @@ void up_disable_dcache(void) } while (sets--); - ARM_DSB(); - ARM_ISB(); + UP_MB(); } #endif /* CONFIG_ARMV8M_DCACHE */ @@ -665,7 +656,7 @@ void up_invalidate_dcache(uintptr_t start, uintptr_t end) * (ssize - 1) = 0x007f : Mask of the set field */ - ARM_DSB(); + UP_DSB(); if ((start & (ssize - 1)) != 0) { @@ -695,8 +686,7 @@ void up_invalidate_dcache(uintptr_t start, uintptr_t end) putreg32(start, NVIC_DCCIMVAC); } - ARM_DSB(); - ARM_ISB(); + UP_MB(); } #endif /* CONFIG_ARMV8M_DCACHE */ @@ -744,7 +734,7 @@ void up_invalidate_dcache_all(void) wshift = arm_clz(ways) & 0x1f; - ARM_DSB(); + UP_DSB(); /* Invalidate the entire D-Cache */ @@ -761,8 +751,7 @@ void up_invalidate_dcache_all(void) } while (sets--); - ARM_DSB(); - ARM_ISB(); + UP_MB(); } #endif /* CONFIG_ARMV8M_DCACHE */ @@ -819,7 +808,7 @@ void up_clean_dcache(uintptr_t start, uintptr_t end) #endif start &= ~(ssize - 1); - ARM_DSB(); + UP_DSB(); do { @@ -839,8 +828,7 @@ void up_clean_dcache(uintptr_t start, uintptr_t end) while (start < end); #endif /* !CONFIG_ARMV8M_DCACHE_WRITETHROUGH */ - ARM_DSB(); - ARM_ISB(); + UP_MB(); } #endif /* CONFIG_ARMV8M_DCACHE */ @@ -898,7 +886,7 @@ void up_clean_dcache_all(void) wshift = arm_clz(ways) & 0x1f; - ARM_DSB(); + UP_DSB(); /* Clean the entire D-Cache */ @@ -916,8 +904,7 @@ void up_clean_dcache_all(void) while (sets--); #endif /* !CONFIG_ARMV8M_DCACHE_WRITETHROUGH */ - ARM_DSB(); - ARM_ISB(); + UP_MB(); } #endif /* CONFIG_ARMV8M_DCACHE */ @@ -974,7 +961,7 @@ void up_flush_dcache(uintptr_t start, uintptr_t end) #endif start &= ~(ssize - 1); - ARM_DSB(); + UP_DSB(); do { @@ -993,8 +980,7 @@ void up_flush_dcache(uintptr_t start, uintptr_t end) } while (start < end); - ARM_DSB(); - ARM_ISB(); + UP_MB(); #else up_invalidate_dcache(start, end); #endif /* !CONFIG_ARMV8M_DCACHE_WRITETHROUGH */ @@ -1054,7 +1040,7 @@ void up_flush_dcache_all(void) wshift = arm_clz(ways) & 0x1f; - ARM_DSB(); + UP_DSB(); /* Clean and invalidate the entire D-Cache */ @@ -1071,8 +1057,7 @@ void up_flush_dcache_all(void) } while (sets--); - ARM_DSB(); - ARM_ISB(); + UP_MB(); #else up_invalidate_dcache_all(); #endif /* !CONFIG_ARMV8M_DCACHE_WRITETHROUGH */ diff --git a/arch/arm/src/armv8-m/arm_mpu.c b/arch/arm/src/armv8-m/arm_mpu.c index 60d6236fd8..3473f3e4cb 100644 --- a/arch/arm/src/armv8-m/arm_mpu.c +++ b/arch/arm/src/armv8-m/arm_mpu.c @@ -30,10 +30,10 @@ #include #include #include +#include #include "mpu.h" #include "arm_internal.h" -#include "barriers.h" /**************************************************************************** * Pre-processor Definitions @@ -88,8 +88,7 @@ static void mpu_reset_internal(void) putreg32(0, MPU_CTRL); - ARM_DSB(); - ARM_ISB(); + UP_MB(); } #endif @@ -146,8 +145,7 @@ void mpu_freeregion(unsigned int region) putreg32(0, MPU_RLAR); putreg32(0, MPU_RBAR); g_mpu_region &= ~(1 << region); - ARM_DSB(); - ARM_ISB(); + UP_MB(); } /**************************************************************************** @@ -200,8 +198,7 @@ void mpu_control(bool enable, bool hfnmiena, bool privdefena) /* Ensure MPU setting take effects */ - ARM_DSB(); - ARM_ISB(); + UP_MB(); } /**************************************************************************** @@ -254,8 +251,7 @@ void mpu_modify_region(unsigned int region, uintptr_t base, size_t size, /* Ensure MPU setting take effects */ - ARM_DSB(); - ARM_ISB(); + UP_MB(); } /**************************************************************************** diff --git a/arch/arm/src/armv8-r/arm_arch_timer.c b/arch/arm/src/armv8-r/arm_arch_timer.c index 736401cad9..6ec70af674 100644 --- a/arch/arm/src/armv8-r/arm_arch_timer.c +++ b/arch/arm/src/armv8-r/arm_arch_timer.c @@ -30,12 +30,12 @@ #include #include +#include #include #include #include #include -#include "barriers.h" #include "arm_gic.h" #include "arm_arch_timer.h" diff --git a/arch/arm/src/armv8-r/arm_cache.c b/arch/arm/src/armv8-r/arm_cache.c index 0825fbe6db..2f1c9b4bfe 100644 --- a/arch/arm/src/armv8-r/arm_cache.c +++ b/arch/arm/src/armv8-r/arm_cache.c @@ -28,9 +28,9 @@ #include #include #include +#include #include "cp15_cacheops.h" -#include "barriers.h" #include "l2cc.h" /**************************************************************************** diff --git a/arch/arm/src/armv8-r/arm_gicv3.c b/arch/arm/src/armv8-r/arm_gicv3.c index 192f31a1f6..b6fd63861e 100644 --- a/arch/arm/src/armv8-r/arm_gicv3.c +++ b/arch/arm/src/armv8-r/arm_gicv3.c @@ -29,12 +29,12 @@ #include #include +#include #include #include #include #include "arm_internal.h" -#include "barriers.h" #include "arm_gic.h" /*************************************************************************** @@ -333,7 +333,7 @@ static void arm_gic_eoi_group0(unsigned int intid) * DEVICE nGnRnE attribute. */ - ARM_DSB(); + UP_DSB(); /* (AP -> Pending) Or (Active -> Inactive) or (AP to AP) nested case * Write a Group 0 interrupt completion @@ -367,7 +367,7 @@ void arm_gic_eoi(unsigned int intid) * DEVICE nGnRnE attribute. */ - ARM_DSB(); + UP_DSB(); /* (AP -> Pending) Or (Active -> Inactive) or (AP to AP) nested case */ @@ -393,9 +393,9 @@ static int arm_gic_send_sgi(unsigned int sgi_id, uint64_t target_aff, sgi_val = GICV3_SGIR_VALUE(aff3, aff2, aff1, sgi_id, SGIR_IRM_TO_AFF, target_list); - ARM_DSB(); + UP_DSB(); CP15_SET64(ICC_SGI1R, sgi_val); - ARM_ISB(); + UP_ISB(); return 0; } diff --git a/arch/arm/src/armv8-r/arm_l2cc_pl310.c b/arch/arm/src/armv8-r/arm_l2cc_pl310.c index 5ed37c9401..96f0b9b531 100644 --- a/arch/arm/src/armv8-r/arm_l2cc_pl310.c +++ b/arch/arm/src/armv8-r/arm_l2cc_pl310.c @@ -39,9 +39,9 @@ #include #include +#include #include "arm_internal.h" -#include "barriers.h" #include "l2cc.h" #include "l2cc_pl310.h" @@ -292,8 +292,7 @@ static void l2cc_disable_nolock(void) /* Disable the L2CC-P310 L2 cache by clearing the Control Register (CR) */ putreg32(0, L2CC_CR); - ARM_DSB(); - ARM_ISB(); + UP_MB(); } /**************************************************************************** @@ -457,8 +456,7 @@ void arm_l2ccinitialize(void) l2cc_invalidate_all(); putreg32(L2CC_CR_L2CEN, L2CC_CR); - ARM_DSB(); - ARM_ISB(); + UP_MB(); } sinfo("(%d ways) * (%d bytes/way) = %d bytes\n", @@ -533,8 +531,7 @@ void l2cc_enable(void) l2cc_invalidate_all_nolock(); putreg32(L2CC_CR_L2CEN, L2CC_CR); - ARM_DSB(); - ARM_ISB(); + UP_MB(); spin_unlock_irqrestore(&g_l2cc_lock, flags); } diff --git a/arch/arm/src/armv8-r/cp15_cacheops.c b/arch/arm/src/armv8-r/cp15_cacheops.c index efd217263b..32a1d91417 100644 --- a/arch/arm/src/armv8-r/cp15_cacheops.c +++ b/arch/arm/src/armv8-r/cp15_cacheops.c @@ -113,7 +113,7 @@ static void cp15_dcache_op_mva(uintptr_t start, uintptr_t end, int op) line = cp15_dcache_linesize(); - ARM_DSB(); + UP_DSB(); if ((start & (line - 1)) != 0) { @@ -152,7 +152,7 @@ static void cp15_dcache_op_mva(uintptr_t start, uintptr_t end, int op) start += line; } - ARM_ISB(); + UP_ISB(); } /**************************************************************************** @@ -181,7 +181,7 @@ void cp15_dcache_op_level(uint32_t level, int op) way_shift = 32 - ilog2(ways); set_shift = ilog2(line); - ARM_DSB(); + UP_DSB(); /* A: Log2(ways) * B: L+S @@ -220,7 +220,7 @@ void cp15_dcache_op_level(uint32_t level, int op) } } - ARM_ISB(); + UP_ISB(); } void cp15_invalidate_icache(uintptr_t start, uintptr_t end) @@ -230,7 +230,7 @@ void cp15_invalidate_icache(uintptr_t start, uintptr_t end) line = cp15_icache_linesize(); start &= ~(line - 1); - ARM_DSB(); + UP_DSB(); while (start < end) { @@ -238,7 +238,7 @@ void cp15_invalidate_icache(uintptr_t start, uintptr_t end) start += line; } - ARM_ISB(); + UP_ISB(); } void cp15_coherent_dcache(uintptr_t start, uintptr_t end) diff --git a/arch/arm/src/armv8-r/cp15_cacheops.h b/arch/arm/src/armv8-r/cp15_cacheops.h index 5e4f6fd8c2..cadd8f8590 100644 --- a/arch/arm/src/armv8-r/cp15_cacheops.h +++ b/arch/arm/src/armv8-r/cp15_cacheops.h @@ -594,7 +594,7 @@ static inline void cp15_enable_dcache(void) sctlr = CP15_GET(SCTLR); sctlr |= SCTLR_C; CP15_SET(SCTLR, sctlr); - ARM_ISB(); + UP_ISB(); } /**************************************************************************** @@ -618,7 +618,7 @@ static inline void cp15_disable_dcache(void) sctlr = CP15_GET(SCTLR); sctlr &= ~SCTLR_C; CP15_SET(SCTLR, sctlr); - ARM_ISB(); + UP_ISB(); } /**************************************************************************** @@ -642,7 +642,7 @@ static inline void cp15_enable_icache(void) sctlr = CP15_GET(SCTLR); sctlr |= SCTLR_I; CP15_SET(SCTLR, sctlr); - ARM_ISB(); + UP_ISB(); } /**************************************************************************** @@ -666,7 +666,7 @@ static inline void cp15_disable_icache(void) sctlr = CP15_GET(SCTLR); sctlr &= ~SCTLR_I; CP15_SET(SCTLR, sctlr); - ARM_ISB(); + UP_ISB(); } /**************************************************************************** @@ -686,7 +686,7 @@ static inline void cp15_disable_icache(void) static inline void cp15_invalidate_icache_inner_sharable(void) { CP15_SET(ICIALLUIS, 0); - ARM_ISB(); + UP_ISB(); } /**************************************************************************** @@ -706,7 +706,7 @@ static inline void cp15_invalidate_icache_inner_sharable(void) static inline void cp15_invalidate_btb_inner_sharable(void) { CP15_SET(BPIALLIS, 0); - ARM_ISB(); + UP_ISB(); } /**************************************************************************** @@ -727,7 +727,7 @@ static inline void cp15_invalidate_btb_inner_sharable(void) static inline void cp15_invalidate_icache_all(void) { CP15_SET(ICIALLU, 0); - ARM_ISB(); + UP_ISB(); } /**************************************************************************** @@ -747,7 +747,7 @@ static inline void cp15_invalidate_icache_all(void) static inline void cp15_invalidate_icache_bymva(unsigned int va) { CP15_SET(ICIMVAU, va); - ARM_ISB(); + UP_ISB(); } /**************************************************************************** @@ -767,7 +767,7 @@ static inline void cp15_invalidate_icache_bymva(unsigned int va) static inline void cp15_flush_btb(void) { CP15_SET(BPIALL, 0); - ARM_ISB(); + UP_ISB(); } /**************************************************************************** @@ -787,7 +787,7 @@ static inline void cp15_flush_btb(void) static inline void cp15_flush_btb_bymva(unsigned int va) { CP15_SET(BPIMVA, va); - ARM_ISB(); + UP_ISB(); } /**************************************************************************** @@ -809,7 +809,7 @@ static inline void cp15_flush_btb_bymva(unsigned int va) static inline void cp15_invalidate_dcacheline_bymva(unsigned int va) { CP15_SET(DCIMVAC, va); - ARM_ISB(); + UP_ISB(); } /**************************************************************************** @@ -831,7 +831,7 @@ static inline void cp15_invalidate_dcacheline_bymva(unsigned int va) static inline void cp15_invalidate_dcacheline_bysetway(unsigned int setway) { CP15_SET(DCISW, setway); - ARM_ISB(); + UP_ISB(); } /**************************************************************************** @@ -853,7 +853,7 @@ static inline void cp15_invalidate_dcacheline_bysetway(unsigned int setway) static inline void cp15_clean_dcache_bymva(unsigned int va) { CP15_SET(DCCMVAC, va); - ARM_ISB(); + UP_ISB(); } /**************************************************************************** @@ -873,7 +873,7 @@ static inline void cp15_clean_dcache_bymva(unsigned int va) static inline void cp15_clean_dcache_bysetway(unsigned int setway) { CP15_SET(DCCSW, setway); - ARM_ISB(); + UP_ISB(); } /**************************************************************************** @@ -893,7 +893,7 @@ static inline void cp15_clean_dcache_bysetway(unsigned int setway) static inline void cp15_clean_ucache_bymva(unsigned int va) { CP15_SET(DCCMVAU, va); - ARM_ISB(); + UP_ISB(); } /**************************************************************************** @@ -913,7 +913,7 @@ static inline void cp15_clean_ucache_bymva(unsigned int va) static inline void cp15_cleaninvalidate_dcacheline_bymva(unsigned int va) { CP15_SET(DCCIMVAC, va); - ARM_ISB(); + UP_ISB(); } /**************************************************************************** @@ -933,7 +933,7 @@ static inline void cp15_cleaninvalidate_dcacheline_bymva(unsigned int va) static inline void cp15_cleaninvalidate_dcacheline(unsigned int setway) { CP15_SET(DCCISW, setway); - ARM_ISB(); + UP_ISB(); } #endif /* __ASSEMBLY__ */ diff --git a/arch/arm/src/armv8-r/sctlr.h b/arch/arm/src/armv8-r/sctlr.h index 775b6faf70..36a3239e7e 100644 --- a/arch/arm/src/armv8-r/sctlr.h +++ b/arch/arm/src/armv8-r/sctlr.h @@ -34,10 +34,9 @@ * Included Files ****************************************************************************/ +#include #include -#include "barriers.h" - /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ @@ -543,14 +542,14 @@ static inline unsigned int cp15_rdsctlr(void) static inline void cp15_wrsctlr(unsigned int sctlr) { CP15_SET(SCTLR, sctlr); - ARM_NOP(); - ARM_NOP(); - ARM_NOP(); - ARM_NOP(); - ARM_NOP(); - ARM_NOP(); - ARM_NOP(); - ARM_NOP(); + UP_NOP(); + UP_NOP(); + UP_NOP(); + UP_NOP(); + UP_NOP(); + UP_NOP(); + UP_NOP(); + UP_NOP(); } /* Read/write the vector base address register (VBAR) */ diff --git a/arch/arm/src/fvp-v8r-aarch32/fvp_boot.c b/arch/arm/src/fvp-v8r-aarch32/fvp_boot.c index a383f39c39..44ffec8e94 100644 --- a/arch/arm/src/fvp-v8r-aarch32/fvp_boot.c +++ b/arch/arm/src/fvp-v8r-aarch32/fvp_boot.c @@ -30,12 +30,12 @@ #include #include +#include #include #include #include "arm_internal.h" -#include "barriers.h" #include "arm_gic.h" #include "chip.h" #include "fvp_boot.h" @@ -69,7 +69,7 @@ void arm_el_init(void) CP15_SET(ICC_HSRE, ICC_SRE_ELX_SRE_BIT | ICC_SRE_ELX_DFB_BIT | ICC_SRE_ELX_DIB_BIT | ICC_SRE_EL3_EN_BIT); - ARM_ISB(); + UP_ISB(); } /**************************************************************************** diff --git a/arch/arm/src/imx6/imx_cpuboot.c b/arch/arm/src/imx6/imx_cpuboot.c index d619e0f788..2dc875fb47 100644 --- a/arch/arm/src/imx6/imx_cpuboot.c +++ b/arch/arm/src/imx6/imx_cpuboot.c @@ -31,6 +31,7 @@ #include #include +#include #include #include "arm_internal.h" @@ -40,7 +41,6 @@ #include "scu.h" #include "gic.h" #include "mmu.h" -#include "barriers.h" #ifdef CONFIG_SMP @@ -209,7 +209,7 @@ void imx_cpu_enable(void) memcpy((uint32_t *)(PGTABLE_BASE_VADDR + PGTABLE_SIZE * cpu), (uint32_t *)PGTABLE_BASE_VADDR, PGTABLE_SIZE); - ARM_DSB(); + UP_DSB(); #endif /* Set the start up address */ diff --git a/arch/arm/src/imx9/imx9_clockconfig.c b/arch/arm/src/imx9/imx9_clockconfig.c index 6b187fd372..6a02e95ebf 100644 --- a/arch/arm/src/imx9/imx9_clockconfig.c +++ b/arch/arm/src/imx9/imx9_clockconfig.c @@ -34,8 +34,7 @@ #include #include - -#include "barriers.h" +#include #include "arm_internal.h" #include "hardware/imx9_gpc.h" @@ -52,16 +51,6 @@ #define ROOT_CLOCK_OFFSET 41 -/* Common barrier */ - -#define mb() \ - do \ - { \ - ARM_DSB(); \ - ARM_ISB(); \ - } \ - while (0) - /**************************************************************************** * Public Functions ****************************************************************************/ diff --git a/arch/arm/src/imx9/imx9_mpuinit.c b/arch/arm/src/imx9/imx9_mpuinit.c index 94feca1822..e353fa8c3b 100644 --- a/arch/arm/src/imx9/imx9_mpuinit.c +++ b/arch/arm/src/imx9/imx9_mpuinit.c @@ -32,8 +32,9 @@ #include +#include + #include "mpu.h" -#include "barriers.h" #include "hardware/imx9_memorymap.h" @@ -104,7 +105,7 @@ void imx9_mpu_initialize(void) #ifdef CONFIG_ARMV7M_DCACHE /* Memory barrier */ - ARM_DMB(); + UP_DMB(); #endif #ifdef CONFIG_BUILD_PROTECTED diff --git a/arch/arm/src/imx9/imx9_start.c b/arch/arm/src/imx9/imx9_start.c index 972d48617c..7d9530529d 100644 --- a/arch/arm/src/imx9/imx9_start.c +++ b/arch/arm/src/imx9/imx9_start.c @@ -34,9 +34,9 @@ #include #include #include +#include #include "arm_internal.h" -#include "barriers.h" #include "nvic.h" #include "mpu.h" @@ -107,8 +107,7 @@ static inline void imx9_tcmenable(void) { uint32_t regval; - ARM_DSB(); - ARM_ISB(); + UP_MB(); /* Enabled/disabled ITCM */ @@ -130,8 +129,7 @@ static inline void imx9_tcmenable(void) #endif putreg32(regval, NVIC_DTCMCR); - ARM_DSB(); - ARM_ISB(); + UP_MB(); } /**************************************************************************** diff --git a/arch/arm/src/imxrt/imxrt106x_flash.c b/arch/arm/src/imxrt/imxrt106x_flash.c index 7d3a9f9324..7bceac41d7 100644 --- a/arch/arm/src/imxrt/imxrt106x_flash.c +++ b/arch/arm/src/imxrt/imxrt106x_flash.c @@ -31,14 +31,13 @@ #include #include #include +#include #include #include #include #include -#include "barriers.h" - #include "hardware/rt106x/imxrt106x_memorymap.h" #include "arm_internal.h" diff --git a/arch/arm/src/imxrt/imxrt_enet.c b/arch/arm/src/imxrt/imxrt_enet.c index 289731b8bd..95617302e2 100644 --- a/arch/arm/src/imxrt/imxrt_enet.c +++ b/arch/arm/src/imxrt/imxrt_enet.c @@ -35,7 +35,6 @@ #include #include #include -#include #include #include @@ -55,6 +54,7 @@ # include #endif +#include #include #include "arm_internal.h" @@ -778,7 +778,7 @@ static int imxrt_transmit(struct imxrt_driver_s *priv) #ifdef CONFIG_ARMV7M_DCACHE_WRITETHROUGH /* Make sure that descriptors are flushed */ - ARM_DSB(); + UP_DSB(); #else up_clean_dcache((uintptr_t)txdesc, (uintptr_t)txdesc + sizeof(struct enet_desc_s)); @@ -1033,7 +1033,7 @@ static void imxrt_receive(struct imxrt_driver_s *priv) rxdesc->status1 |= RXDESC_E; #ifdef CONFIG_ARMV7M_DCACHE_WRITETHROUGH - ARM_DSB(); + UP_DSB(); #else up_clean_dcache((uintptr_t)rxdesc, (uintptr_t)rxdesc + sizeof(struct enet_desc_s)); @@ -1473,7 +1473,7 @@ static int imxrt_ifup_action(struct net_driver_s *dev, bool resetphy) #ifdef CONFIG_ARMV7M_DCACHE_WRITETHROUGH /* Make sure that descriptors are flushed */ - ARM_DSB(); + UP_DSB(); #endif /* Indicate that there have been empty receive buffers produced */ diff --git a/arch/arm/src/imxrt/imxrt_flexio.c b/arch/arm/src/imxrt/imxrt_flexio.c index 5064c70617..696f6cee10 100644 --- a/arch/arm/src/imxrt/imxrt_flexio.c +++ b/arch/arm/src/imxrt/imxrt_flexio.c @@ -35,6 +35,7 @@ #include #include +#include #include #include @@ -44,7 +45,6 @@ #include #include "arm_internal.h" -#include "barriers.h" #include "imxrt_gpio.h" #include "imxrt_periphclks.h" diff --git a/arch/arm/src/imxrt/imxrt_flexspi.c b/arch/arm/src/imxrt/imxrt_flexspi.c index 31d3d2076b..864260d5c9 100644 --- a/arch/arm/src/imxrt/imxrt_flexspi.c +++ b/arch/arm/src/imxrt/imxrt_flexspi.c @@ -35,6 +35,7 @@ #include #include +#include #include #include @@ -44,7 +45,6 @@ #include #include "arm_internal.h" -#include "barriers.h" #include "imxrt_gpio.h" #include "imxrt_periphclks.h" diff --git a/arch/arm/src/imxrt/imxrt_mpuinit.c b/arch/arm/src/imxrt/imxrt_mpuinit.c index c47186e005..51c8f211dd 100644 --- a/arch/arm/src/imxrt/imxrt_mpuinit.c +++ b/arch/arm/src/imxrt/imxrt_mpuinit.c @@ -30,9 +30,9 @@ #include #include +#include #include "mpu.h" -#include "barriers.h" #include "hardware/imxrt_memorymap.h" @@ -101,7 +101,7 @@ void imxrt_mpu_initialize(void) #ifdef CONFIG_ARMV7M_DCACHE /* Memory barrier */ - ARM_DMB(); + UP_DMB(); #ifdef CONFIG_IMXFT_QSPI /* Make QSPI memory region strongly ordered */ diff --git a/arch/arm/src/imxrt/imxrt_periphclks.c b/arch/arm/src/imxrt/imxrt_periphclks.c index 74c761698b..6c7873d7ab 100644 --- a/arch/arm/src/imxrt/imxrt_periphclks.c +++ b/arch/arm/src/imxrt/imxrt_periphclks.c @@ -28,8 +28,9 @@ #include +#include + #include "arm_internal.h" -#include "barriers.h" #include "imxrt_periphclks.h" /**************************************************************************** @@ -72,8 +73,7 @@ void imxrt_periphclk_configure(unsigned int index, unsigned int value) putreg32(regval, IMXRT_CCM_LPCG_DIR(index)); - ARM_DSB(); - ARM_ISB(); + UP_MB(); /* Ensure the clock setting is written and active before we return */ @@ -105,8 +105,7 @@ void imxrt_periphclk_configure(uintptr_t regaddr, unsigned int index, unsigned int value) { modifyreg32(regaddr, CCM_CCGRX_CG_MASK(index), CCM_CCGRX_CG(index, value)); - ARM_DSB(); - ARM_ISB(); + UP_MB(); } #endif diff --git a/arch/arm/src/imxrt/imxrt_start.c b/arch/arm/src/imxrt/imxrt_start.c index 6bc3f04587..af06b441b8 100644 --- a/arch/arm/src/imxrt/imxrt_start.c +++ b/arch/arm/src/imxrt/imxrt_start.c @@ -32,10 +32,10 @@ #include #include +#include #include #include "arm_internal.h" -#include "barriers.h" #include "nvic.h" #include "imxrt_clockconfig.h" @@ -101,8 +101,7 @@ static inline void imxrt_tcmenable(void) { uint32_t regval; - ARM_DSB(); - ARM_ISB(); + UP_MB(); /* Enabled/disabled ITCM */ @@ -124,8 +123,7 @@ static inline void imxrt_tcmenable(void) #endif putreg32(regval, NVIC_DTCMCR); - ARM_DSB(); - ARM_ISB(); + UP_MB(); #ifdef CONFIG_ARMV7M_ITCM /* Copy TCM code from flash to ITCM */ diff --git a/arch/arm/src/mps/mps_start.c b/arch/arm/src/mps/mps_start.c index 992d3d7c69..ee5f5b0d46 100644 --- a/arch/arm/src/mps/mps_start.c +++ b/arch/arm/src/mps/mps_start.c @@ -28,10 +28,10 @@ #include #include +#include #include #include "arm_internal.h" -#include "barriers.h" #include "nvic.h" #include "mps_irq.h" #include "mps_userspace.h" @@ -76,8 +76,7 @@ static inline void mps_tcmenable(void) { uint32_t regval; - ARM_DSB(); - ARM_ISB(); + UP_MB(); /* Enabled/disabled ITCM */ @@ -99,8 +98,7 @@ static inline void mps_tcmenable(void) #endif putreg32(regval, NVIC_DTCMCR); - ARM_DSB(); - ARM_ISB(); + UP_MB(); } /**************************************************************************** @@ -164,7 +162,7 @@ void __start(void) #ifdef CONFIG_ARMV7M_DCACHE /* Memory barrier */ - ARM_DMB(); + UP_DMB(); #endif diff --git a/arch/arm/src/mps/mps_userspace.c b/arch/arm/src/mps/mps_userspace.c index caea8e665e..fba936a79f 100644 --- a/arch/arm/src/mps/mps_userspace.c +++ b/arch/arm/src/mps/mps_userspace.c @@ -30,9 +30,9 @@ #include #include #include +#include #include "mpu.h" -#include "barriers.h" #include "arm_internal.h" #include "mps_userspace.h" diff --git a/arch/arm/src/nrf52/nrf52_nvmc.c b/arch/arm/src/nrf52/nrf52_nvmc.c index 73acf184ef..36676cf3bc 100644 --- a/arch/arm/src/nrf52/nrf52_nvmc.c +++ b/arch/arm/src/nrf52/nrf52_nvmc.c @@ -43,8 +43,9 @@ #include #include +#include + #include "arm_internal.h" -#include "barriers.h" #include "hardware/nrf52_ficr.h" #include "hardware/nrf52_nvmc.h" @@ -99,8 +100,7 @@ static inline void wait_for_flash_ready(void) static inline void nrf_mem_barrier(void) { - ARM_ISB(); - ARM_DSB(); + UP_MB(); } /**************************************************************************** diff --git a/arch/arm/src/nrf52/nrf52_qspi.c b/arch/arm/src/nrf52/nrf52_qspi.c index 287a2257c2..9376e7b2d6 100644 --- a/arch/arm/src/nrf52/nrf52_qspi.c +++ b/arch/arm/src/nrf52/nrf52_qspi.c @@ -52,10 +52,6 @@ #define QSPI_BLOCK_ERASE 0xd8 #define QSPI_ALL_ERASE 0xc7 -/* QSPI memory synchronization */ - -#define MEMORY_SYNC() do { ARM_DSB(); ARM_ISB(); } while (0) - /**************************************************************************** * Private Types ****************************************************************************/ diff --git a/arch/arm/src/nrf52/nrf52_spi.c b/arch/arm/src/nrf52/nrf52_spi.c index 716b568570..9ab4f36f66 100644 --- a/arch/arm/src/nrf52/nrf52_spi.c +++ b/arch/arm/src/nrf52/nrf52_spi.c @@ -34,11 +34,11 @@ #include #include #include +#include #include #include #include "arm_internal.h" -#include "barriers.h" #include "nrf52_gpio.h" #include "nrf52_spi.h" @@ -492,8 +492,7 @@ static int nrf52_spi_deinit(struct nrf52_spidev_s *priv) */ nrf52_spi_putreg(priv, NRF52_SPIM_POWER_OFFSET, 0); - ARM_DSB(); - ARM_ISB(); + UP_MB(); nrf52_spi_putreg(priv, NRF52_SPIM_POWER_OFFSET, 1); #endif diff --git a/arch/arm/src/nrf53/nrf53_flash.c b/arch/arm/src/nrf53/nrf53_flash.c index 7b66eb6867..42ef436ada 100644 --- a/arch/arm/src/nrf53/nrf53_flash.c +++ b/arch/arm/src/nrf53/nrf53_flash.c @@ -30,9 +30,9 @@ #include #include +#include #include "arm_internal.h" -#include "barriers.h" #include "hardware/nrf53_ficr.h" #include "hardware/nrf53_nvmc.h" @@ -41,8 +41,6 @@ * Pre-processor Definitions ****************************************************************************/ -#define MEMORY_SYNC() ARM_ISB(); ARM_DSB() - /* Sizes and masks */ #define NRF53_FLASH_ERASEDVAL (0xff) @@ -220,7 +218,7 @@ ssize_t up_progmem_eraseblock(size_t block) /* Memory sync */ - MEMORY_SYNC(); + UP_MB(); /* Erase the page by writting 0xffffffff into the first 32-bit word of * the flash page @@ -240,7 +238,7 @@ ssize_t up_progmem_eraseblock(size_t block) /* Memory sync */ - MEMORY_SYNC(); + UP_MB(); /* Verify */ @@ -356,7 +354,7 @@ ssize_t up_progmem_write(size_t addr, const void *buf, size_t count) /* Memory sync */ - MEMORY_SYNC(); + UP_MB(); /* Write the word */ @@ -374,7 +372,7 @@ ssize_t up_progmem_write(size_t addr, const void *buf, size_t count) /* Memory sync */ - MEMORY_SYNC(); + UP_MB(); /* Verify */ diff --git a/arch/arm/src/nrf53/nrf53_qspi.c b/arch/arm/src/nrf53/nrf53_qspi.c index a29efa3845..8de286ae41 100644 --- a/arch/arm/src/nrf53/nrf53_qspi.c +++ b/arch/arm/src/nrf53/nrf53_qspi.c @@ -62,10 +62,6 @@ #define QSPI_BLOCK_ERASE 0xd8 #define QSPI_ALL_ERASE 0xc7 -/* QSPI memory synchronization */ - -#define MEMORY_SYNC() do { ARM_DSB(); ARM_ISB(); } while (0) - /**************************************************************************** * Private Types ****************************************************************************/ diff --git a/arch/arm/src/nrf53/nrf53_spi.c b/arch/arm/src/nrf53/nrf53_spi.c index ddabd34d3d..12e1021932 100644 --- a/arch/arm/src/nrf53/nrf53_spi.c +++ b/arch/arm/src/nrf53/nrf53_spi.c @@ -34,11 +34,11 @@ #include #include #include +#include #include #include #include "arm_internal.h" -#include "barriers.h" #include "nrf53_gpio.h" #include "nrf53_spi.h" diff --git a/arch/arm/src/nrf91/nrf91_errata.c b/arch/arm/src/nrf91/nrf91_errata.c index eb54e90d93..a0067278c3 100644 --- a/arch/arm/src/nrf91/nrf91_errata.c +++ b/arch/arm/src/nrf91/nrf91_errata.c @@ -26,8 +26,9 @@ #include +#include + #include "arm_internal.h" -#include "barriers.h" #include "hardware/nrf91_memorymap.h" #include "hardware/nrf91_regulators.h" @@ -39,8 +40,6 @@ * Pre-processor Definitions ****************************************************************************/ -#define MEMORY_SYNC() ARM_ISB(); ARM_DSB() - /**************************************************************************** * Private Functions ****************************************************************************/ @@ -87,7 +86,7 @@ void nrf91_uicr_recover(void) /* Memory sync */ - MEMORY_SYNC(); + UP_MB(); /* Write HFXOSRC */ @@ -104,7 +103,7 @@ void nrf91_uicr_recover(void) /* Memory sync */ - MEMORY_SYNC(); + UP_MB(); /* Write HFXOCNT */ @@ -121,7 +120,7 @@ void nrf91_uicr_recover(void) /* Memory sync */ - MEMORY_SYNC(); + UP_MB(); /* Read only access */ diff --git a/arch/arm/src/nrf91/nrf91_flash.c b/arch/arm/src/nrf91/nrf91_flash.c index 5a0fab558f..bbf1d8f833 100644 --- a/arch/arm/src/nrf91/nrf91_flash.c +++ b/arch/arm/src/nrf91/nrf91_flash.c @@ -30,9 +30,9 @@ #include #include +#include #include "arm_internal.h" -#include "barriers.h" #include "hardware/nrf91_ficr.h" #include "hardware/nrf91_nvmc.h" @@ -41,8 +41,6 @@ * Pre-processor Definitions ****************************************************************************/ -#define MEMORY_SYNC() ARM_ISB(); ARM_DSB() - /* Sizes and masks */ #define NRF91_FLASH_ERASEDVAL (0xff) @@ -220,7 +218,7 @@ ssize_t up_progmem_eraseblock(size_t block) /* Memory sync */ - MEMORY_SYNC(); + UP_MB(); /* Erase the page by writting 0xffffffff into the first 32-bit word of * the flash page @@ -240,7 +238,7 @@ ssize_t up_progmem_eraseblock(size_t block) /* Memory sync */ - MEMORY_SYNC(); + UP_MB(); /* Verify */ @@ -356,7 +354,7 @@ ssize_t up_progmem_write(size_t addr, const void *buf, size_t count) /* Memory sync */ - MEMORY_SYNC(); + UP_MB(); /* Write the word */ @@ -374,7 +372,7 @@ ssize_t up_progmem_write(size_t addr, const void *buf, size_t count) /* Memory sync */ - MEMORY_SYNC(); + UP_MB(); /* Verify */ diff --git a/arch/arm/src/nrf91/nrf91_spi.c b/arch/arm/src/nrf91/nrf91_spi.c index 932a30ae66..bf0ef270b9 100644 --- a/arch/arm/src/nrf91/nrf91_spi.c +++ b/arch/arm/src/nrf91/nrf91_spi.c @@ -34,11 +34,11 @@ #include #include #include +#include #include #include #include "arm_internal.h" -#include "barriers.h" #include "nrf91_gpio.h" #include "nrf91_spi.h" diff --git a/arch/arm/src/rp2040/rp2040_cyw43439.c b/arch/arm/src/rp2040/rp2040_cyw43439.c index b962f08bab..3d91b0c06d 100644 --- a/arch/arm/src/rp2040/rp2040_cyw43439.c +++ b/arch/arm/src/rp2040/rp2040_cyw43439.c @@ -33,8 +33,7 @@ #include #include #include - -#include "barriers.h" +#include #include "rp2040_cyw43439.h" #include "rp2040_pio.h" @@ -499,7 +498,7 @@ static int my_write(struct gspi_dev_s *gspi, /* Assert gpio_select by pulling line low */ rp2040_gpio_put(rp_io->gpio_select, false); - ARM_DMB(); + UP_DMB(); /* Enable the state machine. This starts the pio program running */ @@ -524,7 +523,7 @@ static int my_write(struct gspi_dev_s *gspi, /* Un-assert select by pulling line high. */ - ARM_DMB(); + UP_DMB(); rp2040_gpio_put(rp_io->gpio_select, true); /* Free the DMA controller */ @@ -725,7 +724,7 @@ static int my_read(struct gspi_dev_s *gspi, /* Assert gpio_select by pulling line low */ rp2040_gpio_put(rp_io->gpio_select, false); - ARM_DMB(); + UP_DMB(); /* Enable the state machine. This starts the pio program running */ @@ -741,7 +740,7 @@ static int my_read(struct gspi_dev_s *gspi, /* Un-assert select by pulling line high. */ - ARM_DMB(); + UP_DMB(); rp2040_gpio_put(rp_io->gpio_select, true); /* Free the DMA controllers */ diff --git a/arch/arm/src/rp23xx/rp23xx_testset.c b/arch/arm/src/rp23xx/rp23xx_testset.c index d1d45d4d3e..4e9e6e0124 100644 --- a/arch/arm/src/rp23xx/rp23xx_testset.c +++ b/arch/arm/src/rp23xx/rp23xx_testset.c @@ -75,7 +75,7 @@ spinlock_t up_testset(volatile spinlock_t *lock) if (ret == SP_UNLOCKED) { *lock = SP_LOCKED; - SP_DMB(); + UP_DMB(); } /* Unlock hardware spinlock */ diff --git a/arch/arm/src/s32k3xx/s32k3xx_emac.c b/arch/arm/src/s32k3xx/s32k3xx_emac.c index 9cf06d0906..128ef13647 100644 --- a/arch/arm/src/s32k3xx/s32k3xx_emac.c +++ b/arch/arm/src/s32k3xx/s32k3xx_emac.c @@ -72,10 +72,6 @@ * Pre-processor Definitions ****************************************************************************/ -/* Memory synchronization */ - -#define MEMORY_SYNC() //do { ARM_DSB(); ARM_ISB(); } while (0) - /* If processing is not done at the interrupt level, then work queue support * is required. */ @@ -839,7 +835,7 @@ static int s32k3xx_transmit(struct s32k3xx_driver_s *priv) s32k3xx_disableint(priv, EMAC_DMA_CH0_INTERRUPT_ENABLE_RIE); } - MEMORY_SYNC(); + UP_MB(); /* Enable TX interrupts */ diff --git a/arch/arm/src/s32k3xx/s32k3xx_mpuinit.c b/arch/arm/src/s32k3xx/s32k3xx_mpuinit.c index e7aa8304b8..6db24e9caa 100644 --- a/arch/arm/src/s32k3xx/s32k3xx_mpuinit.c +++ b/arch/arm/src/s32k3xx/s32k3xx_mpuinit.c @@ -28,9 +28,9 @@ #include #include +#include #include "mpu.h" -#include "barriers.h" #include "s32k3xx_mpuinit.h" #include "arm_internal.h" @@ -106,7 +106,7 @@ void s32k3xx_mpuinitialize(void) #ifdef CONFIG_ARMV7M_DCACHE /* Memory barrier */ - ARM_DMB(); + UP_DMB(); #endif diff --git a/arch/arm/src/s32k3xx/s32k3xx_qspi.c b/arch/arm/src/s32k3xx/s32k3xx_qspi.c index 7fe9b79e96..f127067e49 100644 --- a/arch/arm/src/s32k3xx/s32k3xx_qspi.c +++ b/arch/arm/src/s32k3xx/s32k3xx_qspi.c @@ -38,6 +38,7 @@ #include #include +#include #include #include @@ -50,7 +51,6 @@ #include #include "arm_internal.h" -#include "barriers.h" #ifdef CONFIG_S32K3XX_QSPI_DMA #include "hardware/s32k3xx_dmamux.h" @@ -66,10 +66,6 @@ * Pre-processor Definitions ****************************************************************************/ -/* QSPI memory synchronization */ - -#define MEMORY_SYNC() do { ARM_DSB(); ARM_ISB(); } while (0) - /* LUT entries used for various command sequences */ #define QSPI_LUT_READ 0U /* Quad Output read */ #define QSPI_LUT_WRITE 1U /* Quad write */ @@ -736,7 +732,7 @@ static int qspi_receive_blocking(struct s32k3xx_qspidev_s *priv, up_clean_dcache((uintptr_t)S32K3XX_QSPI_RBDR(0), (uintptr_t)S32K3XX_QSPI_RBDR(0) + readlen); - MEMORY_SYNC(); + UP_MB(); memcpy(data, (void *)S32K3XX_QSPI_RBDR(0), readlen); data += readlen; @@ -1299,7 +1295,7 @@ static int qspi_command(struct qspi_dev_s *dev, /* Wait for the interrupt routine to finish it's magic */ nxsem_wait(&priv->op_sem); - MEMORY_SYNC(); + UP_MB(); if (QSPICMD_ISREAD(cmdinfo->flags)) { @@ -1370,7 +1366,7 @@ static int qspi_memory(struct qspi_dev_s *dev, #endif } - MEMORY_SYNC(); + UP_MB(); return ret; } diff --git a/arch/arm/src/sama5/sam_qspi.c b/arch/arm/src/sama5/sam_qspi.c index c0f37e3751..3087b51d4b 100644 --- a/arch/arm/src/sama5/sam_qspi.c +++ b/arch/arm/src/sama5/sam_qspi.c @@ -35,6 +35,7 @@ #include #include +#include #include #include @@ -47,7 +48,6 @@ #include #include "arm_internal.h" -#include "barriers.h" #include "sam_pio.h" #include "sam_dmac.h" @@ -118,10 +118,6 @@ #define DMA_TIMEOUT_MS (800) #define DMA_TIMEOUT_TICKS MSEC2TICK(DMA_TIMEOUT_MS) -/* QSPI memory synchronization */ - -#define MEMORY_SYNC() do { ARM_DSB(); ARM_ISB(); } while (0) - /* Debug ********************************************************************/ /* Check if QSPI debug is enabled */ @@ -955,7 +951,7 @@ static int qspi_memory_dma(struct sam_qspidev_s *priv, qspi_putreg(priv, QSPI_CR_LASTXFER, SAM_QSPI_CR_OFFSET); while ((qspi_getreg(priv, SAM_QSPI_SR_OFFSET) & QSPI_SR_INSTRE) == 0); - MEMORY_SYNC(); + UP_MB(); /* Dump the sampled DMA registers */ @@ -1016,7 +1012,7 @@ static int qspi_memory_nodma(struct sam_qspidev_s *priv, meminfo->buflen); } - MEMORY_SYNC(); + UP_MB(); /* Indicate the end of the transfer as soon as the transmission * registers are empty. @@ -1520,7 +1516,7 @@ static int qspi_command(struct qspi_dev_s *dev, (const uint8_t *) priv->membase, cmdinfo->buflen); } - MEMORY_SYNC(); + UP_MB(); /* Indicate the end of the transfer as soon as the transmission * registers are empty. @@ -1553,7 +1549,7 @@ static int qspi_command(struct qspi_dev_s *dev, QSPI_IFR_NBDUM(0); qspi_putreg(priv, ifr, SAM_QSPI_IFR_OFFSET); - MEMORY_SYNC(); + UP_MB(); /* If the instruction frame does not include data, writing to the IFR * triggers sending of the instruction frame. Fall through to INSTRE diff --git a/arch/arm/src/samv7/sam_eefc.c b/arch/arm/src/samv7/sam_eefc.c index 8d8fb2516e..d39de06a69 100644 --- a/arch/arm/src/samv7/sam_eefc.c +++ b/arch/arm/src/samv7/sam_eefc.c @@ -30,10 +30,9 @@ #include #include +#include #include -#include "barriers.h" - #include "hardware/sam_memorymap.h" #include "sam_eefc.h" diff --git a/arch/arm/src/samv7/sam_mpuinit.c b/arch/arm/src/samv7/sam_mpuinit.c index 70c46c7094..a4ac8a9693 100644 --- a/arch/arm/src/samv7/sam_mpuinit.c +++ b/arch/arm/src/samv7/sam_mpuinit.c @@ -30,9 +30,9 @@ #include #include +#include #include "mpu.h" -#include "barriers.h" #include "hardware/sam_memorymap.h" @@ -75,7 +75,7 @@ void sam_mpu_initialize(void) #ifdef CONFIG_ARMV7M_DCACHE /* Memory barrier */ - ARM_DMB(); + UP_DMB(); #ifdef CONFIG_SAMV7_QSPI /* Make QSPI memory region strongly ordered */ diff --git a/arch/arm/src/samv7/sam_progmem.c b/arch/arm/src/samv7/sam_progmem.c index 1ae38dff8d..19c80a0521 100644 --- a/arch/arm/src/samv7/sam_progmem.c +++ b/arch/arm/src/samv7/sam_progmem.c @@ -32,10 +32,10 @@ #include #include +#include #include #include "arm_internal.h" -#include "barriers.h" #include "hardware/sam_memorymap.h" @@ -549,7 +549,7 @@ ssize_t up_progmem_write(size_t address, const void *buffer, size_t buflen) *dest++ = *src++; #ifdef CONFIG_ARMV7M_DCACHE_WRITETHROUGH - ARM_DMB(); + UP_DMB(); #endif } diff --git a/arch/arm/src/samv7/sam_qspi.c b/arch/arm/src/samv7/sam_qspi.c index 50be765533..749b79e31a 100644 --- a/arch/arm/src/samv7/sam_qspi.c +++ b/arch/arm/src/samv7/sam_qspi.c @@ -35,6 +35,7 @@ #include #include +#include #include #include @@ -47,7 +48,6 @@ #include #include "arm_internal.h" -#include "barriers.h" #include "sam_gpio.h" #include "sam_xdmac.h" @@ -118,10 +118,6 @@ #define DMA_TIMEOUT_MS (800) #define DMA_TIMEOUT_TICKS MSEC2TICK(DMA_TIMEOUT_MS) -/* QSPI memory synchronization */ - -#define MEMORY_SYNC() do { ARM_DSB(); ARM_ISB(); } while (0) - /* Debug ********************************************************************/ /* Check if QSPI debug is enabled */ @@ -910,7 +906,7 @@ static int qspi_memory_dma(struct sam_qspidev_s *priv, qspi_putreg(priv, QSPI_CR_LASTXFER, SAM_QSPI_CR_OFFSET); while ((qspi_getreg(priv, SAM_QSPI_SR_OFFSET) & QSPI_SR_INSTRE) == 0); - MEMORY_SYNC(); + UP_MB(); /* Dump the sampled DMA registers */ @@ -971,7 +967,7 @@ static int qspi_memory_nodma(struct sam_qspidev_s *priv, meminfo->buflen); } - MEMORY_SYNC(); + UP_MB(); /* Indicate the end of the transfer as soon as the transmission * registers are empty. @@ -1465,7 +1461,7 @@ static int qspi_command(struct qspi_dev_s *dev, (const uint8_t *)SAM_QSPIMEM_BASE, cmdinfo->buflen); } - MEMORY_SYNC(); + UP_MB(); /* Indicate the end of the transfer as soon as the transmission * registers are empty. @@ -1498,7 +1494,7 @@ static int qspi_command(struct qspi_dev_s *dev, QSPI_IFR_NBDUM(0); qspi_putreg(priv, ifr, SAM_QSPI_IFR_OFFSET); - MEMORY_SYNC(); + UP_MB(); /* If the insruction frame does not include data, writing to the IFR * triggers sending of the instruction frame. Fall through to INSTRE diff --git a/arch/arm/src/samv7/sam_start.c b/arch/arm/src/samv7/sam_start.c index e7be42701d..b2f42bd76c 100644 --- a/arch/arm/src/samv7/sam_start.c +++ b/arch/arm/src/samv7/sam_start.c @@ -32,10 +32,10 @@ #include #include +#include #include #include "arm_internal.h" -#include "barriers.h" #include "nvic.h" #include "sam_clockconfig.h" @@ -103,8 +103,7 @@ static inline void sam_tcmenable(void) { uint32_t regval; - ARM_DSB(); - ARM_ISB(); + UP_MB(); /* Assure that GPNVM 7-8 settings are as expected */ #warning Missing logic @@ -129,8 +128,7 @@ static inline void sam_tcmenable(void) #endif putreg32(regval, NVIC_DTCMCR); - ARM_DSB(); - ARM_ISB(); + UP_MB(); #ifdef CONFIG_ARMV7M_ITCM /* Copy TCM code from flash to ITCM */ diff --git a/arch/arm/src/samv7/sam_us.c b/arch/arm/src/samv7/sam_us.c index 3371c5b805..f3720f95a8 100644 --- a/arch/arm/src/samv7/sam_us.c +++ b/arch/arm/src/samv7/sam_us.c @@ -30,10 +30,10 @@ #include #include +#include #include #include "arm_internal.h" -#include "barriers.h" #include "hardware/sam_memorymap.h" @@ -126,7 +126,7 @@ int sam_write_user_signature(void *buffer, size_t buflen) *dest++ = g_page_buffer[i]; #ifdef CONFIG_ARMV7M_DCACHE_WRITETHROUGH - ARM_DMB(); + UP_DMB(); #endif } diff --git a/arch/arm/src/samv7/sam_usbdevhs.c b/arch/arm/src/samv7/sam_usbdevhs.c index 08a6e91f0f..5ec0b42536 100644 --- a/arch/arm/src/samv7/sam_usbdevhs.c +++ b/arch/arm/src/samv7/sam_usbdevhs.c @@ -60,10 +60,10 @@ #include #include +#include #include #include "arm_internal.h" -#include "barriers.h" #include "chip.h" #include "sam_periphclks.h" @@ -150,10 +150,6 @@ #define EPR_TXDTOG_MASK (USB_EPR_STATTX_MASK | EPR_NOTOG_MASK) #define EPR_RXDTOG_MASK (USB_EPR_STATRX_MASK | EPR_NOTOG_MASK) -/* Cache-related */ - -#define MEMORY_SYNC() do { ARM_DSB();ARM_ISB(); } while (0) - /* Request queue operations *************************************************/ #define sam_rqempty(q) ((q)->head == NULL) @@ -1566,7 +1562,7 @@ static void sam_req_rddone(struct sam_usbdev_s *priv, *dest++ = *fifo++; } - MEMORY_SYNC(); + UP_MB(); } /**************************************************************************** @@ -1832,7 +1828,7 @@ static void sam_ep0_read(uint8_t *buffer, size_t buflen) *buffer++ = *fifo++; } - MEMORY_SYNC(); + UP_MB(); } /**************************************************************************** @@ -1864,7 +1860,7 @@ static void sam_ctrlep_write(struct sam_ep_s *privep, const uint8_t *buffer, *fifo++ = *buffer++; } - MEMORY_SYNC(); + UP_MB(); /* Indicate that there is data in the TX packet memory. This will * be cleared when the next NAKIN interrupt is received. @@ -1926,7 +1922,7 @@ static void sam_ep_write(struct sam_ep_s *privep, const uint8_t *buffer, *fifo++ = *buffer++; } - MEMORY_SYNC(); + UP_MB(); /* Indicate that there is data in the TX packet memory. This will * be cleared when the next data out interrupt is received. @@ -3337,7 +3333,7 @@ static int sam_usbhs_interrupt(int irq, void *context, void *arg) } usbtrace(TRACE_INTEXIT(SAM_TRACEINTID_INTERRUPT), devisr); - MEMORY_SYNC(); + UP_MB(); return OK; } diff --git a/arch/arm/src/stm32f7/stm32_ethernet.c b/arch/arm/src/stm32f7/stm32_ethernet.c index 979e99e27e..ade5283d1b 100644 --- a/arch/arm/src/stm32f7/stm32_ethernet.c +++ b/arch/arm/src/stm32f7/stm32_ethernet.c @@ -36,6 +36,7 @@ #include #include +#include #include #include @@ -54,7 +55,6 @@ #endif #include "arm_internal.h" -#include "barriers.h" #include "hardware/stm32_syscfg.h" #include "hardware/stm32_pinmap.h" @@ -76,10 +76,6 @@ * Pre-processor Definitions ****************************************************************************/ -/* Memory synchronization */ - -#define MEMORY_SYNC() do { ARM_DSB(); ARM_ISB(); } while (0) - /* Configuration ************************************************************/ /* See boards/arm/stm32/stm3240g-eval/README.txt for an explanation of the @@ -1225,7 +1221,7 @@ static int stm32_transmit(struct stm32_ethmac_s *priv) /* Check if the TX Buffer unavailable flag is set */ - MEMORY_SYNC(); + UP_MB(); if ((stm32_getreg(STM32_ETH_DMASR) & ETH_DMAINT_TBUI) != 0) { diff --git a/arch/arm/src/stm32f7/stm32_flash.c b/arch/arm/src/stm32f7/stm32_flash.c index f421804e91..05c47515e2 100644 --- a/arch/arm/src/stm32f7/stm32_flash.c +++ b/arch/arm/src/stm32f7/stm32_flash.c @@ -51,13 +51,12 @@ #include #include #include +#include #include #include #include -#include "barriers.h" - #include "hardware/stm32_flash.h" #include "stm32_waste.h" #include "arm_internal.h" @@ -411,7 +410,7 @@ ssize_t up_progmem_write(size_t addr, const void *buf, size_t count) * optimization). */ - ARM_DSB(); + UP_DSB(); while (getreg32(STM32_FLASH_SR) & FLASH_SR_BSY) { diff --git a/arch/arm/src/stm32f7/stm32_qspi.c b/arch/arm/src/stm32f7/stm32_qspi.c index 7de2e82511..1cf9638d25 100644 --- a/arch/arm/src/stm32f7/stm32_qspi.c +++ b/arch/arm/src/stm32f7/stm32_qspi.c @@ -37,6 +37,7 @@ #include #include +#include #include #include @@ -49,7 +50,6 @@ #include #include "arm_internal.h" -#include "barriers.h" #include "stm32_gpio.h" #include "stm32_dma.h" @@ -62,10 +62,6 @@ * Pre-processor Definitions ****************************************************************************/ -/* QSPI memory synchronization */ - -#define MEMORY_SYNC() do { ARM_DSB(); ARM_ISB(); } while (0) - /* Debug ********************************************************************/ /* Check if QSPI debug is enabled */ @@ -1553,7 +1549,7 @@ static int qspi_memory_dma(struct stm32f7_qspidev_s *priv, qspi_waitstatusflags(priv, QSPI_SR_TCF, 1); qspi_waitstatusflags(priv, QSPI_SR_BUSY, 0); - MEMORY_SYNC(); + UP_MB(); /* Dump the sampled DMA registers */ @@ -2091,7 +2087,7 @@ static int qspi_command(struct qspi_dev_s *dev, /* Wait for the interrupt routine to finish it's magic */ nxsem_wait(&priv->op_sem); - MEMORY_SYNC(); + UP_MB(); /* Convey the result */ @@ -2124,7 +2120,7 @@ static int qspi_command(struct qspi_dev_s *dev, ret = qspi_receive_blocking(priv, &xctn); } - MEMORY_SYNC(); + UP_MB(); } else { @@ -2249,7 +2245,7 @@ static int qspi_memory(struct qspi_dev_s *dev, /* Wait for the interrupt routine to finish it's magic */ nxsem_wait(&priv->op_sem); - MEMORY_SYNC(); + UP_MB(); /* convey the result */ @@ -2296,7 +2292,7 @@ static int qspi_memory(struct qspi_dev_s *dev, qspi_waitstatusflags(priv, QSPI_SR_TCF, 1); qspi_waitstatusflags(priv, QSPI_SR_BUSY, 0); - MEMORY_SYNC(); + UP_MB(); } #else @@ -2327,7 +2323,7 @@ static int qspi_memory(struct qspi_dev_s *dev, qspi_waitstatusflags(priv, QSPI_SR_TCF, 1); qspi_waitstatusflags(priv, QSPI_SR_BUSY, 0); - MEMORY_SYNC(); + UP_MB(); #endif diff --git a/arch/arm/src/stm32f7/stm32_start.c b/arch/arm/src/stm32f7/stm32_start.c index 070f93b35f..45b778442b 100644 --- a/arch/arm/src/stm32f7/stm32_start.c +++ b/arch/arm/src/stm32f7/stm32_start.c @@ -32,12 +32,12 @@ #include #include +#include #include #include "arm_internal.h" #include "nvic.h" #include "mpu.h" -#include "barriers.h" #include "stm32_rcc.h" #include "stm32_userspace.h" @@ -122,8 +122,7 @@ static inline void stm32_tcmenable(void) { uint32_t regval; - ARM_DSB(); - ARM_ISB(); + UP_MB(); /* Enabled/disabled ITCM */ @@ -149,8 +148,7 @@ static inline void stm32_tcmenable(void) #endif putreg32(regval, NVIC_DTCMCR); - ARM_DSB(); - ARM_ISB(); + UP_MB(); #ifdef CONFIG_ARMV7M_ITCM /* Copy TCM code from flash to ITCM */ diff --git a/arch/arm/src/stm32h5/stm32_ethernet.c b/arch/arm/src/stm32h5/stm32_ethernet.c index 4324862313..ff193f57b1 100644 --- a/arch/arm/src/stm32h5/stm32_ethernet.c +++ b/arch/arm/src/stm32h5/stm32_ethernet.c @@ -52,9 +52,10 @@ # include #endif +#include + #include #include "arm_internal.h" -#include "barriers.h" #include "hardware/stm32_sbs.h" #include "hardware/stm32_pinmap.h" @@ -76,10 +77,6 @@ * Pre-processor Definitions ****************************************************************************/ -/* Memory synchronization */ - -#define MEMORY_SYNC() do { ARM_DSB(); ARM_ISB(); } while (0) - /* Configuration ************************************************************/ /* See boards/arm/stm32/stm3240g-eval/README.txt for an explanation of the @@ -1266,7 +1263,7 @@ static int stm32_transmit(struct stm32_ethmac_s *priv) stm32_disableint(priv, ETH_DMACIER_RIE); } - MEMORY_SYNC(); + UP_MB(); /* Enable TX interrupts */ diff --git a/arch/arm/src/stm32h5/stm32_qspi.c b/arch/arm/src/stm32h5/stm32_qspi.c index 98fa4960e2..7ec5fa67f9 100644 --- a/arch/arm/src/stm32h5/stm32_qspi.c +++ b/arch/arm/src/stm32h5/stm32_qspi.c @@ -47,8 +47,9 @@ #include #include +#include + #include "arm_internal.h" -#include "barriers.h" #include "stm32_gpio.h" #include "stm32_rcc.h" @@ -64,10 +65,6 @@ * Pre-processor Definitions ****************************************************************************/ -/* QSPI memory synchronization */ - -#define MEMORY_SYNC() do { ARM_DSB(); ARM_ISB(); } while (0) - /* Debug ********************************************************************/ /* Check if QSPI debug is enabled */ @@ -1543,7 +1540,7 @@ static int qspi_memory_dma(struct stm32_qspidev_s *priv, qspi_waitstatusflags(priv, QSPI_SR_TCF, 1); qspi_waitstatusflags(priv, QSPI_SR_BUSY, 0); - MEMORY_SYNC(); + UP_MB(); /* Dump the sampled DMA registers */ @@ -2095,7 +2092,7 @@ static int qspi_command(struct qspi_dev_s *dev, /* Wait for the interrupt routine to finish it's magic */ nxsem_wait(&priv->op_sem); - MEMORY_SYNC(); + UP_MB(); /* Convey the result */ @@ -2128,7 +2125,7 @@ static int qspi_command(struct qspi_dev_s *dev, ret = qspi_receive_blocking(priv, &xctn); } - MEMORY_SYNC(); + UP_MB(); } else { @@ -2251,7 +2248,7 @@ static int qspi_memory(struct qspi_dev_s *dev, /* Wait for the interrupt routine to finish it's magic */ nxsem_wait(&priv->op_sem); - MEMORY_SYNC(); + UP_MB(); /* convey the result */ @@ -2298,7 +2295,7 @@ static int qspi_memory(struct qspi_dev_s *dev, qspi_waitstatusflags(priv, QSPI_SR_TCF, 1); qspi_waitstatusflags(priv, QSPI_SR_BUSY, 0); - MEMORY_SYNC(); + UP_MB(); } #else @@ -2329,7 +2326,7 @@ static int qspi_memory(struct qspi_dev_s *dev, qspi_waitstatusflags(priv, QSPI_SR_TCF, 1); qspi_waitstatusflags(priv, QSPI_SR_BUSY, 0); - MEMORY_SYNC(); + UP_MB(); #endif diff --git a/arch/arm/src/stm32h7/stm32_ethernet.c b/arch/arm/src/stm32h7/stm32_ethernet.c index 1eba295f0b..84d5687608 100644 --- a/arch/arm/src/stm32h7/stm32_ethernet.c +++ b/arch/arm/src/stm32h7/stm32_ethernet.c @@ -37,6 +37,7 @@ #include +#include #include #include @@ -56,7 +57,6 @@ #include #include "arm_internal.h" -#include "barriers.h" #include "hardware/stm32_syscfg.h" #include "hardware/stm32_pinmap.h" @@ -78,10 +78,6 @@ * Pre-processor Definitions ****************************************************************************/ -/* Memory synchronization */ - -#define MEMORY_SYNC() do { ARM_DSB(); ARM_ISB(); } while (0) - /* Configuration ************************************************************/ /* See boards/arm/stm32/stm3240g-eval/README.txt for an explanation of the @@ -1268,7 +1264,7 @@ static int stm32_transmit(struct stm32_ethmac_s *priv) stm32_disableint(priv, ETH_DMACIER_RIE); } - MEMORY_SYNC(); + UP_MB(); /* Enable TX interrupts */ diff --git a/arch/arm/src/stm32h7/stm32_pwr.c b/arch/arm/src/stm32h7/stm32_pwr.c index 88675cadab..c1d9700967 100644 --- a/arch/arm/src/stm32h7/stm32_pwr.c +++ b/arch/arm/src/stm32h7/stm32_pwr.c @@ -26,13 +26,13 @@ #include #include +#include #include #include #include #include -#include "barriers.h" #include "arm_internal.h" #include "stm32_pwr.h" #include "stm32_gpio.h" @@ -139,7 +139,7 @@ void stm32_pwr_enablebkp(bool writable) bool wait = false; flags = enter_critical_section(); - ARM_DSB(); + UP_DSB(); /* Get the current state of the STM32 PWR control register */ @@ -175,7 +175,7 @@ void stm32_pwr_enablebkp(bool writable) wait = true; } - ARM_DSB(); + UP_DSB(); leave_critical_section(flags); if (wait) diff --git a/arch/arm/src/stm32h7/stm32_qspi.c b/arch/arm/src/stm32h7/stm32_qspi.c index 709cd3d6aa..6ce731dd20 100644 --- a/arch/arm/src/stm32h7/stm32_qspi.c +++ b/arch/arm/src/stm32h7/stm32_qspi.c @@ -37,6 +37,7 @@ #include #include +#include #include #include @@ -50,7 +51,6 @@ #include #include "arm_internal.h" -#include "barriers.h" #include "stm32_gpio.h" #include "stm32_dma.h" @@ -63,10 +63,6 @@ * Pre-processor Definitions ****************************************************************************/ -/* QSPI memory synchronization */ - -#define MEMORY_SYNC() do { ARM_DSB(); ARM_ISB(); } while (0) - /* Debug ********************************************************************/ /* Check if QSPI debug is enabled */ @@ -1605,7 +1601,7 @@ static int qspi_memory_dma(struct stm32h7_qspidev_s *priv, qspi_waitstatusflags(priv, QSPI_SR_TCF, 1); qspi_waitstatusflags(priv, QSPI_SR_BUSY, 0); - MEMORY_SYNC(); + UP_MB(); /* Dump the sampled DMA registers */ @@ -2145,7 +2141,7 @@ static int qspi_command(struct qspi_dev_s *dev, /* Wait for the interrupt routine to finish it's magic */ nxsem_wait(&priv->op_sem); - MEMORY_SYNC(); + UP_MB(); /* Convey the result */ @@ -2178,7 +2174,7 @@ static int qspi_command(struct qspi_dev_s *dev, ret = qspi_receive_blocking(priv, &xctn); } - MEMORY_SYNC(); + UP_MB(); } else { @@ -2303,7 +2299,7 @@ static int qspi_memory(struct qspi_dev_s *dev, /* Wait for the interrupt routine to finish it's magic */ nxsem_wait(&priv->op_sem); - MEMORY_SYNC(); + UP_MB(); /* convey the result */ @@ -2350,7 +2346,7 @@ static int qspi_memory(struct qspi_dev_s *dev, qspi_waitstatusflags(priv, QSPI_SR_TCF, 1); qspi_waitstatusflags(priv, QSPI_SR_BUSY, 0); - MEMORY_SYNC(); + UP_MB(); } #else @@ -2381,7 +2377,7 @@ static int qspi_memory(struct qspi_dev_s *dev, qspi_waitstatusflags(priv, QSPI_SR_TCF, 1); qspi_waitstatusflags(priv, QSPI_SR_BUSY, 0); - MEMORY_SYNC(); + UP_MB(); #endif diff --git a/arch/arm/src/stm32h7/stm32_start.c b/arch/arm/src/stm32h7/stm32_start.c index 1cc0fc600a..38b2b1ab5b 100644 --- a/arch/arm/src/stm32h7/stm32_start.c +++ b/arch/arm/src/stm32h7/stm32_start.c @@ -32,10 +32,10 @@ #include #include +#include #include #include "arm_internal.h" -#include "barriers.h" #include "nvic.h" #include "mpu.h" #ifdef CONFIG_ARM_MPU @@ -131,8 +131,7 @@ static inline void stm32_tcmenable(void) { uint32_t regval; - ARM_DSB(); - ARM_ISB(); + UP_MB(); /* Enabled/disabled ITCM */ @@ -158,8 +157,7 @@ static inline void stm32_tcmenable(void) #endif putreg32(regval, NVIC_DTCMCR); - ARM_DSB(); - ARM_ISB(); + UP_MB(); #ifdef CONFIG_ARMV7M_ITCM /* Copy TCM code from flash to ITCM */ diff --git a/arch/arm/src/stm32h7/stm32h743xx_flash.c b/arch/arm/src/stm32h7/stm32h743xx_flash.c index 67fddaa712..1d68c42c78 100644 --- a/arch/arm/src/stm32h7/stm32h743xx_flash.c +++ b/arch/arm/src/stm32h7/stm32h743xx_flash.c @@ -54,13 +54,12 @@ #include #include #include +#include #include #include #include -#include "barriers.h" - #include "hardware/stm32_flash.h" #include "arm_internal.h" @@ -397,7 +396,7 @@ static int stm32h7_wait_for_last_operation(struct stm32h7_flash_priv_s int i; bool timeout = true; - ARM_DSB(); + UP_DSB(); for (i = 0; i < FLASH_TIMEOUT_VALUE; i++) { @@ -878,8 +877,7 @@ ssize_t up_progmem_write(size_t addr, const void *buf, size_t count) fp = (uint32_t *)faddr; rp = ll; - ARM_DSB(); - ARM_ISB(); + UP_MB(); /* Write 8 32 bit word and wait to complete */ @@ -897,8 +895,7 @@ ssize_t up_progmem_write(size_t addr, const void *buf, size_t count) * optimization). */ - ARM_DSB(); - ARM_ISB(); + UP_MB(); if (stm32h7_wait_for_last_operation(priv)) { diff --git a/arch/arm/src/stm32h7/stm32h7b3xx_flash.c b/arch/arm/src/stm32h7/stm32h7b3xx_flash.c index 7390ac0e70..c76b4e307a 100644 --- a/arch/arm/src/stm32h7/stm32h7b3xx_flash.c +++ b/arch/arm/src/stm32h7/stm32h7b3xx_flash.c @@ -54,13 +54,12 @@ #include #include #include +#include #include #include #include -#include "barriers.h" - #include "hardware/stm32_flash.h" #include "arm_internal.h" @@ -371,7 +370,7 @@ static int stm32h7_wait_for_last_operation(struct stm32h7_flash_priv_s int i; bool timeout = true; - ARM_DSB(); + UP_DSB(); for (i = 0; i < FLASH_TIMEOUT_VALUE; i++) { @@ -846,8 +845,7 @@ ssize_t up_progmem_write(size_t addr, const void *buf, size_t count) fp = (uint32_t *)faddr; rp = ll; - ARM_DSB(); - ARM_ISB(); + UP_MB(); /* Write 4 32 bit word and wait to complete */ @@ -861,8 +859,7 @@ ssize_t up_progmem_write(size_t addr, const void *buf, size_t count) * optimization). */ - ARM_DSB(); - ARM_ISB(); + UP_MB(); if (stm32h7_wait_for_last_operation(priv)) { diff --git a/arch/arm/src/stm32l4/stm32l4_qspi.c b/arch/arm/src/stm32l4/stm32l4_qspi.c index 04c814a72c..582a853d1a 100644 --- a/arch/arm/src/stm32l4/stm32l4_qspi.c +++ b/arch/arm/src/stm32l4/stm32l4_qspi.c @@ -36,6 +36,7 @@ #include #include +#include #include #include @@ -47,7 +48,6 @@ #include #include "arm_internal.h" -#include "barriers.h" #include "stm32l4_gpio.h" #include "stm32l4_dma.h" @@ -62,10 +62,6 @@ * Pre-processor Definitions ****************************************************************************/ -/* QSPI memory synchronization */ - -#define MEMORY_SYNC() do { ARM_DSB(); ARM_ISB(); } while (0) - /* Debug ********************************************************************/ /* Check if QSPI debug is enabled */ @@ -1501,7 +1497,7 @@ static int qspi_memory_dma(struct stm32l4_qspidev_s *priv, qspi_waitstatusflags(priv, QSPI_SR_TCF, 1); qspi_waitstatusflags(priv, QSPI_SR_BUSY, 0); - MEMORY_SYNC(); + UP_MB(); /* Dump the sampled DMA registers */ @@ -2039,7 +2035,7 @@ static int qspi_command(struct qspi_dev_s *dev, /* Wait for the interrupt routine to finish it's magic */ nxsem_wait(&priv->op_sem); - MEMORY_SYNC(); + UP_MB(); /* Convey the result */ @@ -2073,7 +2069,7 @@ static int qspi_command(struct qspi_dev_s *dev, ret = qspi_receive_blocking(priv, &xctn); } - MEMORY_SYNC(); + UP_MB(); } else { @@ -2198,7 +2194,7 @@ static int qspi_memory(struct qspi_dev_s *dev, /* Wait for the interrupt routine to finish it's magic */ nxsem_wait(&priv->op_sem); - MEMORY_SYNC(); + UP_MB(); /* convey the result */ @@ -2245,7 +2241,7 @@ static int qspi_memory(struct qspi_dev_s *dev, qspi_waitstatusflags(priv, QSPI_SR_TCF, 1); qspi_waitstatusflags(priv, QSPI_SR_BUSY, 0); - MEMORY_SYNC(); + UP_MB(); } #else @@ -2276,7 +2272,7 @@ static int qspi_memory(struct qspi_dev_s *dev, qspi_waitstatusflags(priv, QSPI_SR_TCF, 1); qspi_waitstatusflags(priv, QSPI_SR_BUSY, 0); - MEMORY_SYNC(); + UP_MB(); #endif diff --git a/boards/arm/imxrt/imxrt1064-evk/src/imxrt_boot_image.c b/boards/arm/imxrt/imxrt1064-evk/src/imxrt_boot_image.c index feeef3029f..06f850431e 100644 --- a/boards/arm/imxrt/imxrt1064-evk/src/imxrt_boot_image.c +++ b/boards/arm/imxrt/imxrt1064-evk/src/imxrt_boot_image.c @@ -33,10 +33,10 @@ #include #include #include +#include #include "nvic.h" #include "arm_internal.h" -#include "barriers.h" /**************************************************************************** * Pre-processor Definitions @@ -85,7 +85,7 @@ static void cleanup_arm_nvic(void) /* Allow any pending interrupts to be recognized */ - ARM_ISB(); + UP_ISB(); cpsid(); /* Disable all interrupts */ diff --git a/boards/arm/nrf52/common/src/nrf52_boot_image.c b/boards/arm/nrf52/common/src/nrf52_boot_image.c index 658c131eb9..e3285e1cc4 100644 --- a/boards/arm/nrf52/common/src/nrf52_boot_image.c +++ b/boards/arm/nrf52/common/src/nrf52_boot_image.c @@ -33,10 +33,10 @@ #include #include #include +#include #include "nvic.h" #include "arm_internal.h" -#include "barriers.h" /**************************************************************************** * Pre-processor Definitions @@ -85,7 +85,7 @@ static void cleanup_arm_nvic(void) /* Allow any pending interrupts to be recognized */ - ARM_ISB(); + UP_ISB(); cpsid(); /* Disable all interrupts */ diff --git a/boards/arm/nrf53/common/src/nrf53_boot_image.c b/boards/arm/nrf53/common/src/nrf53_boot_image.c index 5dfd844f42..a112caf347 100644 --- a/boards/arm/nrf53/common/src/nrf53_boot_image.c +++ b/boards/arm/nrf53/common/src/nrf53_boot_image.c @@ -33,10 +33,10 @@ #include #include #include +#include #include "nvic.h" #include "arm_internal.h" -#include "barriers.h" /**************************************************************************** * Pre-processor Definitions @@ -85,7 +85,7 @@ static void cleanup_arm_nvic(void) /* Allow any pending interrupts to be recognized */ - ARM_ISB(); + UP_ISB(); cpsid(); /* Disable all interrupts */ diff --git a/boards/arm/nrf91/common/src/nrf91_boot_image.c b/boards/arm/nrf91/common/src/nrf91_boot_image.c index ba13a95d90..0076fa8012 100644 --- a/boards/arm/nrf91/common/src/nrf91_boot_image.c +++ b/boards/arm/nrf91/common/src/nrf91_boot_image.c @@ -33,10 +33,10 @@ #include #include #include +#include #include "nvic.h" #include "arm_internal.h" -#include "barriers.h" /**************************************************************************** * Pre-processor Definitions @@ -103,7 +103,7 @@ static void cleanup_arm_nvic(void) /* Allow any pending interrupts to be recognized */ - ARM_ISB(); + UP_ISB(); cpsid(); /* Disable all interrupts */ @@ -205,7 +205,7 @@ int board_boot_image(const char *path, uint32_t hdr_size) __asm__ __volatile__("\tmsr msp_ns, %0\n" : : "r" (vt.spr)); - ARM_ISB(); + UP_ISB(); /* Check if reset is valid */ diff --git a/boards/arm/samv7/common/src/sam_boot_image.c b/boards/arm/samv7/common/src/sam_boot_image.c index 4e1b0d2b2f..c5518e87b7 100644 --- a/boards/arm/samv7/common/src/sam_boot_image.c +++ b/boards/arm/samv7/common/src/sam_boot_image.c @@ -33,10 +33,10 @@ #include #include #include +#include #include "nvic.h" #include "arm_internal.h" -#include "barriers.h" #ifdef CONFIG_ARM_MPU # include "mpu.h" @@ -91,7 +91,7 @@ static void cleanup_arm_nvic(void) /* Allow any pending interrupts to be recognized */ - ARM_ISB(); + UP_ISB(); cpsid(); /* Disable all interrupts */ diff --git a/boards/arm/stm32h7/nucleo-h743zi/src/stm32_boot_image.c b/boards/arm/stm32h7/nucleo-h743zi/src/stm32_boot_image.c index 7343c3d282..b1b09a3887 100644 --- a/boards/arm/stm32h7/nucleo-h743zi/src/stm32_boot_image.c +++ b/boards/arm/stm32h7/nucleo-h743zi/src/stm32_boot_image.c @@ -33,10 +33,10 @@ #include #include #include +#include #include "nvic.h" #include "arm_internal.h" -#include "barriers.h" /**************************************************************************** * Pre-processor Definitions @@ -85,7 +85,7 @@ static void cleanup_arm_nvic(void) /* Allow any pending interrupts to be recognized */ - ARM_ISB(); + UP_ISB(); cpsid(); /* Disable all interrupts */