Added more granular Kconfig options for STM32G0 line. Added CRS and HSI48 defines to get Nuttx to compile.
Minor formatting change Change G0CX to G0C1 in Kconfig Change HAVE_DAC to HAVE_DAC1
This commit is contained in:
kywwilson11
Alan C. Assis
parent
a0aa654c70
commit
6c1781d523
4 changed files with 280 additions and 54 deletions
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@ -453,274 +453,274 @@ config ARCH_CHIP_STM32F098VC
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config ARCH_CHIP_STM32G070CB
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bool "STM32G070CB"
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select STM32F0L0G0_STM32G0
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select STM32F0L0G0_STM32G070
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select STM32F0L0G0_FLASH_CONFIG_B
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depends on ARCH_CHIP_STM32G0
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config ARCH_CHIP_STM32G070KB
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bool "STM32G070KB"
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select STM32F0L0G0_STM32G0
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select STM32F0L0G0_STM32G070
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select STM32F0L0G0_FLASH_CONFIG_B
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depends on ARCH_CHIP_STM32G0
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config ARCH_CHIP_STM32G070RB
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bool "STM32G070RB"
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select STM32F0L0G0_STM32G0
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select STM32F0L0G0_STM32G070
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select STM32F0L0G0_FLASH_CONFIG_B
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depends on ARCH_CHIP_STM32G0
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config ARCH_CHIP_STM32G071EB
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bool "STM32G071EB"
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select STM32F0L0G0_STM32G0
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select STM32F0L0G0_STM32G071
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select STM32F0L0G0_FLASH_CONFIG_B
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depends on ARCH_CHIP_STM32G0
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config ARCH_CHIP_STM32G071G8
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bool "STM32G071G8"
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select STM32F0L0G0_STM32G0
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select STM32F0L0G0_STM32G071
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select STM32F0L0G0_FLASH_CONFIG_8
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depends on ARCH_CHIP_STM32G0
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config ARCH_CHIP_STM32G071GB
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bool "STM32G071GB"
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select STM32F0L0G0_STM32G0
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select STM32F0L0G0_STM32G071
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select STM32F0L0G0_FLASH_CONFIG_B
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depends on ARCH_CHIP_STM32G0
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config ARCH_CHIP_STM32G071G8XN
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bool "STM32G071G8XN"
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select STM32F0L0G0_STM32G0
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select STM32F0L0G0_STM32G071
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select STM32F0L0G0_FLASH_CONFIG_8
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depends on ARCH_CHIP_STM32G0
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config ARCH_CHIP_STM32G071GBXN
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bool "STM32G071GBXN"
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select STM32F0L0G0_STM32G0
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select STM32F0L0G0_STM32G071
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select STM32F0L0G0_FLASH_CONFIG_B
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depends on ARCH_CHIP_STM32G0
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config ARCH_CHIP_STM32G071K8
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bool "STM32G071K8"
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select STM32F0L0G0_STM32G0
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select STM32F0L0G0_STM32G071
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select STM32F0L0G0_FLASH_CONFIG_8
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depends on ARCH_CHIP_STM32G0
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config ARCH_CHIP_STM32G071KB
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bool "STM32G071KB"
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select STM32F0L0G0_STM32G0
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select STM32F0L0G0_STM32G071
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select STM32F0L0G0_FLASH_CONFIG_B
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depends on ARCH_CHIP_STM32G0
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config ARCH_CHIP_STM32G071K8XN
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bool "STM32G071K8XN"
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select STM32F0L0G0_STM32G0
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select STM32F0L0G0_STM32G071
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select STM32F0L0G0_FLASH_CONFIG_8
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depends on ARCH_CHIP_STM32G0
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config ARCH_CHIP_STM32G071KBXN
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bool "STM32G071KBXN"
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select STM32F0L0G0_STM32G0
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select STM32F0L0G0_STM32G071
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select STM32F0L0G0_FLASH_CONFIG_B
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depends on ARCH_CHIP_STM32G0
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config ARCH_CHIP_STM32G071C8
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bool "STM32G071C8"
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select STM32F0L0G0_STM32G0
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select STM32F0L0G0_STM32G071
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select STM32F0L0G0_FLASH_CONFIG_8
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depends on ARCH_CHIP_STM32G0
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config ARCH_CHIP_STM32G071CB
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bool "STM32G071CB"
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select STM32F0L0G0_STM32G0
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select STM32F0L0G0_STM32G071
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select STM32F0L0G0_FLASH_CONFIG_B
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depends on ARCH_CHIP_STM32G0
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config ARCH_CHIP_STM32G071R8
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bool "STM32G071R8"
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select STM32F0L0G0_STM32G0
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select STM32F0L0G0_STM32G071
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select STM32F0L0G0_FLASH_CONFIG_8
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depends on ARCH_CHIP_STM32G0
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config ARCH_CHIP_STM32G071RB
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bool "STM32G071RB"
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select STM32F0L0G0_STM32G0
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select STM32F0L0G0_STM32G071
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select STM32F0L0G0_FLASH_CONFIG_B
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depends on ARCH_CHIP_STM32G0
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config ARCH_CHIP_STM32G0B1KB
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bool "STM32G0B1KB"
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select STM32F0L0G0_STM32G0
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select STM32F0L0G0_STM32G0B1
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select STM32F0L0G0_FLASH_CONFIG_B
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depends on ARCH_CHIP_STM32G0
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config ARCH_CHIP_STM32G0B1CB
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bool "STM32G0B1CB"
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select STM32F0L0G0_STM32G0
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select STM32F0L0G0_STM32G0B1
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select STM32F0L0G0_FLASH_CONFIG_B
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depends on ARCH_CHIP_STM32G0
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config ARCH_CHIP_STM32G0B1RB
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bool "STM32G0B1RB"
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select STM32F0L0G0_STM32G0
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select STM32F0L0G0_STM32G0B1
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select STM32F0L0G0_FLASH_CONFIG_B
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depends on ARCH_CHIP_STM32G0
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config ARCH_CHIP_STM32G0B1MB
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bool "STM32G0B1MB"
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select STM32F0L0G0_STM32G0
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select STM32F0L0G0_STM32G0B1
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select STM32F0L0G0_FLASH_CONFIG_B
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depends on ARCH_CHIP_STM32G0
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config ARCH_CHIP_STM32G0B1VB
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bool "STM32G0B1VB"
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select STM32F0L0G0_STM32G0
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select STM32F0L0G0_STM32G0B1
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select STM32F0L0G0_FLASH_CONFIG_B
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depends on ARCH_CHIP_STM32G0
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config ARCH_CHIP_STM32G0B1KC
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bool "STM32G0B1KC"
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select STM32F0L0G0_STM32G0
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select STM32F0L0G0_STM32G0B1
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select STM32F0L0G0_FLASH_CONFIG_C
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depends on ARCH_CHIP_STM32G0
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config ARCH_CHIP_STM32G0B1CC
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bool "STM32G0B1CC"
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select STM32F0L0G0_STM32G0
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select STM32F0L0G0_STM32G0B1
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select STM32F0L0G0_FLASH_CONFIG_C
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depends on ARCH_CHIP_STM32G0
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config ARCH_CHIP_STM32G0B1RC
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bool "STM32G0B1RC"
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select STM32F0L0G0_STM32G0
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select STM32F0L0G0_STM32G0B1
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select STM32F0L0G0_FLASH_CONFIG_C
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depends on ARCH_CHIP_STM32G0
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config ARCH_CHIP_STM32G0B1MC
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bool "STM32G0B1MC"
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select STM32F0L0G0_STM32G0
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select STM32F0L0G0_STM32G0B1
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select STM32F0L0G0_FLASH_CONFIG_C
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depends on ARCH_CHIP_STM32G0
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config ARCH_CHIP_STM32G0B1VC
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bool "STM32G0B1VC"
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select STM32F0L0G0_STM32G0
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select STM32F0L0G0_STM32G0B1
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select STM32F0L0G0_FLASH_CONFIG_C
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depends on ARCH_CHIP_STM32G0
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config ARCH_CHIP_STM32G0B1KE
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bool "STM32G0B1KE"
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select STM32F0L0G0_STM32G0
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select STM32F0L0G0_STM32G0B1
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select STM32F0L0G0_FLASH_CONFIG_E
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depends on ARCH_CHIP_STM32G0
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config ARCH_CHIP_STM32G0B1CE
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bool "STM32G0B1CE"
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select STM32F0L0G0_STM32G0
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select STM32F0L0G0_STM32G0B1
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select STM32F0L0G0_FLASH_CONFIG_E
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depends on ARCH_CHIP_STM32G0
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config ARCH_CHIP_STM32G0B1RE
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bool "STM32G0B1RE"
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select STM32F0L0G0_STM32G0
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select STM32F0L0G0_STM32G0B1
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select STM32F0L0G0_FLASH_CONFIG_E
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depends on ARCH_CHIP_STM32G0
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config ARCH_CHIP_STM32G0B1NE
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bool "STM32G0B1NE"
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select STM32F0L0G0_STM32G0
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select STM32F0L0G0_STM32G0B1
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select STM32F0L0G0_FLASH_CONFIG_E
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depends on ARCH_CHIP_STM32G0
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config ARCH_CHIP_STM32G0B1ME
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bool "STM32G0B1ME"
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select STM32F0L0G0_STM32G0
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select STM32F0L0G0_STM32G0B1
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select STM32F0L0G0_FLASH_CONFIG_E
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depends on ARCH_CHIP_STM32G0
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config ARCH_CHIP_STM32G0B1VE
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bool "STM32G0B1VE"
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select STM32F0L0G0_STM32G0
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select STM32F0L0G0_STM32G0B1
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select STM32F0L0G0_FLASH_CONFIG_E
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depends on ARCH_CHIP_STM32G0
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config ARCH_CHIP_STM32G0B1KB
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bool "STM32G0B1KB"
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select STM32F0L0G0_STM32G0
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select STM32F0L0G0_STM32G0B1
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depends on ARCH_CHIP_STM32G0
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config ARCH_CHIP_STM32G0B1CB
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bool "STM32G0B1CB"
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select STM32F0L0G0_STM32G0
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select STM32F0L0G0_STM32G0B1
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depends on ARCH_CHIP_STM32G0
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config ARCH_CHIP_STM32G0B1RB
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bool "STM32G0B1RB"
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select STM32F0L0G0_STM32G0
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select STM32F0L0G0_STM32G0B1
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depends on ARCH_CHIP_STM32G0
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config ARCH_CHIP_STM32G0B1MB
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bool "STM32G0B1MB"
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select STM32F0L0G0_STM32G0
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select STM32F0L0G0_STM32G0B1
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depends on ARCH_CHIP_STM32G0
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config ARCH_CHIP_STM32G0B1VB
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bool "STM32G0B1VB"
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select STM32F0L0G0_STM32G0
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select STM32F0L0G0_STM32G0B1
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depends on ARCH_CHIP_STM32G0
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config ARCH_CHIP_STM32G0B1KC
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bool "STM32G0B1KC"
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select STM32F0L0G0_STM32G0
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select STM32F0L0G0_STM32G0B1
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depends on ARCH_CHIP_STM32G0
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config ARCH_CHIP_STM32G0B1CC
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bool "STM32G0B1CC"
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select STM32F0L0G0_STM32G0
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select STM32F0L0G0_STM32G0B1
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depends on ARCH_CHIP_STM32G0
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config ARCH_CHIP_STM32G0B1RC
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bool "STM32G0B1RC"
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select STM32F0L0G0_STM32G0
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select STM32F0L0G0_STM32G0B1
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depends on ARCH_CHIP_STM32G0
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config ARCH_CHIP_STM32G0B1MC
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bool "STM32G0B1MC"
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select STM32F0L0G0_STM32G0
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select STM32F0L0G0_STM32G0B1
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depends on ARCH_CHIP_STM32G0
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config ARCH_CHIP_STM32G0B1VC
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bool "STM32G0B1VC"
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select STM32F0L0G0_STM32G0
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select STM32F0L0G0_STM32G0B1
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depends on ARCH_CHIP_STM32G0
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config ARCH_CHIP_STM32G0B1KE
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bool "STM32G0B1KE"
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select STM32F0L0G0_STM32G0
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select STM32F0L0G0_STM32G0B1
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depends on ARCH_CHIP_STM32G0
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config ARCH_CHIP_STM32G0B1CE
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bool "STM32G0B1CE"
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select STM32F0L0G0_STM32G0
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select STM32F0L0G0_STM32G0B1
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depends on ARCH_CHIP_STM32G0
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config ARCH_CHIP_STM32G0B1RE
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bool "STM32G0B1RE"
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select STM32F0L0G0_STM32G0
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select STM32F0L0G0_STM32G0B1
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depends on ARCH_CHIP_STM32G0
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config ARCH_CHIP_STM32G0B1NE
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bool "STM32G0B1NE"
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select STM32F0L0G0_STM32G0
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select STM32F0L0G0_STM32G0B1
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depends on ARCH_CHIP_STM32G0
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config ARCH_CHIP_STM32G0B1ME
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bool "STM32G0B1ME"
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select STM32F0L0G0_STM32G0
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select STM32F0L0G0_STM32G0B1
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depends on ARCH_CHIP_STM32G0
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config ARCH_CHIP_STM32G0B1VE
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bool "STM32G0B1VE"
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select STM32F0L0G0_STM32G0
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select STM32F0L0G0_STM32G0B1
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depends on ARCH_CHIP_STM32G0
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config ARCH_CHIP_STM32L053C8
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@ -1200,17 +1200,13 @@ config STM32F0L0G0_STM32F0
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config STM32F0L0G0_STM32G0
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bool
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default n
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select STM32F0L0G0_HAVE_USART3
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select STM32F0L0G0_HAVE_USART4
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select STM32F0L0G0_HAVE_ADC1_DMA
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select STM32F0L0G0_HAVE_DMAMUX
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select STM32F0L0G0_HAVE_IP_USART_V2
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select STM32F0L0G0_HAVE_IP_EXTI_V2
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select STM32F0L0G0_HAVE_TIM1
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select STM32F0L0G0_HAVE_TIM3
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select STM32F0L0G0_HAVE_TIM6
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select STM32F0L0G0_HAVE_TIM7
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select STM32F0L0G0_HAVE_TIM14
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select STM32F0L0G0_HAVE_TIM15
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select STM32F0L0G0_HAVE_TIM16
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select STM32F0L0G0_HAVE_TIM17
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select STM32F0L0G0_HAVE_I2C2
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@ -1267,6 +1263,193 @@ config STM32F0L0G0_STM32F09X
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select STM32F0L0G0_HAVE_HSI48
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select STM32F0L0G0_HAVE_DMA2
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config STM32F0L0G0_STM32G030
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bool
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default n
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select STM32F0L0G0_STM32G0
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config STM32F0L0G0_STM32G031
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bool
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default n
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select STM32F0L0G0_STM32G0
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select STM32F0L0G0_HAVE_LPUART1
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config STM32F0L0G0_STM32G041
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bool
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default n
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select STM32F0L0G0_STM32G0
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select STM32F0L0G0_HAVE_RNG
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select STM32F0L0G0_HAVE_AES
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select STM32F0L0G0_HAVE_LPUART1
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config STM32F0L0G0_STM32G050
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bool
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default n
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select STM32F0L0G0_STM32G0
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select STM32F0L0G0_HAVE_TIM6
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select STM32F0L0G0_HAVE_TIM7
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config STM32F0L0G0_STM32G051
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bool
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default n
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select STM32F0L0G0_STM32G0
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select STM32F0L0G0_HAVE_DAC1
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select STM32F0L0G0_HAVE_COMP1
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select STM32F0L0G0_HAVE_COMP2
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select STM32F0L0G0_HAVE_TIM6
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select STM32F0L0G0_HAVE_TIM7
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select STM32F0L0G0_HAVE_TIM15
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select STM32F0L0G0_HAVE_LPUART1
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config STM32F0L0G0_STM32G061
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bool
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default n
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select STM32F0L0G0_STM32G0
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select STM32F0L0G0_HAVE_RNG
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select STM32F0L0G0_HAVE_AES
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select STM32F0L0G0_HAVE_DAC1
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select STM32F0L0G0_HAVE_COMP1
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select STM32F0L0G0_HAVE_COMP2
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select STM32F0L0G0_HAVE_TIM6
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select STM32F0L0G0_HAVE_TIM7
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select STM32F0L0G0_HAVE_TIM15
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select STM32F0L0G0_HAVE_LPUART1
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config STM32F0L0G0_STM32G070
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bool
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default n
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select STM32F0L0G0_STM32G0
|
||||
select STM32F0L0G0_HAVE_USART3
|
||||
select STM32F0L0G0_HAVE_USART4
|
||||
select STM32F0L0G0_HAVE_TIM6
|
||||
select STM32F0L0G0_HAVE_TIM7
|
||||
select STM32F0L0G0_HAVE_TIM15
|
||||
select STM32F0L0G0_HAVE_UCPD1
|
||||
select STM32F0L0G0_HAVE_UCPD2
|
||||
|
||||
config STM32F0L0G0_STM32G071
|
||||
bool
|
||||
default n
|
||||
select STM32F0L0G0_STM32G0
|
||||
select STM32F0L0G0_HAVE_USART3
|
||||
select STM32F0L0G0_HAVE_USART4
|
||||
select STM32F0L0G0_HAVE_DAC1
|
||||
select STM32F0L0G0_HAVE_COMP1
|
||||
select STM32F0L0G0_HAVE_COMP2
|
||||
select STM32F0L0G0_HAVE_TIM6
|
||||
select STM32F0L0G0_HAVE_TIM7
|
||||
select STM32F0L0G0_HAVE_TIM15
|
||||
select STM32F0L0G0_HAVE_UCPD1
|
||||
select STM32F0L0G0_HAVE_UCPD2
|
||||
select STM32F0L0G0_HAVE_CEC
|
||||
select STM32F0L0G0_HAVE_LPUART1
|
||||
|
||||
config STM32F0L0G0_STM32G081
|
||||
bool
|
||||
default n
|
||||
select STM32F0L0G0_STM32G0
|
||||
select STM32F0L0G0_HAVE_USART3
|
||||
select STM32F0L0G0_HAVE_USART4
|
||||
select STM32F0L0G0_HAVE_RNG
|
||||
select STM32F0L0G0_HAVE_AES
|
||||
select STM32F0L0G0_HAVE_DAC1
|
||||
select STM32F0L0G0_HAVE_COMP1
|
||||
select STM32F0L0G0_HAVE_COMP2
|
||||
select STM32F0L0G0_HAVE_TIM6
|
||||
select STM32F0L0G0_HAVE_TIM7
|
||||
select STM32F0L0G0_HAVE_TIM15
|
||||
select STM32F0L0G0_HAVE_UCPD1
|
||||
select STM32F0L0G0_HAVE_UCPD2
|
||||
select STM32F0L0G0_HAVE_CEC
|
||||
select STM32F0L0G0_HAVE_LPUART1
|
||||
|
||||
config STM32F0L0G0_STM32G0B0
|
||||
bool
|
||||
default n
|
||||
select STM32F0L0G0_STM32G0
|
||||
select STM32F0L0G0_HAVE_DMA2
|
||||
select STM32F0L0G0_HAVE_USART3
|
||||
select STM32F0L0G0_HAVE_USART4
|
||||
select STM32F0L0G0_HAVE_USART5
|
||||
select STM32F0L0G0_HAVE_USART6
|
||||
select STM32F0L0G0_HAVE_LPUART1
|
||||
select STM32F0L0G0_HAVE_LPUART2
|
||||
select STM32F0L0G0_HAVE_CRS
|
||||
select STM32F0L0G0_HAVE_TIM4
|
||||
select STM32F0L0G0_HAVE_TIM6
|
||||
select STM32F0L0G0_HAVE_TIM7
|
||||
select STM32F0L0G0_HAVE_TIM15
|
||||
select STM32F0L0G0_HAVE_I2C3
|
||||
select STM32F0L0G0_HAVE_SPI3
|
||||
select STM32F0L0G0_HAVE_I2S2
|
||||
select STM32F0L0G0_HAVE_USBDEV
|
||||
select STM32F0L0G0_HAVE_UCPD1
|
||||
select STM32F0L0G0_HAVE_UCPD2
|
||||
select STM32F0L0G0_HAVE_HSI48
|
||||
|
||||
config STM32F0L0G0_STM32G0B1
|
||||
bool
|
||||
default n
|
||||
select STM32F0L0G0_STM32G0
|
||||
select STM32F0L0G0_HAVE_DMA2
|
||||
select STM32F0L0G0_HAVE_USART3
|
||||
select STM32F0L0G0_HAVE_USART4
|
||||
select STM32F0L0G0_HAVE_USART5
|
||||
select STM32F0L0G0_HAVE_USART6
|
||||
select STM32F0L0G0_HAVE_LPUART1
|
||||
select STM32F0L0G0_HAVE_LPUART2
|
||||
select STM32F0L0G0_HAVE_CRS
|
||||
select STM32F0L0G0_HAVE_DAC1
|
||||
select STM32F0L0G0_HAVE_COMP1
|
||||
select STM32F0L0G0_HAVE_COMP2
|
||||
select STM32F0L0G0_HAVE_COMP3
|
||||
select STM32F0L0G0_HAVE_TIM4
|
||||
select STM32F0L0G0_HAVE_TIM6
|
||||
select STM32F0L0G0_HAVE_TIM7
|
||||
select STM32F0L0G0_HAVE_TIM15
|
||||
select STM32F0L0G0_HAVE_I2C3
|
||||
select STM32F0L0G0_HAVE_SPI3
|
||||
select STM32F0L0G0_HAVE_I2S2
|
||||
select STM32F0L0G0_HAVE_USBDEV
|
||||
select STM32F0L0G0_HAVE_UCPD1
|
||||
select STM32F0L0G0_HAVE_UCPD2
|
||||
select STM32F0L0G0_HAVE_FDCAN1
|
||||
select STM32F0L0G0_HAVE_FDCAN2
|
||||
select STM32F0L0G0_HAVE_CEC
|
||||
select STM32F0L0G0_HAVE_HSI48
|
||||
|
||||
config STM32F0L0G0_STM32G0C1
|
||||
bool
|
||||
default n
|
||||
select STM32F0L0G0_STM32G0
|
||||
select STM32F0L0G0_HAVE_DMA2
|
||||
select STM32F0L0G0_HAVE_USART3
|
||||
select STM32F0L0G0_HAVE_USART4
|
||||
select STM32F0L0G0_HAVE_USART5
|
||||
select STM32F0L0G0_HAVE_USART6
|
||||
select STM32F0L0G0_HAVE_CRS
|
||||
select STM32F0L0G0_HAVE_RNG
|
||||
select STM32F0L0G0_HAVE_AES
|
||||
select STM32F0L0G0_HAVE_DAC1
|
||||
select STM32F0L0G0_HAVE_COMP1
|
||||
select STM32F0L0G0_HAVE_COMP2
|
||||
select STM32F0L0G0_HAVE_COMP3
|
||||
select STM32F0L0G0_HAVE_TIM4
|
||||
select STM32F0L0G0_HAVE_TIM6
|
||||
select STM32F0L0G0_HAVE_TIM7
|
||||
select STM32F0L0G0_HAVE_TIM15
|
||||
select STM32F0L0G0_HAVE_I2C3
|
||||
select STM32F0L0G0_HAVE_SPI3
|
||||
select STM32F0L0G0_HAVE_I2S2
|
||||
select STM32F0L0G0_HAVE_LPUART2
|
||||
select STM32F0L0G0_HAVE_USBDEV
|
||||
select STM32F0L0G0_HAVE_UCPD1
|
||||
select STM32F0L0G0_HAVE_UCPD2
|
||||
select STM32F0L0G0_HAVE_FDCAN1
|
||||
select STM32F0L0G0_HAVE_FDCAN2
|
||||
select STM32F0L0G0_HAVE_CEC
|
||||
select STM32F0L0G0_HAVE_HSI48
|
||||
|
||||
config STM32F0L0G0_VALUELINE
|
||||
bool
|
||||
default n
|
||||
|
|
@ -1468,6 +1651,14 @@ config STM32F0L0G0_HAVE_USART8
|
|||
bool
|
||||
default n
|
||||
|
||||
config STM32F0L0G0_HAVE_LPUART1
|
||||
bool
|
||||
default n
|
||||
|
||||
config STM32F0L0G0_HAVE_LPUART2
|
||||
bool
|
||||
default n
|
||||
|
||||
config STM32F0L0G0_HAVE_TIM1
|
||||
bool
|
||||
default n
|
||||
|
|
@ -1480,6 +1671,10 @@ config STM32F0L0G0_HAVE_TIM3
|
|||
bool
|
||||
default n
|
||||
|
||||
config STM32F0L0G0_HAVE_TIM4
|
||||
bool
|
||||
default n
|
||||
|
||||
config STM32F0L0G0_HAVE_TIM6
|
||||
bool
|
||||
default n
|
||||
|
|
@ -1532,6 +1727,10 @@ config STM32F0L0G0_HAVE_COMP2
|
|||
bool
|
||||
default n
|
||||
|
||||
config STM32F0L0G0_HAVE_COMP3
|
||||
bool
|
||||
default n
|
||||
|
||||
config STM32F0L0G0_HAVE_DAC1
|
||||
bool
|
||||
default n
|
||||
|
|
@ -1548,6 +1747,10 @@ config STM32F0L0G0_HAVE_RNG
|
|||
bool
|
||||
default n
|
||||
|
||||
config STM32F0L0G0_HAVE_CRS
|
||||
bool
|
||||
default n
|
||||
|
||||
config STM32F0L0G0_HAVE_I2C2
|
||||
bool
|
||||
default n
|
||||
|
|
@ -1596,6 +1799,22 @@ config STM32F0L0G0_HAVE_FDCAN1
|
|||
bool
|
||||
default n
|
||||
|
||||
config STM32F0L0G0_HAVE_FDCAN2
|
||||
bool
|
||||
default n
|
||||
|
||||
config STM32F0L0G0_HAVE_I2S2
|
||||
bool
|
||||
default n
|
||||
|
||||
config STM32F0L0G0_HAVE_UCPD1
|
||||
bool
|
||||
default n
|
||||
|
||||
config STM32F0L0G0_HAVE_UCPD2
|
||||
bool
|
||||
default n
|
||||
|
||||
# These are STM32 peripherals IP blocks
|
||||
|
||||
config STM32F0L0G0_HAVE_IP_USART_V1
|
||||
|
|
|
|||
|
|
@ -74,6 +74,7 @@
|
|||
#define STM32_USART4_BASE 0x40004c00 /* 0x40004c00-0x40004fff USART4 */
|
||||
#define STM32_I2C1_BASE 0x40005400 /* 0x40005400-0x400057ff I2C1 */
|
||||
#define STM32_I2C2_BASE 0x40005800 /* 0x40005800-0x40005bff I2C2 */
|
||||
#define STM32_CRS_BASE 0x40006C00 /* 0x40006C00-0x40006fff CRS */
|
||||
#define STM32_PWR_BASE 0x40007000 /* 0x40007000-0x400073ff PWR */
|
||||
#define STM32_DAC1_BASE 0x40007400 /* 0x40007400-0x400077ff DAC 1 */
|
||||
#define STM32_CEC_BASE 0x40007800 /* 0x40007800-0x40007bff HDMI CEC */
|
||||
|
|
|
|||
|
|
@ -93,7 +93,9 @@
|
|||
#define RCC_CR_HSEBYP (1 << 18) /* Bit 18: External high speed clock bypass */
|
||||
|
||||
#define RCC_CR_CSSON (1 << 19) /* Bit 19: Clock security system enable */
|
||||
/* Bits 20-23: Reserved */
|
||||
/* Bits 20-21: Reserved */
|
||||
#define RCC_CR_HSI48ON (1 << 22) /* Bit 22: HSI48 On */
|
||||
#define RCC_CR_HSI48RDY (1 << 23) /* Bit 23: HSI48 Ready */
|
||||
#define RCC_CR_PLLON (1 << 24) /* Bit 24: PLL enable */
|
||||
#define RCC_CR_PLLRDY (1 << 25) /* Bit 25: PLL clock ready flag */
|
||||
/* Bits 26-27: Reserved */
|
||||
|
|
|
|||
|
|
@ -45,6 +45,10 @@
|
|||
# define STM32_HSI48_REG STM32_RCC_CRRCR
|
||||
# define STM32_HSI48ON RCC_CRRCR_HSI48ON
|
||||
# define STM32_HSI48RDY RCC_CRRCR_HSI48RDY
|
||||
#elif defined(CONFIG_ARCH_CHIP_STM32G0)
|
||||
# define STM32_HSI48_REG STM32_RCC_CR
|
||||
# define STM32_HSI48ON RCC_CR_HSI48ON
|
||||
# define STM32_HSI48RDY RCC_CR_HSI48RDY
|
||||
#else
|
||||
# error "Unsupported STM32F0/L0 HSI48"
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue