From 6fe1f5a96c05199f281fb153b8cd25e0839975cd Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Mon, 8 Jan 2018 10:01:23 -0600 Subject: [PATCH] Squashed commit of the following: arch/mips/src/pic32mz: Commits the basic architecture port for the PIC32MZEF. arch/mips/src/pic32mz: Begin adding PIC32MZEF files. Initial commit are simply PIC32MZEC files with name changes. arch/mips/include/pic32mz: Add support for the PIC32MZEF family. --- arch/mips/include/pic32mz/chip.h | 90 +- arch/mips/include/pic32mz/irq.h | 4 +- arch/mips/include/pic32mz/irq_pic32mzxxxec.h | 21 +- arch/mips/include/pic32mz/irq_pic32mzxxxef.h | 325 ++++ arch/mips/src/pic32mz/Kconfig | 28 +- arch/mips/src/pic32mz/chip/pic32mz-features.h | 4 +- .../mips/src/pic32mz/chip/pic32mz-memorymap.h | 4 +- arch/mips/src/pic32mz/chip/pic32mz-pps.h | 4 +- .../src/pic32mz/chip/pic32mzec-features.h | 8 +- .../src/pic32mz/chip/pic32mzec-memorymap.h | 7 + arch/mips/src/pic32mz/chip/pic32mzec-pps.h | 12 +- .../src/pic32mz/chip/pic32mzef-features.h | 540 ++++++ .../src/pic32mz/chip/pic32mzef-memorymap.h | 147 ++ arch/mips/src/pic32mz/chip/pic32mzef-pps.h | 1719 +++++++++++++++++ arch/mips/src/pic32mz/pic32mz-config.h | 14 + arch/mips/src/pic32mz/pic32mz-head.S | 36 +- configs/flipnclick-sam3x/README.txt | 2 +- 17 files changed, 2929 insertions(+), 36 deletions(-) create mode 100644 arch/mips/include/pic32mz/irq_pic32mzxxxef.h create mode 100644 arch/mips/src/pic32mz/chip/pic32mzef-features.h create mode 100644 arch/mips/src/pic32mz/chip/pic32mzef-memorymap.h create mode 100644 arch/mips/src/pic32mz/chip/pic32mzef-pps.h diff --git a/arch/mips/include/pic32mz/chip.h b/arch/mips/include/pic32mz/chip.h index d36c451525..c54679c66a 100644 --- a/arch/mips/include/pic32mz/chip.h +++ b/arch/mips/include/pic32mz/chip.h @@ -1,7 +1,7 @@ /**************************************************************************** * arch/mips/include/pic32mz/chip.h * - * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Copyright (C) 2015, 2018 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -52,7 +52,8 @@ */ #if defined(CONFIG_ARCH_CHIP_PIC32MZ2048ECH) -# define CHIP_PIC32MZEC 1 +# define CHIP_PIC32MZEC 1 /* PIC32MZEC family */ +# undef CHIP_PIC32MZEF /* Not PIC32MZEF family */ # define CHIP_BOOTFLASH_KB 160 /* 160Kb boot FLASH */ # define CHIP_PROGFLASH_KB 2048 /* 2048Kb program FLASH */ # define CHIP_DATAMEM_KB 512 /* 512Kb data memory */ @@ -63,7 +64,7 @@ # define CHIP_UARTFIFOD 8 /* 8 level deep UART FIFOs */ # define CHIP_NSPI 6 /* 6 SPI/I2S interfaces */ # define CHIP_NCAN 2 /* 2 CAN interfaces */ -# define CHIP_NCRTYPO 0 /* No crtypo support */ +# define CHIP_NCRTYPO 0 /* No crypto support */ # define CHIP_RNG 1 /* 1 Random number generator */ # define CHIP_NDMACH 8 /* 8 programmable DMA channels */ # define CHIP_NUSBDMACHAN 16 /* 16 dedicated DMA channels */ @@ -86,7 +87,8 @@ */ #elif defined(CONFIG_ARCH_CHIP_PIC32MZ2048ECM) -# define CHIP_PIC32MZEC 1 +# define CHIP_PIC32MZEC 1 /* PIC32MZEC family */ +# undef CHIP_PIC32MZEF /* Not PIC32MZEF family */ # define CHIP_BOOTFLASH_KB 160 /* 160Kb boot FLASH */ # define CHIP_PROGFLASH_KB 2048 /* 2048Kb program FLASH */ # define CHIP_DATAMEM_KB 512 /* 512Kb data memory */ @@ -97,7 +99,85 @@ # define CHIP_UARTFIFOD 8 /* 8 level deep UART FIFOs */ # define CHIP_NSPI 6 /* 6 SPI/I2S interfaces */ # define CHIP_NCAN 2 /* 2 CAN interfaces */ -# define CHIP_NCRTYPO 1 /* Has crtypo support */ +# define CHIP_NCRTYPO 1 /* Has crypto support */ +# define CHIP_RNG 1 /* 1 Random number generator */ +# define CHIP_NDMACH 8 /* 8 programmable DMA channels */ +# define CHIP_NUSBDMACHAN 18 /* 18 dedicated DMA channels */ +# define CHIP_NADC10 48 /* 48 ADC channels */ +# define CHIP_NCM 2 /* 2 Analog comparators */ +# define CHIP_USBHSOTG 1 /* 1 USB 2.0 HSOTG */ +# define CHIP_NI2C 5 /* 5 I2C interfaces */ +# define CHIP_NPMP 1 /* Have parallel master port */ +# define CHIP_NEBI 1 /* Have eternal bus interface */ +# define CHIP_NSQI 1 /* 1 Serial quad interface */ +# define CHIP_NRTCC 1 /* Has RTCC */ +# define CHIP_NETHERNET 1 /* 1 Ethernet MAC */ +# define CHIP_NPORTS 10 /* 10 ports (A-H, J-K) */ +# define CHIP_NJTAG 1 /* Has JTAG */ +# define CHIP_NTRACE 1 /* Has trace capability */ + +/* Available in 64/100/124/144 pin packages. Description here is specifically + * for the 124 and 144 pin packages (PIC32MZ2048EFH1100, and + * PIC32MZ2048EFH144). The PIC32MZ2048EFH1100 differs in that it has only + * 40 ADC channels. The PIC32MZ2048EFH1064 differs in that it has only 24 ADC + * channels, two fewer SPI/I2S, one fewer I2C, and no EBI. There are + * additional differences between all family members in the number of pins + * how they may be mapped. + */ + +#elif defined(CONFIG_ARCH_CHIP_PIC32MZ2048EFH) +# undef CHIP_PIC32MZEC /* Not PIC32MZEC family */ +# define CHIP_PIC32MZEF 1 /* PIC32MZEF family */ +# define CHIP_BOOTFLASH_KB 160 /* 160Kb boot FLASH */ +# define CHIP_PROGFLASH_KB 2048 /* 2048Kb program FLASH */ +# define CHIP_DATAMEM_KB 512 /* 512Kb data memory */ +# define CHIP_NTIMERS 9 /* 5 timers */ +# define CHIP_NIC 9 /* 5 input capture */ +# define CHIP_NOC 9 /* 5 output compare */ +# define CHIP_NUARTS 6 /* 6 UARTS */ +# define CHIP_UARTFIFOD 8 /* 8 level deep UART FIFOs */ +# define CHIP_NSPI 6 /* 6 SPI/I2S interfaces */ +# define CHIP_NCAN 2 /* 2 CAN 2.0B interfaces */ +# define CHIP_NCRTYPO 0 /* No crypto support */ +# define CHIP_RNG 1 /* 1 Random number generator */ +# define CHIP_NDMACH 8 /* 8 programmable DMA channels */ +# define CHIP_NUSBDMACHAN 16 /* 16 dedicated DMA channels */ +# define CHIP_NADC10 48 /* 48 ADC channels */ +# define CHIP_NCM 2 /* 2 Analog comparators */ +# define CHIP_USBHSOTG 1 /* 1 USB 2.0 HSOTG */ +# define CHIP_NI2C 5 /* 5 I2C interfaces */ +# define CHIP_NPMP 1 /* Have parallel master port */ +# define CHIP_NEBI 1 /* Have eternal bus interface */ +# define CHIP_NSQI 1 /* 1 Serial quad interface */ +# define CHIP_NRTCC 1 /* Has RTCC */ +# define CHIP_NETHERNET 1 /* 1 Ethernet MAC */ +# define CHIP_NPORTS 10 /* 10 ports (A-H, J-K) */ +# define CHIP_NJTAG 1 /* Has JTAG */ +# define CHIP_NTRACE 1 /* Has trace capability */ + +/* Available in 64/100/124/144 pin packages. Description here is specifically + * for the 124, and 144 pin packages (PIC32MZ2048EFM124, and + * PIC32MZ2048EFH144). The PIC32MZ2048EFM100 differs in that it has only 40 + * ADC channels. The PIC32MZ2048EFM064 differs in that it has only 24 ADC + * channels, two fewer SPI/I2S, one fewer I2C, and no EBI. There are + * additional differences between all family members in the number of pins + * how they may be mapped. + */ + +#elif defined(CONFIG_ARCH_CHIP_PIC32MZ2048EFM) +# undef CHIP_PIC32MZEC /* Not PIC32MZEC family */ +# define CHIP_PIC32MZEF 1 /* PIC32MZEF family */ +# define CHIP_BOOTFLASH_KB 160 /* 160Kb boot FLASH */ +# define CHIP_PROGFLASH_KB 2048 /* 2048Kb program FLASH */ +# define CHIP_DATAMEM_KB 512 /* 512Kb data memory */ +# define CHIP_NTIMERS 9 /* 5 timers */ +# define CHIP_NIC 9 /* 5 input capture */ +# define CHIP_NOC 9 /* 5 output compare */ +# define CHIP_NUARTS 6 /* 6 UARTS */ +# define CHIP_UARTFIFOD 8 /* 8 level deep UART FIFOs */ +# define CHIP_NSPI 6 /* 6 SPI/I2S interfaces */ +# define CHIP_NCAN 2 /* 2 CAN 2.0B interfaces */ +# define CHIP_NCRTYPO 1 /* Has crypto support */ # define CHIP_RNG 1 /* 1 Random number generator */ # define CHIP_NDMACH 8 /* 8 programmable DMA channels */ # define CHIP_NUSBDMACHAN 18 /* 18 dedicated DMA channels */ diff --git a/arch/mips/include/pic32mz/irq.h b/arch/mips/include/pic32mz/irq.h index f00dc0beba..06d36b0d06 100644 --- a/arch/mips/include/pic32mz/irq.h +++ b/arch/mips/include/pic32mz/irq.h @@ -1,7 +1,7 @@ /**************************************************************************** * arch/mips/include/pic32mz/irq.h * - * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Copyright (C) 2015, 2018 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -49,6 +49,8 @@ #if defined(CHIP_PIC32MZEC) # include +#elif defined(CHIP_PIC32MZEF) +# include #else # error "Unknown PIC32MZ family #endif diff --git a/arch/mips/include/pic32mz/irq_pic32mzxxxec.h b/arch/mips/include/pic32mz/irq_pic32mzxxxec.h index 64c0727c4d..bbbd534adc 100644 --- a/arch/mips/include/pic32mz/irq_pic32mzxxxec.h +++ b/arch/mips/include/pic32mz/irq_pic32mzxxxec.h @@ -62,6 +62,7 @@ #define PIC32MZ_IRQ_OC1 7 /* Vector: 7, Output Compare 1 */ #define PIC32MZ_IRQ_INT1 8 /* Vector: 8, External Interrupt 1 */ #define PIC32MZ_IRQ_T2 9 /* Vector: 9, Timer 2 */ + #define PIC32MZ_IRQ_ICE2 10 /* Vector: 10, Input Capture 2 Error */ #define PIC32MZ_IRQ_IC2 11 /* Vector: 11, Input Capture 2 */ #define PIC32MZ_IRQ_OC2 12 /* Vector: 12, Output Compare 2 */ @@ -72,6 +73,7 @@ #define PIC32MZ_IRQ_OC3 17 /* Vector: 17, Output Compare 3 */ #define PIC32MZ_IRQ_INT3 18 /* Vector: 18, External Interrupt 3 */ #define PIC32MZ_IRQ_T4 19 /* Vector: 19, Timer 4 */ + #define PIC32MZ_IRQ_ICE4 20 /* Vector: 20, Input Capture 4 Error */ #define PIC32MZ_IRQ_IC4 21 /* Vector: 21, Input Capture 4 */ #define PIC32MZ_IRQ_OC4 22 /* Vector: 22, Output Compare 4 */ @@ -82,6 +84,7 @@ #define PIC32MZ_IRQ_OC5 27 /* Vector: 27, Output Compare 5 */ #define PIC32MZ_IRQ_T6 28 /* Vector: 28, Timer 6 */ #define PIC32MZ_IRQ_ICE6 29 /* Vector: 29, Input Capture 6 Error */ + #define PIC32MZ_IRQ_IC6 30 /* Vector: 30, Input Capture 6 */ #define PIC32MZ_IRQ_OC6 31 /* Vector: 31, Output Compare 6 */ #define PIC32MZ_IRQ_T7 32 /* Vector: 32, Timer 7 */ @@ -92,6 +95,7 @@ #define PIC32MZ_IRQ_ICE8 37 /* Vector: 37, Input Capture 8 Error */ #define PIC32MZ_IRQ_IC8 38 /* Vector: 38, Input Capture 8 */ #define PIC32MZ_IRQ_OC8 39 /* Vector: 39, Output Compare 8 */ + #define PIC32MZ_IRQ_T9 40 /* Vector: 40, Timer 9 */ #define PIC32MZ_IRQ_ICE9 41 /* Vector: 41, Input Capture 9 Error */ #define PIC32MZ_IRQ_IC9 42 /* Vector: 42, Input Capture 9 */ @@ -102,6 +106,7 @@ #define PIC32MZ_IRQ_AD1CMP2 47 /* Vector: 47, ADC1 Digital Comparator 2 */ #define PIC32MZ_IRQ_AD1CMP3 48 /* Vector: 48, ADC1 Digital Comparator 3 */ #define PIC32MZ_IRQ_AD1CMP4 49 /* Vector: 49, ADC1 Digital Comparator 4 */ + #define PIC32MZ_IRQ_AD1CMP5 50 /* Vector: 50, ADC1 Digital Comparator 5 */ #define PIC32MZ_IRQ_AD1CMP6 51 /* Vector: 51, ADC1 Digital Comparator 6 */ #define PIC32MZ_IRQ_AD1FLT1 52 /* Vector: 52, ADC1 Digital Filter 1 */ @@ -112,6 +117,7 @@ #define PIC32MZ_IRQ_AD1FLT6 57 /* Vector: 57, ADC1 Digital Filter 6 */ /* Vector: 58, Reserved */ #define PIC32MZ_IRQ_AD1DAT0 59 /* Vector: 59, ADC1 Data 0 */ + #define PIC32MZ_IRQ_AD1DAT1 60 /* Vector: 60, ADC1 Data 1 */ #define PIC32MZ_IRQ_AD1DAT2 61 /* Vector: 61, ADC1 Data 2 */ #define PIC32MZ_IRQ_AD1DAT3 62 /* Vector: 62, ADC1 Data 3 */ @@ -122,6 +128,7 @@ #define PIC32MZ_IRQ_AD1DAT8 67 /* Vector: 67, ADC1 Data 8 */ #define PIC32MZ_IRQ_AD1DAT9 68 /* Vector: 68, ADC1 Data 9 */ #define PIC32MZ_IRQ_AD1DAT10 69 /* Vector: 69, ADC1 Data 10 */ + #define PIC32MZ_IRQ_AD1DAT11 70 /* Vector: 70, ADC1 Data 11 */ #define PIC32MZ_IRQ_AD1DAT12 71 /* Vector: 71, ADC1 Data 12 */ #define PIC32MZ_IRQ_AD1DAT13 72 /* Vector: 72, ADC1 Data 13 */ @@ -132,6 +139,7 @@ #define PIC32MZ_IRQ_AD1DAT18 77 /* Vector: 77, ADC1 Data 18 */ #define PIC32MZ_IRQ_AD1DAT19 78 /* Vector: 78, ADC1 Data 19 */ #define PIC32MZ_IRQ_AD1DAT20 79 /* Vector: 79, ADC1 Data 20 */ + #define PIC32MZ_IRQ_AD1DAT21 80 /* Vector: 80, ADC1 Data 21 */ #define PIC32MZ_IRQ_AD1DAT22 81 /* Vector: 81, ADC1 Data 22 */ #define PIC32MZ_IRQ_AD1DAT23 82 /* Vector: 82, ADC1 Data 23 */ @@ -142,6 +150,7 @@ #define PIC32MZ_IRQ_AD1DAT28 87 /* Vector: 87, ADC1 Data 28 */ #define PIC32MZ_IRQ_AD1DAT29 88 /* Vector: 88, ADC1 Data 29 */ #define PIC32MZ_IRQ_AD1DAT30 89 /* Vector: 89, ADC1 Data 30 */ + #define PIC32MZ_IRQ_AD1DAT31 90 /* Vector: 90, ADC1 Data 31 */ #define PIC32MZ_IRQ_AD1DAT32 91 /* Vector: 91, ADC1 Data 32 */ #define PIC32MZ_IRQ_AD1DAT33 92 /* Vector: 92, ADC1 Data 33 */ @@ -152,6 +161,7 @@ #define PIC32MZ_IRQ_AD1DAT38 97 /* Vector: 97, ADC1 Data 38 */ #define PIC32MZ_IRQ_AD1DAT39 98 /* Vector: 98, ADC1 Data 39 */ #define PIC32MZ_IRQ_AD1DAT40 99 /* Vector: 99, ADC1 Data 40 */ + #define PIC32MZ_IRQ_AD1DAT41 100 /* Vector: 100, ADC1 Data 41 */ #define PIC32MZ_IRQ_AD1DAT42 101 /* Vector: 101, ADC1 Data 42 */ #define PIC32MZ_IRQ_AD1DAT43 102 /* Vector: 102, ADC1 Data 43 */ @@ -162,6 +172,7 @@ #define PIC32MZ_IRQ_CTYPTO 107 /* Vector: 107, Crypto Engine Event */ /* Vector: 108, Reserved */ #define PIC32MZ_IRQ_SPI1F 109 /* Vector: 109, SPI1 Fault */ + #define PIC32MZ_IRQ_SPI1RX 110 /* Vector: 110, SPI1 Receive Done */ #define PIC32MZ_IRQ_SPI1TX 111 /* Vector: 111, SPI1 Transfer Done */ #define PIC32MZ_IRQ_U1E 112 /* Vector: 112, UART1 Fault */ @@ -172,6 +183,7 @@ #define PIC32MZ_IRQ_I2C1M 117 /* Vector: 117, I2C1 Master Event */ #define PIC32MZ_IRQ_PORTA 118 /* Vector: 118, PORTA Input Change Interrupt */ #define PIC32MZ_IRQ_PORTB 119 /* Vector: 119, PORTB Input Change Interrupt */ + #define PIC32MZ_IRQ_PORTC 120 /* Vector: 120, PORTC Input Change Interrupt */ #define PIC32MZ_IRQ_PORTD 121 /* Vector: 121, PORTD Input Change Interrupt */ #define PIC32MZ_IRQ_PORTE 122 /* Vector: 122, PORTE Input Change Interrupt */ @@ -182,6 +194,7 @@ #define PIC32MZ_IRQ_PORTK 127 /* Vector: 127, PORTK Input Change Interrupt */ #define PIC32MZ_IRQ_PMP 128 /* Vector: 128, Parallel Master Port */ #define PIC32MZ_IRQ_PMPE 129 /* Vector: 129, Parallel Master Port Error */ + #define PIC32MZ_IRQ_CMP1 130 /* Vector: 130, Comparator 1 Interrupt */ #define PIC32MZ_IRQ_CMP2 131 /* Vector: 131, Comparator 2 Interrupt */ #define PIC32MZ_IRQ_USBGEN 132 /* Vector: 132, USB General Event */ @@ -192,6 +205,7 @@ #define PIC32MZ_IRQ_DMA3 137 /* Vector: 137, DMA Channel 3 */ #define PIC32MZ_IRQ_DMA4 138 /* Vector: 138, DMA Channel 4 */ #define PIC32MZ_IRQ_DMA5 139 /* Vector: 139, DMA Channel 5 */ + #define PIC32MZ_IRQ_DMA6 140 /* Vector: 140, DMA Channel 6 */ #define PIC32MZ_IRQ_DMA7 141 /* Vector: 141, DMA Channel 7 */ #define PIC32MZ_IRQ_SPI2F 142 /* Vector: 142, SPI2 Fault */ @@ -202,6 +216,7 @@ #define PIC32MZ_IRQ_U2TX 147 /* Vector: 147, UART2 Transfer Done */ #define PIC32MZ_IRQ_I2C2COL 148 /* Vector: 148, I2C2 Bus Collision Event */ #define PIC32MZ_IRQ_I2C2S 149 /* Vector: 149, I2C2 Slave Event */ + #define PIC32MZ_IRQ_I2C2M 150 /* Vector: 150, I2C2 Master Event */ #define PIC32MZ_IRQ_CAN1 151 /* Vector: 151, Control Area Network 1 */ #define PIC32MZ_IRQ_CAN2 152 /* Vector: 152, Control Area Network 2 */ @@ -212,7 +227,8 @@ #define PIC32MZ_IRQ_U3E 157 /* Vector: 157, UART3 Fault */ #define PIC32MZ_IRQ_U3RX 158 /* Vector: 158, UART3 Receive Done */ #define PIC32MZ_IRQ_U3TX 159 /* Vector: 159, UART3 Transfer Done */ -#define PIC32MZ_IRQ_I2C3COL 160 /* Vector: 160, I2C3 Bus Collision Event */ + +#define PIC32MZ_IRQ_I2C3COL 160 /* Vector: 160, I2C3 Bus Collision Event */ #define PIC32MZ_IRQ_I2C3S 161 /* Vector: 161, I2C3 Slave Event */ #define PIC32MZ_IRQ_I2C3M 162 /* Vector: 162, I2C3 Master Event */ #define PIC32MZ_IRQ_SPI4F 163 /* Vector: 163, SPI4 Fault */ @@ -222,6 +238,7 @@ #define PIC32MZ_IRQ_FCE 167 /* Vector: 167, Flash Control Event */ #define PIC32MZ_IRQ_PMSEC 168 /* Vector: 168, Prefetch Module SEC Event */ #define PIC32MZ_IRQ_SQI1 169 /* Vector: 169, SQI1 Event */ + #define PIC32MZ_IRQ_U4E 170 /* Vector: 170, UART4 Fault */ #define PIC32MZ_IRQ_U4RX 171 /* Vector: 171, UART4 Receive Done */ #define PIC32MZ_IRQ_U4TX 172 /* Vector: 172, UART4 Transfer Done */ @@ -232,6 +249,7 @@ #define PIC32MZ_IRQ_SPI5RX 177 /* Vector: 177, SPI5 Receive Done */ #define PIC32MZ_IRQ_SPI5TX 178 /* Vector: 178, SPI5 Transfer Done */ #define PIC32MZ_IRQ_U5E 179 /* Vector: 179, UART5 Fault */ + #define PIC32MZ_IRQ_U5RX 180 /* Vector: 180, UART5 Receive Done */ #define PIC32MZ_IRQ_U5TX 181 /* Vector: 181, UART5 Transfer Done */ #define PIC32MZ_IRQ_I2C5COL 182 /* Vector: 182, I2C5 Bus Collision Event */ @@ -242,6 +260,7 @@ #define PIC32MZ_IRQ_SPI6TX 187 /* Vector: 187, SPI6 Transfer Done */ #define PIC32MZ_IRQ_U6E 188 /* Vector: 188, UART6 Fault */ #define PIC32MZ_IRQ_U6RX 189 /* Vector: 189, UART6 Receive Done */ + #define PIC32MZ_IRQ_U6TX 190 /* Vector: 190, UART6 Transfer Done */ #define PIC32MZ_IRQ_BAD 191 /* Not a real IRQ number */ diff --git a/arch/mips/include/pic32mz/irq_pic32mzxxxef.h b/arch/mips/include/pic32mz/irq_pic32mzxxxef.h new file mode 100644 index 0000000000..e1e1dd6d75 --- /dev/null +++ b/arch/mips/include/pic32mz/irq_pic32mzxxxef.h @@ -0,0 +1,325 @@ +/**************************************************************************** + * arch/mips/include/pic32mz/irq_pic32mzxxxef.h + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/* This file should never be included directed but, rather, only indirectly + * through nuttx/irq.h + */ + +#ifndef __ARCH_MIPS_INCLUDE_PIC32MZ_IRQ_PIC32MZXXXEF_H +#define __ARCH_MIPS_INCLUDE_PIC32MZ_IRQ_PIC32MZXXXEF_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Interrupt vector numbers. These should be used to attach to interrupts + * and to change interrupt priorities. + */ + +#define PIC32MZ_IRQ_CT 0 /* Vector: 0, Core Timer Interrupt */ +#define PIC32MZ_IRQ_CS0 1 /* Vector: 1, Core Software Interrupt 0 */ +#define PIC32MZ_IRQ_CS1 2 /* Vector: 2, Core Software Interrupt 1 */ +#define PIC32MZ_IRQ_INT0 3 /* Vector: 3, External Interrupt 0 */ +#define PIC32MZ_IRQ_T1 4 /* Vector: 4, Timer 1 */ +#define PIC32MZ_IRQ_ICE1 5 /* Vector: 5, Input Capture 1 Error */ +#define PIC32MZ_IRQ_IC1 6 /* Vector: 6, Input Capture 1 */ +#define PIC32MZ_IRQ_OC1 7 /* Vector: 7, Output Compare 1 */ +#define PIC32MZ_IRQ_INT1 8 /* Vector: 8, External Interrupt 1 */ +#define PIC32MZ_IRQ_T2 9 /* Vector: 9, Timer 2 */ + +#define PIC32MZ_IRQ_ICE2 10 /* Vector: 10, Input Capture 2 Error */ +#define PIC32MZ_IRQ_IC2 11 /* Vector: 11, Input Capture 2 */ +#define PIC32MZ_IRQ_OC2 12 /* Vector: 12, Output Compare 2 */ +#define PIC32MZ_IRQ_INT2 13 /* Vector: 13, External Interrupt 2 */ +#define PIC32MZ_IRQ_T3 14 /* Vector: 14, Timer 3 */ +#define PIC32MZ_IRQ_ICE3 15 /* Vector: 15, Input Capture 3 Error */ +#define PIC32MZ_IRQ_IC3 16 /* Vector: 16, Input Capture 3 */ +#define PIC32MZ_IRQ_OC3 17 /* Vector: 17, Output Compare 3 */ +#define PIC32MZ_IRQ_INT3 18 /* Vector: 18, External Interrupt 3 */ +#define PIC32MZ_IRQ_T4 19 /* Vector: 19, Timer 4 */ + +#define PIC32MZ_IRQ_ICE4 20 /* Vector: 20, Input Capture 4 Error */ +#define PIC32MZ_IRQ_IC4 21 /* Vector: 21, Input Capture 4 */ +#define PIC32MZ_IRQ_OC4 22 /* Vector: 22, Output Compare 4 */ +#define PIC32MZ_IRQ_INT4 23 /* Vector: 23, External Interrupt 4 */ +#define PIC32MZ_IRQ_T5 24 /* Vector: 24, Timer 5 */ +#define PIC32MZ_IRQ_ICE5 25 /* Vector: 25, Input Capture 5 Error */ +#define PIC32MZ_IRQ_IC5 26 /* Vector: 26, Input Capture 5 */ +#define PIC32MZ_IRQ_OC5 27 /* Vector: 27, Output Compare 5 */ +#define PIC32MZ_IRQ_T6 28 /* Vector: 28, Timer 6 */ +#define PIC32MZ_IRQ_ICE6 29 /* Vector: 29, Input Capture 6 Error */ + +#define PIC32MZ_IRQ_IC6 30 /* Vector: 30, Input Capture 6 */ +#define PIC32MZ_IRQ_OC6 31 /* Vector: 31, Output Compare 6 */ +#define PIC32MZ_IRQ_T7 32 /* Vector: 32, Timer 7 */ +#define PIC32MZ_IRQ_ICE7 33 /* Vector: 33, Input Capture 7 Error */ +#define PIC32MZ_IRQ_IC7 34 /* Vector: 34, Input Capture 7 */ +#define PIC32MZ_IRQ_OC7 35 /* Vector: 35, Output Compare 7 */ +#define PIC32MZ_IRQ_T8 36 /* Vector: 36, Timer 8 */ +#define PIC32MZ_IRQ_ICE8 37 /* Vector: 37, Input Capture 8 Error */ +#define PIC32MZ_IRQ_IC8 38 /* Vector: 38, Input Capture 8 */ +#define PIC32MZ_IRQ_OC8 39 /* Vector: 39, Output Compare 8 */ + +#define PIC32MZ_IRQ_T9 40 /* Vector: 40, Timer 9 */ +#define PIC32MZ_IRQ_ICE9 41 /* Vector: 41, Input Capture 9 Error */ +#define PIC32MZ_IRQ_IC9 42 /* Vector: 42, Input Capture 9 */ +#define PIC32MZ_IRQ_OC9 43 /* Vector: 43, Output Compare 9 */ +#define PIC32MZ_IRQ_AD1 44 /* Vector: 44, ADC1 Global Interrupt */ +#define PIC32MZ_IRQ_AD1FIFO 45 /* Vector: 45, ADC1 FIFO Data Ready Interrupt */ +#define PIC32MZ_IRQ_AD1CMP1 46 /* Vector: 46, ADC1 Digital Comparator 1 */ +#define PIC32MZ_IRQ_AD1CMP2 47 /* Vector: 47, ADC1 Digital Comparator 2 */ +#define PIC32MZ_IRQ_AD1CMP3 48 /* Vector: 48, ADC1 Digital Comparator 3 */ +#define PIC32MZ_IRQ_AD1CMP4 49 /* Vector: 49, ADC1 Digital Comparator 4 */ + +#define PIC32MZ_IRQ_AD1CMP5 50 /* Vector: 50, ADC1 Digital Comparator 5 */ +#define PIC32MZ_IRQ_AD1CMP6 51 /* Vector: 51, ADC1 Digital Comparator 6 */ +#define PIC32MZ_IRQ_AD1FLT1 52 /* Vector: 52, ADC1 Digital Filter 1 */ +#define PIC32MZ_IRQ_AD1FLT2 53 /* Vector: 53, ADC1 Digital Filter 2 */ +#define PIC32MZ_IRQ_AD1FLT3 54 /* Vector: 54, ADC1 Digital Filter 3 */ +#define PIC32MZ_IRQ_AD1FLT4 55 /* Vector: 55, ADC1 Digital Filter 4 */ +#define PIC32MZ_IRQ_AD1FLT5 56 /* Vector: 56, ADC1 Digital Filter 5 */ +#define PIC32MZ_IRQ_AD1FLT6 57 /* Vector: 57, ADC1 Digital Filter 6 */ +#define PIC32MZ_IRQ_AD1FAULT 59 /* Vector: 58, ADC1 Fault */ +#define PIC32MZ_IRQ_AD1DAT0 59 /* Vector: 59, ADC1 Data 0 */ + +#define PIC32MZ_IRQ_AD1DAT1 60 /* Vector: 60, ADC1 Data 1 */ +#define PIC32MZ_IRQ_AD1DAT2 61 /* Vector: 61, ADC1 Data 2 */ +#define PIC32MZ_IRQ_AD1DAT3 62 /* Vector: 62, ADC1 Data 3 */ +#define PIC32MZ_IRQ_AD1DAT4 63 /* Vector: 63, ADC1 Data 4 */ +#define PIC32MZ_IRQ_AD1DAT5 64 /* Vector: 64, ADC1 Data 5 */ +#define PIC32MZ_IRQ_AD1DAT6 65 /* Vector: 65, ADC1 Data 6 */ +#define PIC32MZ_IRQ_AD1DAT7 66 /* Vector: 66, ADC1 Data 7 */ +#define PIC32MZ_IRQ_AD1DAT8 67 /* Vector: 67, ADC1 Data 8 */ +#define PIC32MZ_IRQ_AD1DAT9 68 /* Vector: 68, ADC1 Data 9 */ +#define PIC32MZ_IRQ_AD1DAT10 69 /* Vector: 69, ADC1 Data 10 */ + +#define PIC32MZ_IRQ_AD1DAT11 70 /* Vector: 70, ADC1 Data 11 */ +#define PIC32MZ_IRQ_AD1DAT12 71 /* Vector: 71, ADC1 Data 12 */ +#define PIC32MZ_IRQ_AD1DAT13 72 /* Vector: 72, ADC1 Data 13 */ +#define PIC32MZ_IRQ_AD1DAT14 73 /* Vector: 73, ADC1 Data 14 */ +#define PIC32MZ_IRQ_AD1DAT15 74 /* Vector: 74, ADC1 Data 15 */ +#define PIC32MZ_IRQ_AD1DAT16 75 /* Vector: 75, ADC1 Data 16 */ +#define PIC32MZ_IRQ_AD1DAT17 76 /* Vector: 76, ADC1 Data 17 */ +#define PIC32MZ_IRQ_AD1DAT18 77 /* Vector: 77, ADC1 Data 18 */ +#define PIC32MZ_IRQ_AD1DAT19 78 /* Vector: 78, ADC1 Data 19 */ +#define PIC32MZ_IRQ_AD1DAT20 79 /* Vector: 79, ADC1 Data 20 */ + +#define PIC32MZ_IRQ_AD1DAT21 80 /* Vector: 80, ADC1 Data 21 */ +#define PIC32MZ_IRQ_AD1DAT22 81 /* Vector: 81, ADC1 Data 22 */ +#define PIC32MZ_IRQ_AD1DAT23 82 /* Vector: 82, ADC1 Data 23 */ +#define PIC32MZ_IRQ_AD1DAT24 83 /* Vector: 83, ADC1 Data 24 */ +#define PIC32MZ_IRQ_AD1DAT25 84 /* Vector: 84, ADC1 Data 25 */ +#define PIC32MZ_IRQ_AD1DAT26 85 /* Vector: 85, ADC1 Data 26 */ +#define PIC32MZ_IRQ_AD1DAT27 86 /* Vector: 86, ADC1 Data 27 */ +#define PIC32MZ_IRQ_AD1DAT28 87 /* Vector: 87, ADC1 Data 28 */ +#define PIC32MZ_IRQ_AD1DAT29 88 /* Vector: 88, ADC1 Data 29 */ +#define PIC32MZ_IRQ_AD1DAT30 89 /* Vector: 89, ADC1 Data 30 */ + +#define PIC32MZ_IRQ_AD1DAT31 90 /* Vector: 90, ADC1 Data 31 */ +#define PIC32MZ_IRQ_AD1DAT32 91 /* Vector: 91, ADC1 Data 32 */ +#define PIC32MZ_IRQ_AD1DAT33 92 /* Vector: 92, ADC1 Data 33 */ +#define PIC32MZ_IRQ_AD1DAT34 93 /* Vector: 93, ADC1 Data 34 */ +#define PIC32MZ_IRQ_AD1DAT35 94 /* Vector: 94, ADC1 Data 35 */ +#define PIC32MZ_IRQ_AD1DAT36 95 /* Vector: 95, ADC1 Data 36 */ +#define PIC32MZ_IRQ_AD1DAT37 96 /* Vector: 96, ADC1 Data 37 */ +#define PIC32MZ_IRQ_AD1DAT38 97 /* Vector: 97, ADC1 Data 38 */ +#define PIC32MZ_IRQ_AD1DAT39 98 /* Vector: 98, ADC1 Data 39 */ +#define PIC32MZ_IRQ_AD1DAT40 99 /* Vector: 99, ADC1 Data 40 */ + +#define PIC32MZ_IRQ_AD1DAT41 100 /* Vector: 100, ADC1 Data 41 */ +#define PIC32MZ_IRQ_AD1DAT42 101 /* Vector: 101, ADC1 Data 42 */ +#define PIC32MZ_IRQ_AD1DAT43 102 /* Vector: 102, ADC1 Data 43 */ +#define PIC32MZ_IRQ_AD1DAT44 103 /* Vector: 103, ADC1 Data 44 */ +#define PIC32MZ_IRQ_COREPERF 104 /* Vector: 104, Core Performance Counter Interrupt */ +#define PIC32MZ_IRQ_COREFDBG 105 /* Vector: 105, Core Fast Debug Channel Interrupt */ +#define PIC32MZ_IRQ_BUSPROT 106 /* Vector: 106, System Bus Protection Violation */ +#define PIC32MZ_IRQ_CTYPTO 107 /* Vector: 107, Crypto Engine Event */ + /* Vector: 108, Reserved */ +#define PIC32MZ_IRQ_SPI1F 109 /* Vector: 109, SPI1 Fault */ + +#define PIC32MZ_IRQ_SPI1RX 110 /* Vector: 110, SPI1 Receive Done */ +#define PIC32MZ_IRQ_SPI1TX 111 /* Vector: 111, SPI1 Transfer Done */ +#define PIC32MZ_IRQ_U1E 112 /* Vector: 112, UART1 Fault */ +#define PIC32MZ_IRQ_U1RX 113 /* Vector: 113, UART1 Receive Done */ +#define PIC32MZ_IRQ_U1TX 114 /* Vector: 114, UART1 Transfer Done */ +#define PIC32MZ_IRQ_I2C1COL 115 /* Vector: 115, I2C1 Bus Collision Event */ +#define PIC32MZ_IRQ_I2C1S 116 /* Vector: 116, I2C1 Slave Event */ +#define PIC32MZ_IRQ_I2C1M 117 /* Vector: 117, I2C1 Master Event */ +#define PIC32MZ_IRQ_PORTA 118 /* Vector: 118, PORTA Input Change Interrupt */ +#define PIC32MZ_IRQ_PORTB 119 /* Vector: 119, PORTB Input Change Interrupt */ + +#define PIC32MZ_IRQ_PORTC 120 /* Vector: 120, PORTC Input Change Interrupt */ +#define PIC32MZ_IRQ_PORTD 121 /* Vector: 121, PORTD Input Change Interrupt */ +#define PIC32MZ_IRQ_PORTE 122 /* Vector: 122, PORTE Input Change Interrupt */ +#define PIC32MZ_IRQ_PORTF 123 /* Vector: 123, PORTF Input Change Interrupt */ +#define PIC32MZ_IRQ_PORTG 124 /* Vector: 124, PORTG Input Change Interrupt */ +#define PIC32MZ_IRQ_PORTH 125 /* Vector: 125, PORTH Input Change Interrupt */ +#define PIC32MZ_IRQ_PORTJ 126 /* Vector: 126, PORTJ Input Change Interrupt */ +#define PIC32MZ_IRQ_PORTK 127 /* Vector: 127, PORTK Input Change Interrupt */ +#define PIC32MZ_IRQ_PMP 128 /* Vector: 128, Parallel Master Port */ +#define PIC32MZ_IRQ_PMPE 129 /* Vector: 129, Parallel Master Port Error */ + +#define PIC32MZ_IRQ_CMP1 130 /* Vector: 130, Comparator 1 Interrupt */ +#define PIC32MZ_IRQ_CMP2 131 /* Vector: 131, Comparator 2 Interrupt */ +#define PIC32MZ_IRQ_USBGEN 132 /* Vector: 132, USB General Event */ +#define PIC32MZ_IRQ_USBDMA 133 /* Vector: 133, USB DMA Event */ +#define PIC32MZ_IRQ_DMA0 134 /* Vector: 134, DMA Channel 0 */ +#define PIC32MZ_IRQ_DMA1 135 /* Vector: 135, DMA Channel 1 */ +#define PIC32MZ_IRQ_DMA2 136 /* Vector: 136, DMA Channel 2 */ +#define PIC32MZ_IRQ_DMA3 137 /* Vector: 137, DMA Channel 3 */ +#define PIC32MZ_IRQ_DMA4 138 /* Vector: 138, DMA Channel 4 */ +#define PIC32MZ_IRQ_DMA5 139 /* Vector: 139, DMA Channel 5 */ + +#define PIC32MZ_IRQ_DMA6 140 /* Vector: 140, DMA Channel 6 */ +#define PIC32MZ_IRQ_DMA7 141 /* Vector: 141, DMA Channel 7 */ +#define PIC32MZ_IRQ_SPI2F 142 /* Vector: 142, SPI2 Fault */ +#define PIC32MZ_IRQ_SPI2RX 143 /* Vector: 143, SPI2 Receive Done */ +#define PIC32MZ_IRQ_SPI2TX 144 /* Vector: 144, SPI2 Transfer Done */ +#define PIC32MZ_IRQ_U2E 145 /* Vector: 145, UART2 Fault */ +#define PIC32MZ_IRQ_U2RX 146 /* Vector: 146, UART2 Receive Done */ +#define PIC32MZ_IRQ_U2TX 147 /* Vector: 147, UART2 Transfer Done */ +#define PIC32MZ_IRQ_I2C2COL 148 /* Vector: 148, I2C2 Bus Collision Event */ +#define PIC32MZ_IRQ_I2C2S 149 /* Vector: 149, I2C2 Slave Event */ + +#define PIC32MZ_IRQ_I2C2M 150 /* Vector: 150, I2C2 Master Event */ +#define PIC32MZ_IRQ_CAN1 151 /* Vector: 151, Control Area Network 1 */ +#define PIC32MZ_IRQ_CAN2 152 /* Vector: 152, Control Area Network 2 */ +#define PIC32MZ_IRQ_ETH 153 /* Vector: 153, Ethernet interrupt */ +#define PIC32MZ_IRQ_SPI3F 154 /* Vector: 154, SPI3 Fault */ +#define PIC32MZ_IRQ_SPI3RX 155 /* Vector: 155, SPI3 Receive Done */ +#define PIC32MZ_IRQ_SPI3TX 156 /* Vector: 156, SPI3 Transfer Done */ +#define PIC32MZ_IRQ_U3E 157 /* Vector: 157, UART3 Fault */ +#define PIC32MZ_IRQ_U3RX 158 /* Vector: 158, UART3 Receive Done */ +#define PIC32MZ_IRQ_U3TX 159 /* Vector: 159, UART3 Transfer Done */ + +#define PIC32MZ_IRQ_I2C3COL 160 /* Vector: 160, I2C3 Bus Collision Event */ +#define PIC32MZ_IRQ_I2C3S 161 /* Vector: 161, I2C3 Slave Event */ +#define PIC32MZ_IRQ_I2C3M 162 /* Vector: 162, I2C3 Master Event */ +#define PIC32MZ_IRQ_SPI4F 163 /* Vector: 163, SPI4 Fault */ +#define PIC32MZ_IRQ_SPI4RX 164 /* Vector: 164, SPI4 Receive Done */ +#define PIC32MZ_IRQ_SPI4TX 165 /* Vector: 165, SPI4 Transfer Done */ +#define PIC32MZ_IRQ_RTCC 166 /* Vector: 166, Real-Time Clock and Calendar */ +#define PIC32MZ_IRQ_FCE 167 /* Vector: 167, Flash Control Event */ +#define PIC32MZ_IRQ_PMSEC 168 /* Vector: 168, Prefetch Module SEC Event */ +#define PIC32MZ_IRQ_SQI1 169 /* Vector: 169, SQI1 Event */ + +#define PIC32MZ_IRQ_U4E 170 /* Vector: 170, UART4 Fault */ +#define PIC32MZ_IRQ_U4RX 171 /* Vector: 171, UART4 Receive Done */ +#define PIC32MZ_IRQ_U4TX 172 /* Vector: 172, UART4 Transfer Done */ +#define PIC32MZ_IRQ_I2C4COL 173 /* Vector: 173, I2C4 Bus Collision Event */ +#define PIC32MZ_IRQ_I2C4S 174 /* Vector: 174, I2C4 Slave Event */ +#define PIC32MZ_IRQ_I2C4M 175 /* Vector: 175, I2C4 Master Event */ +#define PIC32MZ_IRQ_SPI5F 176 /* Vector: 176, SPI5 Fault */ +#define PIC32MZ_IRQ_SPI5RX 177 /* Vector: 177, SPI5 Receive Done */ +#define PIC32MZ_IRQ_SPI5TX 178 /* Vector: 178, SPI5 Transfer Done */ +#define PIC32MZ_IRQ_U5E 179 /* Vector: 179, UART5 Fault */ + +#define PIC32MZ_IRQ_U5RX 180 /* Vector: 180, UART5 Receive Done */ +#define PIC32MZ_IRQ_U5TX 181 /* Vector: 181, UART5 Transfer Done */ +#define PIC32MZ_IRQ_I2C5COL 182 /* Vector: 182, I2C5 Bus Collision Event */ +#define PIC32MZ_IRQ_I2C5S 183 /* Vector: 183, I2C5 Slave Event */ +#define PIC32MZ_IRQ_I2C5M 184 /* Vector: 184, I2C5 Master Event */ +#define PIC32MZ_IRQ_SPI6F 185 /* Vector: 185, SPI6 Fault */ +#define PIC32MZ_IRQ_SPI6RX 186 /* Vector: 186, SPI6 Receive Done */ +#define PIC32MZ_IRQ_SPI6TX 187 /* Vector: 187, SPI6 Transfer Done */ +#define PIC32MZ_IRQ_U6E 188 /* Vector: 188, UART6 Fault */ +#define PIC32MZ_IRQ_U6RX 189 /* Vector: 189, UART6 Receive Done */ + +#define PIC32MZ_IRQ_U6TX 190 /* Vector: 190, UART6 Transfer Done */ + /* Vector: 191, Reserved */ +#define PIC32MZ_IRQ_ADCESR 192 /* Vector: ADC End of Scan Ready */ +#define PIC32MZ_IRQ_ADCACR 193 /* Vector: ADC Analog Circuits Ready */ +#define PIC32MZ_IRQ_ADCUR 194 /* Vector: ADC Update Ready */ + /* Vector: 195, Reserved */ +#define PIC32MZ_IRQ_ADCGEIR 196 /* Vector: ADC Group Early Interrupt Request */ + /* Vector: 197, Reserved */ +#define PIC32MZ_IRQ_ADC0ER 198 /* Vector: ADC0 Early Interrupt */ +#define PIC32MZ_IRQ_ADC1ER 199 /* Vector: ADC1 Early Interrupt */ +#define PIC32MZ_IRQ_ADC2ER 200 /* Vector: ADC2 Early Interrupt */ +#define PIC32MZ_IRQ_ADC3ER 201 /* Vector: ADC3 Early Interrupt */ +#define PIC32MZ_IRQ_ADC4ER 202 /* Vector: ADC4 Early Interrupt */ + /* Vector: 203, Reserved */ + /* Vector: 204, Reserved */ +#define PIC32MZ_IRQ_ADC7ER 205 /* Vector: ADC7 Early Interrupt */ +#define PIC32MZ_IRQ_ADC0WI 206 /* Vector: ADC0 Warm Interrupt */ +#define PIC32MZ_IRQ_ADC1WI 207 /* Vector: ADC1 Warm Interrupt */ +#define PIC32MZ_IRQ_ADC2WI 208 /* Vector: ADC2 Warm Interrupt */ +#define PIC32MZ_IRQ_ADC3WI 209 /* Vector: ADC3 Warm Interrupt */ +#define PIC32MZ_IRQ_ADC4WI 210 /* Vector: ADC4 Warm Interrupt */ + /* Vector: 211, Reserved */ + /* Vector: 212, Reserved */ +#define PIC32MZ_IRQ_ADC7WI 213 /* Vector: ADC7 Warm Interrupt */ + +#define PIC32MZ_IRQ_BAD 214 /* Not a real IRQ number */ +#define NR_IRQS 214 + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/**************************************************************************** + * Inline functions + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +#undef EXTERN +#ifdef __cplusplus +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_MIPS_INCLUDE_PIC32MZ_IRQ_PIC32MZXXXEF_H */ + diff --git a/arch/mips/src/pic32mz/Kconfig b/arch/mips/src/pic32mz/Kconfig index 0ea6cfeae4..3dd8f32e86 100644 --- a/arch/mips/src/pic32mz/Kconfig +++ b/arch/mips/src/pic32mz/Kconfig @@ -14,13 +14,32 @@ config ARCH_CHIP_PIC32MZ2048ECH bool "PIC32MZ2048ECH" select ARCH_CHIP_PIC32MZEC ---help--- - Microchip PIC32MZ2048ECH (MIPS32 M14K) + Microchip PIC32MZ2048ECH (MIPS32 M14K) such as the + PIC32MZ2048ECH144-I/PH used with the PIC32MZ EC STARTER KIT + DM320006 (no longer available) config ARCH_CHIP_PIC32MZ2048ECM bool "PIC32MZ2048ECM" select ARCH_CHIP_PIC32MZEC ---help--- - Microchip PIC32MZ2048ECM with Crypto Engine (MIPS32 M14K) + Microchip PIC32MZ2048ECM with Crypto Engine (MIPS32 M14K) such as + the ARCH_CHIP_PIC32MZ2048ECM144-I/PH used with the PIC32MZ EC + STARTER KIT DM320006-C (no longer available) + +config ARCH_CHIP_PIC32MZ2048EFH + bool "PIC32MZ2048EFH" + select ARCH_CHIP_PIC32MZEF + ---help--- + Microchip PIC32MZ2048EFH (MIPS32 M14K) such as the + PIC32MZ2048EFH144-I/PH used in the PIC32MZ EF STARTER KIT or as the + PIC32MZ2048EFH100 used with the Mikro Flip&Clip for PIC32MZ. + +config ARCH_CHIP_PIC32MZ2048EFM + bool "PIC32MZ2048EFM" + select ARCH_CHIP_PIC32MZEF + ---help--- + Microchip PIC32MZ2048EFH with Crypto Engine (MIPS32 M14K) such as + the PIC32MZ2048EFM144-I/PH used in the PIC32MZ EF STARTER KIT endchoice @@ -29,6 +48,11 @@ config ARCH_CHIP_PIC32MZEC default n select ARCH_MIPS_M14K +config ARCH_CHIP_PIC32MZEF + bool + default n + select ARCH_MIPS_M14K + config PIC32MZ_MVEC bool default n diff --git a/arch/mips/src/pic32mz/chip/pic32mz-features.h b/arch/mips/src/pic32mz/chip/pic32mz-features.h index 4bc21f2583..6e80282a39 100644 --- a/arch/mips/src/pic32mz/chip/pic32mz-features.h +++ b/arch/mips/src/pic32mz/chip/pic32mz-features.h @@ -1,7 +1,7 @@ /************************************************************************************ * arch/mips/src/pic32mz/chip/pic32mz-features.h * - * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Copyright (C) 2015, 2018 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -44,6 +44,8 @@ #if defined(CONFIG_ARCH_CHIP_PIC32MZEC) # include +#elif defined(CONFIG_ARCH_CHIP_PIC32MZEF) +# include #else # error Unknown PIC32MZ family #endif diff --git a/arch/mips/src/pic32mz/chip/pic32mz-memorymap.h b/arch/mips/src/pic32mz/chip/pic32mz-memorymap.h index a03adba1a8..cb50d34434 100644 --- a/arch/mips/src/pic32mz/chip/pic32mz-memorymap.h +++ b/arch/mips/src/pic32mz/chip/pic32mz-memorymap.h @@ -1,7 +1,7 @@ /************************************************************************************ * arch/mips/src/pic32mz/chip/pic32mz-memorymap.h * - * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Copyright (C) 2015, 2018 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -44,6 +44,8 @@ #if defined(CONFIG_ARCH_CHIP_PIC32MZEC) # include "chip/pic32mzec-memorymap.h" +#elif defined(CONFIG_ARCH_CHIP_PIC32MZEF) +# include "chip/pic32mzef-memorymap.h" #else # error Unknown PIC32MZ family #endif diff --git a/arch/mips/src/pic32mz/chip/pic32mz-pps.h b/arch/mips/src/pic32mz/chip/pic32mz-pps.h index c0fbd48fa5..c59ebab6df 100644 --- a/arch/mips/src/pic32mz/chip/pic32mz-pps.h +++ b/arch/mips/src/pic32mz/chip/pic32mz-pps.h @@ -1,7 +1,7 @@ /******************************************************************************************** * arch/mips/src/pic32mz/pic32mz-pps.h * - * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Copyright (C) 2015, 2018 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -51,6 +51,8 @@ #if defined(CONFIG_ARCH_CHIP_PIC32MZEC) # include "chip/pic32mzec-pps.h" +#elif defined(CONFIG_ARCH_CHIP_PIC32MZEF) +# include "chip/pic32mzef-pps.h" #else # error Unknown PIC32MZ family #endif diff --git a/arch/mips/src/pic32mz/chip/pic32mzec-features.h b/arch/mips/src/pic32mz/chip/pic32mzec-features.h index 3a676f887e..270f58d176 100644 --- a/arch/mips/src/pic32mz/chip/pic32mzec-features.h +++ b/arch/mips/src/pic32mz/chip/pic32mzec-features.h @@ -432,10 +432,10 @@ # define DEVCFG1_FWDT_DISABLED (0 << 23) /* Bit 23=0: Watchdog disabled, can be enabled */ #define DEVCFG1_FWDTWINSZ_SHIFT (24) /* Bits 24-25: Watchdog Timer Window Size bits */ #define DEVCFG1_FWDTWINSZ_MASK (3 << DEVCFG1_FWDTWINSZ_SHIFT) -# define DEVCFG1_FWDTWINSZ_75 (0 << DEVCFG1_FWDTWINSZ_SHIFT) /* Window size is 75% */ -# define DEVCFG1_FWDTWINSZ_50 (1 << DEVCFG1_FWDTWINSZ_SHIFT) /* Window size is 50% */ -# define DEVCFG1_FWDTWINSZ_37p5 (2 << DEVCFG1_FWDTWINSZ_SHIFT) /* Window size is 37.5% */ -# define DEVCFG1_FWDTWINSZ_25 (3 << DEVCFG1_FWDTWINSZ_SHIFT) /* Window size is 25% */ +# define DEVCFG1_FWDTWINSZ_75 (0 << DEVCFG1_FWDTWINSZ_SHIFT) /* Window size is 75% */ +# define DEVCFG1_FWDTWINSZ_50 (1 << DEVCFG1_FWDTWINSZ_SHIFT) /* Window size is 50% */ +# define DEVCFG1_FWDTWINSZ_37p5 (2 << DEVCFG1_FWDTWINSZ_SHIFT) /* Window size is 37.5% */ +# define DEVCFG1_FWDTWINSZ_25 (3 << DEVCFG1_FWDTWINSZ_SHIFT) /* Window size is 25% */ #define DEVCFG1_DMTCNT_SHIFT (26) /* Bits 26-30: Deadman Timer Count Select bits */ #define DEVCFG1_DMTCNT_MASK (31 << DEVCFG1_DMTCNT_SHIFT) # define DEVCFG1_DMTCNT(n) ((uint32_t)((n)-8) << DEVCFG1_DMTCNT_SHIFT) /* 2**n, n=8..31 */ diff --git a/arch/mips/src/pic32mz/chip/pic32mzec-memorymap.h b/arch/mips/src/pic32mz/chip/pic32mzec-memorymap.h index dc878ea96d..54d95e49ba 100644 --- a/arch/mips/src/pic32mz/chip/pic32mzec-memorymap.h +++ b/arch/mips/src/pic32mz/chip/pic32mzec-memorymap.h @@ -117,26 +117,33 @@ #define PIC32MZ_CVREF_K1BASE (PIC32MZ_SFR_K1BASE + 0x00000e00) /* CVREF */ #define PIC32MZ_OSC_K1BASE (PIC32MZ_SFR_K1BASE + 0x00001200) /* Oscillator */ #define PIC32MZ_PPS_K1BASE (PIC32MZ_SFR_K1BASE + 0x00001400) /* PPS */ + #define PIC32MZ_INT_K1BASE (PIC32MZ_SFR_K1BASE + 0x00010000) /* Interrupt Controller */ #define PIC32MZ_DMA_K1BASE (PIC32MZ_SFR_K1BASE + 0x00011000) /* DMA */ + #define PIC32MZ_I2C_K1BASE (PIC32MZ_SFR_K1BASE + 0x00020000) /* I2C1-I2C5 */ #define PIC32MZ_SPI_K1BASE (PIC32MZ_SFR_K1BASE + 0x00021000) /* SPI1-SPI6 */ #define PIC32MZ_UART_K1BASE (PIC32MZ_SFR_K1BASE + 0x00022000) /* UART1-UART6 */ #define PIC32MZ_PMP_K1BASE (PIC32MZ_SFR_K1BASE + 0x0002e000) /* PMP */ + #define PIC32MZ_TIMER_K1BASE (PIC32MZ_SFR_K1BASE + 0x00040000) /* Timer1-Timer9 */ #define PIC32MZ_IC_K1BASE (PIC32MZ_SFR_K1BASE + 0x00042000) /* IC1-IC9 */ #define PIC32MZ_OC_K1BASE (PIC32MZ_SFR_K1BASE + 0x00044000) /* OC1-OC9 */ #define PIC32MZ_ADC1_K1BASE (PIC32MZ_SFR_K1BASE + 0x0004b000) /* ADC1 */ #define PIC32MZ_CMP_K1BASE (PIC32MZ_SFR_K1BASE + 0x0004c000) /* Comparator 1, 2 */ + #define PIC32MZ_IOPORT_K1BASE (PIC32MZ_SFR_K1BASE + 0x00060000) /* PORTA-PORTK */ + #define PIC32MZ_CAN_K1BASE (PIC32MZ_SFR_K1BASE + 0x00080000) /* CAN1 and CAN2 */ #define PIC32MZ_ETH_K1BASE (PIC32MZ_SFR_K1BASE + 0x00082000) /* Ethernet */ + #define PIC32MZ_PREFETCH_K1BASE (PIC32MZ_SFR_K1BASE + 0x000e0000) /* Prefetch */ #define PIC32MZ_EBI_K1BASE (PIC32MZ_SFR_K1BASE + 0x000e1000) /* EBI */ #define PIC32MZ_SQI1_K1BASE (PIC32MZ_SFR_K1BASE + 0x000e2000) /* SQI1 */ #define PIC32MZ_USB_K1BASE (PIC32MZ_SFR_K1BASE + 0x000e3000) /* USB */ #define PIC32MZ_CRYPTO_K1BASE (PIC32MZ_SFR_K1BASE + 0x000e5000) /* Crypto */ #define PIC32MZ_RNG_K1BASE (PIC32MZ_SFR_K1BASE + 0x000e6000) /* RNG */ + #define PIC32MZ_SYSBUS_K1BASE (PIC32MZ_SFR_K1BASE + 0x000f0000) /* System Bus */ #endif /* __ARCH_MIPS_SRC_PIC32MZ_CHIP_PIC32MZEC_MEMORYMAP_H */ diff --git a/arch/mips/src/pic32mz/chip/pic32mzec-pps.h b/arch/mips/src/pic32mz/chip/pic32mzec-pps.h index 8ee9f4d7e7..c027d6a346 100644 --- a/arch/mips/src/pic32mz/chip/pic32mzec-pps.h +++ b/arch/mips/src/pic32mz/chip/pic32mzec-pps.h @@ -47,6 +47,8 @@ ********************************************************************************************/ /* PPS Register Offsets *********************************************************************/ +/* Peripheral pin select input register map */ + #define PIC32MZ_INTnR_OFFSET(n) (0x1400 + ((n << 2)) /* n=1..4 */ # define PIC32MZ_INT1R_OFFSET 0x1404 # define PIC32MZ_INT2R_OFFSET 0x1408 @@ -93,7 +95,7 @@ # define PIC32MZ_SDI4R_OFFSET 0x14c0 # define PIC32MZ_SDI5R_OFFSET 0x14cc # define PIC32MZ_SDI6R_OFFSET 0x14d8 -#define PIC32MZ_SSnR_OFFSET(n) (0x1490 + 12*(n)) /* n=1..6 */ +#define PIC32MZ_SSnR_OFFSET(n) (0x1494 + 12*(n)) /* n=1..6 */ # define PIC32MZ_SS1R_OFFSET 0x14a0 # define PIC32MZ_SS2R_OFFSET 0x14ac # define PIC32MZ_SS3R_OFFSET 0x14b8 @@ -107,6 +109,9 @@ # define PIC32MZ_REFCLKI1R_OFFSET 0x14e8 # define PIC32MZ_REFCLKI3R_OFFSET 0x14f0 # define PIC32MZ_REFCLKI4R_OFFSET 0x14f4 + +/* Peripheral pin select output register map */ + #define PIC32MZ_RPAnR_OFFSET(n) (0x1500 + ((n) << 2)) /* n=14,15 */ # define PIC32MZ_RPA14R_OFFSET 0x1538 # define PIC32MZ_RPA15R_OFFSET 0x153c @@ -236,6 +241,9 @@ # define PIC32MZ_REFCLKI1R (PIC32MZ_SFR_K1BASE+PIC32MZ_REFCLKI1R_OFFSET) # define PIC32MZ_REFCLKI3R (PIC32MZ_SFR_K1BASE+PIC32MZ_REFCLKI3R_OFFSET) # define PIC32MZ_REFCLKI4R (PIC32MZ_SFR_K1BASE+PIC32MZ_REFCLKI4R_OFFSET) + +/* Peripheral pin select output register map */ + #define PIC32MZ_RPAnR(n) (PIC32MZ_SFR_K1BASE+PIC32MZ_RPAnR_OFFSET(n)) # define PIC32MZ_RPA14R (PIC32MZ_SFR_K1BASE+PIC32MZ_RPA14R_OFFSET) # define PIC32MZ_RPA15R (PIC32MZ_SFR_K1BASE+PIC32MZ_RPA15R_OFFSET) @@ -764,8 +772,8 @@ #define T2CKR_RPF1 4 #define T2CKR_RPF4 2 #define T2CKR_RPG1 12 - #define T2CKR_RPG8 1 + #define T3CKR_RPB0 5 #define T3CKR_RPB7 7 #define T3CKR_RPB8 2 diff --git a/arch/mips/src/pic32mz/chip/pic32mzef-features.h b/arch/mips/src/pic32mz/chip/pic32mzef-features.h new file mode 100644 index 0000000000..9a042287bf --- /dev/null +++ b/arch/mips/src/pic32mz/chip/pic32mzef-features.h @@ -0,0 +1,540 @@ +/************************************************************************************ + * arch/mips/src/pic32mz/chip/pic32mzef-features.h + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_MIPS_SRC_PIC32MZ_CHIP_PIC32MZEF_FEATURES_H +#define __ARCH_MIPS_SRC_PIC32MZ_CHIP_PIC32MZEF_FEATURES_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ +/* Register/Flash Offsets ***********************************************************/ + +/* Device ID, Revision, and Configuration (SFR PIC32MZ_CONFIG_K1BASE) */ + +#define PIC32MZ_CFGCON_OFFSET 0x0000 /* Configuration control register */ +#define PIC32MZ_DEVID_OFFSET 0x0020 /* Device ID and revision register */ +#define PIC32MZ_SYSKEY_OFFSET 0x0030 /* System key register */ +#define PIC32MZ_CFGEBIA_OFFSET 0x00c0 /* External bus interface address pin configuration register */ +#define PIC32MZ_CFGEBIC_OFFSET 0x00d0 /* External bus interface address pin control register */ +#define PIC32MZ_CFGPG_OFFSET 0x00e0 /* Permission group configuration register */ + +/* Alternate Device Configuration (Boot Flash PIC32MZ_BOOTCFG_K1BASE) */ + +#define PIC32MZ_ADEVCFG3_OFFSET 0x0040 /* Alternate device configuration word 3 */ +#define PIC32MZ_ADEVCFG2_OFFSET 0x0044 /* Alternate device configuration word 2 */ +#define PIC32MZ_ADEVCFG1_OFFSET 0x0048 /* Alternate device configuration word 1 */ +#define PIC32MZ_ADEVCFG0_OFFSET 0x004c /* Alternate device configuration word 0 */ +#define PIC32MZ_ADEVCP3_OFFSET 0x0050 /* Alternate device code protect word 3 */ +#define PIC32MZ_ADEVCP2_OFFSET 0x0054 /* Alternate device code protect word 2 */ +#define PIC32MZ_ADEVCP1_OFFSET 0x0058 /* Alternate device code protect word 1 */ +#define PIC32MZ_ADEVCP0_OFFSET 0x005c /* Alternate device code protect word 0 */ +#define PIC32MZ_ADEVSIGN3_OFFSET 0x0060 /* Alternate device signature word 3 */ +#define PIC32MZ_ADEVSIGN2_OFFSET 0x0064 /* Alternate device signature word 2 */ +#define PIC32MZ_ADEVSIGN1_OFFSET 0x0068 /* Alternate device signature word 1 */ +#define PIC32MZ_ADEVSIGN0_OFFSET 0x006c /* Alternate device signature word 0 */ + +/* Device Configuration (Boot Flash PIC32MZ_BOOTCFG_K1BASE) */ + +#define PIC32MZ_DEVCFG3_OFFSET 0x00c0 /* Device configuration word 3 */ +#define PIC32MZ_DEVCFG2_OFFSET 0x00c4 /* Device configuration word 2 */ +#define PIC32MZ_DEVCFG1_OFFSET 0x00c8 /* Device configuration word 1 */ +#define PIC32MZ_DEVCFG0_OFFSET 0x00cc /* Device configuration word 0 */ +#define PIC32MZ_DEVCP3_OFFSET 0x00d0 /* Device code protect word 3 */ +#define PIC32MZ_DEVCP2_OFFSET 0x00d4 /* Device code protect word 2 */ +#define PIC32MZ_DEVCP1_OFFSET 0x00d8 /* Device code protect word 1 */ +#define PIC32MZ_DEVCP0_OFFSET 0x00dc /* Device code protect word 0 */ +#define PIC32MZ_DEVSIGN3_OFFSET 0x00e0 /* Device signature word 3 */ +#define PIC32MZ_DEVSIGN2_OFFSET 0x00e4 /* Device signature word 2 */ +#define PIC32MZ_DEVSIGN1_OFFSET 0x00e8 /* Device signature word 1 */ +#define PIC32MZ_DEVSIGN0_OFFSET 0x00ec /* Device signature word 0 */ + +/* Device ADC Calibration (Boot Flash PIC32MZ_DEVSN_K1BASE) */ + +#define PIC32MZ_DEVADC0_OFFSET 0x0000 /* ADC0 Calibration */ +#define PIC32MZ_DEVADC1_OFFSET 0x0004 /* ADC1 Calibration */ +#define PIC32MZ_DEVADC2_OFFSET 0x0008 /* ADC2 Calibration */ +#define PIC32MZ_DEVADC3_OFFSET 0x000c /* ADC3 Calibration */ +#define PIC32MZ_DEVADC4_OFFSET 0x0010 /* ADC4 Calibration */ +#define PIC32MZ_DEVADC7_OFFSET 0x001c /* ADC7 Calibration */ + +/* Device Serial Number (Boot Flash PIC32MZ_DEVSN_K1BASE) */ + +#define PIC32MZ_DEVSN0_OFFSET 0x0020 /* Device serial number 0 */ +#define PIC32MZ_DEVSN1_OFFSET 0x0024 /* Device serial number 1 */ + +/* Register/Flash Addresses *********************************************************/ + +/* Device ID, Revision, and Configuration (SFR PIC32MZ_CONFIG_K1BASE) */ + +#define PIC32MZ_CFGCON (PIC32MZ_CONFIG_K1BASE+PIC32MZ_CFGCON_OFFSET) +#define PIC32MZ_DEVID (PIC32MZ_CONFIG_K1BASE+PIC32MZ_DEVID_OFFSET) +#define PIC32MZ_SYSKEY (PIC32MZ_CONFIG_K1BASE+PIC32MZ_SYSKEY_OFFSET) +#define PIC32MZ_CFGEBIA (PIC32MZ_CONFIG_K1BASE+PIC32MZ_CFGEBIA_OFFSET) +#define PIC32MZ_CFGEBIC (PIC32MZ_CONFIG_K1BASE+PIC32MZ_CFGEBIC_OFFSET) +#define PIC32MZ_CFGPG (PIC32MZ_CONFIG_K1BASE+PIC32MZ_CFGPG_OFFSET) + +/* Alternate Device Configuration (Boot Flash PIC32MZ_BOOTCFG_K1BASE) */ + +#define PIC32MZ_ADEVCFG3 (PIC32MZ_BOOTCFG_K1BASE+PIC32MZ_ADEVCFG3_OFFSET) +#define PIC32MZ_ADEVCFG2 (PIC32MZ_BOOTCFG_K1BASE+PIC32MZ_ADEVCFG2_OFFSET) +#define PIC32MZ_ADEVCFG1 (PIC32MZ_BOOTCFG_K1BASE+PIC32MZ_ADEVCFG1_OFFSET) +#define PIC32MZ_ADEVCFG0 (PIC32MZ_BOOTCFG_K1BASE+PIC32MZ_ADEVCFG0_OFFSET) +#define PIC32MZ_ADEVCP3 (PIC32MZ_BOOTCFG_K1BASE+PIC32MZ_ADEVCP3_OFFSET) +#define PIC32MZ_ADEVCP2 (PIC32MZ_BOOTCFG_K1BASE+PIC32MZ_ADEVCP2_OFFSET) +#define PIC32MZ_ADEVCP1 (PIC32MZ_BOOTCFG_K1BASE+PIC32MZ_ADEVCP1_OFFSET) +#define PIC32MZ_ADEVCP0 (PIC32MZ_BOOTCFG_K1BASE+PIC32MZ_ADEVCP0_OFFSET) +#define PIC32MZ_ADEVSIGN3 (PIC32MZ_BOOTCFG_K1BASE+PIC32MZ_ADEVSIGN3_OFFSET) +#define PIC32MZ_ADEVSIGN2 (PIC32MZ_BOOTCFG_K1BASE+PIC32MZ_ADEVSIGN2_OFFSET) +#define PIC32MZ_ADEVSIGN1 (PIC32MZ_BOOTCFG_K1BASE+PIC32MZ_ADEVSIGN1_OFFSET) +#define PIC32MZ_ADEVSIGN0 (PIC32MZ_BOOTCFG_K1BASE+PIC32MZ_ADEVSIGN0_OFFSET) + +/* Device Configuration (Boot Flash PIC32MZ_BOOTCFG_K1BASE) */ + +#define PIC32MZ_DEVCFG3 (PIC32MZ_BOOTCFG_K1BASE+PIC32MZ_DEVCFG3_OFFSET) +#define PIC32MZ_DEVCFG2 (PIC32MZ_BOOTCFG_K1BASE+PIC32MZ_DEVCFG2_OFFSET) +#define PIC32MZ_DEVCFG1 (PIC32MZ_BOOTCFG_K1BASE+PIC32MZ_DEVCFG1_OFFSET) +#define PIC32MZ_DEVCFG0 (PIC32MZ_BOOTCFG_K1BASE+PIC32MZ_DEVCFG0_OFFSET) +#define PIC32MZ_DEVCP3 (PIC32MZ_BOOTCFG_K1BASE+PIC32MZ_DEVCP3_OFFSET) +#define PIC32MZ_DEVCP2 (PIC32MZ_BOOTCFG_K1BASE+PIC32MZ_DEVCP2_OFFSET) +#define PIC32MZ_DEVCP1 (PIC32MZ_BOOTCFG_K1BASE+PIC32MZ_DEVCP1_OFFSET) +#define PIC32MZ_DEVCP0 (PIC32MZ_BOOTCFG_K1BASE+PIC32MZ_DEVCP0_OFFSET) +#define PIC32MZ_DEVSIGN3 (PIC32MZ_BOOTCFG_K1BASE+PIC32MZ_DEVSIGN3_OFFSET) +#define PIC32MZ_DEVSIGN2 (PIC32MZ_BOOTCFG_K1BASE+PIC32MZ_DEVSIGN2_OFFSET) +#define PIC32MZ_DEVSIGN1 (PIC32MZ_BOOTCFG_K1BASE+PIC32MZ_DEVSIGN1_OFFSET) +#define PIC32MZ_DEVSIGN0 (PIC32MZ_BOOTCFG_K1BASE+PIC32MZ_DEVSIGN0_OFFSET) + +/* Device ADC Calibration (Boot Flash PIC32MZ_DEVSN_K1BASE) */ + +#define PIC32MZ_DEVADC0 (PIC32MZ_DEVSN_K1BASE+PIC32MZ_DEVADC0_OFFSET) +#define PIC32MZ_DEVADC1 (PIC32MZ_DEVSN_K1BASE+PIC32MZ_DEVADC1_OFFSET) +#define PIC32MZ_DEVADC2 (PIC32MZ_DEVSN_K1BASE+PIC32MZ_DEVADC2_OFFSET) +#define PIC32MZ_DEVADC3 (PIC32MZ_DEVSN_K1BASE+PIC32MZ_DEVADC3_OFFSET) +#define PIC32MZ_DEVADC4 (PIC32MZ_DEVSN_K1BASE+PIC32MZ_DEVADC4_OFFSET) +#define PIC32MZ_DEVADC7 (PIC32MZ_DEVSN_K1BASE+PIC32MZ_DEVADC7_OFFSET) + +/* Device Serial Number (Boot Flash PIC32MZ_DEVSN_K1BASEPIC32MZ_DEVSN_K1BASE) */ + +#define PIC32MZ_DEVSN0 (PIC32MZ_DEVSN_K1BASE+PIC32MZ_DEVSN0_OFFSET) +#define PIC32MZ_DEVSN1 (PIC32MZ_DEVSN_K1BASE+PIC32MZ_DEVSN1_OFFSET) + +/* Register/Flash Bit Field Definitions *********************************************/ + +/* Device ID, Revision, and Configuration (SFR PIC32MZ_CONFIG_K1BASE) */ +/* Configuration control register + * + * NOTE: To change many of the bits in the register, the unlock sequence must first + * be performed. + */ + +#define CFGCON_TDOEN (1 << 0) /* Bit 0: TDO Enable for 2-Wire JTAG */ +#define CFGCON_TROEN (1 << 2) /* Bit 2: Trace Output Enable bit */ +#define CFGCON_JTAGEN (1 << 3) /* Bit 3: JTAG Port Enable bit */ +#define CFGCON_ECCCON_SHIFT (4) /* Bits 4-5: Flash ECC Configuration bits */ +#define CFGCON_ECCCON_MASK (7 << CFGCON_ECCCON_SHIFT) +# define CFGCON_ECCCON_ECC (0 << CFGCON_ECCCON_SHIFT) /* Flash ECC enabled */ +# define CFGCON_ECCCON_DYNECC (1 << CFGCON_ECCCON_SHIFT) /* Dynamic Flash ECC enabled */ +# define CFGCON_ECCCON_DISLCK (2 << CFGCON_ECCCON_SHIFT) /* ECC / dynamic ECC disabled (locked) */ +# define CFGCON_ECCCON_DISWR (3 << CFGCON_ECCCON_SHIFT) /* ECC / dynamic ECC disabled (writable) */ +#define CFGCON_IOANCPEN (1 << 7) /* Bit 7: I/O Analog Charge Pump Enable bit */ +#define CFGCON_USBSSEN (1 << 8) /* Bit 8: USB Suspend Sleep Enable bit */ +#define CFGCON_PGLOCK (1 << 11) /* Bit 11: Permission Group Lock bit */ +#define CFGCON_PMDLOCK (1 << 12) /* Bit 12: Peripheral Module Disable bit */ +#define CFGCON_IOLOCK (1 << 13) /* Bit 13: Peripheral Pin Select Lock bit */ +#define CFGCON_OCACLK (1 << 16) /* Bit 16: Output Compare Alternate Clock Selection bit */ +#define CFGCON_ICACLK (1 << 17) /* Bit 17: Input Capture Alternate Clock Selection bit */ +#define CFGCON_CPUPRI (1 << 24) /* Bit 24: CPU Arbitration Priority to SRAM */ +#define CFGCON_DMAPRI (1 << 25) /* Bit 25: DMA Read and DMA Write Arbitration Priority */ + +/* Device ID and revision register */ + +#define DEVID_SHIFT (0) /* Bits 0-27: Device ID */ +#define DEVID_MASK (0x0ffffff << DEVID_SHIFT) +#define DEVID_VER_SHIFT (28) /* Bits 28-31: Revision Identifier bits */ +#define DEVID_VER_MASK (15 << DEVID_VER_SHIFT) + +/* System key register: 32-bit key value */ + +#define UNLOCK_SYSKEY_0 (0xaa996655ul) +#define UNLOCK_SYSKEY_1 (0x556699aaul) + +/* External bus interface address pin configuration register */ + +#define CFGEBIA_EBIA0N_SHIFT (0) /* Bits 0-23: EBI address pin 0 enable */ +#define CFGEBIA_EBIA0N_MASK (0x00ffffff << CFGEBIA_EBIA0N_SHIFT) +# define CFGEBIA_EBIA0EN (1 << 0) /* Bit 0: EBI address pin 0 enable */ +# define CFGEBIA_EBIA1EN (1 << 1) /* Bit 1: EBI address pin 1 enable */ +# define CFGEBIA_EBIA2EN (1 << 2) /* Bit 2: EBI address pin 2 enable */ +# define CFGEBIA_EBIA3EN (1 << 3) /* Bit 3: EBI address pin 3 enable */ +# define CFGEBIA_EBIA4EN (1 << 4) /* Bit 4: EBI address pin 4 enable */ +# define CFGEBIA_EBIA5EN (1 << 5) /* Bit 5: EBI address pin 5 enable */ +# define CFGEBIA_EBIA6EN (1 << 6) /* Bit 6: EBI address pin 6 enable */ +# define CFGEBIA_EBIA7EN (1 << 7) /* Bit 7: EBI address pin 7 enable */ +# define CFGEBIA_EBIA8EN (1 << 8) /* Bit 8: EBI address pin 8 enable */ +# define CFGEBIA_EBIA9EN (1 << 9) /* Bit 9: EBI address pin 9 enable */ +# define CFGEBIA_EBIA10EN (1 << 10) /* Bit 10: EBI address pin 10 enable */ +# define CFGEBIA_EBIA11EN (1 << 11) /* Bit 11: EBI address pin 11 enable */ +# define CFGEBIA_EBIA12EN (1 << 12) /* Bit 12: EBI address pin 12 enable */ +# define CFGEBIA_EBIA13EN (1 << 13) /* Bit 13: EBI address pin 13 enable */ +# define CFGEBIA_EBIA14EN (1 << 14) /* Bit 14: EBI address pin 14 enable */ +# define CFGEBIA_EBIA15EN (1 << 15) /* Bit 15: EBI address pin 15 enable */ +# define CFGEBIA_EBIA16EN (1 << 16) /* Bit 16: EBI address pin 16 enable */ +# define CFGEBIA_EBIA17EN (1 << 17) /* Bit 17: EBI address pin 17 enable */ +# define CFGEBIA_EBIA18EN (1 << 18) /* Bit 18: EBI address pin 18 enable */ +# define CFGEBIA_EBIA19EN (1 << 19) /* Bit 19: EBI address pin 19 enable */ +# define CFGEBIA_EBIA20EN (1 << 20) /* Bit 20: EBI address pin 20 enable */ +# define CFGEBIA_EBIA21EN (1 << 21) /* Bit 21: EBI address pin 21 enable */ +# define CFGEBIA_EBIA22EN (1 << 22) /* Bit 22: EBI address pin 22 enable */ +# define CFGEBIA_EBIA23EN (1 << 23) /* Bit 23: EBI address pin 23 enable */ +#define CFGEBIA_EBIPINEN (1 << 31) /* Bit 31: EBI Pin Enable bit */ + +/* External bus interface address pin control register */ + +#define CFGEBIC_EBIDEN0 (1 << 0) /* Bit 0: EBI Data Lower Byte Pin Enable bit */ +#define CFGEBIC_EBIDEN1 (1 << 1) /* Bit 1: EBI Data Upper Byte Pin Enable bit */ +#define CFGEBIC_EBICSEN0 (1 << 4) /* Bit 4: EBICS0 Pin Enable bit */ +#define CFGEBIC_EBICSEN1 (1 << 5) /* Bit 5: EBICS1 Pin Enable bit */ +#define CFGEBIC_EBICSEN2 (1 << 6) /* Bit 6: EBICS2 Pin Enable bit */ +#define CFGEBIC_EBICSEN3 (1 << 7) /* Bit 7: EBICS3 Pin Enable bit */ +#define CFGEBIC_EBIBSEN0 (1 << 8) /* Bit 8: EBIBS0 Pin Enable bit */ +#define CFGEBIC_EBIBSEN1 (1 << 9) /* Bit 9: EBIBS1 Pin Enable bit */ +#define CFGEBIC_EBIOEEN (1 << 12) /* Bit 12: EBIOE Pin Enable bit */ +#define CFGEBIC_EBIWEEN (1 << 13) /* Bit 13: EBIWE Pin Enable bit */ +#define CFGEBIC_EBIRPEN (1 << 16) /* Bit 16: EBIRP Pin Sensitivity Control bit */ +#define CFGEBIC_EBIRDYLVL (1 << 17) /* Bit 17: EBIRDYx Pin Sensitivity Control bit */ +#define CFGEBIC_EBIRDYEN1 (1 << 25) /* Bit 25: EBIRDY1 Pin Enable bit */ +#define CFGEBIC_EBIRDYEN2 (1 << 26) /* Bit 26: EBIRDY2 Pin Enable bit */ +#define CFGEBIC_EBIRDYEN3 (1 << 27) /* Bit 27: EBIRDY3 Pin Enable bit */ +#define CFGEBIC_EBIRDYINV1 (1 << 29) /* Bit 29: EBIRDY1 Inversion Control bit */ +#define CFGEBIC_EBIRDYINV2 (1 << 30) /* Bit 30: EBIRDY2 Inversion Control bit */ +#define CFGEBIC_EBIRDYINV3 (1 << 31) /* Bit 31: EBIRDY3 Inversion Control bit */ + +/* Permission group configuration register */ + +#define CFGPG_GROUP0 0 /* Initiator is assigned to Permission Group 0 */ +#define CFGPG_GROUP1 1 /* Initiator is assigned to Permission Group 1 */ +#define CFGPG_GROUP2 2 /* Initiator is assigned to Permission Group 2 */ +#define CFGPG_GROUP3 3 /* Initiator is assigned to Permission Group 3 */ + +#define CFGPG_CPUPG_SHIFT (0) /* Bits 0-1: CPU Permission Group bits */ +#define CFGPG_CPUPG_MASK (3 << CFGPG_CPUPG_SHIFT) +# define CFGPG_CPUPG(n) ((uint32_t)(n) << CFGPG_CPUPG_SHIFT) +# define CFGPG_CPUPG_GROUP0 CFGPG_CPUPG(CFGPG_GROUP0) +# define CFGPG_CPUPG_GROUP1 CFGPG_CPUPG(CFGPG_GROUP1) +# define CFGPG_CPUPG_GROUP2 CFGPG_CPUPG(CFGPG_GROUP2) +# define CFGPG_CPUPG_GROUP3 CFGPG_CPUPG(CFGPG_GROUP3) +#define CFGPG_DMAPG_SHIFT (4) /* Bits 4-5: DMA Module Permission Group bits */ +#define CFGPG_DMAPG_MASK (3 << CFGPG_DMAPG_SHIFT) +# define CFGPG_DMAPG(n) ((uint32_t)(n) << CFGPG_DMAPG_SHIFT) +# define CFGPG_DMAPG_GROUP0 CFGPG_DMAPG(CFGPG_GROUP0) +# define CFGPG_DMAPG_GROUP1 CFGPG_DMAPG(CFGPG_GROUP1) +# define CFGPG_DMAPG_GROUP2 CFGPG_DMAPG(CFGPG_GROUP2) +# define CFGPG_DMAPG_GROUP3 CFGPG_DMAPG(CFGPG_GROUP3) +#define CFGPG_USBPG_SHIFT (8) /* Bits 8-9: USB Module Permission Group bits */ +#define CFGPG_USBPG_MASK (3 << CFGPG_USBPG_SHIFT) +# define CFGPG_USBPG(n) ((uint32_t)(n) << CFGPG_USBPG_SHIFT) +# define CFGPG_USBPG_GROUP0 CFGPG_USBPG(CFGPG_GROUP0) +# define CFGPG_USBPG_GROUP1 CFGPG_USBPG(CFGPG_GROUP1) +# define CFGPG_USBPG_GROUP2 CFGPG_USBPG(CFGPG_GROUP2) +# define CFGPG_USBPG_GROUP3 CFGPG_USBPG(CFGPG_GROUP3) +#define CFGPG_CAN1PG_SHIFT (12) /* Bits 12-13: CAN1 Module Permission Group bits */ +#define CFGPG_CAN1PG_MASK (3 << CFGPG_CAN1PG_SHIFT) +# define CFGPG_CAN1PG(n) ((uint32_t)(n) << CFGPG_CAN1PG_SHIFT) +# define CFGPG_CAN1PG_GROUP0 CFGPG_CAN1PG(CFGPG_GROUP0) +# define CFGPG_CAN1PG_GROUP1 CFGPG_CAN1PG(CFGPG_GROUP1) +# define CFGPG_CAN1PG_GROUP2 CFGPG_CAN1PG(CFGPG_GROUP2) +# define CFGPG_CAN1PG_GROUP3 CFGPG_CAN1PG(CFGPG_GROUP3) +#define CFGPG_CAN2PG_SHIFT (14) /* Bits 14-15: CAN2 Module Permission Group bits */ +#define CFGPG_CAN2PG_MASK (3 << CFGPG_CAN2PG_SHIFT) +# define CFGPG_CAN2PG(n) ((uint32_t)(n) << CFGPG_CAN2PG_SHIFT) +# define CFGPG_CAN2PG_GROUP0 CFGPG_CAN2PG(CFGPG_GROUP0) +# define CFGPG_CAN2PG_GROUP1 CFGPG_CAN2PG(CFGPG_GROUP1) +# define CFGPG_CAN2PG_GROUP2 CFGPG_CAN2PG(CFGPG_GROUP2) +# define CFGPG_CAN2PG_GROUP3 CFGPG_CAN2PG(CFGPG_GROUP3) +#define CFGPG_ETHPG_SHIFT (16) /* Bits 16-17: Ethernet Module Permission Group bits */ +#define CFGPG_ETHPG_MASK (3 << CFGPG_ETHPG_SHIFT) +# define CFGPG_ETHPG(n) ((uint32_t)(n) << CFGPG_ETHPG_SHIFT) +# define CFGPG_ETHPG_GROUP0 CFGPG_ETHPG(CFGPG_GROUP0) +# define CFGPG_ETHPG_GROUP1 CFGPG_ETHPG(CFGPG_GROUP1) +# define CFGPG_ETHPG_GROUP2 CFGPG_ETHPG(CFGPG_GROUP2) +# define CFGPG_ETHPG_GROUP3 CFGPG_ETHPG(CFGPG_GROUP3) +#define CFGPG_SQI1PG_SHIFT (20) /* Bits 20-21: SQI Module Permission Group bits */ +#define CFGPG_SQI1PG_MASK (3 << CFGPG_SQI1PG_SHIFT) +# define CFGPG_SQI1PG(n) ((uint32_t)(n) << CFGPG_SQI1PG_SHIFT) +# define CFGPG_SQI1PG_GROUP0 CFGPG_SQI1PG(CFGPG_GROUP0) +# define CFGPG_SQI1PG_GROUP1 CFGPG_SQI1PG(CFGPG_GROUP1) +# define CFGPG_SQI1PG_GROUP2 CFGPG_SQI1PG(CFGPG_GROUP2) +# define CFGPG_SQI1PG_GROUP3 CFGPG_SQI1PG(CFGPG_GROUP3) +#define CFGPG_FCPG_SHIFT (22) /* Bits 22-23: Flash Control Permission Group bits */ +#define CFGPG_FCPG_MASK (3 << CFGPG_FCPG_SHIFT) +# define CFGPG_FCPG(n) ((uint32_t)(n) << CFGPG_FCPG_SHIFT) +# define CFGPG_FCPG_GROUP0 CFGPG_FCPG(CFGPG_GROUP0) +# define CFGPG_FCPG_GROUP1 CFGPG_FCPG(CFGPG_GROUP1) +# define CFGPG_FCPG_GROUP2 CFGPG_FCPG(CFGPG_GROUP2) +# define CFGPG_FCPG_GROUP3 CFGPG_FCPG(CFGPG_GROUP3) +#define CFGPG_CRYPTPG_SHIFT (24) /* Bits 24-25: Crypto Engine Permission Group bits */ +#define CFGPG_CRYPTPG_MASK (3 << CFGPG_CRYPTPG_SHIFT) +# define CFGPG_CRYPTPG(n) ((uint32_t)(n) << CFGPG_CRYPTPG_SHIFT) +# define CFGPG_CRYPTPG_GROUP0 CFGPG_CRYPTPG(CFGPG_GROUP0) +# define CFGPG_CRYPTPG_GROUP1 CFGPG_CRYPTPG(CFGPG_GROUP1) +# define CFGPG_CRYPTPG_GROUP2 CFGPG_CRYPTPG(CFGPG_GROUP2) +# define CFGPG_CRYPTPG_GROUP3 CFGPG_CRYPTPG(CFGPG_GROUP3) + +/* Alternate Device Configuration (Boot Flash PIC32MZ_BOOTCFG_K1BASE) */ +/* Device Configuration (Boot Flash PIC32MZ_BOOTCFG_K1BASE) */ +/* Device configuration word 3 / Alternate device configuration word 3 */ + +#define DEVCFG3_USERID_SHIFT (0) /* Bit 0-15: 16-bit user defined value */ +#define DEVCFG3_USERID_MASK (0xffff << DEVCFG3_USERID_SHIFT) +# define DEVCFG3_USERID(n) ((uint32_t)(n) << DEVCFG3_USERID_SHIFT) +#define DEVCFG3_FMIIEN_SHIFT (24) /* Bit 24: Ethernet MII Enable Configuration bit */ +#define DEVCFG3_FMIIEN (1 << 24) /* Bit 24: Ethernet MII Enable Configuration bit */ +#define DEVCFG3_FETHIO_SHIFT (25) /* Bit 25: Ethernet I/O Pin Selection Configuration bit */ +#define DEVCFG3_FETHIO (1 << 25) /* Bit 25: Ethernet I/O Pin Selection Configuration bit */ +#define DEVCFG3_PGL1WAY_SHIFT (27) /* Bit 27: Permission Group Lock One Way Configuration bit */ +#define DEVCFG3_PGL1WAY (1 << 27) /* Bit 27: Permission Group Lock One Way Configuration bit */ +#define DEVCFG3_PMDL1WAY_SHIFT (28) /* Bit 28: Peripheral Module Disable Configuration bit */ +#define DEVCFG3_PMDL1WAY (1 << 28) /* Bit 28: Peripheral Module Disable Configuration bit */ +#define DEVCFG3_IOL1WAY_SHIFT (29) /* Bit 29: Peripheral Pin Select Configuration bit */ +#define DEVCFG3_IOL1WAY (1 << 29) /* Bit 29: Peripheral Pin Select Configuration bit */ +#define DEVCFG3_FUSBIDIO_SHIFT (30) /* Bit 30: USB USBID Selection bit */ +#define DEVCFG3_FUSBIDIO (1 << 30) /* Bit 30: USB USBID Selection bit */ + +#define DEVCFG3_RWO 0x84ff0000 /* Bits 16-23, 31: Reserved, write as one */ + +/* Device configuration word 2 / Alternate device configuration word 2 */ + +#define DEVCFG2_FPLLIDIV_SHIFT (0) /* Bits 0-2: PLL Input Divider bits */ +#define DEVCFG2_FPLLIDIV_MASK (7 << DEVCFG2_FPLLIDIV_SHIFT) +# define DEVCFG2_FPLLIDIV(n) ((uint32_t)((n)-1) << DEVCFG2_FPLLIDIV_SHIFT) /* n=1..8 */ +# define DEVCFG2_FPLLIDIV_1 (0 << DEVCFG2_FPLLIDIV_SHIFT) /* Divide by 1 */ +# define DEVCFG2_FPLLIDIV_2 (1 << DEVCFG2_FPLLIDIV_SHIFT) /* Divide by 2 */ +# define DEVCFG2_FPLLIDIV_3 (2 << DEVCFG2_FPLLIDIV_SHIFT) /* Divide by 3 */ +# define DEVCFG2_FPLLIDIV_4 (3 << DEVCFG2_FPLLIDIV_SHIFT) /* Divide by 4 */ +# define DEVCFG2_FPLLIDIV_5 (4 << DEVCFG2_FPLLIDIV_SHIFT) /* Divide by 5 */ +# define DEVCFG2_FPLLIDIV_6 (5 << DEVCFG2_FPLLIDIV_SHIFT) /* Divide by 6 */ +# define DEVCFG2_FPLLIDIV_7 (6 << DEVCFG2_FPLLIDIV_SHIFT) /* Divide by 7 */ +# define DEVCFG2_FPLLIDIV_8 (7 << DEVCFG2_FPLLIDIV_SHIFT) /* Divide by 8 */ +#define DEVCFG2_FPLLRNG_SHIFT (4) /* Bits 4-6: System PLL Divided Input Clock Frequency Range bits */ +#define DEVCFG2_FPLLRNG_MASK (7 << DEVCFG2_FPLLRNG_SHIFT) +# define DEVCFG2_FPLLRNG_BYPASS (0 << DEVCFG2_FPLLRNG_SHIFT) /* Bypass */ +# define DEVCFG2_FPLLRNG_5_10MHZ (1 << DEVCFG2_FPLLRNG_SHIFT) /* 5-10 MHz */ +# define DEVCFG2_FPLLRNG_8_16MHZ (2 << DEVCFG2_FPLLRNG_SHIFT) /* 8-16 MHz */ +# define DEVCFG2_FPLLRNG_13_26MHZ (3 << DEVCFG2_FPLLRNG_SHIFT) /* 13-26 MHz */ +# define DEVCFG2_FPLLRNG_21_42MHZ (4 << DEVCFG2_FPLLRNG_SHIFT) /* 21-42 MHz */ +# define DEVCFG2_FPLLRNG_34_64MHZ (5 << DEVCFG2_FPLLRNG_SHIFT) /* 34-64 MHz */ +#define DEVCFG2_FPLLICLK (1 << 7) /* Bit 7: System PLL Input Clock Select bit */ +#define DEVCFG2_FPLLMULT_SHIFT (8) /* Bits 8-14: System PLL Feedback Divider bits */ +#define DEVCFG2_FPLLMULT_MASK (0x7f << DEVCFG2_FPLLMULT_SHIFT) +# define DEVCFG2_FPLLMULT(n) ((uint32_t)((n)-1) << DEVCFG2_FPLLMULT_SHIFT) /* n=1..128 */ +#define DEVCFG2_FPLLODIV_SHIFT (16) /* Bits 16-18: Default System PLL Output Divisor bits */ +#define DEVCFG2_FPLLODIV_MASK (7 << DEVCFG2_FPLLODIV_SHIFT) +# define DEVCFG2_FPLLODIV_2 (1 << DEVCFG2_FPLLODIV_SHIFT) /* PLL output divided by 2 */ +# define DEVCFG2_FPLLODIV_4 (2 << DEVCFG2_FPLLODIV_SHIFT) /* PLL output divided by 4 */ +# define DEVCFG2_FPLLODIV_8 (3 << DEVCFG2_FPLLODIV_SHIFT) /* PLL output divided by 8 */ +# define DEVCFG2_FPLLODIV_16 (4 << DEVCFG2_FPLLODIV_SHIFT) /* PLL output divided by 16 */ +# define DEVCFG2_FPLLODIV_32 (5 << DEVCFG2_FPLLODIV_SHIFT) /* PLL output divided by 32 */ +#define DEVCFG2_UPLLFSEL (1 << 30) /* Bit 30: USB PLL Input Frequency Select bit */ +# define DEVCFG2_UPLLFSEL_24MHZ (1 << 30) /* Bit 30=1: UPLL input clock is 24 MHz */ +# define DEVCFG2_UPLLFSEL_12MHZ (0 << 30) /* Bit 30=0: UPLL input clock is 12 MHz */ + +#define DEVCFG2_RWO 0xbff88008 /* Bits 3, 15, 19-29, 31: Reserved, write as one */ + +/* Device configuration word 1 / Alternate device configuration word 1 */ + +#define DEVCFG1_FNOSC_SHIFT (0) /* Bits 0-2: Oscillator Selection bits */ +#define DEVCFG1_FNOSC_MASK (7 << DEVCFG1_FNOSC_SHIFT) +# define DEVCFG1_FNOSC_FRC (0 << DEVCFG1_FNOSC_SHIFT) /* FRC divided by FRCDIV */ +# define DEVCFG1_FNOSC_SPLL (1 << DEVCFG1_FNOSC_SHIFT) /* SPLL */ +# define DEVCFG1_FNOSC_POSC (2 << DEVCFG1_FNOSC_SHIFT) /* POSC (HS, EC) */ +# define DEVCFG1_FNOSC_SOSC (4 << DEVCFG1_FNOSC_SHIFT) /* SOSC */ +# define DEVCFG1_FNOSC_LPRC (5 << DEVCFG1_FNOSC_SHIFT) /* LPRC */ +# define DEVCFG1_FNOSC_FRCDIV (7 << DEVCFG1_FNOSC_SHIFT) /* FRC divided by FRCDIV<2:0> */ +#define DEVCFG1_DMTINV_SHIFT (3) /* Bits 3-5: Deadman Timer Count Window Interval bits */ +#define DEVCFG1_DMTINV_MASK (7 << DEVCFG1_DMTINV_SHIFT) +# define DEVCFG1_DMTINV_0 (0 << DEVCFG1_DMTINV_SHIFT) /* Window/Interval value zero */ +# define DEVCFG1_DMTINV_1_2 (1 << DEVCFG1_DMTINV_SHIFT) /* Window/Interval value 1/2 counter */ +# define DEVCFG1_DMTINV_3_4 (2 << DEVCFG1_DMTINV_SHIFT) /* Window/Interval value 3/4 counter */ +# define DEVCFG1_DMTINV_7_8 (3 << DEVCFG1_DMTINV_SHIFT) /* Window/Interval value 7/8 counter */ +# define DEVCFG1_DMTINV_15_16 (4 << DEVCFG1_DMTINV_SHIFT) /* Window/Interval value 15/16 counter */ +# define DEVCFG1_DMTINV_31_32 (5 << DEVCFG1_DMTINV_SHIFT) /* Window/Interval value 31/32 counter */ +# define DEVCFG1_DMTINV_63_64 (6 << DEVCFG1_DMTINV_SHIFT) /* Window/Interval value 63/64 counter */ +# define DEVCFG1_DMTINV_127_128 (7 << DEVCFG1_DMTINV_SHIFT) /* Window/Interval value 127/128 counter */ +#define DEVCFG1_FSOSCEN (1 << 6) /* Bit 6: Secondary Oscillator Enable bit */ +#define DEVCFG1_IESO (1 << 7) /* Bit 7: Internal External Switchover bit */ +#define DEVCFG1_POSCMOD_SHIFT (8) /* Bits 8-9: Primary Oscillator Configuration bits */ +#define DEVCFG1_POSCMOD_MASK (3 << DEVCFG1_POSCMOD_SHIFT) +# define DEVCFG1_POSCMOD_EC (0 << DEVCFG1_POSCMOD_SHIFT) /* EC mode selected */ +# define DEVCFG1_POSCMOD_HS (2 << DEVCFG1_POSCMOD_SHIFT) /* HS Oscillator mode selected */ +# define DEVCFG1_POSCMOD_DIS (3 << DEVCFG1_POSCMOD_SHIFT) /* POSC disabled */ +#define DEVCFG1_OSCIOFNC (1 << 10) /* Bit 10: CLKO Enable Configuration bit */ +#define DEVCFG1_FCKSM_SHIFT (14) /* Bits 14-15: Clock Switching and Monitoring Selection */ +#define DEVCFG1_FCKSM_MASK (3 << DEVCFG1_FCKSM_SHIFT) +# define DEVCFG1_FCKSM_NONE (0 << DEVCFG1_FCKSM_SHIFT) /* Clock switching/monitoring disabled */ +# define DEVCFG1_FCKSM_SWITCH (1 << DEVCFG1_FCKSM_SHIFT) /* Clock switching enabled */ +# define DEVCFG1_FCKSM_MONITOR (2 << DEVCFG1_FCKSM_SHIFT) /* Clock monitoring enabled */ +# define DEVCFG1_FCKSM_BOTH (3 << DEVCFG1_FCKSM_SHIFT) /* Clock switching/monitoring enabled */ +#define DEVCFG1_WDTPS_SHIFT (16) /* Bits 16-20: Watchdog Timer Postscale Select bits */ +#define DEVCFG1_WDTPS_MASK (31 << DEVCFG1_WDTPS_SHIFT) +# define DEVCFG1_WDTPS_1 (0 << DEVCFG1_WDTPS_SHIFT) /* 1:1 */ +# define DEVCFG1_WDTPS_2 (1 << DEVCFG1_WDTPS_SHIFT) /* 1:2 */ +# define DEVCFG1_WDTPS_4 (2 << DEVCFG1_WDTPS_SHIFT) /* 1:4 */ +# define DEVCFG1_WDTPS_8 (3 << DEVCFG1_WDTPS_SHIFT) /* 1:8 */ +# define DEVCFG1_WDTPS_16 (4 << DEVCFG1_WDTPS_SHIFT) /* 1:16 */ +# define DEVCFG1_WDTPS_32 (5 << DEVCFG1_WDTPS_SHIFT) /* 1:32 */ +# define DEVCFG1_WDTPS_64 (6 << DEVCFG1_WDTPS_SHIFT) /* 1:64 */ +# define DEVCFG1_WDTPS_128 (7 << DEVCFG1_WDTPS_SHIFT) /* 1:128 */ +# define DEVCFG1_WDTPS_256 (8 << DEVCFG1_WDTPS_SHIFT) /* 1:256 */ +# define DEVCFG1_WDTPS_512 (9 << DEVCFG1_WDTPS_SHIFT) /* 1:512 */ +# define DEVCFG1_WDTPS_1024 (10 << DEVCFG1_WDTPS_SHIFT) /* 1:1024 */ +# define DEVCFG1_WDTPS_2048 (11 << DEVCFG1_WDTPS_SHIFT) /* 1:2048 */ +# define DEVCFG1_WDTPS_4096 (12 << DEVCFG1_WDTPS_SHIFT) /* 1:4096 */ +# define DEVCFG1_WDTPS_8192 (13 << DEVCFG1_WDTPS_SHIFT) /* 1:8192 */ +# define DEVCFG1_WDTPS_16384 (14 << DEVCFG1_WDTPS_SHIFT) /* 1:16384 */ +# define DEVCFG1_WDTPS_32768 (15 << DEVCFG1_WDTPS_SHIFT) /* 1:32768 */ +# define DEVCFG1_WDTPS_65536 (16 << DEVCFG1_WDTPS_SHIFT) /* 1:65536 */ +# define DEVCFG1_WDTPS_131072 (17 << DEVCFG1_WDTPS_SHIFT) /* 1:131072 */ +# define DEVCFG1_WDTPS_262144 (18 << DEVCFG1_WDTPS_SHIFT) /* 1:262144 */ +# define DEVCFG1_WDTPS_524288 (19 << DEVCFG1_WDTPS_SHIFT) /* 1:524288 */ +# define DEVCFG1_WDTPS_1048576 (20 << DEVCFG1_WDTPS_SHIFT) /* 1:1048576 */ +#define DEVCFG1_WDTSPGM (1 << 21) /* Bit 21: WDT stop/run during flash programming bit */ +# define DEVCFG1_WDTSPGM_STOP (1 << 21) /* Bit 21=1: WDT stops during flash programming */ +# define DEVCFG1_WDTSPGM_RUN (0 << 21) /* Bit 21=0: WDT runs during flash programming */ +#define DEVCFG1_WINDIS (1 << 22) /* Bit 22: Watchdog Timer Window Enable bit */ +# define DEVCFG1_WDT_NORMAL (1 << 22) /* Bit 22=1: Watchdog normal mode */ +# define DEVCFG1_WDT_WINDOW (0 << 22) /* Bit 22=0: Watchdog window mode */ +#define DEVCFG1_FWDTEN (1 << 23) /* Bit 23: Watchdog Timer Enable bit */ +# define DEVCFG1_FWDT_ENABLED (1 << 23) /* Bit 23=1: Watchdog enabled, cannot be disabled */ +# define DEVCFG1_FWDT_DISABLED (0 << 23) /* Bit 23=0: Watchdog disabled, can be enabled */ +#define DEVCFG1_FWDTWINSZ_SHIFT (24) /* Bits 24-25: Watchdog Timer Window Size bits */ +#define DEVCFG1_FWDTWINSZ_MASK (3 << DEVCFG1_FWDTWINSZ_SHIFT) +# define DEVCFG1_FWDTWINSZ_75 (0 << DEVCFG1_FWDTWINSZ_SHIFT) /* Window size is 75% */ +# define DEVCFG1_FWDTWINSZ_50 (1 << DEVCFG1_FWDTWINSZ_SHIFT) /* Window size is 50% */ +# define DEVCFG1_FWDTWINSZ_37p5 (2 << DEVCFG1_FWDTWINSZ_SHIFT) /* Window size is 37.5% */ +# define DEVCFG1_FWDTWINSZ_25 (3 << DEVCFG1_FWDTWINSZ_SHIFT) /* Window size is 25% */ +#define DEVCFG1_DMTCNT_SHIFT (26) /* Bits 26-30: Deadman Timer Count Select bits */ +#define DEVCFG1_DMTCNT_MASK (31 << DEVCFG1_DMTCNT_SHIFT) +# define DEVCFG1_DMTCNT(n) ((uint32_t)((n)-8) << DEVCFG1_DMTCNT_SHIFT) /* 2**n, n=8..31 */ +# define DEVCFG1_DMTCNT_MIN (0 << DEVCFG1_DMTCNT_SHIFT) /* 2**8 (256) */ +# define DEVCFG1_DMTCNT_MAX (23 << DEVCFG1_DMTCNT_SHIFT) /* 2**31 (2147483648) */ +#define DEVCFG1_FDMTEN (1 << 31) /* Bit 31: Deadman Timer enable bit */ + +#define DEVCFG1_RWO 0x00003800 /* Bits 11-13: Reserved, write as one */ + +/* Device configuration word 0 / Alternate device configuration word 0 */ + +#define DEVCFG0_DEBUG_SHIFT (0) /* Bits 0-1: Background Debugger Enable bits */ +#define DEVCFG0_DEBUG_MASK (3 << DEVCFG0_DEBUG_SHIFT) +# define DEVCFG0_DEBUG_ENABLED (2 << DEVCFG0_DEBUG_SHIFT) /* Debugger is enabled */ +# define DEVCFG0_DEBUG_DISABLED (3 << DEVCFG0_DEBUG_SHIFT) /* Debugger is disabled */ +#define DEVCFG0_JTAGEN (1 << 2) /* Bit 2: JTAG Enable bit(1) */ +#define DEVCFG0_ICESEL_SHIFT (3) /* Bits 3-4: ICE Communication Channel Select bits */ +#define DEVCFG0_ICESEL_MASK (3 << DEVCFG0_ICESEL_SHIFT) +# define DEVCFG0_ICESEL_1 (3 << DEVCFG0_ICESEL_SHIFT) /* PGEC1/PGED1 pair is used */ +# define DEVCFG0_ICESEL_2 (2 << DEVCFG0_ICESEL_SHIFT) /* PGEC2/PGED2 pair is used */ +#define DEVCFG0_TRCEN (1 << 5) /* Bit 5: Trace Enable bit */ +#define DEVCFG0_BOOTISA (1 << 6) /* Bit 6: Boot ISA Selection bit */ +# define DEVCFG0_BOOT_MIPS32 (1 << 6) /* Bit 6=1: Boot code and Exception code is MIPS32 */ +# define DEVCFG0_BOOT_MICROMIPS (0 << 6) /* Bit 6=0: Boot code and Exception code is microMIPS */ +#define DEVCFG0_FECCCON_SHIFT (8) /* Bit 8-9: Dynamic Flash ECC Configuration bits */ +#define DEVCFG0_FECCCON_MASK (3 << DEVCFG0_FECCCON_SHIFT) +# define DEVCFG0_FECCCON_ECC (0 << DEVCFG0_FECCCON_SHIFT) /* Flash ECC enabled (locked) */ +# define DEVCFG0_FECCCON_DYNECC (1 << DEVCFG0_FECCCON_SHIFT) /* Dynamic Flash ECC enabled (locked) */ +# define DEVCFG0_FECCCON_DISLCK (2 << DEVCFG0_FECCCON_SHIFT) /* ECC / dynamic ECC disabled (locked) */ +# define DEVCFG0_FECCCON_DISWR (3 << DEVCFG0_FECCCON_SHIFT) /* ECC / dynamic ECC disabled (writable) */ +#define DEVCFG0_FSLEEP (1 << 10) /* Bit 10: Flash Sleep Mode bit */ +# define DEVCFG0_FSLEEP_OFF (1 << 10) /* Bit 10=1: Flash powered down in sleep mode */ +# define DEVCFG0_FSLEEP_ON (0 << 10) /* Bit 10=0: Flash powerdown controlled by VREGS bit */ +#define DEVCFG0_DBGPER_SHIFT (12) /* Bits 12-14: Debug Mode CPU Access Permission bits */ +#define DEVCFG0_DBGPER_MASK (7 << DEVCFG0_DBGPER_SHIFT) +# define DEVCFG0_DBGPER_GROUP0 (1 << DEVCFG0_DBGPER_SHIFT) /* Allow/deny access to group 0 regions */ +# define DEVCFG0_DBGPER_GROUP1 (2 << DEVCFG0_DBGPER_SHIFT) /* Allow/deny access to group 1 regions */ +# define DEVCFG0_DBGPER_GROUP2 (4 << DEVCFG0_DBGPER_SHIFT) /* Allow/deny access to group 2 regions */ +# define DEVCFG0_DBGPER_ALL (7 << DEVCFG0_DBGPER_SHIFT) /* Allow/deny access to all regions */ +#define DEVCFG0_SMCLR (1 << 15) /* Bit 15: Soft Master Clear Enable bit */ +#define DEVCFG0_SOSCGAIN_SHIFT (16) /* Bits 16-17: Secondary Oscillator Gain Control bits */ +#define DEVCFG0_SOSCGAIN_MASK (3 << DEVCFG0_SOSCGAIN_SHIFT) +# define DEVCFG0_SOSCGAIN(n) ((uint32_t)(n) << DEVCFG0_SOSCGAIN_SHIFT) +# define DEVCFG0_SOSCGAIN_LOW (0 << DEVCFG0_SOSCGAIN_SHIFT) +# define DEVCFG0_SOSCGAIN_HIGH (3 << DEVCFG0_SOSCGAIN_SHIFT) +#define DEVCFG0_SOSCBOOST (1 << 18) /* Bit 18: Secondary Oscillator Boost Kick Start Enable bit */ +#define DEVCFG0_POSCGAIN_SHIFT (19) /* Bits 19-20: Primary Oscillator Gain Control bits */ +#define DEVCFG0_POSCGAIN_MASK (3 << DEVCFG0_POSCGAIN_SHIFT) +# define DEVCFG0_POSCGAIN(n) ((uint32_t)(n) << DEVCFG0_POSCGAIN_SHIFT) +# define DEVCFG0_POSCGAIN_LOW (0 << DEVCFG0_POSCGAIN_SHIFT) +# define DEVCFG0_POSCGAIN_HIGH (3 << DEVCFG0_POSCGAIN_SHIFT) +#define DEVCFG0_POSCBOOST (1 << 21) /* Bit 21: Primary Oscillator Boost Kick Start Enable bit */ +#define DEVCFG0_EJTAGBEN (1 << 30) /* Bit 30: EJTAG Boot Enable bit */ +# define DEVCFG0_EJTAG_NORMAL (1 << 30) /* Bit 30=1: Normal EJTAG functionality */ +# define DEVCFG0_EJTAG_REDUCED (0 << 30) /* Bit 30=0: Reduced EJTAG functionality */ + +#define DEVCFG0_RW0 0xbfe00880 /* Bits 7, 11, 21-29, 31: Reserved, write as one */ + +/* Device code protect words 1-3 / Alternate device code protect words 1-3 + * + * The DEVCP1 through DEVCP3 and ADEVCP1 through ADEVCP3 registers are used + * for Quad Word programming operation when programming the DEVCP0/ADEVCP0 + * registers, and do not contain any valid information. + */ + +/* Device code protect word 0 / Alternate device code protect word 0 */ + +#define DEVCP0_CP (1 << 28) /* Bit 28: Code-protect bit */ +#define DEVCP0_RWO 0xefffffff /* Bits 0-27, 28-31: Reserved, write as one */ + +/* Device signature words 1-3 / Alternate device signature words 1-3 + * + * The DEVSIGN1 through DEVSIGN3 and ADEVSIGN1 through ADEVSIGN3 registers + * are used for Quad Word programming operation when programming the + * DEVSIGN0/ADESIGN0 registers, and do not contain any valid information. + */ + +/* Device signature word 0 / Alternate device signature word 0 */ + +#define DEVSIGN0_RWZ 0x80000000 /* Bit 31: Reserved, write as zero */ +#define DEVSIGN0_RWO 0x7fffffff /* Bits 0-30: Reserved, write as one */ + +/* Device ADC Calibration (Boot Flash PIC32MZ_DEVSN_K1BASE) */ +/* ADC0-4,7 Calibration: 32-bit calibration values */ + +/* Device Serial Number (Boot Flash PIC32MZ_DEVSN_K1BASE) */ +/* Device serial number 0-1: 32-bit serial number data */ + +#endif /* __ARCH_MIPS_SRC_PIC32MZ_CHIP_PIC32MZEF_FEATURES_H */ diff --git a/arch/mips/src/pic32mz/chip/pic32mzef-memorymap.h b/arch/mips/src/pic32mz/chip/pic32mzef-memorymap.h new file mode 100644 index 0000000000..d54e7296bd --- /dev/null +++ b/arch/mips/src/pic32mz/chip/pic32mzef-memorymap.h @@ -0,0 +1,147 @@ +/************************************************************************************ + * arch/mips/src/pic32mz/chip/pic32mzef-memorymap.h + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_MIPS_SRC_PIC32MZ_CHIP_PIC32MZEF_MEMORYMAP_H +#define __ARCH_MIPS_SRC_PIC32MZ_CHIP_PIC32MZEF_MEMORYMAP_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include "mips32-memorymap.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ +/* Physical Memory Map **************************************************************/ +/* Memory Regions */ + +#define PIC32MZ_DATAMEM_PBASE 0x00000000 /* Size depends on CHIP_DATAMEM_KB */ +#define PIC32MZ_PROGFLASH_PBASE 0x1d000000 /* Size depends on CHIP_PROGFLASH_KB */ +#define PIC32MZ_SFR_PBASE 0x1f800000 /* Special function registers */ +#define PIC32MZ_BOOTFLASH_PBASE 0x1fc00000 /* Size depends on CHIP_BOOTFLASH_KB */ +#define PIC32MZ_EBIMEM_PBASE 0x20000000 /* External memory via EBI */ +#define PIC32MZ_SQIMEM_PBASE 0x30000000 /* External memory via SQI */ + +/* Boot FLASH */ + +#define PIC32MZ_LOWERBOOT_PBASE 0x1fc00000 /* Lower boot alias */ +#define PIC32MZ_BOOTCFG_PBASE 0x1fc0ff00 /* Configuration space */ +#define PIC32MZ_UPPERBOOT_PBASE 0x1fc20000 /* Upper boot alias */ +#define PIC32MZ_BOOT1_PBASE 0x1fc40000 /* Boot flash 1 */ +#define PIC32MZ_SEQCFG1_PBASE 0x1fc4ff00 /* Sequence/configuration space 1 */ +#define PIC32MZ_DEVSN_PBASE 0x1fc54000 /* Device serial number */ +#define PIC32MZ_BOOT2_PBASE 0x1fc60000 /* Boot flash 2 */ +#define PIC32MZ_SEQCFG2_PBASE 0x1fc6ff00 /* Sequence/configuration space 2 */ + +/* Virtual Memory Map ***************************************************************/ + +#define PIC32MZ_DATAMEM_K0BASE (KSEG0_BASE + PIC32MZ_DATAMEM_PBASE) +#define PIC32MZ_PROGFLASH_K0BASE (KSEG0_BASE + PIC32MZ_PROGFLASH_PBASE) +#define PIC32MZ_SFR_K0BASE (KSEG0_BASE + PIC32MZ_SFR_PBASE) +#define PIC32MZ_BOOTFLASH_K0BASE (KSEG0_BASE + PIC32MZ_BOOTFLASH_PBASE) +#define PIC32MZ_EBIMEM_K0BASE (KSEG0_BASE + PIC32MZ_EBIMEM_PBASE) +#define PIC32MZ_SQIMEM_K0BASE (KSEG0_BASE + PIC32MZ_SQIMEM_PBASE) + +#define PIC32MZ_DATAMEM_K1BASE (KSEG1_BASE + PIC32MZ_DATAMEM_PBASE) +#define PIC32MZ_PROGFLASH_K1BASE (KSEG1_BASE + PIC32MZ_PROGFLASH_PBASE) +#define PIC32MZ_SFR_K1BASE (KSEG1_BASE + PIC32MZ_SFR_PBASE) +#define PIC32MZ_BOOTFLASH_K1BASE (KSEG1_BASE + PIC32MZ_BOOTFLASH_PBASE) +#define PIC32MZ_EBIMEM_K1BASE (KSEG1_BASE + PIC32MZ_EBIMEM_PBASE) +#define PIC32MZ_SQIMEM_K1BASE (KSEG1_BASE + PIC32MZ_SQIMEM_PBASE) + +/* Boot FLASH */ + +#define PIC32MZ_LOWERBOOT_K0BASE (KSEG0_BASE + PIC32MZ_LOWERBOOT_PBASE) +#define PIC32MZ_BOOTCFG_K0BASE (KSEG0_BASE + PIC32MZ_BOOTCFG_PBASE) +#define PIC32MZ_UPPERBOOT_K0BASE (KSEG0_BASE + PIC32MZ_UPPERBOOT_PBASE) +#define PIC32MZ_BOOT1_K0BASE (KSEG0_BASE + PIC32MZ_BOOT1_PBASE) +#define PIC32MZ_SEQCFG1_K0BASE (KSEG0_BASE + PIC32MZ_SEQCFG1_PBASE) +#define PIC32MZ_DEVSN_K0BASE (KSEG0_BASE + PIC32MZ_DEVSN_PBASE) +#define PIC32MZ_BOOT2_K0BASE (KSEG0_BASE + PIC32MZ_BOOT2_PBASE) +#define PIC32MZ_SEQCFG2_K0BASE (KSEG0_BASE + PIC32MZ_SEQCFG2_PBASE) + +#define PIC32MZ_LOWERBOOT_K1BASE (KSEG1_BASE + PIC32MZ_LOWERBOOT_PBASE) +#define PIC32MZ_BOOTCFG_K1BASE (KSEG1_BASE + PIC32MZ_BOOTCFG_PBASE) +#define PIC32MZ_UPPERBOOT_K1BASE (KSEG1_BASE + PIC32MZ_UPPERBOOT_PBASE) +#define PIC32MZ_BOOT1_K1BASE (KSEG1_BASE + PIC32MZ_BOOT1_PBASE) +#define PIC32MZ_SEQCFG1_K1BASE (KSEG1_BASE + PIC32MZ_SEQCFG1_PBASE) +#define PIC32MZ_DEVSN_K1BASE (KSEG1_BASE + PIC32MZ_DEVSN_PBASE) +#define PIC32MZ_BOOT2_K1BASE (KSEG1_BASE + PIC32MZ_BOOT2_PBASE) +#define PIC32MZ_SEQCFG2_K1BASE (KSEG1_BASE + PIC32MZ_SEQCFG2_PBASE) + +/* Register Base Addresses **********************************************************/ + +#define PIC32MZ_CONFIG_K1BASE (PIC32MZ_SFR_K1BASE + 0x00000000) /* Configuration */ +#define PIC32MZ_FLASHC_K1BASE (PIC32MZ_SFR_K1BASE + 0x00000600) /* Flash Controller */ +#define PIC32MZ_WDT_K1BASE (PIC32MZ_SFR_K1BASE + 0x00000800) /* Watchdog Timer */ +#define PIC32MZ_DMT_K1BASE (PIC32MZ_SFR_K1BASE + 0x00000a00) /* Deadman Timer */ +#define PIC32MZ_RTCC_K1BASE (PIC32MZ_SFR_K1BASE + 0x00000c00) /* RTCC */ +#define PIC32MZ_CVREF_K1BASE (PIC32MZ_SFR_K1BASE + 0x00000e00) /* CVREF */ +#define PIC32MZ_OSC_K1BASE (PIC32MZ_SFR_K1BASE + 0x00001200) /* Oscillator */ +#define PIC32MZ_PPS_K1BASE (PIC32MZ_SFR_K1BASE + 0x00001400) /* PPS */ + +#define PIC32MZ_INT_K1BASE (PIC32MZ_SFR_K1BASE + 0x00010000) /* Interrupt Controller */ +#define PIC32MZ_DMA_K1BASE (PIC32MZ_SFR_K1BASE + 0x00011000) /* DMA */ + +#define PIC32MZ_I2C_K1BASE (PIC32MZ_SFR_K1BASE + 0x00020000) /* I2C1-I2C5 */ +#define PIC32MZ_SPI_K1BASE (PIC32MZ_SFR_K1BASE + 0x00021000) /* SPI1-SPI6 */ +#define PIC32MZ_UART_K1BASE (PIC32MZ_SFR_K1BASE + 0x00022000) /* UART1-UART6 */ +#define PIC32MZ_PMP_K1BASE (PIC32MZ_SFR_K1BASE + 0x0002e000) /* PMP */ + +#define PIC32MZ_TIMER_K1BASE (PIC32MZ_SFR_K1BASE + 0x00040000) /* Timer1-Timer9 */ +#define PIC32MZ_IC_K1BASE (PIC32MZ_SFR_K1BASE + 0x00042000) /* IC1-IC9 */ +#define PIC32MZ_OC_K1BASE (PIC32MZ_SFR_K1BASE + 0x00044000) /* OC1-OC9 */ +#define PIC32MZ_ADC1_K1BASE (PIC32MZ_SFR_K1BASE + 0x0004b000) /* ADC1 */ +#define PIC32MZ_CMP_K1BASE (PIC32MZ_SFR_K1BASE + 0x0004c000) /* Comparator 1, 2 */ + +#define PIC32MZ_IOPORT_K1BASE (PIC32MZ_SFR_K1BASE + 0x00060000) /* PORTA-PORTK */ + +#define PIC32MZ_CAN_K1BASE (PIC32MZ_SFR_K1BASE + 0x00080000) /* CAN1 and CAN2 */ +#define PIC32MZ_ETH_K1BASE (PIC32MZ_SFR_K1BASE + 0x00082000) /* Ethernet */ +#define PIC32MZ_USBCR_K1BASE (PIC32MZ_SFR_K1BASE + 0x00084000) /* USBCR */ + +#define PIC32MZ_PREFETCH_K1BASE (PIC32MZ_SFR_K1BASE + 0x000e0000) /* Prefetch */ +#define PIC32MZ_EBI_K1BASE (PIC32MZ_SFR_K1BASE + 0x000e1000) /* EBI */ +#define PIC32MZ_SQI1_K1BASE (PIC32MZ_SFR_K1BASE + 0x000e2000) /* SQI1 */ +#define PIC32MZ_USB_K1BASE (PIC32MZ_SFR_K1BASE + 0x000e3000) /* USB */ +#define PIC32MZ_CRYPTO_K1BASE (PIC32MZ_SFR_K1BASE + 0x000e5000) /* Crypto */ +#define PIC32MZ_RNG_K1BASE (PIC32MZ_SFR_K1BASE + 0x000e6000) /* RNG */ + +#define PIC32MZ_SYSBUS_K1BASE (PIC32MZ_SFR_K1BASE + 0x000f0000) /* System Bus */ + +#endif /* __ARCH_MIPS_SRC_PIC32MZ_CHIP_PIC32MZEF_MEMORYMAP_H */ diff --git a/arch/mips/src/pic32mz/chip/pic32mzef-pps.h b/arch/mips/src/pic32mz/chip/pic32mzef-pps.h new file mode 100644 index 0000000000..8e65d3f3e9 --- /dev/null +++ b/arch/mips/src/pic32mz/chip/pic32mzef-pps.h @@ -0,0 +1,1719 @@ +/******************************************************************************************** + * arch/mips/src/pic32mz/pic32mzef-pps.h + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ********************************************************************************************/ + +#ifndef __ARCH_MIPS_SRC_PIC32MZ_CHIP_PIC32MZEF_PPS_H +#define __ARCH_MIPS_SRC_PIC32MZ_CHIP_PIC32MZEF_PPS_H + +/******************************************************************************************** + * Included Files + ********************************************************************************************/ + +#include "pic32mz-memorymap.h" + +/******************************************************************************************** + * Pre-processor Definitions + ********************************************************************************************/ +/* PPS Register Offsets *********************************************************************/ + +/* Peripheral pin select input register map */ + +#define PIC32MZ_INTnR_OFFSET(n) (0x1400 + ((n << 2)) /* n=1..4 */ +# define PIC32MZ_INT1R_OFFSET 0x1404 +# define PIC32MZ_INT2R_OFFSET 0x1408 +# define PIC32MZ_INT3R_OFFSET 0x140c +# define PIC32MZ_INT4R_OFFSET 0x1410 +#define PIC32MZ_TnCKR_OFFSET(n) (0x1410 + ((n << 2)) /* n=2..9 */ +# define PIC32MZ_I2TKR_OFFSET 0x1418 +# define PIC32MZ_I3TKR_OFFSET 0x141c +# define PIC32MZ_I4TKR_OFFSET 0x1420 +# define PIC32MZ_I5TKR_OFFSET 0x1424 +# define PIC32MZ_I6TKR_OFFSET 0x1428 +# define PIC32MZ_I7TKR_OFFSET 0x142c +# define PIC32MZ_I8TKR_OFFSET 0x1430 +# define PIC32MZ_I9TKR_OFFSET 0x1434 +#define PIC32MZ_ICnR_OFFSET(n) (0x1434 + ((n << 2)) /* n=1..9 */ +# define PIC32MZ_IC1R_OFFSET 0x1438 +# define PIC32MZ_IC2R_OFFSET 0x143c +# define PIC32MZ_IC3R_OFFSET 0x1440 +# define PIC32MZ_IC4R_OFFSET 0x1444 +# define PIC32MZ_IC5R_OFFSET 0x1448 +# define PIC32MZ_IC6R_OFFSET 0x144c +# define PIC32MZ_IC7R_OFFSET 0x1450 +# define PIC32MZ_IC8R_OFFSET 0x1454 +# define PIC32MZ_IC9R_OFFSET 0x1458 +#define PIC32MZ_OCFAR_OFFSET 0x1460 +#define PIC32MZ_UnRXR_OFFSET(n) (0x1460 + ((n << 3)) /* n=1..6 */ +# define PIC32MZ_U1RXR_OFFSET 0x1468 +# define PIC32MZ_U2RXR_OFFSET 0x1470 +# define PIC32MZ_U3RXR_OFFSET 0x1478 +# define PIC32MZ_U4RXR_OFFSET 0x1480 +# define PIC32MZ_U5RXR_OFFSET 0x1488 +# define PIC32MZ_U6RXR_OFFSET 0x1490 +#define PIC32MZ_UnCTSR_OFFSET(n) (0x1464 + ((n << 3)) /* n=1..6 */ +# define PIC32MZ_U1CTSR_OFFSET 0x146c +# define PIC32MZ_U2CTSR_OFFSET 0x1474 +# define PIC32MZ_U3CTSR_OFFSET 0x147c +# define PIC32MZ_U4CTSR_OFFSET 0x1484 +# define PIC32MZ_U5CTSR_OFFSET 0x148c +# define PIC32MZ_U6CTSR_OFFSET 0x1494 +#define PIC32MZ_SDInR_OFFSET(n) (0x1490 + 12*(n)) /* n=1..6 */ +# define PIC32MZ_SDI1R_OFFSET 0x149c +# define PIC32MZ_SDI2R_OFFSET 0x14a8 +# define PIC32MZ_SDI3R_OFFSET 0x14b4 +# define PIC32MZ_SDI4R_OFFSET 0x14c0 +# define PIC32MZ_SDI5R_OFFSET 0x14cc +# define PIC32MZ_SDI6R_OFFSET 0x14d8 +#define PIC32MZ_SSnR_OFFSET(n) (0x1494 + 12*(n)) /* n=1..6 */ +# define PIC32MZ_SS1R_OFFSET 0x14a0 +# define PIC32MZ_SS2R_OFFSET 0x14ac +# define PIC32MZ_SS3R_OFFSET 0x14b8 +# define PIC32MZ_SS4R_OFFSET 0x14c4 +# define PIC32MZ_SS5R_OFFSET 0x14d0 +# define PIC32MZ_SS6R_OFFSET 0x14dc +#define PIC32MZ_CnRXR_OFFSET(n) (0x14dc + ((n) << 2)) /* n=1..2 */ +# define PIC32MZ_C1RXR_OFFSET 0x14e0 +# define PIC32MZ_C2RXR_OFFSET 0x14e4 +#define PIC32MZ_REFCLKInR_OFFSET(n) (0x14e4 + ((n) << 2)) /* n=1,3,4 */ +# define PIC32MZ_REFCLKI1R_OFFSET 0x14e8 +# define PIC32MZ_REFCLKI3R_OFFSET 0x14f0 +# define PIC32MZ_REFCLKI4R_OFFSET 0x14f4 + +/* Peripheral pin select output register map */ + +#define PIC32MZ_RPAnR_OFFSET(n) (0x1500 + ((n) << 2)) /* n=14,15 */ +# define PIC32MZ_RPA14R_OFFSET 0x1538 +# define PIC32MZ_RPA15R_OFFSET 0x153c +#define PIC32MZ_RPBnR_OFFSET(n) (0x1540 + ((n) << 2)) /* n=0..,15 */ +# define PIC32MZ_RPB0R_OFFSET 0x1540 +# define PIC32MZ_RPB1R_OFFSET 0x1544 +# define PIC32MZ_RPB2R_OFFSET 0x1548 +# define PIC32MZ_RPB3R_OFFSET 0x154c +# define PIC32MZ_RPB4R_OFFSET 0x1550 +# define PIC32MZ_RPB5R_OFFSET 0x1554 +# define PIC32MZ_RPB6R_OFFSET 0x1558 +# define PIC32MZ_RPB7R_OFFSET 0x155c +# define PIC32MZ_RPB8R_OFFSET 0x1560 +# define PIC32MZ_RPB9R_OFFSET 0x1564 +# define PIC32MZ_RPB10R_OFFSET 0x1568 +# define PIC32MZ_RPB11R_OFFSET 0x156c +# define PIC32MZ_RPB12R_OFFSET 0x1570 +# define PIC32MZ_RPB13R_OFFSET 0x1574 +# define PIC32MZ_RPB14R_OFFSET 0x1578 +# define PIC32MZ_RPB15R_OFFSET 0x157c +#define PIC32MZ_RPCnR_OFFSET(n) (0x1580 + ((n) << 2)) /* n=1..4,13,14 */ +# define PIC32MZ_RPC1R_OFFSET 0x1584 +# define PIC32MZ_RPC2R_OFFSET 0x1588 +# define PIC32MZ_RPC3R_OFFSET 0x158c +# define PIC32MZ_RPC4R_OFFSET 0x1590 +# define PIC32MZ_RPC13R_OFFSET 0x15b4 +# define PIC32MZ_RPC14R_OFFSET 0x15b8 +#define PIC32MZ_RPDnR_OFFSET(n) (0x15c0 + ((n) << 2)) /* n=0..15 */ +# define PIC32MZ_RPD0R_OFFSET 0x15c0 +# define PIC32MZ_RPD1R_OFFSET 0x15c4 +# define PIC32MZ_RPD2R_OFFSET 0x15c8 +# define PIC32MZ_RPD3R_OFFSET 0x15cc +# define PIC32MZ_RPD4R_OFFSET 0x15d0 +# define PIC32MZ_RPD5R_OFFSET 0x15d4 +# define PIC32MZ_RPD6R_OFFSET 0x15d8 +# define PIC32MZ_RPD7R_OFFSET 0x15dc +# define PIC32MZ_RPD8R_OFFSET 0x15e0 +# define PIC32MZ_RPD9R_OFFSET 0x15e4 +# define PIC32MZ_RPD10R_OFFSET 0x15e8 +# define PIC32MZ_RPD11R_OFFSET 0x15ec +# define PIC32MZ_RPD12R_OFFSET 0x15f0 +# define PIC32MZ_RPD13R_OFFSET 0x15f4 +# define PIC32MZ_RPD14R_OFFSET 0x15f8 +# define PIC32MZ_RPD15R_OFFSET 0x15fc +#define PIC32MZ_RPEnR_OFFSET(n) (0x1600 + ((n) << 2)) /* n=3,5,8-9 */ +# define PIC32MZ_RPE3R_OFFSET 0x160c +# define PIC32MZ_RPE4R_OFFSET 0x1614 +# define PIC32MZ_RPE8R_OFFSET 0x1620 +# define PIC32MZ_RPE9R_OFFSET 0x1624 +#define PIC32MZ_RPFnR_OFFSET(n) (0x1640 + ((n) << 2)) /* n=0-5,8,12-13 */ +# define PIC32MZ_RPF0R_OFFSET 0x1640 +# define PIC32MZ_RPF1R_OFFSET 0x1644 +# define PIC32MZ_RPF2R_OFFSET 0x1648 +# define PIC32MZ_RPF3R_OFFSET 0x164c +# define PIC32MZ_RPF4R_OFFSET 0x1650 +# define PIC32MZ_RPF5R_OFFSET 0x1654 +# define PIC32MZ_RPF8R_OFFSET 0x1660 +# define PIC32MZ_RPF12R_OFFSET 0x1670 +# define PIC32MZ_RPF13R_OFFSET 0x1674 +#define PIC32MZ_RPGnR_OFFSET(n) (0x1680 + ((n) << 2)) /* n=0-1,6-8,9 */ +# define PIC32MZ_RPG0R_OFFSET 0x1680 +# define PIC32MZ_RPG1R_OFFSET 0x1684 +# define PIC32MZ_RPG6R_OFFSET 0x1698 +# define PIC32MZ_RPG7R_OFFSET 0x169c +# define PIC32MZ_RPG8R_OFFSET 0x16a0 +# define PIC32MZ_RPG9R_OFFSET 0x16a4 + +/* PPS Register Addresses *******************************************************************/ + +/* Peripheral pin select input register map */ + +#define PIC32MZ_INTnR(n) (PIC32MZ_SFR_K1BASE+PIC32MZ_INTnR_OFFSET(n)) +# define PIC32MZ_INT1R (PIC32MZ_SFR_K1BASE+PIC32MZ_INT1R_OFFSET) +# define PIC32MZ_INT2R (PIC32MZ_SFR_K1BASE+PIC32MZ_INT2R_OFFSET) +# define PIC32MZ_INT3R (PIC32MZ_SFR_K1BASE+PIC32MZ_INT3R_OFFSET) +# define PIC32MZ_INT4R (PIC32MZ_SFR_K1BASE+PIC32MZ_INT4R_OFFSET) +#define PIC32MZ_TnCKR(n) (PIC32MZ_SFR_K1BASE+PIC32MZ_TnCKR_OFFSET(n)) +# define PIC32MZ_I2TKR (PIC32MZ_SFR_K1BASE+PIC32MZ_I2TKR_OFFSET) +# define PIC32MZ_I3TKR (PIC32MZ_SFR_K1BASE+PIC32MZ_I3TKR_OFFSET) +# define PIC32MZ_I4TKR (PIC32MZ_SFR_K1BASE+PIC32MZ_I4TKR_OFFSET) +# define PIC32MZ_I5TKR (PIC32MZ_SFR_K1BASE+PIC32MZ_I5TKR_OFFSET) +# define PIC32MZ_I6TKR (PIC32MZ_SFR_K1BASE+PIC32MZ_I6TKR_OFFSET) +# define PIC32MZ_I7TKR (PIC32MZ_SFR_K1BASE+PIC32MZ_I7TKR_OFFSET) +# define PIC32MZ_I8TKR (PIC32MZ_SFR_K1BASE+PIC32MZ_I8TKR_OFFSET) +# define PIC32MZ_I9TKR (PIC32MZ_SFR_K1BASE+PIC32MZ_I9TKR_OFFSET) +#define PIC32MZ_ICnR(n) (PIC32MZ_SFR_K1BASE+PIC32MZ_ICnR_OFFSET(n)) +# define PIC32MZ_IC1R (PIC32MZ_SFR_K1BASE+PIC32MZ_IC1R_OFFSET) +# define PIC32MZ_IC2R (PIC32MZ_SFR_K1BASE+PIC32MZ_IC2R_OFFSET) +# define PIC32MZ_IC3R (PIC32MZ_SFR_K1BASE+PIC32MZ_IC3R_OFFSET) +# define PIC32MZ_IC4R (PIC32MZ_SFR_K1BASE+PIC32MZ_IC4R_OFFSET) +# define PIC32MZ_IC5R (PIC32MZ_SFR_K1BASE+PIC32MZ_IC5R_OFFSET) +# define PIC32MZ_IC6R (PIC32MZ_SFR_K1BASE+PIC32MZ_IC6R_OFFSET) +# define PIC32MZ_IC7R (PIC32MZ_SFR_K1BASE+PIC32MZ_IC7R_OFFSET) +# define PIC32MZ_IC8R (PIC32MZ_SFR_K1BASE+PIC32MZ_IC8R_OFFSET) +# define PIC32MZ_IC9R (PIC32MZ_SFR_K1BASE+PIC32MZ_IC9R_OFFSET) +#define PIC32MZ_OCFAR (PIC32MZ_SFR_K1BASE+PIC32MZ_OCFAR_OFFSET) +#define PIC32MZ_UnRXR(n) (PIC32MZ_SFR_K1BASE+PIC32MZ_UnRXR_OFFSET(n)) +# define PIC32MZ_U1RXR (PIC32MZ_SFR_K1BASE+PIC32MZ_U1RXR_OFFSET) +# define PIC32MZ_U2RXR (PIC32MZ_SFR_K1BASE+PIC32MZ_U2RXR_OFFSET) +# define PIC32MZ_U3RXR (PIC32MZ_SFR_K1BASE+PIC32MZ_U3RXR_OFFSET) +# define PIC32MZ_U4RXR (PIC32MZ_SFR_K1BASE+PIC32MZ_U4RXR_OFFSET) +# define PIC32MZ_U5RXR (PIC32MZ_SFR_K1BASE+PIC32MZ_U5RXR_OFFSET) +# define PIC32MZ_U6RXR (PIC32MZ_SFR_K1BASE+PIC32MZ_U6RXR_OFFSET) +#define PIC32MZ_UnCTSR(n) (PIC32MZ_SFR_K1BASE+PIC32MZ_UnCTSR_OFFSET(n) +# define PIC32MZ_U1CTSR (PIC32MZ_SFR_K1BASE+PIC32MZ_U1CTSR_OFFSET) +# define PIC32MZ_U2CTSR (PIC32MZ_SFR_K1BASE+PIC32MZ_U2CTSR_OFFSET) +# define PIC32MZ_U3CTSR (PIC32MZ_SFR_K1BASE+PIC32MZ_U3CTSR_OFFSET) +# define PIC32MZ_U4CTSR (PIC32MZ_SFR_K1BASE+PIC32MZ_U4CTSR_OFFSET) +# define PIC32MZ_U5CTSR (PIC32MZ_SFR_K1BASE+PIC32MZ_U5CTSR_OFFSET) +# define PIC32MZ_U6CTSR (PIC32MZ_SFR_K1BASE+PIC32MZ_U6CTSR_OFFSET) +#define PIC32MZ_SDInR(n) (PIC32MZ_SFR_K1BASE+PIC32MZ_SDInR_OFFSET(n)) +# define PIC32MZ_SDI1R (PIC32MZ_SFR_K1BASE+PIC32MZ_SDI1R_OFFSET) +# define PIC32MZ_SDI2R (PIC32MZ_SFR_K1BASE+PIC32MZ_SDI2R_OFFSET) +# define PIC32MZ_SDI3R (PIC32MZ_SFR_K1BASE+PIC32MZ_SDI3R_OFFSET) +# define PIC32MZ_SDI4R (PIC32MZ_SFR_K1BASE+PIC32MZ_SDI4R_OFFSET) +# define PIC32MZ_SDI5R (PIC32MZ_SFR_K1BASE+PIC32MZ_SDI5R_OFFSET) +# define PIC32MZ_SDI6R (PIC32MZ_SFR_K1BASE+PIC32MZ_SDI6R_OFFSET) +#define PIC32MZ_SSnR(n) (PIC32MZ_SFR_K1BASE+PIC32MZ_SSnR_OFFSET(n)) +# define PIC32MZ_SS1R (PIC32MZ_SFR_K1BASE+PIC32MZ_SS1R_OFFSET) +# define PIC32MZ_SS2R (PIC32MZ_SFR_K1BASE+PIC32MZ_SS2R_OFFSET) +# define PIC32MZ_SS3R (PIC32MZ_SFR_K1BASE+PIC32MZ_SS3R_OFFSET) +# define PIC32MZ_SS4R (PIC32MZ_SFR_K1BASE+PIC32MZ_SS4R_OFFSET) +# define PIC32MZ_SS5R (PIC32MZ_SFR_K1BASE+PIC32MZ_SS5R_OFFSET) +# define PIC32MZ_SS6R (PIC32MZ_SFR_K1BASE+PIC32MZ_SS6R_OFFSET) +#define PIC32MZ_CnRXR(n) (PIC32MZ_SFR_K1BASE+PIC32MZ_CnRXR_OFFSET(n)) +# define PIC32MZ_C1RXR (PIC32MZ_SFR_K1BASE+PIC32MZ_C1RXR_OFFSET) +# define PIC32MZ_C2RXR (PIC32MZ_SFR_K1BASE+PIC32MZ_C2RXR_OFFSET) +#define PIC32MZ_REFCLKInR(n) (PIC32MZ_SFR_K1BASE+PIC32MZ_REFCLKInR_OFFSET(n)) +# define PIC32MZ_REFCLKI1R (PIC32MZ_SFR_K1BASE+PIC32MZ_REFCLKI1R_OFFSET) +# define PIC32MZ_REFCLKI3R (PIC32MZ_SFR_K1BASE+PIC32MZ_REFCLKI3R_OFFSET) +# define PIC32MZ_REFCLKI4R (PIC32MZ_SFR_K1BASE+PIC32MZ_REFCLKI4R_OFFSET) + +/* Peripheral pin select output register map */ + +#define PIC32MZ_RPAnR(n) (PIC32MZ_SFR_K1BASE+PIC32MZ_RPAnR_OFFSET(n)) +# define PIC32MZ_RPA14R (PIC32MZ_SFR_K1BASE+PIC32MZ_RPA14R_OFFSET) +# define PIC32MZ_RPA15R (PIC32MZ_SFR_K1BASE+PIC32MZ_RPA15R_OFFSET) +#define PIC32MZ_RPBnR(n) (PIC32MZ_SFR_K1BASE+PIC32MZ_RPBnR_OFFSET(n)) +# define PIC32MZ_RPB0R (PIC32MZ_SFR_K1BASE+PIC32MZ_RPB0R_OFFSET) +# define PIC32MZ_RPB1R (PIC32MZ_SFR_K1BASE+PIC32MZ_RPB1R_OFFSET) +# define PIC32MZ_RPB2R (PIC32MZ_SFR_K1BASE+PIC32MZ_RPB2R_OFFSET) +# define PIC32MZ_RPB3R (PIC32MZ_SFR_K1BASE+PIC32MZ_RPB3R_OFFSET) +# define PIC32MZ_RPB4R (PIC32MZ_SFR_K1BASE+PIC32MZ_RPB4R_OFFSET) +# define PIC32MZ_RPB5R (PIC32MZ_SFR_K1BASE+PIC32MZ_RPB5R_OFFSET) +# define PIC32MZ_RPB6R (PIC32MZ_SFR_K1BASE+PIC32MZ_RPB6R_OFFSET) +# define PIC32MZ_RPB7R (PIC32MZ_SFR_K1BASE+PIC32MZ_RPB7R_OFFSET) +# define PIC32MZ_RPB8R (PIC32MZ_SFR_K1BASE+PIC32MZ_RPB8R_OFFSET) +# define PIC32MZ_RPB9R (PIC32MZ_SFR_K1BASE+PIC32MZ_RPB9R_OFFSET) +# define PIC32MZ_RPB10R (PIC32MZ_SFR_K1BASE+PIC32MZ_RPB10R_OFFSET) +# define PIC32MZ_RPB11R (PIC32MZ_SFR_K1BASE+PIC32MZ_RPB11R_OFFSET) +# define PIC32MZ_RPB12R (PIC32MZ_SFR_K1BASE+PIC32MZ_RPB12R_OFFSET) +# define PIC32MZ_RPB13R (PIC32MZ_SFR_K1BASE+PIC32MZ_RPB13R_OFFSET) +# define PIC32MZ_RPB14R (PIC32MZ_SFR_K1BASE+PIC32MZ_RPB14R_OFFSET) +# define PIC32MZ_RPB15R (PIC32MZ_SFR_K1BASE+PIC32MZ_RPB15R_OFFSET) +#define PIC32MZ_RPCnR(n) (PIC32MZ_SFR_K1BASE+PIC32MZ_RPCnR_OFFSET(n)) +# define PIC32MZ_RPC1R (PIC32MZ_SFR_K1BASE+PIC32MZ_RPC1R_OFFSET) +# define PIC32MZ_RPC2R (PIC32MZ_SFR_K1BASE+PIC32MZ_RPC2R_OFFSET) +# define PIC32MZ_RPC3R (PIC32MZ_SFR_K1BASE+PIC32MZ_RPC3R_OFFSET) +# define PIC32MZ_RPC4R (PIC32MZ_SFR_K1BASE+PIC32MZ_RPC4R_OFFSET) +# define PIC32MZ_RPC13R (PIC32MZ_SFR_K1BASE+PIC32MZ_RPC13R_OFFSET) +# define PIC32MZ_RPC14R (PIC32MZ_SFR_K1BASE+PIC32MZ_RPC14R_OFFSET) +#define PIC32MZ_RPDnR(n) (PIC32MZ_SFR_K1BASE+PIC32MZ_RPDnR_OFFSET(n)) +# define PIC32MZ_RPD0R (PIC32MZ_SFR_K1BASE+PIC32MZ_RPD0R_OFFSET) +# define PIC32MZ_RPD1R (PIC32MZ_SFR_K1BASE+PIC32MZ_RPD1R_OFFSET) +# define PIC32MZ_RPD2R (PIC32MZ_SFR_K1BASE+PIC32MZ_RPD2R_OFFSET) +# define PIC32MZ_RPD3R (PIC32MZ_SFR_K1BASE+PIC32MZ_RPD3R_OFFSET) +# define PIC32MZ_RPD4R (PIC32MZ_SFR_K1BASE+PIC32MZ_RPD4R_OFFSET) +# define PIC32MZ_RPD5R (PIC32MZ_SFR_K1BASE+PIC32MZ_RPD5R_OFFSET) +# define PIC32MZ_RPD6R (PIC32MZ_SFR_K1BASE+PIC32MZ_RPD6R_OFFSET) +# define PIC32MZ_RPD7R (PIC32MZ_SFR_K1BASE+PIC32MZ_RPD7R_OFFSET) +# define PIC32MZ_RPD8R (PIC32MZ_SFR_K1BASE+PIC32MZ_RPD8R_OFFSET) +# define PIC32MZ_RPD9R (PIC32MZ_SFR_K1BASE+PIC32MZ_RPD9R_OFFSET) +# define PIC32MZ_RPD10R (PIC32MZ_SFR_K1BASE+PIC32MZ_RPD10R_OFFSET) +# define PIC32MZ_RPD11R (PIC32MZ_SFR_K1BASE+PIC32MZ_RPD11R_OFFSET) +# define PIC32MZ_RPD12R (PIC32MZ_SFR_K1BASE+PIC32MZ_RPD12R_OFFSET) +# define PIC32MZ_RPD13R (PIC32MZ_SFR_K1BASE+PIC32MZ_RPD13R_OFFSET) +# define PIC32MZ_RPD14R (PIC32MZ_SFR_K1BASE+PIC32MZ_RPD14R_OFFSET) +# define PIC32MZ_RPD15R (PIC32MZ_SFR_K1BASE+PIC32MZ_RPD15R_OFFSET) +#define PIC32MZ_RPEnR(n) (PIC32MZ_SFR_K1BASE+PIC32MZ_RPEnR_OFFSET(n)) +# define PIC32MZ_RPE3R (PIC32MZ_SFR_K1BASE+PIC32MZ_RPE3R_OFFSET) +# define PIC32MZ_RPE4R (PIC32MZ_SFR_K1BASE+PIC32MZ_RPE4R_OFFSET) +# define PIC32MZ_RPE8R (PIC32MZ_SFR_K1BASE+PIC32MZ_RPE8R_OFFSET) +# define PIC32MZ_RPE9R (PIC32MZ_SFR_K1BASE+PIC32MZ_RPE9R_OFFSET) +#define PIC32MZ_RPFnR(n) (PIC32MZ_SFR_K1BASE+PIC32MZ_RPFnR_OFFSET(n)) +# define PIC32MZ_RPF0R (PIC32MZ_SFR_K1BASE+PIC32MZ_RPF0R_OFFSET) +# define PIC32MZ_RPF1R (PIC32MZ_SFR_K1BASE+PIC32MZ_RPF1R_OFFSET) +# define PIC32MZ_RPF2R (PIC32MZ_SFR_K1BASE+PIC32MZ_RPF2R_OFFSET) +# define PIC32MZ_RPF3R (PIC32MZ_SFR_K1BASE+PIC32MZ_RPF3R_OFFSET) +# define PIC32MZ_RPF4R (PIC32MZ_SFR_K1BASE+PIC32MZ_RPF4R_OFFSET) +# define PIC32MZ_RPF5R (PIC32MZ_SFR_K1BASE+PIC32MZ_RPF5R_OFFSET) +# define PIC32MZ_RPF8R (PIC32MZ_SFR_K1BASE+PIC32MZ_RPF8R_OFFSET) +# define PIC32MZ_RPF12R (PIC32MZ_SFR_K1BASE+PIC32MZ_RPF12R_OFFSET) +# define PIC32MZ_RPF13R (PIC32MZ_SFR_K1BASE+PIC32MZ_RPF13R_OFFSET) +#define PIC32MZ_RPGnR(n) (PIC32MZ_SFR_K1BASE+PIC32MZ_RPGnR_OFFSET(n)) +# define PIC32MZ_RPG0R (PIC32MZ_SFR_K1BASE+PIC32MZ_RPG0R_OFFSET) +# define PIC32MZ_RPG1R (PIC32MZ_SFR_K1BASE+PIC32MZ_RPG1R_OFFSET) +# define PIC32MZ_RPG6R (PIC32MZ_SFR_K1BASE+PIC32MZ_RPG6R_OFFSET) +# define PIC32MZ_RPG7R (PIC32MZ_SFR_K1BASE+PIC32MZ_RPG7R_OFFSET) +# define PIC32MZ_RPG8R (PIC32MZ_SFR_K1BASE+PIC32MZ_RPG8R_OFFSET) +# define PIC32MZ_RPG9R (PIC32MZ_SFR_K1BASE+PIC32MZ_RPG9R_OFFSET) + +/* Input Pin Selection **********************************************************************/ +/* The encoding of the input pin selection is simple. Since we know the devices, we also + * can infer the register address so we need only the value for the register which is + * exactly what is provided by the following definitions. + */ + +#define C1RXR_RPA15 13 +#define C1RXR_RPB1 5 +#define C1RXR_RPB3 8 +#define C1RXR_RPC4 10 +#define C1RXR_RPC13 7 +#define C1RXR_RPD3 0 +#define C1RXR_RPD7 14 +#define C1RXR_RPD11 3 +#define C1RXR_RPD15 11 +#define C1RXR_RPE5 6 +#define C1RXR_RPF0 4 +#define C1RXR_RPF5 2 +#define C1RXR_RPG0 12 +#define C1RXR_RPG7 1 + +#define C2RXR_RPB0 5 +#define C2RXR_RPB7 7 +#define C2RXR_RPB8 2 +#define C2RXR_RPB15 3 +#define C2RXR_RPC3 12 +#define C2RXR_RPD4 4 +#define C2RXR_RPD9 0 +#define C2RXR_RPD12 10 +#define C2RXR_RPE3 6 +#define C2RXR_RPE9 13 +#define C2RXR_RPF8 11 +#define C2RXR_RPF12 9 +#define C2RXR_RPG6 1 + +#define IC1R_RPB2 7 +#define IC1R_RPB6 5 +#define IC1R_RPB14 2 +#define IC1R_RPC2 12 +#define IC1R_RPD0 3 +#define IC1R_RPD1 0 +#define IC1R_RPD5 6 +#define IC1R_RPE8 13 +#define IC1R_RPF2 11 +#define IC1R_RPF3 8 +#define IC1R_RPF13 9 +#define IC1R_RPG9 1 + +#define IC2R_RPB0 5 +#define IC2R_RPB7 7 +#define IC2R_RPB8 2 +#define IC2R_RPB15 3 +#define IC2R_RPC3 12 +#define IC2R_RPD4 4 +#define IC2R_RPD9 0 +#define IC2R_RPD12 10 +#define IC2R_RPE3 6 +#define IC2R_RPE9 13 +#define IC2R_RPF8 11 +#define IC2R_RPF12 9 +#define IC2R_RPG6 1 + +#define IC3R_RPA14 13 +#define IC3R_RPB5 8 +#define IC3R_RPB9 5 +#define IC3R_RPB10 6 +#define IC3R_RPC1 10 +#define IC3R_RPC14 7 +#define IC3R_RPD2 0 +#define IC3R_RPD6 14 +#define IC3R_RPD10 3 +#define IC3R_RPD14 11 +#define IC3R_RPF1 4 +#define IC3R_RPF4 2 +#define IC3R_RPG1 12 +#define IC3R_RPG8 1 + +#define IC4R_RPA15 13 +#define IC4R_RPB1 5 +#define IC4R_RPB3 8 +#define IC4R_RPC4 10 +#define IC4R_RPC13 7 +#define IC4R_RPD3 0 +#define IC4R_RPD7 14 +#define IC4R_RPD11 3 +#define IC4R_RPD15 11 +#define IC4R_RPE5 6 +#define IC4R_RPF0 4 +#define IC4R_RPF5 2 +#define IC4R_RPG0 12 +#define IC4R_RPG7 1 + +#define IC5R_RPB0 5 +#define IC5R_RPB7 7 +#define IC5R_RPB8 2 +#define IC5R_RPB15 3 +#define IC5R_RPC3 12 +#define IC5R_RPD4 4 +#define IC5R_RPD9 0 +#define IC5R_RPD12 10 +#define IC5R_RPE3 6 +#define IC5R_RPE9 13 +#define IC5R_RPF8 11 +#define IC5R_RPF12 9 +#define IC5R_RPG6 1 + +#define IC6R_RPB2 7 +#define IC6R_RPB6 5 +#define IC6R_RPB14 2 +#define IC6R_RPC2 12 +#define IC6R_RPD0 3 +#define IC6R_RPD1 0 +#define IC6R_RPD5 6 +#define IC6R_RPE8 13 +#define IC6R_RPF2 11 +#define IC6R_RPF3 8 +#define IC6R_RPF13 9 +#define IC6R_RPG9 1 + +#define IC7R_RPA14 13 +#define IC7R_RPB5 8 +#define IC7R_RPB9 5 +#define IC7R_RPB10 6 +#define IC7R_RPC1 10 +#define IC7R_RPC14 7 +#define IC7R_RPD2 0 +#define IC7R_RPD6 14 +#define IC7R_RPD10 3 +#define IC7R_RPD14 11 +#define IC7R_RPF1 4 +#define IC7R_RPF4 2 +#define IC7R_RPG1 12 +#define IC7R_RPG8 1 + +#define IC8R_RPA15 13 +#define IC8R_RPB1 5 +#define IC8R_RPB3 8 +#define IC8R_RPC4 10 +#define IC8R_RPC13 7 +#define IC8R_RPD3 0 +#define IC8R_RPD7 14 +#define IC8R_RPD11 3 +#define IC8R_RPD15 11 +#define IC8R_RPE5 6 +#define IC8R_RPF0 4 +#define IC8R_RPF5 2 +#define IC8R_RPG0 12 +#define IC8R_RPG7 1 + +#define IC9R_RPB0 5 +#define IC9R_RPB7 7 +#define IC9R_RPB8 2 +#define IC9R_RPB15 3 +#define IC9R_RPC3 12 +#define IC9R_RPD4 4 +#define IC9R_RPD9 0 +#define IC9R_RPD12 10 +#define IC9R_RPE3 6 +#define IC9R_RPE9 13 +#define IC9R_RPF8 11 +#define IC9R_RPF12 9 +#define IC9R_RPG6 1 + +#define INT1R_RPB2 7 +#define INT1R_RPB6 5 +#define INT1R_RPB14 2 +#define INT1R_RPC2 12 +#define INT1R_RPD0 3 +#define INT1R_RPD1 0 +#define INT1R_RPD5 6 +#define INT1R_RPE8 13 +#define INT1R_RPF2 11 +#define INT1R_RPF3 8 +#define INT1R_RPF13 9 +#define INT1R_RPG9 1 + +#define INT2R_RPB0 5 +#define INT2R_RPB7 7 +#define INT2R_RPB8 2 +#define INT2R_RPB15 3 +#define INT2R_RPC3 12 +#define INT2R_RPD4 4 +#define INT2R_RPD9 0 +#define INT2R_RPD12 10 +#define INT2R_RPE3 6 +#define INT2R_RPE9 13 +#define INT2R_RPF8 11 +#define INT2R_RPF12 9 +#define INT2R_RPG6 1 + +#define INT3R_RPA14 13 +#define INT3R_RPB5 8 +#define INT3R_RPB9 5 +#define INT3R_RPB10 6 +#define INT3R_RPC1 10 +#define INT3R_RPC14 7 +#define INT3R_RPD2 0 +#define INT3R_RPD6 14 +#define INT3R_RPD10 3 +#define INT3R_RPD14 11 +#define INT3R_RPF1 4 +#define INT3R_RPF4 2 +#define INT3R_RPG1 12 +#define INT3R_RPG8 1 + +#define INT4R_RPA15 13 +#define INT4R_RPB1 5 +#define INT4R_RPB3 8 +#define INT4R_RPC4 10 +#define INT4R_RPC13 7 +#define INT4R_RPD3 0 +#define INT4R_RPD7 14 +#define INT4R_RPD11 3 +#define INT4R_RPD15 11 +#define INT4R_RPE5 6 +#define INT4R_RPF0 4 +#define INT4R_RPF5 2 +#define INT4R_RPG0 12 +#define INT4R_RPG7 1 + +#define OCFAR_RPB2 7 +#define OCFAR_RPB6 5 +#define OCFAR_RPB14 2 +#define OCFAR_RPC2 12 +#define OCFAR_RPD0 3 +#define OCFAR_RPD1 0 +#define OCFAR_RPD5 6 +#define OCFAR_RPE8 13 +#define OCFAR_RPF2 11 +#define OCFAR_RPF3 8 +#define OCFAR_RPF13 9 +#define OCFAR_RPG9 1 + +#define REFCLKI1R_RPA14 13 +#define REFCLKI1R_RPB5 8 +#define REFCLKI1R_RPB9 5 +#define REFCLKI1R_RPB10 6 +#define REFCLKI1R_RPC1 10 +#define REFCLKI1R_RPC14 7 +#define REFCLKI1R_RPD2 0 +#define REFCLKI1R_RPD6 14 +#define REFCLKI1R_RPD10 3 +#define REFCLKI1R_RPD14 11 +#define REFCLKI1R_RPF1 4 +#define REFCLKI1R_RPF4 2 +#define REFCLKI1R_RPG1 12 +#define REFCLKI1R_RPG8 1 + +#define REFCLKI3R_RPB2 7 +#define REFCLKI3R_RPB6 5 +#define REFCLKI3R_RPB14 2 +#define REFCLKI3R_RPC2 12 +#define REFCLKI3R_RPD0 3 +#define REFCLKI3R_RPD1 0 +#define REFCLKI3R_RPD5 6 +#define REFCLKI3R_RPE8 13 +#define REFCLKI3R_RPF2 11 +#define REFCLKI3R_RPF3 8 +#define REFCLKI3R_RPF13 9 +#define REFCLKI3R_RPG9 1 + +#define REFCLKI4R_RPA15 13 +#define REFCLKI4R_RPB1 5 +#define REFCLKI4R_RPB3 8 +#define REFCLKI4R_RPC4 10 +#define REFCLKI4R_RPC13 7 +#define REFCLKI4R_RPD3 0 +#define REFCLKI4R_RPD7 14 +#define REFCLKI4R_RPD11 3 +#define REFCLKI4R_RPD15 11 +#define REFCLKI4R_RPE5 6 +#define REFCLKI4R_RPF0 4 +#define REFCLKI4R_RPF5 2 +#define REFCLKI4R_RPG0 12 +#define REFCLKI4R_RPG7 1 + +#define SDI1R_RPA14 13 +#define SDI1R_RPB5 8 +#define SDI1R_RPB9 5 +#define SDI1R_RPB10 6 +#define SDI1R_RPC1 10 +#define SDI1R_RPC14 7 +#define SDI1R_RPD2 0 +#define SDI1R_RPD6 14 +#define SDI1R_RPD10 3 +#define SDI1R_RPD14 11 +#define SDI1R_RPF1 4 +#define SDI1R_RPF4 2 +#define SDI1R_RPG1 12 +#define SDI1R_RPG8 1 + +#define SDI2R_RPA15 13 +#define SDI2R_RPB1 5 +#define SDI2R_RPB3 8 +#define SDI2R_RPC4 10 +#define SDI2R_RPC13 7 +#define SDI2R_RPD3 0 +#define SDI2R_RPD7 14 +#define SDI2R_RPD11 3 +#define SDI2R_RPD15 11 +#define SDI2R_RPE5 6 +#define SDI2R_RPF0 4 +#define SDI2R_RPF5 2 +#define SDI2R_RPG0 12 +#define SDI2R_RPG7 1 + +#define SDI3R_RPA14 13 +#define SDI3R_RPB5 8 +#define SDI3R_RPB9 5 +#define SDI3R_RPB10 6 +#define SDI3R_RPC1 10 +#define SDI3R_RPC14 7 +#define SDI3R_RPD2 0 +#define SDI3R_RPD10 3 +#define SDI3R_RPD14 11 +#define SDI3R_RPD6 14 +#define SDI3R_RPF1 4 +#define SDI3R_RPF4 2 +#define SDI3R_RPG1 12 +#define SDI3R_RPG8 1 + +#define SDI4R_RPA15 13 +#define SDI4R_RPB1 5 +#define SDI4R_RPB3 8 +#define SDI4R_RPC4 10 +#define SDI4R_RPC13 7 +#define SDI4R_RPD3 0 +#define SDI4R_RPD7 14 +#define SDI4R_RPD11 3 +#define SDI4R_RPD15 11 +#define SDI4R_RPE5 6 +#define SDI4R_RPF0 4 +#define SDI4R_RPF5 2 +#define SDI4R_RPG0 12 +#define SDI4R_RPG7 1 + +#define SDI5R_RPA14 13 +#define SDI5R_RPB5 8 +#define SDI5R_RPB9 5 +#define SDI5R_RPB10 6 +#define SDI5R_RPC1 10 +#define SDI5R_RPC14 7 +#define SDI5R_RPD2 0 +#define SDI5R_RPD6 14 +#define SDI5R_RPD10 3 +#define SDI5R_RPD14 11 +#define SDI5R_RPF1 4 +#define SDI5R_RPF4 2 +#define SDI5R_RPG1 12 +#define SDI5R_RPG8 1 + +#define SDI6R_RPB2 7 +#define SDI6R_RPB6 5 +#define SDI6R_RPB14 2 +#define SDI6R_RPC2 12 +#define SDI6R_RPD0 3 +#define SDI6R_RPD1 0 +#define SDI6R_RPD5 6 +#define SDI6R_RPE8 13 +#define SDI6R_RPF2 11 +#define SDI6R_RPF3 8 +#define SDI6R_RPF13 9 +#define SDI6R_RPG9 1 + +#define SS1R_RPB0 5 +#define SS1R_RPB15 3 +#define SS1R_RPB7 7 +#define SS1R_RPB8 2 +#define SS1R_RPC3 12 +#define SS1R_RPD4 4 +#define SS1R_RPD9 0 +#define SS1R_RPD12 10 +#define SS1R_RPE3 6 +#define SS1R_RPE9 13 +#define SS1R_RPF8 11 +#define SS1R_RPF12 9 +#define SS1R_RPG6 1 + +#define SS2R_RPB2 7 +#define SS2R_RPB6 5 +#define SS2R_RPB14 2 +#define SS2R_RPC2 12 +#define SS2R_RPD0 3 +#define SS2R_RPD1 0 +#define SS2R_RPD5 6 +#define SS2R_RPE8 13 +#define SS2R_RPF2 11 +#define SS2R_RPF3 8 +#define SS2R_RPF13 9 +#define SS2R_RPG9 1 + +#define SS3R_RPB0 5 +#define SS3R_RPB7 7 +#define SS3R_RPB8 2 +#define SS3R_RPB15 3 +#define SS3R_RPC3 12 +#define SS3R_RPD4 4 +#define SS3R_RPD9 0 +#define SS3R_RPD12 10 +#define SS3R_RPE3 6 +#define SS3R_RPE9 13 +#define SS3R_RPF8 11 +#define SS3R_RPF12 9 +#define SS3R_RPG6 1 + +#define SS4R_RPB0 5 +#define SS4R_RPB7 7 +#define SS4R_RPB8 2 +#define SS4R_RPB15 3 +#define SS4R_RPC3 12 +#define SS4R_RPD4 4 +#define SS4R_RPD9 0 +#define SS4R_RPD12 10 +#define SS4R_RPE3 6 +#define SS4R_RPE9 13 +#define SS4R_RPF8 11 +#define SS4R_RPF12 9 +#define SS4R_RPG6 1 + +#define SS5R_RPB0 5 +#define SS5R_RPB7 7 +#define SS5R_RPB8 2 +#define SS5R_RPB15 3 +#define SS5R_RPC3 12 +#define SS5R_RPD4 4 +#define SS5R_RPD9 0 +#define SS5R_RPD12 10 +#define SS5R_RPE3 6 +#define SS5R_RPE9 13 +#define SS5R_RPF12 9 +#define SS5R_RPF8 11 +#define SS5R_RPG6 1 + +#define SS6R_RPA14 13 +#define SS6R_RPB5 8 +#define SS6R_RPB9 5 +#define SS6R_RPB10 6 +#define SS6R_RPC1 10 +#define SS6R_RPC14 7 +#define SS6R_RPD2 0 +#define SS6R_RPD6 14 +#define SS6R_RPD10 3 +#define SS6R_RPD14 11 +#define SS6R_RPF1 4 +#define SS6R_RPF4 2 +#define SS6R_RPG1 12 +#define SS6R_RPG8 1 + +#define T2CKR_RPA14 13 +#define T2CKR_RPB5 8 +#define T2CKR_RPB9 5 +#define T2CKR_RPB10 6 +#define T2CKR_RPC1 10 +#define T2CKR_RPC14 7 +#define T2CKR_RPD2 0 +#define T2CKR_RPD6 14 +#define T2CKR_RPD10 3 +#define T2CKR_RPD14 11 +#define T2CKR_RPF1 4 +#define T2CKR_RPF4 2 +#define T2CKR_RPG1 12 + +#define T2CKR_RPG8 1 +#define T3CKR_RPB0 5 +#define T3CKR_RPB7 7 +#define T3CKR_RPB8 2 +#define T3CKR_RPB15 3 +#define T3CKR_RPC3 12 +#define T3CKR_RPD4 4 +#define T3CKR_RPD9 0 +#define T3CKR_RPD12 10 +#define T3CKR_RPE3 6 +#define T3CKR_RPE9 13 +#define T3CKR_RPF8 11 +#define T3CKR_RPF12 9 +#define T3CKR_RPG6 1 + +#define T4CKR_RPB2 7 +#define T4CKR_RPB6 5 +#define T4CKR_RPB14 2 +#define T4CKR_RPC2 12 +#define T4CKR_RPD0 3 +#define T4CKR_RPD1 0 +#define T4CKR_RPD5 6 +#define T4CKR_RPE8 13 +#define T4CKR_RPF2 11 +#define T4CKR_RPF3 8 +#define T4CKR_RPF13 9 +#define T4CKR_RPG9 1 + +#define T5CKR_RPA15 13 +#define T5CKR_RPB1 5 +#define T5CKR_RPB3 8 +#define T5CKR_RPC4 10 +#define T5CKR_RPC13 7 +#define T5CKR_RPD3 0 +#define T5CKR_RPD7 14 +#define T5CKR_RPD11 3 +#define T5CKR_RPD15 11 +#define T5CKR_RPE5 6 +#define T5CKR_RPF0 4 +#define T5CKR_RPF5 2 +#define T5CKR_RPG0 12 +#define T5CKR_RPG7 1 + +#define T6CKR_RPA14 13 +#define T6CKR_RPB5 8 +#define T6CKR_RPB9 5 +#define T6CKR_RPB10 6 +#define T6CKR_RPC1 10 +#define T6CKR_RPC14 7 +#define T6CKR_RPD2 0 +#define T6CKR_RPD6 14 +#define T6CKR_RPD10 3 +#define T6CKR_RPD14 11 +#define T6CKR_RPF1 4 +#define T6CKR_RPF4 2 +#define T6CKR_RPG1 12 +#define T6CKR_RPG8 1 + +#define T7CKR_RPA15 13 +#define T7CKR_RPB1 5 +#define T7CKR_RPB3 8 +#define T7CKR_RPC4 10 +#define T7CKR_RPC13 7 +#define T7CKR_RPD3 0 +#define T7CKR_RPD7 14 +#define T7CKR_RPD11 3 +#define T7CKR_RPD15 11 +#define T7CKR_RPE5 6 +#define T7CKR_RPF0 4 +#define T7CKR_RPF5 2 +#define T7CKR_RPG0 12 +#define T7CKR_RPG7 1 + +#define T8CKR_RPB0 5 +#define T8CKR_RPB7 7 +#define T8CKR_RPB8 2 +#define T8CKR_RPB15 3 +#define T8CKR_RPC3 12 +#define T8CKR_RPD4 4 +#define T8CKR_RPD9 0 +#define T8CKR_RPD12 10 +#define T8CKR_RPE3 6 +#define T8CKR_RPE9 13 +#define T8CKR_RPF8 11 +#define T8CKR_RPF12 9 +#define T8CKR_RPG6 1 + +#define T9CKR_RPB2 7 +#define T9CKR_RPB6 5 +#define T9CKR_RPB14 2 +#define T9CKR_RPC2 12 +#define T9CKR_RPD0 3 +#define T9CKR_RPD1 0 +#define T9CKR_RPD5 6 +#define T9CKR_RPE8 13 +#define T9CKR_RPF2 11 +#define T9CKR_RPF3 8 +#define T9CKR_RPF13 9 +#define T9CKR_RPG9 1 + +#define U1CTSR_RPB0 5 +#define U1CTSR_RPB7 7 +#define U1CTSR_RPB8 2 +#define U1CTSR_RPB15 3 +#define U1CTSR_RPC3 12 +#define U1CTSR_RPD4 4 +#define U1CTSR_RPD9 0 +#define U1CTSR_RPD12 10 +#define U1CTSR_RPE3 6 +#define U1CTSR_RPE9 13 +#define U1CTSR_RPF8 11 +#define U1CTSR_RPF12 9 +#define U1CTSR_RPG6 1 + +#define U1RXR_RPA14 13 +#define U1RXR_RPB5 8 +#define U1RXR_RPB9 5 +#define U1RXR_RPB10 6 +#define U1RXR_RPC1 10 +#define U1RXR_RPC14 7 +#define U1RXR_RPD2 0 +#define U1RXR_RPD6 14 +#define U1RXR_RPD10 3 +#define U1RXR_RPD14 11 +#define U1RXR_RPF1 4 +#define U1RXR_RPF4 2 +#define U1RXR_RPG1 12 +#define U1RXR_RPG8 1 + +#define U2CTSR_RPA14 13 +#define U2CTSR_RPB5 8 +#define U2CTSR_RPB9 5 +#define U2CTSR_RPB10 6 +#define U2CTSR_RPC1 10 +#define U2CTSR_RPC14 7 +#define U2CTSR_RPD2 0 +#define U2CTSR_RPD6 14 +#define U2CTSR_RPD10 3 +#define U2CTSR_RPD14 11 +#define U2CTSR_RPF1 4 +#define U2CTSR_RPF4 2 +#define U2CTSR_RPG1 12 +#define U2CTSR_RPG8 1 + +#define U2RXR_RPB0 5 +#define U2RXR_RPB7 7 +#define U2RXR_RPB8 2 +#define U2RXR_RPB15 3 +#define U2RXR_RPC3 12 +#define U2RXR_RPD4 4 +#define U2RXR_RPD9 0 +#define U2RXR_RPD12 10 +#define U2RXR_RPE3 6 +#define U2RXR_RPE9 13 +#define U2RXR_RPF8 11 +#define U2RXR_RPF12 9 +#define U2RXR_RPG6 1 + +#define U3CTSR_RPB2 7 +#define U3CTSR_RPB6 5 +#define U3CTSR_RPB14 2 +#define U3CTSR_RPC2 12 +#define U3CTSR_RPD0 3 +#define U3CTSR_RPD1 0 +#define U3CTSR_RPD5 6 +#define U3CTSR_RPE8 13 +#define U3CTSR_RPF2 11 +#define U3CTSR_RPF3 8 +#define U3CTSR_RPF13 9 +#define U3CTSR_RPG9 1 + +#define U3RXR_RPA15 13 +#define U3RXR_RPB1 5 +#define U3RXR_RPB3 8 +#define U3RXR_RPC4 10 +#define U3RXR_RPC13 7 +#define U3RXR_RPD3 0 +#define U3RXR_RPD7 14 +#define U3RXR_RPD11 3 +#define U3RXR_RPD15 11 +#define U3RXR_RPE5 6 +#define U3RXR_RPF0 4 +#define U3RXR_RPF5 2 +#define U3RXR_RPG0 12 +#define U3RXR_RPG7 1 + +#define U4CTSR_RPA15 13 +#define U4CTSR_RPB1 5 +#define U4CTSR_RPB3 8 +#define U4CTSR_RPC4 10 +#define U4CTSR_RPC13 7 +#define U4CTSR_RPD3 0 +#define U4CTSR_RPD7 14 +#define U4CTSR_RPD11 3 +#define U4CTSR_RPD15 11 +#define U4CTSR_RPE5 6 +#define U4CTSR_RPF0 4 +#define U4CTSR_RPF5 2 +#define U4CTSR_RPG0 12 +#define U4CTSR_RPG7 1 + +#define U4RXR_RPB2 7 +#define U4RXR_RPB6 5 +#define U4RXR_RPB14 2 +#define U4RXR_RPC2 12 +#define U4RXR_RPD0 3 +#define U4RXR_RPD1 0 +#define U4RXR_RPD5 6 +#define U4RXR_RPE8 13 +#define U4RXR_RPF2 11 +#define U4RXR_RPF3 8 +#define U4RXR_RPF13 9 +#define U4RXR_RPG9 1 + +#define U5CTSR_RPB0 5 +#define U5CTSR_RPB7 7 +#define U5CTSR_RPB8 2 +#define U5CTSR_RPB15 3 +#define U5CTSR_RPC3 12 +#define U5CTSR_RPD4 4 +#define U5CTSR_RPD9 0 +#define U5CTSR_RPD12 10 +#define U5CTSR_RPE3 6 +#define U5CTSR_RPE9 13 +#define U5CTSR_RPF8 11 +#define U5CTSR_RPF12 9 +#define U5CTSR_RPG6 1 + +#define U5RXR_RPA14 13 +#define U5RXR_RPB5 8 +#define U5RXR_RPB9 5 +#define U5RXR_RPB10 6 +#define U5RXR_RPC1 10 +#define U5RXR_RPC14 7 +#define U5RXR_RPD2 0 +#define U5RXR_RPD6 14 +#define U5RXR_RPD10 3 +#define U5RXR_RPD14 11 +#define U5RXR_RPF1 4 +#define U5RXR_RPF4 2 +#define U5RXR_RPG1 12 +#define U5RXR_RPG8 1 + +#define U6CTSR_RPA14 13 +#define U6CTSR_RPB5 8 +#define U6CTSR_RPB9 5 +#define U6CTSR_RPB10 6 +#define U6CTSR_RPC1 10 +#define U6CTSR_RPC14 7 +#define U6CTSR_RPD2 0 +#define U6CTSR_RPD6 14 +#define U6CTSR_RPD10 3 +#define U6CTSR_RPD14 11 +#define U6CTSR_RPF1 4 +#define U6CTSR_RPF4 2 +#define U6CTSR_RPG1 12 +#define U6CTSR_RPG8 1 + +#define U6RXR_RPB2 7 +#define U6RXR_RPB6 5 +#define U6RXR_RPB14 2 +#define U6RXR_RPC2 12 +#define U6RXR_RPD0 3 +#define U6RXR_RPD1 0 +#define U6RXR_RPD5 6 +#define U6RXR_RPE8 13 +#define U6RXR_RPF2 11 +#define U6RXR_RPF3 8 +#define U6RXR_RPF13 9 +#define U6RXR_RPG9 1 + +/* Output Pin Selection *********************************************************************/ +/* The encoding of the output pin selection is a little more complex. Knowing the device + * does not provide sufficient information. So the following definitions include both the + * register value and the register address. + */ + +#define C1OUT_RPB0R 14, PI32MZ_RPB0R +#define C1OUT_RPB7R 14, PI32MZ_RPB7R +#define C1OUT_RPB8R 14, PI32MZ_RPB8R +#define C1OUT_RPB15R 14, PI32MZ_RPB15R +#define C1OUT_RPC3R 14, PI32MZ_RPC3R +#define C1OUT_RPD4R 14, PI32MZ_RPD4R +#define C1OUT_RPD9R 14, PI32MZ_RPD9R +#define C1OUT_RPD12R 14, PI32MZ_RPD12R +#define C1OUT_RPE3R 14, PI32MZ_RPE3R +#define C1OUT_RPE9R 14, PI32MZ_RPE9R +#define C1OUT_RPF8R 14, PI32MZ_RPF8R +#define C1OUT_RPF12R 14, PI32MZ_RPF12R +#define C1OUT_RPG6R 14, PI32MZ_RPG6R + +#define C1TX_RPA14R 15, PI32MZ_RPA14R +#define C1TX_RPB5R 15, PI32MZ_RPB5R +#define C1TX_RPB9R 15, PI32MZ_RPB9R +#define C1TX_RPB10R 15, PI32MZ_RPB10R +#define C1TX_RPC1R 15, PI32MZ_RPC1R +#define C1TX_RPC14R 15, PI32MZ_RPC14R +#define C1TX_RPD2R 15, PI32MZ_RPD2R +#define C1TX_RPD6R 15, PI32MZ_RPD6R +#define C1TX_RPD10R 15, PI32MZ_RPD10R +#define C1TX_RPD14R 15, PI32MZ_RPD14R +#define C1TX_RPF1R 15, PI32MZ_RPF1R +#define C1TX_RPF4R 15, PI32MZ_RPF4R +#define C1TX_RPG1R 15, PI32MZ_RPG1R +#define C1TX_RPG8R 15, PI32MZ_RPG8R + +#define C2OUT_RPA14R 14, PI32MZ_RPA14R +#define C2OUT_RPB5R 14, PI32MZ_RPB5R +#define C2OUT_RPB9R 14, PI32MZ_RPB9R +#define C2OUT_RPB10R 14, PI32MZ_RPB10R +#define C2OUT_RPC1R 14, PI32MZ_RPC1R +#define C2OUT_RPC14R 14, PI32MZ_RPC14R +#define C2OUT_RPD2R 14, PI32MZ_RPD2R +#define C2OUT_RPD6R 14, PI32MZ_RPD6R +#define C2OUT_RPD10R 14, PI32MZ_RPD10R +#define C2OUT_RPD14R 14, PI32MZ_RPD14R +#define C2OUT_RPF1R 14, PI32MZ_RPF1R +#define C2OUT_RPF4R 14, PI32MZ_RPF4R +#define C2OUT_RPG1R 14, PI32MZ_RPG1R +#define C2OUT_RPG8R 14, PI32MZ_RPG8R + +#define C2TX_RPB2R 15, PI32MZ_RPB2R +#define C2TX_RPB6R 15, PI32MZ_RPB6R +#define C2TX_RPB14R 15, PI32MZ_RPB14R +#define C2TX_RPC2R 15, PI32MZ_RPC2R +#define C2TX_RPD0R 15, PI32MZ_RPD0R +#define C2TX_RPD1R 15, PI32MZ_RPD1R +#define C2TX_RPD5R 15, PI32MZ_RPD5R +#define C2TX_RPE8R 15, PI32MZ_RPE8R +#define C2TX_RPF2R 15, PI32MZ_RPF2R +#define C2TX_RPF3R 15, PI32MZ_RPF3R +#define C2TX_RPF13R 15, PI32MZ_RPF13R +#define C2TX_RPG9R 15, PI32MZ_RPG9R + +#define OC1_RPB2R 12, PI32MZ_RPB2R +#define OC1_RPB6R 12, PI32MZ_RPB6R +#define OC1_RPB14R 12, PI32MZ_RPB14R +#define OC1_RPC2R 12, PI32MZ_RPC2R +#define OC1_RPD0R 12, PI32MZ_RPD0R +#define OC1_RPD1R 12, PI32MZ_RPD1R +#define OC1_RPD5R 12, PI32MZ_RPD5R +#define OC1_RPE8R 12, PI32MZ_RPE8R +#define OC1_RPF2R 12, PI32MZ_RPF2R +#define OC1_RPF3R 12, PI32MZ_RPF3R +#define OC1_RPF13R 12, PI32MZ_RPF13R +#define OC1_RPG9R 12, PI32MZ_RPG9R + +#define OC2_RPB2R 11, PI32MZ_RPB2R +#define OC2_RPB6R 11, PI32MZ_RPB6R +#define OC2_RPB14R 11, PI32MZ_RPB14R +#define OC2_RPC2R 11, PI32MZ_RPC2R +#define OC2_RPD0R 11, PI32MZ_RPD0R +#define OC2_RPD1R 11, PI32MZ_RPD1R +#define OC2_RPD5R 11, PI32MZ_RPD5R +#define OC2_RPE8R 11, PI32MZ_RPE8R +#define OC2_RPF2R 11, PI32MZ_RPF2R +#define OC2_RPF3R 11, PI32MZ_RPF3R +#define OC2_RPF13R 11, PI32MZ_RPF13R +#define OC2_RPG9R 11, PI32MZ_RPG9R + +#define OC3_RPA14R 11, PI32MZ_RPA14R +#define OC3_RPB5R 11, PI32MZ_RPB5R +#define OC3_RPB9R 11, PI32MZ_RPB9R +#define OC3_RPB10R 11, PI32MZ_RPB10R +#define OC3_RPC1R 11, PI32MZ_RPC1R +#define OC3_RPC14R 11, PI32MZ_RPC14R +#define OC3_RPD2R 11, PI32MZ_RPD2R +#define OC3_RPD6R 11, PI32MZ_RPD6R +#define OC3_RPD10R 11, PI32MZ_RPD10R +#define OC3_RPD14R 11, PI32MZ_RPD14R +#define OC3_RPF1R 11, PI32MZ_RPF1R +#define OC3_RPF4R 11, PI32MZ_RPF4R +#define OC3_RPG1R 11, PI32MZ_RPG1R +#define OC3_RPG8R 11, PIC32MZ_RPG8R + +#define OC4_RPA15R 11, PIC32MZ_RPA15R +#define OC4_RPB1R 11, PIC32MZ_RPB1R +#define OC4_RPB3R 11, PIC32MZ_RPB3R +#define OC4_RPC4R 11, PIC32MZ_RPC4R +#define OC4_RPC13R 11, PIC32MZ_RPC13R +#define OC4_RPD3R 11, PIC32MZ_RPD3R +#define OC4_RPD7R 11, PIC32MZ_RPD7R +#define OC4_RPD11R 11, PIC32MZ_RPD11R +#define OC4_RPD15R 11, PIC32MZ_RPD15R +#define OC4_RPE5R 11, PIC32MZ_RPE5R +#define OC4_RPF0R 11, PIC32MZ_RPF0R +#define OC4_RPF5R 11, PIC32MZ_RPF5R +#define OC4_RPG0R 11, PIC32MZ_RPG0R +#define OC4_RPG7R 11, PIC32MZ_RPG7R + +#define OC5_RPB0R 11, PIC32MZ_RPB0R +#define OC5_RPB7R 11, PIC32MZ_RPB7R +#define OC5_RPB8R 11, PIC32MZ_RPB8R +#define OC5_RPB15R 11, PIC32MZ_RPB15R +#define OC5_RPC3R 11, PIC32MZ_RPC3R +#define OC5_RPD4R 11, PIC32MZ_RPD4R +#define OC5_RPD9R 11, PIC32MZ_RPD9R +#define OC5_RPD12R 11, PIC32MZ_RPD12R +#define OC5_RPE3R 11, PIC32MZ_RPE3R +#define OC5_RPE9R 11, PIC32MZ_RPE9R +#define OC5_RPF8R 11, PIC32MZ_RPF8R +#define OC5_RPF12R 11, PIC32MZ_RPF12R +#define OC5_RPG6R 11, PIC32MZ_RPG6R + +#define OC6_RPA14R 12, PIC32MZ_RPA14R +#define OC6_RPB5R 12, PIC32MZ_RPB5R +#define OC6_RPB9R 12, PIC32MZ_RPB9R +#define OC6_RPB10R 12, PIC32MZ_RPB10R +#define OC6_RPC1R 12, PIC32MZ_RPC1R +#define OC6_RPC14R 12, PIC32MZ_RPC14R +#define OC6_RPD2R 12, PIC32MZ_RPD2R +#define OC6_RPD6R 12, PIC32MZ_RPD6R +#define OC6_RPD10R 12, PIC32MZ_RPD10R +#define OC6_RPD14R 12, PIC32MZ_RPD14R +#define OC6_RPF1R 12, PIC32MZ_RPF1R +#define OC6_RPF4R 12, PIC32MZ_RPF4R +#define OC6_RPG1R 12, PIC32MZ_RPG1R +#define OC6_RPG8R 12, PIC32MZ_RPG8R + +#define OC7_RPA15R 12, PIC32MZ_RPA15R +#define OC7_RPB1R 12, PIC32MZ_RPB1R +#define OC7_RPB3R 12, PIC32MZ_RPB3R +#define OC7_RPC4R 12, PIC32MZ_RPC4R +#define OC7_RPC13R 12, PIC32MZ_RPC13R +#define OC7_RPD3R 12, PIC32MZ_RPD3R +#define OC7_RPD7R 12, PIC32MZ_RPD7R +#define OC7_RPD11R 12, PIC32MZ_RPD11R +#define OC7_RPD15R 12, PIC32MZ_RPD15R +#define OC7_RPE5R 12, PIC32MZ_RPE5R +#define OC7_RPF0R 12, PIC32MZ_RPF0R +#define OC7_RPF5R 12, PIC32MZ_RPF5R +#define OC7_RPG0R 12, PIC32MZ_RPG0R +#define OC7_RPG7R 12, PIC32MZ_RPG7R + +#define OC8_RPB0R 12, PIC32MZ_RPB0R +#define OC8_RPB7R 12, PIC32MZ_RPB7R +#define OC8_RPB8R 12, PIC32MZ_RPB8R +#define OC8_RPB15R 12, PIC32MZ_RPB15R +#define OC8_RPC3R 12, PIC32MZ_RPC3R +#define OC8_RPD4R 12, PIC32MZ_RPD4R +#define OC8_RPD9R 12, PIC32MZ_RPD9R +#define OC8_RPD12R 12, PIC32MZ_RPD12R +#define OC8_RPE3R 12, PIC32MZ_RPE3R +#define OC8_RPE9R 12, PIC32MZ_RPE9R +#define OC8_RPF8R 12, PIC32MZ_RPF8R +#define OC8_RPF12R 12, PIC32MZ_RPF12R +#define OC8_RPG6R 12, PIC32MZ_RPG6R + +#define OC9_RPB2R 13, PIC32MZ_RPB2R +#define OC9_RPB6R 13, PIC32MZ_RPB6R +#define OC9_RPB14R 13, PIC32MZ_RPB14R +#define OC9_RPC2R 13, PIC32MZ_RPC2R +#define OC9_RPD0R 13, PIC32MZ_RPD0R +#define OC9_RPD1R 13, PIC32MZ_RPD1R +#define OC9_RPD5R 13, PIC32MZ_RPD5R +#define OC9_RPE8R 13, PIC32MZ_RPE8R +#define OC9_RPF2R 13, PIC32MZ_RPF2R +#define OC9_RPF3R 13, PIC32MZ_RPF3R +#define OC9_RPF13R 13, PIC32MZ_RPF13R +#define OC9_RPG9R 13, PIC32MZ_RPG9R + +#define REFCLKO1_RPA15R 15, PIC32MZ_RPA15R +#define REFCLKO1_RPB1R 15, PIC32MZ_RPB1R +#define REFCLKO1_RPB3R 15, PIC32MZ_RPB3R +#define REFCLKO1_RPC4R 15, PIC32MZ_RPC4R +#define REFCLKO1_RPC13R 15, PIC32MZ_RPC13R +#define REFCLKO1_RPD3R 15, PIC32MZ_RPD3R +#define REFCLKO1_RPD7R 15, PIC32MZ_RPD7R +#define REFCLKO1_RPD11R 15, PIC32MZ_RPD11R +#define REFCLKO1_RPD15R 15, PIC32MZ_RPD15R +#define REFCLKO1_RPE5R 15, PIC32MZ_RPE5R +#define REFCLKO1_RPF0R 15, PIC32MZ_RPF0R +#define REFCLKO1_RPF5R 15, PIC32MZ_RPF5R +#define REFCLKO1_RPG0R 15, PIC32MZ_RPG0R +#define REFCLKO1_RPG7R 15, PIC32MZ_RPG7R + +#define REFCLKO3_RPG6R 15, PIC32MZ_RPG6R +#define REFCLKO3_RPB0R 15, PIC32MZ_RPB0R +#define REFCLKO3_RPB7R 15, PIC32MZ_RPB7R +#define REFCLKO3_RPB8R 15, PIC32MZ_RPB8R +#define REFCLKO3_RPB15R 15, PIC32MZ_RPB15R +#define REFCLKO3_RPC3R 15, PIC32MZ_RPC3R +#define REFCLKO3_RPD4R 15, PIC32MZ_RPD4R +#define REFCLKO3_RPD9R 15, PIC32MZ_RPD9R +#define REFCLKO3_RPD12R 15, PIC32MZ_RPD12R +#define REFCLKO3_RPE3R 15, PIC32MZ_RPE3R +#define REFCLKO3_RPE9R 15, PIC32MZ_RPE9R +#define REFCLKO3_RPF8R 15, PIC32MZ_RPF8R +#define REFCLKO3_RPF12R 15, PIC32MZ_RPF12R + +#define REFCLKO4_RPA14R 13, PIC32MZ_RPA14R +#define REFCLKO4_RPB5R 13, PIC32MZ_RPB5R +#define REFCLKO4_RPB9R 13, PIC32MZ_RPB9R +#define REFCLKO4_RPB10R 13, PIC32MZ_RPB10R +#define REFCLKO4_RPC1R 13, PIC32MZ_RPC1R +#define REFCLKO4_RPC14R 13, PIC32MZ_RPC14R +#define REFCLKO4_RPD2R 13, PIC32MZ_RPD2R +#define REFCLKO4_RPD6R 13, PIC32MZ_RPD6R +#define REFCLKO4_RPD10R 13, PIC32MZ_RPD10R +#define REFCLKO4_RPD14R 13, PIC32MZ_RPD14R +#define REFCLKO4_RPF1R 13, PIC32MZ_RPF1R +#define REFCLKO4_RPF4R 13, PIC32MZ_RPF4R +#define REFCLKO4_RPG1R 13, PIC32MZ_RPG1R +#define REFCLKO4_RPG8R 13, PIC32MZ_RPG8R + +#define SDO1_RPA14R 5, PIC32MZ_RPA14R +#define SDO1_RPA15R 5, PIC32MZ_RPA15R +#define SDO1_RPB1R 5, PIC32MZ_RPB1R +#define SDO1_RPB3R 5, PIC32MZ_RPB3R +#define SDO1_RPB5R 5, PIC32MZ_RPB5R +#define SDO1_RPB9R 5, PIC32MZ_RPB9R +#define SDO1_RPB10R 5, PIC32MZ_RPB10R +#define SDO1_RPC1R 5, PIC32MZ_RPC1R +#define SDO1_RPC4R 5, PIC32MZ_RPC4R +#define SDO1_RPC13R 5, PIC32MZ_RPC13R +#define SDO1_RPC14R 5, PIC32MZ_RPC14R +#define SDO1_RPD2R 5, PIC32MZ_RPD2R +#define SDO1_RPD3R 5, PIC32MZ_RPD3R +#define SDO1_RPD6R 5, PIC32MZ_RPD6R +#define SDO1_RPD7R 5, PIC32MZ_RPD7R +#define SDO1_RPD10R 5, PIC32MZ_RPD10R +#define SDO1_RPD11R 5, PIC32MZ_RPD11R +#define SDO1_RPD14R 5, PIC32MZ_RPD14R +#define SDO1_RPD15R 5, PIC32MZ_RPD15R +#define SDO1_RPE5R 5, PIC32MZ_RPE5R +#define SDO1_RPF0R 5, PIC32MZ_RPF0R +#define SDO1_RPF1R 5, PIC32MZ_RPF1R +#define SDO1_RPF4R 5, PIC32MZ_RPF4R +#define SDO1_RPF5R 5, PIC32MZ_RPF5R +#define SDO1_RPG0R 5, PIC32MZ_RPG0R +#define SDO1_RPG1R 5, PIC32MZ_RPG1R +#define SDO1_RPG7R 5, PIC32MZ_RPG7R +#define SDO1_RPG8R 5, PIC32MZ_RPG8R + +#define SDO2_RPA14R 6, PIC32MZ_RPA14R +#define SDO2_RPA15R 6, PIC32MZ_RPA15R +#define SDO2_RPB1R 6, PIC32MZ_RPB1R +#define SDO2_RPB3R 6, PIC32MZ_RPB3R +#define SDO2_RPB5R 6, PIC32MZ_RPB5R +#define SDO2_RPB9R 6, PIC32MZ_RPB9R +#define SDO2_RPB10R 6, PIC32MZ_RPB10R +#define SDO2_RPC1R 6, PIC32MZ_RPC1R +#define SDO2_RPC4R 6, PIC32MZ_RPC4R +#define SDO2_RPC13R 6, PIC32MZ_RPC13R +#define SDO2_RPC14R 6, PIC32MZ_RPC14R +#define SDO2_RPD2R 6, PIC32MZ_RPD2R +#define SDO2_RPD3R 6, PIC32MZ_RPD3R +#define SDO2_RPD6R 6, PIC32MZ_RPD6R +#define SDO2_RPD7R 6, PIC32MZ_RPD7R +#define SDO2_RPD10R 6, PIC32MZ_RPD10R +#define SDO2_RPD11R 6, PIC32MZ_RPD11R +#define SDO2_RPD14R 6, PIC32MZ_RPD14R +#define SDO2_RPD15R 6, PIC32MZ_RPD15R +#define SDO2_RPE5R 6, PIC32MZ_RPE5R +#define SDO2_RPF0R 6, PIC32MZ_RPF0R +#define SDO2_RPF1R 6, PIC32MZ_RPF1R +#define SDO2_RPF4R 6, PIC32MZ_RPF4R +#define SDO2_RPF5R 6, PIC32MZ_RPF5R +#define SDO2_RPG0R 6, PIC32MZ_RPG0R +#define SDO2_RPG1R 6, PIC32MZ_RPG1R +#define SDO2_RPG7R 6, PIC32MZ_RPG7R +#define SDO2_RPG8R 6, PIC32MZ_RPG8R + +#define SDO3_RPA14R 7, PIC32MZ_RPA14R +#define SDO3_RPA15R 7, PIC32MZ_RPA15R +#define SDO3_RPB1R 7, PIC32MZ_RPB1R +#define SDO3_RPB3R 7, PIC32MZ_RPB3R +#define SDO3_RPB5R 7, PIC32MZ_RPB5R +#define SDO3_RPB9R 7, PIC32MZ_RPB9R +#define SDO3_RPB10R 7, PIC32MZ_RPB10R +#define SDO3_RPC1R 7, PIC32MZ_RPC1R +#define SDO3_RPC4R 7, PIC32MZ_RPC4R +#define SDO3_RPC13R 7, PIC32MZ_RPC13R +#define SDO3_RPC14R 7, PIC32MZ_RPC14R +#define SDO3_RPD2R 7, PIC32MZ_RPD2R +#define SDO3_RPD3R 7, PIC32MZ_RPD3R +#define SDO3_RPD6R 7, PIC32MZ_RPD6R +#define SDO3_RPD7R 7, PIC32MZ_RPD7R +#define SDO3_RPD10R 7, PIC32MZ_RPD10R +#define SDO3_RPD11R 7, PIC32MZ_RPD11R +#define SDO3_RPD14R 7, PIC32MZ_RPD14R +#define SDO3_RPD15R 7, PIC32MZ_RPD15R +#define SDO3_RPE5R 7, PIC32MZ_RPE5R +#define SDO3_RPF0R 7, PIC32MZ_RPF0R +#define SDO3_RPF1R 7, PIC32MZ_RPF1R +#define SDO3_RPF4R 7, PIC32MZ_RPF4R +#define SDO3_RPF5R 7, PIC32MZ_RPF5R +#define SDO3_RPG0R 7, PIC32MZ_RPG0R +#define SDO3_RPG1R 7, PIC32MZ_RPG1R +#define SDO3_RPG7R 7, PIC32MZ_RPG7R +#define SDO3_RPG8R 7, PIC32MZ_RPG8R + +#define SDO4_RPA15R 8, PIC32MZ_RPA15R +#define SDO4_RPB1R 8, PIC32MZ_RPB1R +#define SDO4_RPB2R 8, PIC32MZ_RPB2R +#define SDO4_RPB3R 8, PIC32MZ_RPB3R +#define SDO4_RPB6R 8, PIC32MZ_RPB6R +#define SDO4_RPB14R 8, PIC32MZ_RPB14R +#define SDO4_RPC2R 8, PIC32MZ_RPC2R +#define SDO4_RPC4R 8, PIC32MZ_RPC4R +#define SDO4_RPC13R 8, PIC32MZ_RPC13R +#define SDO4_RPD0R 8, PIC32MZ_RPD0R +#define SDO4_RPD1R 8, PIC32MZ_RPD1R +#define SDO4_RPD3R 8, PIC32MZ_RPD3R +#define SDO4_RPD5R 8, PIC32MZ_RPD5R +#define SDO4_RPD7R 8, PIC32MZ_RPD7R +#define SDO4_RPD11R 8, PIC32MZ_RPD11R +#define SDO4_RPD15R 8, PIC32MZ_RPD15R +#define SDO4_RPE5R 8, PIC32MZ_RPE5R +#define SDO4_RPE8R 8, PIC32MZ_RPE8R +#define SDO4_RPF0R 8, PIC32MZ_RPF0R +#define SDO4_RPF2R 8, PIC32MZ_RPF2R +#define SDO4_RPF3R 8, PIC32MZ_RPF3R +#define SDO4_RPF5R 8, PIC32MZ_RPF5R +#define SDO4_RPF13R 8, PIC32MZ_RPF13R +#define SDO4_RPG0R 8, PIC32MZ_RPG0R +#define SDO4_RPG7R 8, PIC32MZ_RPG7R +#define SDO4_RPG9R 8, PIC32MZ_RPG9R + +#define SDO5_RPA14R 9, PIC32MZ_RPA14R +#define SDO5_RPA15R 9, PIC32MZ_RPA15R +#define SDO5_RPB1R 9, PIC32MZ_RPB1R +#define SDO5_RPB3R 9, PIC32MZ_RPB3R +#define SDO5_RPB5R 9, PIC32MZ_RPB5R +#define SDO5_RPB9R 9, PIC32MZ_RPB9R +#define SDO5_RPB10R 9, PIC32MZ_RPB10R +#define SDO5_RPC1R 9, PIC32MZ_RPC1R +#define SDO5_RPC4R 9, PIC32MZ_RPC4R +#define SDO5_RPC13R 9, PIC32MZ_RPC13R +#define SDO5_RPC14R 9, PIC32MZ_RPC14R +#define SDO5_RPD2R 9, PIC32MZ_RPD2R +#define SDO5_RPD3R 9, PIC32MZ_RPD3R +#define SDO5_RPD6R 9, PIC32MZ_RPD6R +#define SDO5_RPD7R 9, PIC32MZ_RPD7R +#define SDO5_RPD10R 9, PIC32MZ_RPD10R +#define SDO5_RPD11R 9, PIC32MZ_RPD11R +#define SDO5_RPD14R 9, PIC32MZ_RPD14R +#define SDO5_RPD15R 9, PIC32MZ_RPD15R +#define SDO5_RPE5R 9, PIC32MZ_RPE5R +#define SDO5_RPF0R 9, PIC32MZ_RPF0R +#define SDO5_RPF1R 9, PIC32MZ_RPF1R +#define SDO5_RPF4R 9, PIC32MZ_RPF4R +#define SDO5_RPF5R 9, PIC32MZ_RPF5R +#define SDO5_RPG0R 9, PIC32MZ_RPG0R +#define SDO5_RPG1R 9, PIC32MZ_RPG1R +#define SDO5_RPG7R 9, PIC32MZ_RPG7R +#define SDO5_RPG8R 9, PIC32MZ_RPG8R + +#define SDO6_RPB0R 10, PIC32MZ_RPB0R +#define SDO6_RPB2R 10, PIC32MZ_RPB2R +#define SDO6_RPB6R 10, PIC32MZ_RPB6R +#define SDO6_RPB7R 10, PIC32MZ_RPB7R +#define SDO6_RPB8R 10, PIC32MZ_RPB8R +#define SDO6_RPB14R 10, PIC32MZ_RPB14R +#define SDO6_RPB15R 10, PIC32MZ_RPB15R +#define SDO6_RPC2R 10, PIC32MZ_RPC2R +#define SDO6_RPC3R 10, PIC32MZ_RPC3R +#define SDO6_RPD0R 10, PIC32MZ_RPD0R +#define SDO6_RPD1R 10, PIC32MZ_RPD1R +#define SDO6_RPD4R 10, PIC32MZ_RPD4R +#define SDO6_RPD5R 10, PIC32MZ_RPD5R +#define SDO6_RPD9R 10, PIC32MZ_RPD9R +#define SDO6_RPD12R 10, PIC32MZ_RPD12R +#define SDO6_RPE3R 10, PIC32MZ_RPE3R +#define SDO6_RPE8R 10, PIC32MZ_RPE8R +#define SDO6_RPE9R 10, PIC32MZ_RPE9R +#define SDO6_RPF2R 10, PIC32MZ_RPF2R +#define SDO6_RPF3R 10, PIC32MZ_RPF3R +#define SDO6_RPF8R 10, PIC32MZ_RPF8R +#define SDO6_RPF12R 10, PIC32MZ_RPF12R +#define SDO6_RPF13R 10, PIC32MZ_RPF13R +#define SDO6_RPG6R 10, PIC32MZ_RPG6R +#define SDO6_RPG9R 10, PIC32MZ_RPG9R + +#define SS1_RPB0R 5, PIC32MZ_RPB0R +#define SS1_RPB7R 5, PIC32MZ_RPB7R +#define SS1_RPB8R 5, PIC32MZ_RPB8R +#define SS1_RPB15R 5, PIC32MZ_RPB15R +#define SS1_RPC3R 5, PIC32MZ_RPC3R +#define SS1_RPD4R 5, PIC32MZ_RPD4R +#define SS1_RPD9R 5, PIC32MZ_RPD9R +#define SS1_RPD12R 5, PIC32MZ_RPD12R +#define SS1_RPE3R 5, PIC32MZ_RPE3R +#define SS1_RPE9R 5, PIC32MZ_RPE9R +#define SS1_RPF8R 5, PIC32MZ_RPF8R +#define SS1_RPF12R 5, PIC32MZ_RPF12R +#define SS1_RPG6R 5, PIC32MZ_RPG6R + +#define SS2_RPB2R 6, PIC32MZ_RPB2R +#define SS2_RPB6R 6, PIC32MZ_RPB6R +#define SS2_RPB14R 6, PIC32MZ_RPB14R +#define SS2_RPC2R 6, PIC32MZ_RPC2R +#define SS2_RPD0R 6, PIC32MZ_RPD0R +#define SS2_RPD1R 6, PIC32MZ_RPD1R +#define SS2_RPD5R 6, PIC32MZ_RPD5R +#define SS2_RPE8R 6, PIC32MZ_RPE8R +#define SS2_RPF2R 6, PIC32MZ_RPF2R +#define SS2_RPF3R 6, PIC32MZ_RPF3R +#define SS2_RPF13R 6, PIC32MZ_RPF13R +#define SS2_RPG9R 6, PIC32MZ_RPG9R + +#define SS3_RPB0R 7, PIC32MZ_RPB0R +#define SS3_RPB7R 7, PIC32MZ_RPB7R +#define SS3_RPB8R 7, PIC32MZ_RPB8R +#define SS3_RPB15R 7, PIC32MZ_RPB15R +#define SS3_RPC3R 7, PIC32MZ_RPC3R +#define SS3_RPD4R 7, PIC32MZ_RPD4R +#define SS3_RPD9R 7, PIC32MZ_RPD9R +#define SS3_RPD12R 7, PIC32MZ_RPD12R +#define SS3_RPE3R 7, PIC32MZ_RPE3R +#define SS3_RPE9R 7, PIC32MZ_RPE9R +#define SS3_RPF8R 7, PIC32MZ_RPF8R +#define SS3_RPF12R 7, PIC32MZ_RPF12R +#define SS3_RPG6R 7, PIC32MZ_RPG6R + +#define SS4_RPB0R 8, PIC32MZ_RPB0R +#define SS4_RPB7R 8, PIC32MZ_RPB7R +#define SS4_RPB8R 8, PIC32MZ_RPB8R +#define SS4_RPB15R 8, PIC32MZ_RPB15R +#define SS4_RPC3R 8, PIC32MZ_RPC3R +#define SS4_RPD4R 8, PIC32MZ_RPD4R +#define SS4_RPD9R 8, PIC32MZ_RPD9R +#define SS4_RPD12R 8, PIC32MZ_RPD12R +#define SS4_RPE3R 8, PIC32MZ_RPE3R +#define SS4_RPE9R 8, PIC32MZ_RPE9R +#define SS4_RPF8R 8, PIC32MZ_RPF8R +#define SS4_RPF12R 8, PIC32MZ_RPF12R +#define SS4_RPG6R 8, PIC32MZ_RPG6R + +#define SS5_RPB0R 9, PIC32MZ_RPB0R +#define SS5_RPB7R 9, PIC32MZ_RPB7R +#define SS5_RPB8R 9, PIC32MZ_RPB8R +#define SS5_RPB15R 9, PIC32MZ_RPB15R +#define SS5_RPC3R 9, PIC32MZ_RPC3R +#define SS5_RPD4R 9, PIC32MZ_RPD4R +#define SS5_RPD9R 9, PIC32MZ_RPD9R +#define SS5_RPD12R 9, PIC32MZ_RPD12R +#define SS5_RPE3R 9, PIC32MZ_RPE3R +#define SS5_RPE9R 9, PIC32MZ_RPE9R +#define SS5_RPF8R 9, PIC32MZ_RPF8R +#define SS5_RPF12R 9, PIC32MZ_RPF12R +#define SS5_RPG6R 9, PIC32MZ_RPG6R + +#define SS6_RPA14R 10, PIC32MZ_RPA14R +#define SS6_RPB5R 10, PIC32MZ_RPB5R +#define SS6_RPB9R 10, PIC32MZ_RPB9R +#define SS6_RPB10R 10, PIC32MZ_RPB10R +#define SS6_RPC1R 10, PIC32MZ_RPC1R +#define SS6_RPC14R 10, PIC32MZ_RPC14R +#define SS6_RPD2R 10, PIC32MZ_RPD2R +#define SS6_RPD6R 10, PIC32MZ_RPD6R +#define SS6_RPD10R 10, PIC32MZ_RPD10R +#define SS6_RPD14R 10, PIC32MZ_RPD14R +#define SS6_RPF1R 10, PIC32MZ_RPF1R +#define SS6_RPF4R 10, PIC32MZ_RPF4R +#define SS6_RPG1R 10, PIC32MZ_RPG1R +#define SS6_RPG8R 10, PIC32MZ_RPG8R + +#define U1RTS_RPB2R 1, PIC32MZ_RPB2R +#define U1RTS_RPB6R 1, PIC32MZ_RPB6R +#define U1RTS_RPB14R 1, PIC32MZ_RPB14R +#define U1RTS_RPC2R 1, PIC32MZ_RPC2R +#define U1RTS_RPD0R 1, PIC32MZ_RPD0R +#define U1RTS_RPD1R 1, PIC32MZ_RPD1R +#define U1RTS_RPD5R 1, PIC32MZ_RPD5R +#define U1RTS_RPE8R 1, PIC32MZ_RPE8R +#define U1RTS_RPF2R 1, PIC32MZ_RPF2R +#define U1RTS_RPF3R 1, PIC32MZ_RPF3R +#define U1RTS_RPF13R 1, PIC32MZ_RPF13R +#define U1RTS_RPG9R 1, PIC32MZ_RPG9R + +#define U1TX_RPA15R 1, PIC32MZ_RPA15R +#define U1TX_RPB1R 1, PIC32MZ_RPB1R +#define U1TX_RPB3R 1, PIC32MZ_RPB3R +#define U1TX_RPC4R 1, PIC32MZ_RPC4R +#define U1TX_RPC13R 1, PIC32MZ_RPC13R +#define U1TX_RPD3R 1, PIC32MZ_RPD3R +#define U1TX_RPD7R 1, PIC32MZ_RPD7R +#define U1TX_RPD11R 1, PIC32MZ_RPD11R +#define U1TX_RPD15R 1, PIC32MZ_RPD15R +#define U1TX_RPE5R 1, PIC32MZ_RPE5R +#define U1TX_RPF0R 1, PIC32MZ_RPF0R +#define U1TX_RPF5R 1, PIC32MZ_RPF5R +#define U1TX_RPG0R 1, PIC32MZ_RPG0R +#define U1TX_RPG7R 1, PIC32MZ_RPG7R + +#define U2RTS_RPA15R 2, PIC32MZ_RPA15R +#define U2RTS_RPB1R 2, PIC32MZ_RPB1R +#define U2RTS_RPB3R 2, PIC32MZ_RPB3R +#define U2RTS_RPC4R 2, PIC32MZ_RPC4R +#define U2RTS_RPC13R 2, PIC32MZ_RPC13R +#define U2RTS_RPD3R 2, PIC32MZ_RPD3R +#define U2RTS_RPD7R 2, PIC32MZ_RPD7R +#define U2RTS_RPD11R 2, PIC32MZ_RPD11R +#define U2RTS_RPD15R 2, PIC32MZ_RPD15R +#define U2RTS_RPE5R 2, PIC32MZ_RPE5R +#define U2RTS_RPF0R 2, PIC32MZ_RPF0R +#define U2RTS_RPF5R 2, PIC32MZ_RPF5R +#define U2RTS_RPG0R 2, PIC32MZ_RPG0R +#define U2RTS_RPG7R 2, PIC32MZ_RPG7R + +#define U2TX_RPB2R 2, PIC32MZ_RPB2R +#define U2TX_RPB6R 2, PIC32MZ_RPB6R +#define U2TX_RPB14R 2, PIC32MZ_RPB14R +#define U2TX_RPC2R 2, PIC32MZ_RPC2R +#define U2TX_RPD0R 2, PIC32MZ_RPD0R +#define U2TX_RPD1R 2, PIC32MZ_RPD1R +#define U2TX_RPD5R 2, PIC32MZ_RPD5R +#define U2TX_RPE8R 2, PIC32MZ_RPE8R +#define U2TX_RPF2R 2, PIC32MZ_RPF2R +#define U2TX_RPF3R 2, PIC32MZ_RPF3R +#define U2TX_RPF13R 2, PIC32MZ_RPF13R +#define U2TX_RPG9R 2, PIC32MZ_RPG9R + +#define U3RTS_RPB0R 1, PIC32MZ_RPB0R +#define U3RTS_RPB7R 1, PIC32MZ_RPB7R +#define U3RTS_RPB8R 1, PIC32MZ_RPB8R +#define U3RTS_RPB15R 1, PIC32MZ_RPB15R +#define U3RTS_RPC3R 1, PIC32MZ_RPC3R +#define U3RTS_RPD4R 1, PIC32MZ_RPD4R +#define U3RTS_RPD9R 1, PIC32MZ_RPD9R +#define U3RTS_RPD12R 1, PIC32MZ_RPD12R +#define U3RTS_RPE3R 1, PIC32MZ_RPE3R +#define U3RTS_RPE9R 1, PIC32MZ_RPE9R +#define U3RTS_RPF8R 1, PIC32MZ_RPF8R +#define U3RTS_RPF12R 1, PIC32MZ_RPF12R +#define U3RTS_RPG6R 1, PIC32MZ_RPG6R + +#define U3TX_RPA14R 1, PIC32MZ_RPA14R +#define U3TX_RPB5R 1, PIC32MZ_RPB5R +#define U3TX_RPB9R 1, PIC32MZ_RPB9R +#define U3TX_RPB10R 1, PIC32MZ_RPB10R +#define U3TX_RPC1R 1, PIC32MZ_RPC1R +#define U3TX_RPC14R 1, PIC32MZ_RPC14R +#define U3TX_RPD2R 1, PIC32MZ_RPD2R +#define U3TX_RPD6R 1, PIC32MZ_RPD6R +#define U3TX_RPD10R 1, PIC32MZ_RPD10R +#define U3TX_RPD14R 1, PIC32MZ_RPD14R +#define U3TX_RPF1R 1, PIC32MZ_RPF1R +#define U3TX_RPF4R 1, PIC32MZ_RPF4R +#define U3TX_RPG1R 1, PIC32MZ_RPG1R +#define U3TX_RPG8R 1, PIC32MZ_RPG8R + +#define U4RTS_RPA14R 2, PIC32MZ_RPA14R +#define U4RTS_RPB5R 2, PIC32MZ_RPB5R +#define U4RTS_RPB9R 2, PIC32MZ_RPB9R +#define U4RTS_RPB10R 2, PIC32MZ_RPB10R +#define U4RTS_RPC1R 2, PIC32MZ_RPC1R +#define U4RTS_RPC14R 2, PIC32MZ_RPC14R +#define U4RTS_RPD2R 2, PIC32MZ_RPD2R +#define U4RTS_RPD6R 2, PIC32MZ_RPD6R +#define U4RTS_RPD10R 2, PIC32MZ_RPD10R +#define U4RTS_RPD14R 2, PIC32MZ_RPD14R +#define U4RTS_RPF1R 2, PIC32MZ_RPF1R +#define U4RTS_RPF4R 2, PIC32MZ_RPF4R +#define U4RTS_RPG1R 2, PIC32MZ_RPG1R +#define U4RTS_RPG8R 2, PIC32MZ_RPG8R + +#define U4TX_RPB0R 2, PIC32MZ_RPB0R +#define U4TX_RPB7R 2, PIC32MZ_RPB7R +#define U4TX_RPB8R 2, PIC32MZ_RPB8R +#define U4TX_RPB15R 2, PIC32MZ_RPB15R +#define U4TX_RPC3R 2, PIC32MZ_RPC3R +#define U4TX_RPD4R 2, PIC32MZ_RPD4R +#define U4TX_RPD9R 2, PIC32MZ_RPD9R +#define U4TX_RPD12R 2, PIC32MZ_RPD12R +#define U4TX_RPE3R 2, PIC32MZ_RPE3R +#define U4TX_RPE9R 2, PIC32MZ_RPE9R +#define U4TX_RPF8R 2, PIC32MZ_RPF8R +#define U4TX_RPF12R 2, PIC32MZ_RPF12R +#define U4TX_RPG6R 2, PIC32MZ_RPG6R + +#define U5RTS_RPB2R 3, PIC32MZ_RPB2R +#define U5RTS_RPB6R 3, PIC32MZ_RPB6R +#define U5RTS_RPB14R 3, PIC32MZ_RPB14R +#define U5RTS_RPC2R 3, PIC32MZ_RPC2R +#define U5RTS_RPD0R 3, PIC32MZ_RPD0R +#define U5RTS_RPD1R 3, PIC32MZ_RPD1R +#define U5RTS_RPD5R 3, PIC32MZ_RPD5R +#define U5RTS_RPE8R 3, PIC32MZ_RPE8R +#define U5RTS_RPF2R 3, PIC32MZ_RPF2R +#define U5RTS_RPF3R 3, PIC32MZ_RPF3R +#define U5RTS_RPF13R 3, PIC32MZ_RPF13R +#define U5RTS_RPG9R 3, PIC32MZ_RPG9R + +#define U5TX_RPA15R 3, PIC32MZ_RPA15R +#define U5TX_RPB1R 3, PIC32MZ_RPB1R +#define U5TX_RPB3R 3, PIC32MZ_RPB3R +#define U5TX_RPC4R 3, PIC32MZ_RPC4R +#define U5TX_RPC13R 3, PIC32MZ_RPC13R +#define U5TX_RPD3R 3, PIC32MZ_RPD3R +#define U5TX_RPD7R 3, PIC32MZ_RPD7R +#define U5TX_RPD11R 3, PIC32MZ_RPD11R +#define U5TX_RPD15R 3, PIC32MZ_RPD15R +#define U5TX_RPE5R 3, PIC32MZ_RPE5R +#define U5TX_RPF0R 3, PIC32MZ_RPF0R +#define U5TX_RPF5R 3, PIC32MZ_RPF5R +#define U5TX_RPG0R 3, PIC32MZ_RPG0R +#define U5TX_RPG7R 3, PIC32MZ_RPG7R + +#define U6RTS_RPA15R 4, PIC32MZ_RPA15R +#define U6RTS_RPB1R 4, PIC32MZ_RPB1R +#define U6RTS_RPB3R 4, PIC32MZ_RPB3R +#define U6RTS_RPC4R 4, PIC32MZ_RPC4R +#define U6RTS_RPC13R 4, PIC32MZ_RPC13R +#define U6RTS_RPD3R 4, PIC32MZ_RPD3R +#define U6RTS_RPD7R 4, PIC32MZ_RPD7R +#define U6RTS_RPD11R 4, PIC32MZ_RPD11R +#define U6RTS_RPD15R 4, PIC32MZ_RPD15R +#define U6RTS_RPE5R 4, PIC32MZ_RPE5R +#define U6RTS_RPF0R 4, PIC32MZ_RPF0R +#define U6RTS_RPF5R 4, PIC32MZ_RPF5R +#define U6RTS_RPG0R 4, PIC32MZ_RPG0R +#define U6RTS_RPG7R 4, PIC32MZ_RPG7R + +#define U6TX_RPB0R 4, PIC32MZ_RPB0R +#define U6TX_RPB2R 4, PIC32MZ_RPB2R +#define U6TX_RPB6R 4, PIC32MZ_RPB6R +#define U6TX_RPB7R 4, PIC32MZ_RPB7R +#define U6TX_RPB8R 4, PIC32MZ_RPB8R +#define U6TX_RPB14R 4, PIC32MZ_RPB14R +#define U6TX_RPB15R 4, PIC32MZ_RPB15R +#define U6TX_RPC2R 4, PIC32MZ_RPC2R +#define U6TX_RPC3R 4, PIC32MZ_RPC3R +#define U6TX_RPD0R 4, PIC32MZ_RPD0R +#define U6TX_RPD1R 4, PIC32MZ_RPD1R +#define U6TX_RPD4R 4, PIC32MZ_RPD4R +#define U6TX_RPD5R 4, PIC32MZ_RPD5R +#define U6TX_RPD9R 4, PIC32MZ_RPD9R +#define U6TX_RPD12R 4, PIC32MZ_RPD12R +#define U6TX_RPE3R 4, PIC32MZ_RPE3R +#define U6TX_RPE8R 4, PIC32MZ_RPE8R +#define U6TX_RPE9R 4, PIC32MZ_RPE9R +#define U6TX_RPF2R 4, PIC32MZ_RPF2R +#define U6TX_RPF3R 4, PIC32MZ_RPF3R +#define U6TX_RPF8R 4, PIC32MZ_RPF8R +#define U6TX_RPF12R 4, PIC32MZ_RPF12R +#define U6TX_RPF13R 4, PIC32MZ_RPF13R +#define U6TX_RPG6R 4, PIC32MZ_RPG6R +#define U6TX_RPG9R 4, PIC32MZ_RPG9R + +#endif /* __ARCH_MIPS_SRC_PIC32MZ_CHIP_PIC32MZEF_PPS_H */ diff --git a/arch/mips/src/pic32mz/pic32mz-config.h b/arch/mips/src/pic32mz/pic32mz-config.h index af150d4979..dfec8ec1eb 100644 --- a/arch/mips/src/pic32mz/pic32mz-config.h +++ b/arch/mips/src/pic32mz/pic32mz-config.h @@ -537,6 +537,20 @@ /* Not yet configurable settings */ +#if defined(CONFIG_ARCH_CHIP_PIC32MZEC) +# define CONFIG_PIC32MX_SMCLR 0 +# define CONFIG_PIC32MX_SOSCGAIN 0 +# define CONFIG_PIC32MX_SOSCBOOST 0 +# define CONFIG_PIC32MX_POSCGAIN 0 +# define CONFIG_PIC32MX_POSCBOOST 0 +#elif defined(CONFIG_ARCH_CHIP_PIC32MZEF) +# define CONFIG_PIC32MX_SMCLR DEVCFG0_SMCLR +# define CONFIG_PIC32MX_SOSCGAIN DEVCFG0_SOSCGAIN_HIGH +# define CONFIG_PIC32MX_SOSCBOOST DEVCFG0_SOSCBOOST +# define CONFIG_PIC32MX_POSCGAIN DEVCFG0_POSCGAIN_HIGH +# define CONFIG_PIC32MX_POSCBOOST DEVCFG0_POSCBOOST +#endif + #define CONFIG_PIC32MZ_FSLEEP DEVCFG0_FSLEEP_OFF #define CONFIG_PIC32MZ_DBGPER DEVCFG0_DBGPER_ALL #define CONFIG_PIC32MZ_EJTAGBEN DEVCFG0_EJTAG_NORMAL diff --git a/arch/mips/src/pic32mz/pic32mz-head.S b/arch/mips/src/pic32mz/pic32mz-head.S index b04ab231f1..5e64bc25b2 100644 --- a/arch/mips/src/pic32mz/pic32mz-head.S +++ b/arch/mips/src/pic32mz/pic32mz-head.S @@ -690,29 +690,31 @@ devcfg3: DEVCFG3_RWO devcfg2: - .long CONFIG_PIC32MZ_PLLIDIV | CONFIG_PIC32MZ_FPLLRNG | \ - CONFIG_PIC32MZ_FPLLICLK | CONFIG_PIC32MZ_PLLMULT | \ - CONFIG_PIC32MZ_PLLODIV | CONFIG_PIC32MZ_UPLLFSEL | \ + .long CONFIG_PIC32MZ_PLLIDIV | CONFIG_PIC32MZ_FPLLRNG | \ + CONFIG_PIC32MZ_FPLLICLK | CONFIG_PIC32MZ_PLLMULT | \ + CONFIG_PIC32MZ_PLLODIV | CONFIG_PIC32MZ_UPLLFSEL | \ DEVCFG2_RWO devcfg1: - .long CONFIG_PIC32MZ_FNOSC | CONFIG_PIC32MZ_DMTINV |\ - CONFIG_PIC32MZ_FSOSCEN | CONFIG_PIC32MZ_IESO | \ - CONFIG_PIC32MZ_POSCMOD | CONFIG_PIC32MZ_OSCIOFNC | \ - CONFIG_PIC32MZ_FCKSM | CONFIG_PIC32MZ_WDTPS | \ - CONFIG_PIC32MZ_WDTSPGM | CONFIG_PIC32MZ_WINDIS | \ - CONFIG_PIC32MZ_FWDTEN | CONFIG_PIC32MZ_FWDTWINSZ | \ - CONFIG_PIC32MZ_DMTCNT | CONFIG_PIC32MZ_FSOSCEN | \ - CONFIG_PIC32MZ_FSOSCEN | CONFIG_PIC32MZ_FDMTEN | \ + .long CONFIG_PIC32MZ_FNOSC | CONFIG_PIC32MZ_DMTINV |\ + CONFIG_PIC32MZ_FSOSCEN | CONFIG_PIC32MZ_IESO | \ + CONFIG_PIC32MZ_POSCMOD | CONFIG_PIC32MZ_OSCIOFNC | \ + CONFIG_PIC32MZ_FCKSM | CONFIG_PIC32MZ_WDTPS | \ + CONFIG_PIC32MZ_WDTSPGM | CONFIG_PIC32MZ_WINDIS | \ + CONFIG_PIC32MZ_FWDTEN | CONFIG_PIC32MZ_FWDTWINSZ | \ + CONFIG_PIC32MZ_DMTCNT | CONFIG_PIC32MZ_FSOSCEN | \ + CONFIG_PIC32MZ_FSOSCEN | CONFIG_PIC32MZ_FDMTEN | \ DEVCFG1_RWO devcfg0: - .long CONFIG_PIC32MZ_DEBUGGER | CONFIG_PIC32MZ_JTAGEN | \ - CONFIG_PIC32MZ_ICESEL | CONFIG_PIC32MZ_TRCEN | \ - CONFIG_PIC32MZ_BOOTISA | CONFIG_PIC32MZ_FECCCON | \ - CONFIG_PIC32MZ_FSLEEP | CONFIG_PIC32MZ_DBGPER | \ - CONFIG_PIC32MZ_EJTAGBEN | DEVCFG0_RW0 - + .long CONFIG_PIC32MZ_DEBUGGER | CONFIG_PIC32MZ_JTAGEN | \ + CONFIG_PIC32MZ_ICESEL | CONFIG_PIC32MZ_TRCEN | \ + CONFIG_PIC32MZ_BOOTISA | CONFIG_PIC32MZ_FECCCON | \ + CONFIG_PIC32MZ_FSLEEP | CONFIG_PIC32MZ_DBGPER | \ + CONFIG_PIC32MX_SMCLR | CONFIG_PIC32MX_SOSCGAIN | \ + CONFIG_PIC32MX_SOSCBOOST | CONFIG_PIC32MX_POSCGAIN | \ + CONFIG_PIC32MX_POSCBOOST | CONFIG_PIC32MZ_EJTAGBEN | \ + DEVCFG0_RW0 .size devcfg, .-devcfg /* Every word in the configuration space and sequence space has an diff --git a/configs/flipnclick-sam3x/README.txt b/configs/flipnclick-sam3x/README.txt index 9ceb0e74d0..2f3f8a5e84 100644 --- a/configs/flipnclick-sam3x/README.txt +++ b/configs/flipnclick-sam3x/README.txt @@ -28,7 +28,7 @@ STATUS b) Execute the following command which claims to have successfully written to FLASH. - /bossac.exe --info --debug --port COM7 --usb-port=0 --erase --write --verify -b nuttx.bin -R + bossac.exe --info --debug --port COM7 --usb-port=0 --erase --write --verify -b nuttx.bin -R But the code does not boot. There is no indication of life.