diff --git a/arch/xtensa/include/esp32/irq.h b/arch/xtensa/include/esp32/irq.h
index aad3ea0727..bb096ec85b 100644
--- a/arch/xtensa/include/esp32/irq.h
+++ b/arch/xtensa/include/esp32/irq.h
@@ -53,8 +53,9 @@
 /* Interrupt Matrix
  *
  * The Interrupt Matrix embedded in the ESP32 independently allocates
- * peripheral interrupt sources to the two CPUs’ peripheral interrupts. This
- * configuration is highly flexible in order to meet many different needs.
+ * peripheral interrupt sources to the two CPUs’ peripheral interrupts.
+ * This configuration is highly flexible in order to meet many different
+ * needs.
  *
  * Features
  * - Accepts 71 peripheral interrupt sources as input.
@@ -291,9 +292,9 @@
 
 #define ESP32_NIRQ_PERIPH           ESP32_NPERIPHERALS
 
-/* Second level GPIO interrupts.  GPIO interrupts are decoded and dispatched as
- * a second level of decoding:  The first level dispatches to the GPIO interrupt
- * handler.  The second to the decoded GPIO interrupt handler.
+/* Second level GPIO interrupts.  GPIO interrupts are decoded and dispatched
+ * as a second level of decoding:  The first level dispatches to the GPIO
+ * interrupt handler.  The second to the decoded GPIO interrupt handler.
  */
 
 #ifdef CONFIG_ESP32_GPIO_IRQ
diff --git a/arch/xtensa/include/spinlock.h b/arch/xtensa/include/spinlock.h
index b4eddc8d7b..362bb2bf61 100644
--- a/arch/xtensa/include/spinlock.h
+++ b/arch/xtensa/include/spinlock.h
@@ -70,7 +70,7 @@
 typedef uint32_t spinlock_t;
 
 /****************************************************************************
- * Public Functions
+ * Public Function Prototypes
  ****************************************************************************/
 
 /****************************************************************************
diff --git a/arch/xtensa/include/xtensa/xtensa_coproc.h b/arch/xtensa/include/xtensa/xtensa_coproc.h
index 56994c7058..c659e7b54d 100644
--- a/arch/xtensa/include/xtensa/xtensa_coproc.h
+++ b/arch/xtensa/include/xtensa/xtensa_coproc.h
@@ -91,23 +91,26 @@
  *   When a thread solicits a context-swtich, its CPENABLE is cleared - the
  *   compiler has saved the (caller-saved) co-proc state if it needs to.
  *   When a non-running thread loses ownership of a CP, its bit is cleared.
- *   When a thread runs, it's XTENSA_CPENABLE is loaded into the CPENABLE reg.
- *   Avoids co-processor exceptions when no change of ownership is needed.
+ *   When a thread runs, it's XTENSA_CPENABLE is loaded into the CPENABLE
+ *   reg. Avoids co-processor exceptions when no change of ownership is
+ *   needed.
  *
  * XTENSA_CPSTORED
  *   A bitmask with the same layout as CPENABLE, a bit per co-processor.
  *   Indicates whether the state of each co-processor is saved in the state
- *   save area. When the state of a thread is saved, only the state of co-procs
- *   still enabled in CPENABLE is saved. When the co-processor state is
- *   is restored, the state is only resotred for a co-processor if this bit
- *   is set.  This bist set is cleared after after co-processor state has
- *   been restored.
+ *   save area. When the state of a thread is saved, only the state of
+ *   co-procs still enabled in CPENABLE is saved. When the co-processor
+ *   state is restored, the state is only resotred for a co-processor if
+ *   this bit is set.  This bist set is cleared after after co-processor
+ *   state has been restored.
  *
  * XTENSA_CPASA
  *   Pointer to the aligned save area.  Allows it to be aligned more than
- *   the overall save area (which might only be stack-aligned or TCB-aligned).
+ *   the overall save area (which might only be stack-aligned or
+ *   TCB-aligned).
  *   Especially relevant for Xtensa cores configured with a very large data
- *   path that requires alignment greater than 16 bytes (ABI stack alignment).
+ *   path that requires alignment greater than 16 bytes (ABI stack
+ *   alignment).
  */
 
 /* Offsets of each coprocessor save area within the 'aligned save area': */
diff --git a/arch/xtensa/include/xtensa/xtensa_specregs.h b/arch/xtensa/include/xtensa/xtensa_specregs.h
index 7d2843b39b..bb5d699f72 100644
--- a/arch/xtensa/include/xtensa/xtensa_specregs.h
+++ b/arch/xtensa/include/xtensa/xtensa_specregs.h
@@ -134,15 +134,17 @@
 /*  Tensilica-defined user registers:  */
 
 #if 0
-/*#define ...     21..24 */  /* (545CK) */
-/*#define ...    140..143 */ /* (545CK) */
+#if 0
+#define ...           21..24 /* (545CK) */
+#define ...         140..143 /* (545CK) */
+#endif
 #define EXPSTATE      230    /* Diamond */
 #define THREADPTR     231    /* threadptr option */
 #define FCR           232    /* FPU */
 #define FSR           233    /* FPU */
 #define AE_OVF_SAR    240    /* HiFi2 */
 #define AE_BITHEAD    241    /* HiFi2 */
-#define AE_TS_FTS_BU_BP 242 /* HiFi2 */
+#define AE_TS_FTS_BU_BP 242  /* HiFi2 */
 #define AE_SD_NO      243    /* HiFi2 */
 #define VSAR          240    /* VectraLX */
 #define ROUND_LO      242    /* VectraLX */
diff --git a/arch/xtensa/src/common/xtensa.h b/arch/xtensa/src/common/xtensa.h
index c50b269cb9..ab6c1fbe56 100644
--- a/arch/xtensa/src/common/xtensa.h
+++ b/arch/xtensa/src/common/xtensa.h
@@ -188,14 +188,14 @@ extern uint32_t g_intstack[INTERRUPT_STACKWORDS];
 
 extern uint32_t g_idlestack[IDLETHREAD_STACKWORDS];
 
-/* These 'addresses' of these values are setup by the linker script.  They are
- * not actual uint32_t storage locations! They are only used meaningfully in the
- * following way:
+/* These 'addresses' of these values are setup by the linker script.  They
+ * are not actual uint32_t storage locations! They are only used meaningfully
+ * in the following way:
  *
  *  - The linker script defines, for example, the symbol_sdata.
  *  - The declaration extern uint32_t _sdata; makes C happy.  C will believe
- *    that the value _sdata is the address of a uint32_t variable _data (it is
- *    not!).
+ *    that the value _sdata is the address of a uint32_t variable _data (it
+ *    is not!).
  *  - We can recoved the linker value then by simply taking the address of
  *    of _data.  like:  uint32_t *pdata = &_sdata;
  */
@@ -217,10 +217,11 @@ extern uint32_t _eheap;             /* End+1 of heap */
  ****************************************************************************/
 
 /****************************************************************************
- * Public Functions
+ * Public Function Prototypes
  ****************************************************************************/
 
 /* Common Functions *********************************************************/
+
 /* Common functions defined in arch/xtensa/src/common.  These may be replaced
  * with chip-specific functions of the same name if needed.  See also
  * functions prototyped in include/nuttx/arch.h.
@@ -250,6 +251,7 @@ void xtensa_dumpstate(void);
 #endif
 
 /* Common XTENSA functions */
+
 /* Initialization */
 
 #if XCHAL_CP_NUM > 0
@@ -291,7 +293,9 @@ void _xtensa_sig_trampoline(void);
 void xtensa_sig_deliver(void);
 
 /* Chip-specific functions **************************************************/
+
 /* Chip specific functions defined in arch/xtensa/src/<chip> */
+
 /* IRQs */
 
 bool xtensa_pending_irq(int irq);
diff --git a/arch/xtensa/src/common/xtensa_assert.c b/arch/xtensa/src/common/xtensa_assert.c
index deb5742ee1..e18838b1b3 100644
--- a/arch/xtensa/src/common/xtensa_assert.c
+++ b/arch/xtensa/src/common/xtensa_assert.c
@@ -58,6 +58,7 @@
 /****************************************************************************
  * Pre-processor Definitions
  ****************************************************************************/
+
 /* USB trace dumping */
 
 #ifndef CONFIG_USBDEV_TRACE
@@ -128,21 +129,21 @@ static void xtensa_assert(int errorcode)
 
   if (CURRENT_REGS || running_task()->flink == NULL)
     {
-       /* Blink the LEDs forever */
+      /* Blink the LEDs forever */
 
-       up_irq_save();
-        for (; ; )
-          {
+      up_irq_save();
+      for (; ; )
+        {
 #if CONFIG_BOARD_RESET_ON_ASSERT >= 1
-            board_reset(CONFIG_BOARD_ASSERT_RESET_VALUE);
+          board_reset(CONFIG_BOARD_ASSERT_RESET_VALUE);
 #endif
 #ifdef CONFIG_ARCH_LEDS
-            board_autoled_on(LED_PANIC);
-            up_mdelay(250);
-            board_autoled_off(LED_PANIC);
-            up_mdelay(250);
+          board_autoled_on(LED_PANIC);
+          up_mdelay(250);
+          board_autoled_off(LED_PANIC);
+          up_mdelay(250);
 #endif
-          }
+        }
     }
   else
     {
@@ -254,7 +255,8 @@ void xtensa_panic(int xptcode, uint32_t *regs)
  *      Level-1 interrupt as indicated by set level-1 bits in the INTERRUPT
  *      register.
  *   5  AllocaCause
- *      MOVSP instruction, if caller’s registers are not in the register file.
+ *      MOVSP instruction, if caller’s registers are not in the register
+ *      file.
  *   6  IntegerDivideByZeroCause
  *      QUOS, QUOU, REMS, or REMU divisor operand is zero.
  *   7  PCValueErrorCause Next PC Value Illegal
diff --git a/arch/xtensa/src/common/xtensa_attr.h b/arch/xtensa/src/common/xtensa_attr.h
index 72cce41da9..c0531376fd 100644
--- a/arch/xtensa/src/common/xtensa_attr.h
+++ b/arch/xtensa/src/common/xtensa_attr.h
@@ -52,7 +52,8 @@
 
 /* Forces data into RTC slow memory
  * Any variable marked with this attribute will keep its value
- * during a deep sleep / wake cycle. */
+ * during a deep sleep / wake cycle.
+ */
 
 #define RTC_DATA_ATTR __attribute__((section(".rtc.data")))
 
diff --git a/arch/xtensa/src/common/xtensa_checkstack.c b/arch/xtensa/src/common/xtensa_checkstack.c
index bcfbece0d4..7136a881a2 100644
--- a/arch/xtensa/src/common/xtensa_checkstack.c
+++ b/arch/xtensa/src/common/xtensa_checkstack.c
@@ -132,7 +132,7 @@ static size_t do_stackcheck(uintptr_t alloc, size_t size)
       int j;
 
       ptr = (FAR uint32_t *)start;
-      for (i = 0; i < size; i += 4*64)
+      for (i = 0; i < size; i += 4 * 64)
         {
           for (j = 0; j < 64; j++)
             {
@@ -202,7 +202,8 @@ ssize_t up_check_stack_remain(void)
 #if CONFIG_ARCH_INTERRUPTSTACK > 3
 size_t up_check_intstack(void)
 {
-  return do_stackcheck((uintptr_t)&g_intstackalloc, (CONFIG_ARCH_INTERRUPTSTACK & ~3));
+  return do_stackcheck((uintptr_t)&g_intstackalloc,
+                       (CONFIG_ARCH_INTERRUPTSTACK & ~3));
 }
 
 size_t up_check_intstack_remain(void)
diff --git a/arch/xtensa/src/common/xtensa_cpupause.c b/arch/xtensa/src/common/xtensa_cpupause.c
index a19aae38e1..956b0f43c5 100644
--- a/arch/xtensa/src/common/xtensa_cpupause.c
+++ b/arch/xtensa/src/common/xtensa_cpupause.c
@@ -265,7 +265,7 @@ int up_cpu_pause(int cpu)
    * called.  g_cpu_paused will be unlocked in any case.
    */
 
- return ret;
+  return ret;
 }
 
 /****************************************************************************
diff --git a/arch/xtensa/src/common/xtensa_createstack.c b/arch/xtensa/src/common/xtensa_createstack.c
index 5c58528864..9cb3dc8415 100644
--- a/arch/xtensa/src/common/xtensa_createstack.c
+++ b/arch/xtensa/src/common/xtensa_createstack.c
@@ -58,8 +58,8 @@
  * Pre-processor Macros
  ****************************************************************************/
 
-/* XTENSA requires at least a 4-byte stack alignment.  For floating point use,
- * however, the stack must be aligned to 8-byte addresses.
+/* XTENSA requires at least a 4-byte stack alignment.  For floating point
+ * use, however, the stack must be aligned to 8-byte addresses.
  *
  * REVIST: Is this true?  Comes from ARM EABI
  */
@@ -217,19 +217,24 @@ int up_create_stack(FAR struct tcb_s *tcb, size_t stack_size, uint8_t ttype)
        */
 
       cpstart      = (uintptr_t)_CP_ALIGNDOWN(XCHAL_CP0_SA_ALIGN,
-                                              top_of_stack - XCHAL_CP1_SA_ALIGN);
+                                              top_of_stack -
+                                              XCHAL_CP1_SA_ALIGN);
       top_of_stack = cpstart;
 
       /* Initialize the coprocessor save area (see xtensa_coproc.h) */
 
       xcp                   = &tcb->xcp;
-      xcp->cpstate.cpenable = 0;  /* No coprocessors active for this thread */
-      xcp->cpstate.cpstored = 0;  /* No coprocessors saved for this thread */
-      xcp->cpstate.cpasa    = (uint32_t *)cpstart; /* Start of aligned save area */
+      xcp->cpstate.cpenable = 0;                   /* No coprocessors active
+                                                    * for this thread */
+      xcp->cpstate.cpstored = 0;                   /* No coprocessors saved
+                                                    * for this thread */
+      xcp->cpstate.cpasa    = (uint32_t *)cpstart; /* Start of aligned save
+                                                    * area */
 #endif
 
       /* The XTENSA stack must be aligned.  If necessary top_of_stack must be
-       * rounded down to the next boundary to meet this alignment requirement.
+       * rounded down to the next boundary to meet this alignment
+       * requirement.
        *
        * NOTE: Co-processor save area not included in the size of the stack.
        */
@@ -246,5 +251,5 @@ int up_create_stack(FAR struct tcb_s *tcb, size_t stack_size, uint8_t ttype)
       return OK;
     }
 
-   return ERROR;
+  return ERROR;
 }
diff --git a/arch/xtensa/src/common/xtensa_dumpstate.c b/arch/xtensa/src/common/xtensa_dumpstate.c
index 0a6a617153..c5c58eb1d1 100644
--- a/arch/xtensa/src/common/xtensa_dumpstate.c
+++ b/arch/xtensa/src/common/xtensa_dumpstate.c
@@ -216,7 +216,7 @@ void xtensa_dumpstate(void)
 
   if (rtcb->pid == 0) /* Check for CPU0 IDLE thread */
     {
-      ustackbase = (uint32_t)&g_idlestack[IDLETHREAD_STACKWORDS-1];
+      ustackbase = (uint32_t)&g_idlestack[IDLETHREAD_STACKWORDS - 1];
       ustacksize = IDLETHREAD_STACKSIZE;
     }
   else
@@ -229,7 +229,7 @@ void xtensa_dumpstate(void)
 
 #warning REVISIT interrupt stack
 #ifdef HAVE_INTERRUPTSTACK
-  istackbase = (uint32_t)&g_intstack[INTERRUPT_STACKWORDS-1];
+  istackbase = (uint32_t)&g_intstack[INTERRUPT_STACKWORDS - 1];
   istacksize = INTERRUPTSTACK_SIZE;
 
   /* Show interrupt stack info */
diff --git a/arch/xtensa/src/common/xtensa_exit.c b/arch/xtensa/src/common/xtensa_exit.c
index d743ed62bf..ad2de1ba2b 100644
--- a/arch/xtensa/src/common/xtensa_exit.c
+++ b/arch/xtensa/src/common/xtensa_exit.c
@@ -201,8 +201,8 @@ void _exit(int status)
 
   xtensa_context_restore(tcb->xcp.regs);
 
-  /* xtensa_full_context_restore() should not return but could if the software
-   * interrupts are disabled.
+  /* xtensa_full_context_restore() should not return but could if the
+   * software interrupts are disabled.
    */
 
   DEBUGPANIC();
diff --git a/arch/xtensa/src/common/xtensa_idle.c b/arch/xtensa/src/common/xtensa_idle.c
index 9ac16d4e6c..9c683e209c 100644
--- a/arch/xtensa/src/common/xtensa_idle.c
+++ b/arch/xtensa/src/common/xtensa_idle.c
@@ -74,17 +74,18 @@ void up_idle(void)
    * sleep in a reduced power mode until an interrupt occurs to save power
    */
 
-  /* This is a kludge that I still don't understand.  The call to kmm_trysemaphore()
-   * in the nx_start.c IDLE loop seems necessary for the good health of the IDLE
-   * loop.  When the work queue is enabled, this logic is removed from the IDLE
-   * loop and it appears that we are somehow left idling with interrupts non-
-   * functional. The following should be no-op, it just disables then re-enables
-   * interrupts.  But it fixes the problem and will stay here until I understand
-   * the problem/fix better.
+  /* This is a kludge that I still don't understand.  The call to
+   * kmm_trysemaphore() in the nx_start.c IDLE loop seems necessary for the
+   * good health of the IDLE loop.  When the work queue is enabled, this
+   * logic is removed from the IDLE loop and it appears that we are somehow
+   * left idling with interrupts non-functional. The following should be
+   * no-op, it just disables then re-enables interrupts.  But it fixes the
+   * problem and will stay here until I understand the problem/fix better.
    *
-   * And no, the contents of the CP0 status register are not incorrect.  But for
-   * some reason the status register needs to be re-written again on this thread
-   * for it to take effect.  This might be a PIC32-only issue?
+   * And no, the contents of the CP0 status register are not incorrect.
+   * But for some reason the status register needs to be re-written again
+   * on this thread for it to take effect.  This might be a PIC32-only
+   * issue?
    */
 
 #ifdef CONFIG_SCHED_WORKQUEUE
@@ -98,5 +99,4 @@ void up_idle(void)
    */
 
   asm("waiti 0");
-
 }
diff --git a/arch/xtensa/src/common/xtensa_interruptcontext.c b/arch/xtensa/src/common/xtensa_interruptcontext.c
index 8cf096f725..defed9bd61 100644
--- a/arch/xtensa/src/common/xtensa_interruptcontext.c
+++ b/arch/xtensa/src/common/xtensa_interruptcontext.c
@@ -59,5 +59,5 @@
 
 bool up_interrupt_context(void)
 {
-   return CURRENT_REGS != NULL;
+  return CURRENT_REGS != NULL;
 }
diff --git a/arch/xtensa/src/common/xtensa_irqdispatch.c b/arch/xtensa/src/common/xtensa_irqdispatch.c
index 169ae2c6ec..b54511b040 100644
--- a/arch/xtensa/src/common/xtensa_irqdispatch.c
+++ b/arch/xtensa/src/common/xtensa_irqdispatch.c
@@ -99,25 +99,25 @@ uint32_t *xtensa_irq_dispatch(int irq, uint32_t *regs)
   if (regs != CURRENT_REGS)
     {
 #if XCHAL_CP_NUM > 0
-       /* If an interrupt level context switch has occurred, then save the
-        * co-processor state in in the suspended thread's co-processor save
-        * area.
-        *
-        * NOTE 1. The state of the co-processor has not been altered and
-        *         still represents the to-be-suspended thread.
-        * NOTE 2. We saved a reference  TCB of the original thread on entry.
-        */
+      /* If an interrupt level context switch has occurred, then save the
+       * co-processor state in in the suspended thread's co-processor save
+       * area.
+       *
+       * NOTE 1. The state of the co-processor has not been altered and
+       *         still represents the to-be-suspended thread.
+       * NOTE 2. We saved a reference  TCB of the original thread on entry.
+       */
 
-       xtensa_coproc_savestate(&tcb->xcp.cpstate);
+      xtensa_coproc_savestate(&tcb->xcp.cpstate);
 
-       /* Then set up the co-processor state for the to-be-started thread.
-        *
-        * NOTE: The current thread for this CPU is the to-be-started
-        * thread.
-        */
+      /* Then set up the co-processor state for the to-be-started thread.
+       *
+       * NOTE: The current thread for this CPU is the to-be-started
+       * thread.
+       */
 
-       tcb = this_task();
-       xtensa_coproc_restorestate(&tcb->xcp.cpstate);
+      tcb = this_task();
+      xtensa_coproc_restorestate(&tcb->xcp.cpstate);
 #endif
 
 #ifdef CONFIG_ARCH_ADDRENV
diff --git a/arch/xtensa/src/common/xtensa_releasepending.c b/arch/xtensa/src/common/xtensa_releasepending.c
index f43efe2f8f..50795f4075 100644
--- a/arch/xtensa/src/common/xtensa_releasepending.c
+++ b/arch/xtensa/src/common/xtensa_releasepending.c
@@ -74,6 +74,7 @@ void up_release_pending(void)
   /* Merge the g_pendingtasks list into the ready-to-run task list */
 
   /* sched_lock(); */
+
   if (sched_mergepending())
     {
       /* The currently active task has changed!  We will need to
diff --git a/arch/xtensa/src/common/xtensa_reprioritizertr.c b/arch/xtensa/src/common/xtensa_reprioritizertr.c
index 57ab9649f6..80af6860cf 100644
--- a/arch/xtensa/src/common/xtensa_reprioritizertr.c
+++ b/arch/xtensa/src/common/xtensa_reprioritizertr.c
@@ -167,7 +167,8 @@ void up_reprioritize_rtr(struct tcb_s *tcb, uint8_t priority)
 
           /* Copy the exception context into the TCB at the (old) head of the
            * ready-to-run Task list. if up_saveusercontext returns a non-zero
-           * value, then this is really the previously running task restarting!
+           * value, then this is really the previously running task
+           * restarting!
            */
 
           else if (!xtensa_context_save(rtcb->xcp.regs))
diff --git a/arch/xtensa/src/common/xtensa_schedsigaction.c b/arch/xtensa/src/common/xtensa_schedsigaction.c
index e989d4f30f..98885578c5 100644
--- a/arch/xtensa/src/common/xtensa_schedsigaction.c
+++ b/arch/xtensa/src/common/xtensa_schedsigaction.c
@@ -154,9 +154,11 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
 
               CURRENT_REGS[REG_PC] = (uint32_t)_xtensa_sig_trampoline;
 #ifdef __XTENSA_CALL0_ABI__
-              CURRENT_REGS[REG_PS] = (uint32_t)(PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM);
+              CURRENT_REGS[REG_PS] = (uint32_t)
+                  (PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM);
 #else
-              CURRENT_REGS[REG_PS] = (uint32_t)(PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM | PS_WOE);
+              CURRENT_REGS[REG_PS] = (uint32_t)
+                  (PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM | PS_WOE);
 #endif
 
               /* And make sure that the saved context in the TCB is the same
@@ -190,9 +192,11 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
 
           tcb->xcp.regs[REG_PC] = (uint32_t)_xtensa_sig_trampoline;
 #ifdef __XTENSA_CALL0_ABI__
-          tcb->xcp.regs[REG_PS] = (uint32_t)(PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM);
+          tcb->xcp.regs[REG_PS] = (uint32_t)
+              (PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM);
 #else
-          tcb->xcp.regs[REG_PS] = (uint32_t)(PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM | PS_WOE);
+          tcb->xcp.regs[REG_PS] = (uint32_t)
+              (PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM | PS_WOE);
 #endif
         }
     }
@@ -270,8 +274,9 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
 
                   /* Now tcb on the other CPU can be accessed safely */
 
-                  /* Copy tcb->xcp.regs to tcp.xcp.saved. These will be restored
-                   * by the signal trampoline after the signal has been delivered.
+                  /* Copy tcb->xcp.regs to tcp.xcp.saved. These will be
+                   * restored by the signal trampoline after the signal has
+                   * been delivered.
                    *
                    * NOTE: that hi-priority interrupts are not disabled.
                    */
@@ -286,17 +291,20 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
 
                   tcb->xcp.regs[REG_PC] = (uint32_t)_xtensa_sig_trampoline;
 #ifdef __XTENSA_CALL0_ABI__
-                  tcb->xcp.regs[REG_PS] = (uint32_t)(PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM);
+                  tcb->xcp.regs[REG_PS] = (uint32_t)
+                      (PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM);
 #else
-                  tcb->xcp.regs[REG_PS] = (uint32_t)(PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM | PS_WOE);
+                  tcb->xcp.regs[REG_PS] = (uint32_t)
+                      (PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM | PS_WOE);
 #endif
                 }
               else
                 {
                   /* tcb is running on the same CPU */
 
-                  /* Copy tcb->xcp.regs to tcp.xcp.saved. These will be restored
-                   * by the signal trampoline after the signal has been delivered.
+                  /* Copy tcb->xcp.regs to tcp.xcp.saved. These will be
+                   * restored by the signal trampoline after the signal has
+                   * been delivered.
                    *
                    * NOTE: that hi-priority interrupts are not disabled.
                    */
@@ -311,19 +319,21 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
 
                   CURRENT_REGS[REG_PC] = (uint32_t)_xtensa_sig_trampoline;
 #ifdef __XTENSA_CALL0_ABI__
-                  CURRENT_REGS[REG_PS] = (uint32_t)(PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM);
+                  CURRENT_REGS[REG_PS] = (uint32_t)
+                      (PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM);
 #else
-                  CURRENT_REGS[REG_PS] = (uint32_t)(PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM | PS_WOE);
+                  CURRENT_REGS[REG_PS] = (uint32_t)
+                      (PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM | PS_WOE);
 #endif
-                  /* And make sure that the saved context in the TCB is the same
-                   * as the interrupt return context.
+                  /* And make sure that the saved context in the TCB is the
+                   * same as the interrupt return context.
                    */
 
                   xtensa_savestate(tcb->xcp.regs);
                 }
 
-              /* Increment the IRQ lock count so that when the task is restarted,
-               * it will hold the IRQ spinlock.
+              /* Increment the IRQ lock count so that when the task is
+               * restarted, it will hold the IRQ spinlock.
                */
 
               DEBUGASSERT(tcb->irqcount < INT16_MAX);
@@ -331,7 +341,8 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
 
               /* In an SMP configuration, the interrupt disable logic also
                * involves spinlocks that are configured per the TCB irqcount
-               * field.  This is logically equivalent to enter_critical_section().
+               * field.  This is logically equivalent to
+               * enter_critical_section().
                * The matching call to leave_critical_section() will be
                * performed in up_sigdeliver().
                */
@@ -378,9 +389,11 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
 
           tcb->xcp.regs[REG_PC] = (uint32_t)_xtensa_sig_trampoline;
 #ifdef __XTENSA_CALL0_ABI__
-          tcb->xcp.regs[REG_PS] = (uint32_t)(PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM);
+          tcb->xcp.regs[REG_PS] = (uint32_t)
+              (PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM);
 #else
-          tcb->xcp.regs[REG_PS] = (uint32_t)(PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM | PS_WOE);
+          tcb->xcp.regs[REG_PS] = (uint32_t)
+              (PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM | PS_WOE);
 #endif
         }
     }
diff --git a/arch/xtensa/src/common/xtensa_stackframe.c b/arch/xtensa/src/common/xtensa_stackframe.c
index 884225d69a..e00ba6b63a 100644
--- a/arch/xtensa/src/common/xtensa_stackframe.c
+++ b/arch/xtensa/src/common/xtensa_stackframe.c
@@ -51,8 +51,9 @@
 /****************************************************************************
  * Pre-processor Macros
  ****************************************************************************/
-/* XTENSA requires at least a 4-byte stack alignment.  For floating point use,
- * however, the stack must be aligned to 8-byte addresses.
+
+/* XTENSA requires at least a 4-byte stack alignment.  For floating point
+ * use, however, the stack must be aligned to 8-byte addresses.
  */
 
 #ifdef CONFIG_LIBC_FLOATINGPOINT
diff --git a/arch/xtensa/src/common/xtensa_timer.h b/arch/xtensa/src/common/xtensa_timer.h
index b4542ddba3..dba43ef5a0 100644
--- a/arch/xtensa/src/common/xtensa_timer.h
+++ b/arch/xtensa/src/common/xtensa_timer.h
@@ -28,13 +28,17 @@
  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  *
- *******************************************************************************/
+ ****************************************************************************/
 
 #ifndef __ARCH_XTENSA_SRC_COMMON_XTENSA_TIMER_H
 #define __ARCH_XTENSA_SRC_COMMON_XTENSA_TIMER_H
 
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
 #ifdef __ASSEMBLER__
-//#  include <xtensa/coreasm.h>
+/* #  include <xtensa/coreasm.h> */
 #endif
 
 #include <arch/xtensa/core.h>
@@ -44,8 +48,10 @@
 /* Select timer to use for periodic tick, and determine its interrupt number
  * and priority. User may specify a timer by defining XT_TIMER_INDEX with -D,
  * in which case its validity is checked (it must exist in this core and must
- * not be on a high priority interrupt - an error will be reported in invalid).
- * Otherwise select the first low or medium priority interrupt timer available.
+ * not be on a high priority interrupt - an error will be reported in
+ * invalid).
+ * Otherwise select the first low or medium priority interrupt timer
+ * available.
  */
 
 #if XCHAL_NUM_TIMERS == 0
diff --git a/arch/xtensa/src/common/xtensa_udelay.c b/arch/xtensa/src/common/xtensa_udelay.c
index 8ec27f1541..744f4036d4 100644
--- a/arch/xtensa/src/common/xtensa_udelay.c
+++ b/arch/xtensa/src/common/xtensa_udelay.c
@@ -84,6 +84,7 @@ void up_udelay(useconds_t microseconds)
       for (i = 0; i < CONFIG_BOARD_LOOPSPERMSEC; i++)
         {
         }
+
       microseconds -= 1000;
     }
 
@@ -92,6 +93,7 @@ void up_udelay(useconds_t microseconds)
       for (i = 0; i < CONFIG_BOARD_LOOPSPER100USEC; i++)
         {
         }
+
       microseconds -= 100;
     }
 
@@ -100,6 +102,7 @@ void up_udelay(useconds_t microseconds)
       for (i = 0; i < CONFIG_BOARD_LOOPSPER10USEC; i++)
         {
         }
+
       microseconds -= 10;
     }
 
@@ -108,6 +111,7 @@ void up_udelay(useconds_t microseconds)
       for (i = 0; i < CONFIG_BOARD_LOOPSPERUSEC; i++)
         {
         }
+
       microseconds--;
     }
 }
diff --git a/arch/xtensa/src/common/xtensa_usestack.c b/arch/xtensa/src/common/xtensa_usestack.c
index 4faff7341b..dfcfeb01ff 100644
--- a/arch/xtensa/src/common/xtensa_usestack.c
+++ b/arch/xtensa/src/common/xtensa_usestack.c
@@ -53,8 +53,8 @@
  * Pre-processor Definitions
  ****************************************************************************/
 
-/* XTENSA requires at least a 4-byte stack alignment.  For floating point use,
- * however, the stack must be aligned to 8-byte addresses.
+/* XTENSA requires at least a 4-byte stack alignment.  For floating point
+ * use, however, the stack must be aligned to 8-byte addresses.
  */
 
 #ifdef CONFIG_LIBC_FLOATINGPOINT
@@ -127,9 +127,9 @@ int up_use_stack(struct tcb_s *tcb, void *stack, size_t stack_size)
 
   top_of_stack = (uint32_t)tcb->stack_alloc_ptr + stack_size - 4;
 
-  /* The XTENSA stack must be aligned at word (4 byte) or double word (8 byte)
-   * boundaries. If necessary top_of_stack must be rounded down to the
-   * next boundary
+  /* The XTENSA stack must be aligned at word (4 byte) or double word
+   * (8 byte) boundaries. If necessary top_of_stack must be rounded down to
+   * the next boundary
    */
 
   top_of_stack = STACK_ALIGN_DOWN(top_of_stack);
diff --git a/arch/xtensa/src/esp32/chip_macros.h b/arch/xtensa/src/esp32/chip_macros.h
index 44a993b00c..36a7846b9c 100644
--- a/arch/xtensa/src/esp32/chip_macros.h
+++ b/arch/xtensa/src/esp32/chip_macros.h
@@ -61,15 +61,15 @@
  * simply checking bit 1: it's 1 on the APP and 0 on the PRO processor.
  */
 
-	.macro		getcoreid reg
-	rsr.prid	\reg
-	bbci		\reg, 1, 1f
-	movi		\reg, 1
-	j			2f
+    .macro      getcoreid reg
+    rsr.prid    \reg
+    bbci        \reg, 1, 1f
+    movi        \reg, 1
+    j           2f
 1:
-	movi		\reg, 0
+    movii       \reg, 0
 2:
-	.endm
+    .endm
 
 #endif /* __ASSEMBLY */
 #endif /* __ARCH_XTENSA_SRC_ESP32_CHIP_MACROS_H */
diff --git a/arch/xtensa/src/esp32/esp32_clockconfig.c b/arch/xtensa/src/esp32/esp32_clockconfig.c
index cabcb1197b..42a2cfd26a 100644
--- a/arch/xtensa/src/esp32/esp32_clockconfig.c
+++ b/arch/xtensa/src/esp32/esp32_clockconfig.c
@@ -99,7 +99,9 @@ void esp32_clockconfig(void)
       break;
     default:
       freq_mhz = 80;
+
       /* no break */
+
     case 80:
       freq = CPU_80M;
       break;
diff --git a/arch/xtensa/src/esp32/esp32_config.h b/arch/xtensa/src/esp32/esp32_config.h
index 23c0d06169..8359673b0f 100644
--- a/arch/xtensa/src/esp32/esp32_config.h
+++ b/arch/xtensa/src/esp32/esp32_config.h
@@ -48,9 +48,11 @@
 /****************************************************************************
  * Pre-processor Definitions
  ****************************************************************************/
+
 /* GPIO IRQs ****************************************************************/
 
 /* UARTs ********************************************************************/
+
 /* Don't enable UARTs not supported by the chip. */
 
 #if ESP32_NUARTS < 1
@@ -85,6 +87,7 @@
 #endif
 
 /* Serial Console ***********************************************************/
+
 /* Is there a serial console?  There should be no more than one defined.  It
  * could be on any UARTn, n=1,..,ESP32_NUART, or USARTn, n=1,.., ESP32_NUSART
  */
@@ -108,7 +111,8 @@
 #  undef CONFIG_UART2_SERIAL_CONSOLE
 #endif
 
-/* SPI ******************************************************************************/
+/* SPI **********************************************************************/
+
 /* Don't enable SPI peripherals not supported by the chip. */
 
 #if ESP32_NSPI < 1
diff --git a/arch/xtensa/src/esp32/esp32_cpuidlestack.c b/arch/xtensa/src/esp32/esp32_cpuidlestack.c
index 6385524c25..e3524c8e2f 100644
--- a/arch/xtensa/src/esp32/esp32_cpuidlestack.c
+++ b/arch/xtensa/src/esp32/esp32_cpuidlestack.c
@@ -104,14 +104,16 @@ int up_cpu_idlestack(int cpu, FAR struct tcb_s *tcb, size_t stack_size)
 
   /* Save information about pre-allocated IDLE thread stack */
 
-
   tcb->stack_alloc_ptr = g_cpu1_idlestack;
   tcb->adj_stack_size  = CPU1_IDLETHREAD_STACKSIZE;
-  topofstack           = (uintptr_t)g_cpu1_idlestack + CPU1_IDLETHREAD_STACKSIZE;
+  topofstack           = (uintptr_t)g_cpu1_idlestack +
+                         CPU1_IDLETHREAD_STACKSIZE;
   tcb->adj_stack_ptr   = (uint32_t *)topofstack;
 
 #if XCHAL_CP_NUM > 0
-  /* REVISIT: Does it make since to have co-processors enabled on the IDLE thread? */
+  /* REVISIT: Does it make since to have co-processors enabled on the IDLE
+   * thread?
+   */
 #endif
 
   return OK;
diff --git a/arch/xtensa/src/esp32/esp32_gpio.c b/arch/xtensa/src/esp32/esp32_gpio.c
index d83eb2e63e..1f956efa73 100644
--- a/arch/xtensa/src/esp32/esp32_gpio.c
+++ b/arch/xtensa/src/esp32/esp32_gpio.c
@@ -163,7 +163,7 @@ int esp32_configgpio(int pin, gpio_pinattr_t attr)
   uint32_t cntrl;
   unsigned int pinmode;
 
-  DEBUGASSERT(pin >=0 && pin <= ESP32_NIRQ_GPIO);
+  DEBUGASSERT(pin >= 0 && pin <= ESP32_NIRQ_GPIO);
 
   /* Handle input pins */
 
@@ -250,7 +250,7 @@ int esp32_configgpio(int pin, gpio_pinattr_t attr)
 
 void esp32_gpiowrite(int pin, bool value)
 {
-  DEBUGASSERT(pin >=0 && pin <= ESP32_NIRQ_GPIO);
+  DEBUGASSERT(pin >= 0 && pin <= ESP32_NIRQ_GPIO);
 
   if (value)
     {
@@ -288,7 +288,7 @@ bool esp32_gpioread(int pin)
 {
   uint32_t regval;
 
-  DEBUGASSERT(pin >=0 && pin <= ESP32_NIRQ_GPIO);
+  DEBUGASSERT(pin >= 0 && pin <= ESP32_NIRQ_GPIO);
 
   if (pin < 32)
     {
diff --git a/arch/xtensa/src/esp32/esp32_gpio.h b/arch/xtensa/src/esp32/esp32_gpio.h
index dda697e18f..1d5de0a502 100644
--- a/arch/xtensa/src/esp32/esp32_gpio.h
+++ b/arch/xtensa/src/esp32/esp32_gpio.h
@@ -199,11 +199,6 @@ void esp32_gpioirqdisable(int irq);
 #  define esp32_gpioirqdisable(irq)
 #endif
 
-int digitalRead(uint8_t pin);
-
-void attachInterrupt(uint8_t pin, void (*)(void), int mode);
-void detachInterrupt(uint8_t pin);
-
 #ifdef __cplusplus
 }
 #endif
diff --git a/arch/xtensa/src/esp32/esp32_region.c b/arch/xtensa/src/esp32/esp32_region.c
index 1e64aa7e32..a3bc68b03b 100644
--- a/arch/xtensa/src/esp32/esp32_region.c
+++ b/arch/xtensa/src/esp32/esp32_region.c
@@ -57,22 +57,22 @@ static const uint32_t g_protected_pages[] =
 
 static inline void xtensa_write_dtlb(uint32_t vpn, unsigned int attr)
 {
-   __asm__ __volatile__
-   (
-     "wdtlb  %1, %0\n"
-     "dsync\n"
-     : : "r" (vpn), "r" (attr)
-   );
+  __asm__ __volatile__
+  (
+    "wdtlb  %1, %0\n"
+    "dsync\n"
+    : : "r" (vpn), "r" (attr)
+  );
 }
 
 static inline void xtensa_write_itlb(unsigned vpn, unsigned int attr)
 {
-   __asm__ __volatile__
-   (
-     "witlb  %1, %0\n"
-     "isync\n"
-     : : "r" (vpn), "r" (attr)
-   );
+  __asm__ __volatile__
+  (
+    "witlb  %1, %0\n"
+    "isync\n"
+    : : "r" (vpn), "r" (attr)
+  );
 }
 
 /****************************************************************************
diff --git a/arch/xtensa/src/esp32/esp32_serial.c b/arch/xtensa/src/esp32/esp32_serial.c
index 5960abb137..6817afc71a 100644
--- a/arch/xtensa/src/esp32/esp32_serial.c
+++ b/arch/xtensa/src/esp32/esp32_serial.c
@@ -139,6 +139,7 @@
 /****************************************************************************
  * Private Types
  ****************************************************************************/
+
 /* Constant properties of the UART.  Other configuration setting may be
  * changeable via Termios IOCTL calls.
  */
@@ -165,14 +166,14 @@ struct esp32_config_s
 struct esp32_dev_s
 {
   const struct esp32_config_s *config; /* Constant configuration */
-  uint32_t baud;                /* Configured baud */
-  uint32_t status;              /* Saved status bits */
-  uint8_t  cpuint;              /* CPU interrupt assigned to this UART */
-  uint8_t  parity;              /* 0=none, 1=odd, 2=even */
-  uint8_t  bits;                /* Number of bits (5-9) */
-  bool     stopbits2;           /* true: Configure with 2 stop bits instead of 1 */
+  uint32_t baud;                       /* Configured baud */
+  uint32_t status;                     /* Saved status bits */
+  uint8_t  cpuint;                     /* CPU interrupt assigned to this UART */
+  uint8_t  parity;                     /* 0=none, 1=odd, 2=even */
+  uint8_t  bits;                       /* Number of bits (5-9) */
+  bool     stopbits2;                  /* true: Configure with 2 stop bits instead of 1 */
 #if defined(CONFIG_SERIAL_IFLOWCONTROL) || defined(CONFIG_SERIAL_OFLOWCONTROL)
-  bool     flowc;               /* Input flow control (RTS) enabled */
+  bool     flowc;                      /* Input flow control (RTS) enabled */
 #endif
 };
 
@@ -474,7 +475,7 @@ static int esp32_setup(struct uart_dev_s *dev)
 
   if (priv->bits == 5)
     {
-                                       /* 0=5 bits */
+      /* 0=5 bits */
     }
   else if (priv->bits == 6)
     {
@@ -760,26 +761,27 @@ static int esp32_interrupt(int cpuint, void *context, FAR void *arg)
        * data, possibly resulting in an overrun error.
        */
 
-     if ((enabled & (UART_RXFIFO_FULL_INT_ENA |
+      if ((enabled & (UART_RXFIFO_FULL_INT_ENA |
                      UART_RXFIFO_TOUT_INT_ENA)) != 0)
-       {
-         /* Is there any data waiting in the Rx FIFO? */
+        {
+          /* Is there any data waiting in the Rx FIFO? */
 
-         nfifo = (status & UART_RXFIFO_CNT_M) >> UART_RXFIFO_CNT_S;
-         if (nfifo > 0)
+          nfifo = (status & UART_RXFIFO_CNT_M) >> UART_RXFIFO_CNT_S;
+          if (nfifo > 0)
             {
               /* Received data in the RXFIFO! ... Process incoming bytes */
 
               uart_recvchars(dev);
               handled = true;
             }
-       }
+        }
 
       /* Are Tx interrupts enabled?  The upper layer will disable Tx
        * interrupts when it has nothing to send.
        */
 
-      if ((enabled & (UART_TX_DONE_INT_ENA | UART_TXFIFO_EMPTY_INT_ENA)) != 0)
+      if ((enabled & (UART_TX_DONE_INT_ENA | UART_TXFIFO_EMPTY_INT_ENA))
+          != 0)
         {
           nfifo = (status & UART_TXFIFO_CNT_M) >> UART_TXFIFO_CNT_S;
           if (nfifo < 0x7f)
@@ -881,7 +883,7 @@ static int esp32_ioctl(struct file *filep, int cmd, unsigned long arg)
             break;
 
           case 9:
-            termiosp->c_cflag |= CS8 /* CS9 */;
+            termiosp->c_cflag |= CS8 /* CS9 */ ;
             break;
           }
       }
@@ -1075,7 +1077,8 @@ static bool esp32_rxavailable(struct uart_dev_s *dev)
 {
   struct esp32_dev_s *priv = (struct esp32_dev_s *)dev->priv;
 
-  return ((esp32_serialin(priv, UART_STATUS_OFFSET) & UART_RXFIFO_CNT_M) > 0);
+  return ((esp32_serialin(priv, UART_STATUS_OFFSET)
+          & UART_RXFIFO_CNT_M) > 0);
 }
 
 /****************************************************************************
diff --git a/arch/xtensa/src/esp32/esp32_smp.h b/arch/xtensa/src/esp32/esp32_smp.h
index 14da3164ac..3a5bb70321 100644
--- a/arch/xtensa/src/esp32/esp32_smp.h
+++ b/arch/xtensa/src/esp32/esp32_smp.h
@@ -68,7 +68,7 @@
 extern uint32_t g_cpu1_idlestack[CPU1_IDLETHREAD_STACKWORDS];
 
 /****************************************************************************
- * Public Functions
+ * Public Function Prototypes
  ****************************************************************************/
 
 /****************************************************************************
diff --git a/arch/xtensa/src/esp32/esp32_start.c b/arch/xtensa/src/esp32/esp32_start.c
index 8bfbf733e1..f4cd1d8431 100644
--- a/arch/xtensa/src/esp32/esp32_start.c
+++ b/arch/xtensa/src/esp32/esp32_start.c
@@ -87,16 +87,16 @@ void IRAM_ATTR __start(void)
 
   /* Make sure that normal interrupts are disabled.  This is really only an
    * issue when we are started in un-usual ways (such as from IRAM).  In this
-   * case, we can at least defer some unexpected interrupts left over from the
-   * last program execution.
+   * case, we can at least defer some unexpected interrupts left over from
+   * the last program execution.
    */
 
   up_irq_disable();
 
 #ifdef CONFIG_STACK_COLORATION
-  {
-    register uint32_t *ptr;
-    register int i;
+    {
+      register uint32_t *ptr;
+      register int i;
 
       /* If stack debug is enabled, then fill the stack with a recognizable
        * value that we can use later to test for high water marks.
@@ -106,13 +106,13 @@ void IRAM_ATTR __start(void)
         {
           *ptr++ = STACK_COLOR;
         }
-  }
+    }
 #endif
 
   /* Move the stack to a known location.  Although we were give a stack
-   * pointer at start-up, we don't know where that stack pointer is positioned
-   * respect to our memory map.  The only safe option is to switch to a well-
-   * known IDLE thread stack.
+   * pointer at start-up, we don't know where that stack pointer is
+   * positioned respect to our memory map.  The only safe option is to
+   * switch to a well-known IDLE thread stack.
    */
 
   sp = (uint32_t)g_idlestack + IDLETHREAD_STACKSIZE;
@@ -141,7 +141,7 @@ void IRAM_ATTR __start(void)
   esp32_clockconfig();
 
 #ifdef USE_EARLYSERIALINIT
- /* Perform early serial initialization */
+  /* Perform early serial initialization */
 
   xtensa_early_serial_initialize();
 #endif
diff --git a/arch/xtensa/src/esp32/rom/esp32_gpio.h b/arch/xtensa/src/esp32/rom/esp32_gpio.h
index 0f93219cb5..a3d7d6b3d7 100644
--- a/arch/xtensa/src/esp32/rom/esp32_gpio.h
+++ b/arch/xtensa/src/esp32/rom/esp32_gpio.h
@@ -64,7 +64,8 @@ typedef enum gpio_inttype_e GPIO_INT_TYPE;
 
 /* GPIO interrupt handler, registered through gpio_intr_handler_register */
 
-typedef void (*gpio_intr_handler_fn_t)(uint32_t intr_mask, bool high, void *arg);
+typedef void (*gpio_intr_handler_fn_t)(uint32_t intr_mask, bool high,
+              void *arg);
 
 /****************************************************************************
  * Public Function Prototypes
@@ -260,7 +261,8 @@ void gpio_intr_ack_high(uint32_t ack_mask);
  *
  * Input Parameters:
  *   i          - gpio number.
- *   intr_state - only GPIO_PIN_INTR_LOLEVEL\GPIO_PIN_INTR_HILEVEL can be used
+ *   intr_state - only GPIO_PIN_INTR_LOLEVEL\GPIO_PIN_INTR_HILEVEL can be
+ *                used
  *
  * Returned Value:
  *  None
diff --git a/boards/xtensa/esp32/esp32-core/src/esp32-core.h b/boards/xtensa/esp32/esp32-core/src/esp32-core.h
index a5a5bce757..7461d13bc8 100644
--- a/boards/xtensa/esp32/esp32-core/src/esp32-core.h
+++ b/boards/xtensa/esp32/esp32-core/src/esp32-core.h
@@ -59,7 +59,7 @@
 #ifndef __ASSEMBLY__
 
 /****************************************************************************
- * Public Functions
+ * Public Function Prototypes
  ****************************************************************************/
 
 /****************************************************************************
diff --git a/boards/xtensa/esp32/esp32-core/src/esp32_boot.c b/boards/xtensa/esp32/esp32-core/src/esp32_boot.c
index 866c7976fd..fff5c51260 100644
--- a/boards/xtensa/esp32/esp32-core/src/esp32_boot.c
+++ b/boards/xtensa/esp32/esp32-core/src/esp32_boot.c
@@ -79,10 +79,11 @@ void esp32_board_initialize(void)
  * Description:
  *   If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional
  *   initialization call will be performed in the boot-up sequence to a
- *   function called board_late_initialize().  board_late_initialize() will be
- *   called immediately after up_initialize() is called and just before the
- *   initial application is started.  This additional initialization phase
- *   may be used, for example, to initialize board-specific device drivers.
+ *   function called board_late_initialize().  board_late_initialize() will
+ *   be called immediately after up_initialize() is called and just before
+ *   the initial application is started.  This additional initializationi
+ *   phase may be used, for example, to initialize board-specific device
+ *   drivers.
  *
  ****************************************************************************/