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risc-v/espressif/rmt: Update common source code functions

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Updates the common source code for the RMT peripheral used by
Espressif's RISC-Vs SoCs. This enables newer SoCs to be supported
in the future while maintaining backwards compatibility.

Signed-off-by: Tiago Medicci Serrano <tiago.medicci@espressif.com>
This commit is contained in:
Tiago Medicci Serrano 2025-08-26 14:33:58 -03:00 • committed by Matteo Golin
parent 0f29e135e1
commit 78b7cc729b
1 changed files with 49 additions and 14 deletions
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63
arch/risc-v/src/common/espressif/esp_rmt.c
View file

@ -55,6 +55,7 @@
#include "soc/rmt_periph.h"
#include "soc/soc_caps.h"
#include "esp_clk_tree.h"
#include "esp_private/esp_clk_tree_common.h"
#include "esp_rmt.h"
@ -427,8 +428,7 @@ static void rmt_module_enable(void)
rmt_ll_reset_register(0);
}
periph_module_reset(PERIPH_RMT_MODULE);
periph_module_enable(PERIPH_RMT_MODULE);
rmt_ll_mem_power_by_pmu(g_rmtdev_common.hal.regs);
g_rmtdev_common.rmt_module_enabled = true;
}
@ -804,6 +804,7 @@ static int rmt_internal_config(rmt_dev_t *dev,
bool carrier_en = rmt_param->tx_config.carrier_en;
uint32_t rmt_source_clk_hz;
irqstate_t flags;
int ret = OK;
if (!rmt_is_channel_number_valid(channel, mode))
{
@ -834,9 +835,21 @@ static int rmt_internal_config(rmt_dev_t *dev,
esp_clk_tree_src_get_freq_hz((soc_module_clk_t)RMT_BASECLK_XTAL,
ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED,
&rmt_source_clk_hz);
rmt_ll_set_group_clock_src(dev, channel,
(rmt_clock_source_t)RMT_BASECLK_XTAL,
1, 0, 0);
ret = esp_clk_tree_enable_src((soc_module_clk_t)RMT_BASECLK_XTAL,
true);
if (ret != ESP_OK)
{
rmterr("Failed to enable XTAL clock source: %d", ret);
return -EPERM;
}
RMT_CLOCK_SRC_ATOMIC()
{
rmt_ll_set_group_clock_src(dev, channel,
(rmt_clock_source_t)RMT_BASECLK_XTAL,
1, 0, 0);
}
#elif SOC_RMT_SUPPORT_REF_TICK
/* clock src: REF_CLK */
@ -844,9 +857,12 @@ static int rmt_internal_config(rmt_dev_t *dev,
esp_clk_tree_src_get_freq_hz((soc_module_clk_t)RMT_BASECLK_REF,
ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED,
&rmt_source_clk_hz);
rmt_ll_set_group_clock_src(dev, channel,
(rmt_clock_source_t)RMT_BASECLK_REF,
1, 0, 0);
RMT_CLOCK_SRC_ATOMIC()
{
rmt_ll_set_group_clock_src(dev, channel,
(rmt_clock_source_t)RMT_BASECLK_REF,
1, 0, 0);
}
#else
#error "No clock source is aware of DFS"
#endif
@ -858,9 +874,20 @@ static int rmt_internal_config(rmt_dev_t *dev,
esp_clk_tree_src_get_freq_hz((soc_module_clk_t)RMT_BASECLK_DEFAULT,
ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED,
&rmt_source_clk_hz);
rmt_ll_set_group_clock_src(dev, channel,
(rmt_clock_source_t)RMT_BASECLK_DEFAULT,
1, 0, 0);
ret = esp_clk_tree_enable_src((soc_module_clk_t)RMT_BASECLK_DEFAULT,
true);
if (ret != ESP_OK)
{
rmterr("Failed to enable XTAL clock source: %d", ret);
return -EPERM;
}
RMT_CLOCK_SRC_ATOMIC()
{
rmt_ll_set_group_clock_src(dev, channel,
(rmt_clock_source_t)RMT_BASECLK_DEFAULT,
1, 0, 0);
}
}
RMT_CLOCK_SRC_ATOMIC()
@ -1006,7 +1033,7 @@ static int rmt_internal_config(rmt_dev_t *dev,
threshold, filter_cnt);
}
return OK;
return ret;
}
/****************************************************************************
@ -1262,6 +1289,10 @@ static int IRAM_ATTR rmt_driver_isr_default(int irq, void *context,
{
item_len = item_len - p_rmt->rx_item_start_idx;
}
else
{
item_len = p_rmt->rx_item_start_idx - item_len;
}
/* Check for RX buffer max length */
@ -1876,12 +1907,16 @@ static struct rmt_dev_s
if (g_rx_channel != RMT_CHANNEL_MAX && g_tx_channel != RMT_CHANNEL_MAX)
{
uint32_t tx_sig =
rmt_periph_signals.groups[0].channels[g_tx_channel].tx_sig;
uint32_t rx_sig =
rmt_periph_signals.groups[0].channels[g_rx_channel].rx_sig;
esp_configgpio(config.gpio_num, OUTPUT | INPUT);
esp_gpio_matrix_out(config.gpio_num,
RMT_SIG_OUT0_IDX + g_tx_channel,
tx_sig,
0, 0);
esp_gpio_matrix_in(config.gpio_num,
RMT_SIG_IN0_IDX + g_rx_channel,
rx_sig,
0);
rmtwarn("RX channel %d and TX channel %d are used in loop test "
"mode\n", g_rx_channel, g_tx_channel);