From 7aebcc4bf62d84b8034729135a7f9448ca1e61c2 Mon Sep 17 00:00:00 2001 From: YAMAMOTO Takashi Date: Mon, 16 Mar 2020 14:15:14 +0900 Subject: [PATCH] xtensa_user_handler: Fix registers in comments --- arch/xtensa/src/common/xtensa_user_handler.S | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/xtensa/src/common/xtensa_user_handler.S b/arch/xtensa/src/common/xtensa_user_handler.S index 065baef3ed..14acfc10f7 100644 --- a/arch/xtensa/src/common/xtensa_user_handler.S +++ b/arch/xtensa/src/common/xtensa_user_handler.S @@ -337,7 +337,7 @@ _xtensa_syscall_handler: mov a3, sp /* Argument 2: Top of stack = register save area */ call0 xtensa_irq_dispatch /* Call xtensa_int_decode */ - /* On return from xtensa_irq_dispatch, a2 will contain the address of the new + /* On return from xtensa_irq_dispatch, A2 will contain the address of the new * register save area. Usually this would be the same as the current SP. * But in the event of a context switch, A2 will instead refer to the TCB * register save area. @@ -348,9 +348,9 @@ _xtensa_syscall_handler: mov a7, sp /* Argument 2: Top of stack = register save area */ call4 xtensa_irq_dispatch /* Call xtensa_int_decode */ - /* On return from xtensa_irq_dispatch, a5 will contain the address of the new + /* On return from xtensa_irq_dispatch, A6 will contain the address of the new * register save area. Usually this would be the same as the current SP. - * But in the event of a context switch, A2 will instead refer to the TCB + * But in the event of a context switch, A6 will instead refer to the TCB * register save area. */