From 7dbfae87ec28883bb7b9f283839bc462c3c0b26c Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Wed, 7 Oct 2015 13:58:11 -0600 Subject: [PATCH] STM32 F7: Correct some spacing issues --- arch/arm/src/stm32f7/stm32_allocateheap.c | 16 +++---- arch/arm/src/stm32f7/stm32_dma.c | 6 +-- arch/arm/src/stm32f7/stm32_ethernet.c | 51 ++++++++++++----------- arch/arm/src/stm32f7/stm32_irq.c | 10 ++--- arch/arm/src/stm32f7/stm32_lowputc.c | 18 ++++---- arch/arm/src/stm32f7/stm32_procfs_dtcm.c | 2 +- arch/arm/src/stm32f7/stm32_serial.c | 40 +++++++++--------- arch/arm/src/stm32f7/stm32_start.c | 4 +- arch/arm/src/stm32f7/stm32_userspace.c | 10 ++--- arch/arm/src/stm32f7/stm32f74xx75xx_rcc.c | 8 ++-- 10 files changed, 83 insertions(+), 82 deletions(-) diff --git a/arch/arm/src/stm32f7/stm32_allocateheap.c b/arch/arm/src/stm32f7/stm32_allocateheap.c index df02bd3563..628a83ff4f 100644 --- a/arch/arm/src/stm32f7/stm32_allocateheap.c +++ b/arch/arm/src/stm32f7/stm32_allocateheap.c @@ -241,12 +241,12 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size) /* Return the user-space heap settings */ board_led_on(LED_HEAPALLOCATE); - *heap_start = (FAR void*)ubase; + *heap_start = (FAR void *)ubase; *heap_size = usize; /* Colorize the heap for debug */ - up_heap_color((FAR void*)ubase, usize); + up_heap_color((FAR void *)ubase, usize); /* Allow user-mode access to the user heap memory */ @@ -256,7 +256,7 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size) /* Return the heap settings */ board_led_on(LED_HEAPALLOCATE); - *heap_start = (FAR void*)g_idle_topstack; + *heap_start = (FAR void *)g_idle_topstack; *heap_size = SRAM1_END - g_idle_topstack; /* Colorize the heap for debug */ @@ -304,7 +304,7 @@ void up_allocate_kheap(FAR void **heap_start, size_t *heap_size) * that was not dedicated to the user heap). */ - *heap_start = (FAR void*)USERSPACE->us_bssend; + *heap_start = (FAR void *)USERSPACE->us_bssend; *heap_size = ubase - (uintptr_t)USERSPACE->us_bssend; } #endif @@ -331,11 +331,11 @@ void up_addregion(void) /* Colorize the heap for debug */ - up_heap_color((FAR void*)SRAM2_START, SRAM2_END-SRAM2_START); + up_heap_color((FAR void *)SRAM2_START, SRAM2_END-SRAM2_START); /* Add the STM32F20xxx/STM32F40xxx SRAM2 user heap region. */ - kumm_addregion((FAR void*)SRAM2_START, SRAM2_END-SRAM2_START); + kumm_addregion((FAR void *)SRAM2_START, SRAM2_END-SRAM2_START); #ifdef CONFIG_STM32F7_FSMC_SRAM #if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP) @@ -348,11 +348,11 @@ void up_addregion(void) /* Colorize the heap for debug */ - up_heap_color((FAR void*)CONFIG_HEAP2_BASE, CONFIG_HEAP2_SIZE); + up_heap_color((FAR void *)CONFIG_HEAP2_BASE, CONFIG_HEAP2_SIZE); /* Add the external FSMC SRAM user heap region. */ - kumm_addregion((FAR void*)CONFIG_HEAP2_BASE, CONFIG_HEAP2_SIZE); + kumm_addregion((FAR void *)CONFIG_HEAP2_BASE, CONFIG_HEAP2_SIZE); #endif } #endif diff --git a/arch/arm/src/stm32f7/stm32_dma.c b/arch/arm/src/stm32f7/stm32_dma.c index 798a5965bf..6bc5344098 100644 --- a/arch/arm/src/stm32f7/stm32_dma.c +++ b/arch/arm/src/stm32f7/stm32_dma.c @@ -683,7 +683,7 @@ void stm32_dmasetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr, */ regval = dmast_getreg(dmast, STM32_DMA_SCR_OFFSET); - regval &= ~(DMA_SCR_PL_MASK|DMA_SCR_CHSEL_MASK); + regval &= ~(DMA_SCR_PL_MASK | DMA_SCR_CHSEL_MASK); regval |= scr & DMA_SCR_PL_MASK; regval |= (uint32_t)dmast->channel << DMA_SCR_CHSEL_SHIFT; dmast_putreg(dmast, STM32_DMA_SCR_OFFSET, regval); @@ -775,7 +775,7 @@ void stm32_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg, bool * interrupt at the halfway point. */ - if ((scr & (DMA_SCR_DBM|DMA_SCR_CIRC)) == 0) + if ((scr & (DMA_SCR_DBM | DMA_SCR_CIRC)) == 0) { /* Once half of the bytes are transferred, the half-transfer flag (HTIF) is * set and an interrupt is generated if the Half-Transfer Interrupt Enable @@ -784,7 +784,7 @@ void stm32_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg, bool * Interrupt Enable bit (TCIE) is set. */ - scr |= (half ? (DMA_SCR_HTIE|DMA_SCR_TEIE) : (DMA_SCR_TCIE|DMA_SCR_TEIE)); + scr |= (half ? (DMA_SCR_HTIE | DMA_SCR_TEIE) : (DMA_SCR_TCIE | DMA_SCR_TEIE)); } else { diff --git a/arch/arm/src/stm32f7/stm32_ethernet.c b/arch/arm/src/stm32f7/stm32_ethernet.c index 5cd46247dc..768a79979d 100644 --- a/arch/arm/src/stm32f7/stm32_ethernet.c +++ b/arch/arm/src/stm32f7/stm32_ethernet.c @@ -549,7 +549,7 @@ */ #define ETH_DMAINT_NORMAL \ - (ETH_DMAINT_TI | ETH_DMAINT_TBUI |ETH_DMAINT_RI | ETH_DMAINT_ERI) + (ETH_DMAINT_TI | ETH_DMAINT_TBUI | ETH_DMAINT_RI | ETH_DMAINT_ERI) #define ETH_DMAINT_ABNORMAL \ (ETH_DMAINT_TPSI | ETH_DMAINT_TJTI | ETH_DMAINT_ROI | ETH_DMAINT_TUI | \ @@ -815,10 +815,11 @@ static uint32_t stm32_getreg(uint32_t addr) { if (count == 0xffffffff || ++count > 3) { - if (count == 4) - { - lldbg("...\n"); - } + if (count == 4) + { + lldbg("...\n"); + } + return val; } } @@ -827,20 +828,20 @@ static uint32_t stm32_getreg(uint32_t addr) else { - /* Did we print "..." for the previous value? */ + /* Did we print "..." for the previous value? */ - if (count > 3) - { - /* Yes.. then show how many times the value repeated */ + if (count > 3) + { + /* Yes.. then show how many times the value repeated */ - lldbg("[repeats %d more times]\n", count-3); - } + lldbg("[repeats %d more times]\n", count-3); + } - /* Save the new address, value, and count */ + /* Save the new address, value, and count */ - prevaddr = addr; - preval = val; - count = 1; + prevaddr = addr; + preval = val; + count = 1; } /* Show the register value read */ @@ -1624,7 +1625,7 @@ static int stm32_recvframe(struct stm32_ethmac_s *priv) /* Check if this is an intermediate segment in the frame */ - else if (((rxdesc->rdes0 & ETH_RDES0_LS) == 0)&& + else if (((rxdesc->rdes0 & ETH_RDES0_LS) == 0) && ((rxdesc->rdes0 & ETH_RDES0_FS) == 0)) { priv->segments++; @@ -1676,7 +1677,7 @@ static int stm32_recvframe(struct stm32_ethmac_s *priv) */ DEBUGASSERT(dev->d_buf == NULL); - dev->d_buf = (uint8_t*)rxcurr->rdes2; + dev->d_buf = (uint8_t *)rxcurr->rdes2; rxcurr->rdes2 = (uint32_t)buffer; /* Make sure that the modified RX descriptor is written to @@ -1703,7 +1704,7 @@ static int stm32_recvframe(struct stm32_ethmac_s *priv) nllvdbg("rxhead: %p d_buf: %p d_len: %d\n", priv->rxhead, dev->d_buf, dev->d_len); - /* Return success*/ + /* Return success */ return OK; } @@ -1726,7 +1727,7 @@ static int stm32_recvframe(struct stm32_ethmac_s *priv) arch_invalidate_dcache((uintptr_t)rxdesc, (uintptr_t)rxdesc + sizeof(struct eth_rxdesc_s)); - } + } /* We get here after all of the descriptors have been scanned or when rxdesc points * to the first descriptor owned by the DMA. Remember where we left off. @@ -1845,7 +1846,7 @@ static void stm32_receive(struct stm32_ethmac_s *priv) */ if (priv->dev.d_len > 0) - { + { /* Update the Ethernet header with the correct MAC address */ #ifdef CONFIG_NET_IPv4 @@ -1962,7 +1963,7 @@ static void stm32_freeframe(struct stm32_ethmac_s *priv) { /* Yes.. Free the buffer */ - stm32_freebuffer(priv, (uint8_t*)txdesc->tdes2); + stm32_freebuffer(priv, (uint8_t *)txdesc->tdes2); } /* In any event, make sure that TDES2 is nullified. */ @@ -2819,7 +2820,7 @@ static int stm32_addmac(struct net_driver_s *dev, const uint8_t *mac) /* Add the MAC address to the hardware multicast hash table */ - crc = stm32_calcethcrc( mac, 6 ); + crc = stm32_calcethcrc(mac, 6); hashindex = (crc >> 26) & 0x3F; @@ -2876,7 +2877,7 @@ static int stm32_rmmac(struct net_driver_s *dev, const uint8_t *mac) /* Remove the MAC address to the hardware multicast hash table */ - crc = stm32_calcethcrc( mac, 6 ); + crc = stm32_calcethcrc(mac, 6); hashindex = (crc >> 26) & 0x3F; @@ -2896,7 +2897,7 @@ static int stm32_rmmac(struct net_driver_s *dev, const uint8_t *mac) /* If there is no address registered any more, delete multicast filtering */ - if (stm32_getreg(STM32_ETH_MACHTHR ) == 0 && + if (stm32_getreg(STM32_ETH_MACHTHR) == 0 && stm32_getreg(STM32_ETH_MACHTLR) == 0) { temp = stm32_getreg(STM32_ETH_MACFFR); @@ -4258,7 +4259,7 @@ int stm32_ethinitialize(int intf) #ifdef CONFIG_NETDEV_PHY_IOCTL priv->dev.d_ioctl = stm32_ioctl; /* Support PHY ioctl() calls */ #endif - priv->dev.d_private = (void*)g_stm32ethmac; /* Used to recover private state from dev */ + priv->dev.d_private = (void *)g_stm32ethmac; /* Used to recover private state from dev */ priv->intf = intf; /* Remember the interface number */ /* Create a watchdog for timing polling for and timing of transmissions */ diff --git a/arch/arm/src/stm32f7/stm32_irq.c b/arch/arm/src/stm32f7/stm32_irq.c index 5936073662..15a690068d 100644 --- a/arch/arm/src/stm32f7/stm32_irq.c +++ b/arch/arm/src/stm32f7/stm32_irq.c @@ -64,9 +64,9 @@ /* Get a 32-bit version of the default priority */ #define DEFPRIORITY32 \ - (NVIC_SYSH_PRIORITY_DEFAULT << 24 |\ - NVIC_SYSH_PRIORITY_DEFAULT << 16 |\ - NVIC_SYSH_PRIORITY_DEFAULT << 8 |\ + (NVIC_SYSH_PRIORITY_DEFAULT << 24 | \ + NVIC_SYSH_PRIORITY_DEFAULT << 16 | \ + NVIC_SYSH_PRIORITY_DEFAULT << 8 | \ NVIC_SYSH_PRIORITY_DEFAULT) /* Given the address of a NVIC ENABLE register, this is the offset to @@ -344,8 +344,8 @@ static int stm32_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit, else { - *regaddr = NVIC_SYSHCON; - if (irq == STM32_IRQ_MEMFAULT) + *regaddr = NVIC_SYSHCON; + if (irq == STM32_IRQ_MEMFAULT) { *bit = NVIC_SYSHCON_MEMFAULTENA; } diff --git a/arch/arm/src/stm32f7/stm32_lowputc.c b/arch/arm/src/stm32f7/stm32_lowputc.c index 286178096e..603f2be713 100644 --- a/arch/arm/src/stm32f7/stm32_lowputc.c +++ b/arch/arm/src/stm32f7/stm32_lowputc.c @@ -248,10 +248,10 @@ # endif # define USART_CR2_CLRBITS \ - (USART_CR2_ADDM7 | USART_CR2_LBDL | USART_CR2_LBDIE | USART_CR2_LBCL |\ - USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_CLKEN | USART_CR2_STOP_MASK |\ - USART_CR2_LINEN | USART_CR2_RXINV | USART_CR2_TXINV | USART_CR2_DATAINV |\ - USART_CR2_MSBFIRST | USART_CR2_ABREN | USART_CR2_ABRMOD_MASK |\ + (USART_CR2_ADDM7 | USART_CR2_LBDL | USART_CR2_LBDIE | USART_CR2_LBCL | \ + USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_CLKEN | USART_CR2_STOP_MASK | \ + USART_CR2_LINEN | USART_CR2_RXINV | USART_CR2_TXINV | USART_CR2_DATAINV | \ + USART_CR2_MSBFIRST | USART_CR2_ABREN | USART_CR2_ABRMOD_MASK | \ USART_CR2_RTOEN | USART_CR2_ADD8_MASK) # define USART_CR2_SETBITS USART_CR2_STOP2_VALUE @@ -259,10 +259,10 @@ /* CR3 settings */ # define USART_CR3_CLRBITS \ - (USART_CR3_EIE | USART_CR3_IREN | USART_CR3_IRLP | USART_CR3_HDSEL |\ - USART_CR3_NACK | USART_CR3_SCEN | USART_CR3_DMAR | USART_CR3_DMAT |\ - USART_CR3_RTSE | USART_CR3_CTSE | USART_CR3_CTSIE | USART_CR1_ONEBIT |\ - USART_CR1_OVRDIS | USART_CR1_DDRE | USART_CR1_DEM | USART_CR1_DEP |\ + (USART_CR3_EIE | USART_CR3_IREN | USART_CR3_IRLP | USART_CR3_HDSEL | \ + USART_CR3_NACK | USART_CR3_SCEN | USART_CR3_DMAR | USART_CR3_DMAT | \ + USART_CR3_RTSE | USART_CR3_CTSE | USART_CR3_CTSIE | USART_CR1_ONEBIT | \ + USART_CR1_OVRDIS | USART_CR1_DDRE | USART_CR1_DEM | USART_CR1_DEP | \ USART_CR1_SCARCNT_MASK) # define USART_CR3_SETBITS 0 @@ -432,7 +432,7 @@ void stm32_lowsetup(void) /* Enable Rx, Tx, and the USART */ - cr |= (USART_CR1_UE|USART_CR1_TE|USART_CR1_RE); + cr |= (USART_CR1_UE | USART_CR1_TE | USART_CR1_RE); putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET); #endif /* HAVE_CONSOLE && !CONFIG_SUPPRESS_UART_CONFIG */ diff --git a/arch/arm/src/stm32f7/stm32_procfs_dtcm.c b/arch/arm/src/stm32f7/stm32_procfs_dtcm.c index 12b1e91565..14bffc4e34 100644 --- a/arch/arm/src/stm32f7/stm32_procfs_dtcm.c +++ b/arch/arm/src/stm32f7/stm32_procfs_dtcm.c @@ -312,7 +312,7 @@ static int dtcm_stat(const char *relpath, struct stat *buf) return -ENOENT; } - buf->st_mode = S_IFREG|S_IROTH|S_IRGRP|S_IRUSR; + buf->st_mode = S_IFREG | S_IROTH | S_IRGRP | S_IRUSR; buf->st_size = 0; buf->st_blksize = 0; buf->st_blocks = 0; diff --git a/arch/arm/src/stm32f7/stm32_serial.c b/arch/arm/src/stm32f7/stm32_serial.c index 028e45cbe3..fdc31dbc3e 100644 --- a/arch/arm/src/stm32f7/stm32_serial.c +++ b/arch/arm/src/stm32f7/stm32_serial.c @@ -264,7 +264,7 @@ struct up_dev_s const unsigned int rxdma_channel; /* DMA channel assigned */ #endif - int (* const vector)(int irq, void *context); /* Interrupt handler */ + int (*const vector)(int irq, void *context); /* Interrupt handler */ /* RX DMA state */ @@ -1244,7 +1244,7 @@ static void up_set_format(struct uart_dev_s *dev) /* Configure hardware flow control */ regval = up_serialin(priv, STM32_USART_CR3_OFFSET); - regval &= ~(USART_CR3_CTSE|USART_CR3_RTSE); + regval &= ~(USART_CR3_CTSE | USART_CR3_RTSE); #if defined(CONFIG_SERIAL_IFLOWCONTROL) && !defined(CONFIG_STM32F7_FLOWCONTROL_BROKEN) if (priv->iflow && (priv->rts_gpio != 0)) @@ -1397,7 +1397,7 @@ static int up_setup(struct uart_dev_s *dev) config = (config & ~GPIO_MODE_MASK) | GPIO_OUTPUT; #endif stm32_configgpio(config); - } + } #endif #ifdef HAVE_RS485 @@ -1665,9 +1665,9 @@ static int up_attach(struct uart_dev_s *dev) ret = irq_attach(priv->irq, priv->vector); if (ret == OK) { - /* Enable the interrupt (RX and TX interrupts are still disabled - * in the USART - */ + /* Enable the interrupt (RX and TX interrupts are still disabled + * in the USART + */ up_enable_irq(priv->irq); } @@ -1768,17 +1768,17 @@ static int up_interrupt_common(struct up_dev_s *priv) if ((priv->sr & USART_ISR_RXNE) != 0 && (priv->ie & USART_CR1_RXNEIE) != 0) { - /* Received data ready... process incoming bytes. NOTE the check for - * RXNEIE: We cannot call uart_recvchards of RX interrupts are disabled. - */ + /* Received data ready... process incoming bytes. NOTE the check for + * RXNEIE: We cannot call uart_recvchards of RX interrupts are disabled. + */ - uart_recvchars(&priv->dev); - handled = true; + uart_recvchars(&priv->dev); + handled = true; } - /* We may still have to read from the DR register to clear any pending - * error conditions. - */ + /* We may still have to read from the DR register to clear any pending + * error conditions. + */ else if ((priv->sr & (USART_ISR_ORE | USART_ISR_NF | USART_ISR_FE)) != 0) { @@ -1794,10 +1794,10 @@ static int up_interrupt_common(struct up_dev_s *priv) if ((priv->sr & USART_ISR_TXE) != 0 && (priv->ie & USART_CR1_TXEIE) != 0) { - /* Transmit data register empty ... process outgoing bytes */ + /* Transmit data register empty ... process outgoing bytes */ - uart_xmitchars(&priv->dev); - handled = true; + uart_xmitchars(&priv->dev); + handled = true; } } @@ -1869,7 +1869,7 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg) #ifdef CONFIG_SERIAL_TERMIOS case TCGETS: { - struct termios *termiosp = (struct termios*)arg; + struct termios *termiosp = (struct termios *)arg; if (!termiosp) { @@ -1901,7 +1901,7 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg) case TCSETS: { - struct termios *termiosp = (struct termios*)arg; + struct termios *termiosp = (struct termios *)arg; if (!termiosp) { @@ -2122,7 +2122,7 @@ static bool up_rxavailable(struct uart_dev_s *dev) static bool up_rxflowcontrol(struct uart_dev_s *dev, unsigned int nbuffered, bool upper) { - struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; #if defined(CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS) && \ defined(CONFIG_STM32F7_FLOWCONTROL_BROKEN) diff --git a/arch/arm/src/stm32f7/stm32_start.c b/arch/arm/src/stm32f7/stm32_start.c index 5d9ecc9b09..b4f935a397 100644 --- a/arch/arm/src/stm32f7/stm32_start.c +++ b/arch/arm/src/stm32f7/stm32_start.c @@ -105,7 +105,7 @@ static inline void stm32_fpuconfig(void); #endif #ifdef CONFIG_STACK_COLORATION static void go_os_start(void *pv, unsigned int nbytes) - __attribute__ ((naked,no_instrument_function,noreturn)); + __attribute__ ((naked, no_instrument_function, noreturn)); #endif /**************************************************************************** @@ -400,6 +400,6 @@ void __start(void) /* Shouldn't get here */ - for (;;); + for (; ; ); #endif } diff --git a/arch/arm/src/stm32f7/stm32_userspace.c b/arch/arm/src/stm32f7/stm32_userspace.c index 03217a9019..8185db83b5 100644 --- a/arch/arm/src/stm32f7/stm32_userspace.c +++ b/arch/arm/src/stm32f7/stm32_userspace.c @@ -71,8 +71,8 @@ void stm32_userspace(void) DEBUGASSERT(USERSPACE->us_bssstart != 0 && USERSPACE->us_bssend != 0 && USERSPACE->us_bssstart <= USERSPACE->us_bssend); - dest = (uint8_t*)USERSPACE->us_bssstart; - end = (uint8_t*)USERSPACE->us_bssend; + dest = (uint8_t *)USERSPACE->us_bssstart; + end = (uint8_t *)USERSPACE->us_bssend; while (dest != end) { @@ -85,9 +85,9 @@ void stm32_userspace(void) USERSPACE->us_datastart != 0 && USERSPACE->us_dataend != 0 && USERSPACE->us_datastart <= USERSPACE->us_dataend); - src = (uint8_t*)USERSPACE->us_datasource; - dest = (uint8_t*)USERSPACE->us_datastart; - end = (uint8_t*)USERSPACE->us_dataend; + src = (uint8_t *)USERSPACE->us_datasource; + dest = (uint8_t *)USERSPACE->us_datastart; + end = (uint8_t *)USERSPACE->us_dataend; while (dest != end) { diff --git a/arch/arm/src/stm32f7/stm32f74xx75xx_rcc.c b/arch/arm/src/stm32f7/stm32f74xx75xx_rcc.c index dd7dbcbb93..1db43d2551 100644 --- a/arch/arm/src/stm32f7/stm32f74xx75xx_rcc.c +++ b/arch/arm/src/stm32f7/stm32f74xx75xx_rcc.c @@ -100,7 +100,7 @@ static inline void rcc_reset(void) /* Reset HSION, HSEON, CSSON and PLLON bits */ regval = getreg32(STM32_RCC_CR); - regval &= ~(RCC_CR_HSION|RCC_CR_HSEON|RCC_CR_CSSON|RCC_CR_PLLON); + regval &= ~(RCC_CR_HSION | RCC_CR_HSEON | RCC_CR_CSSON | RCC_CR_PLLON); putreg32(regval, STM32_RCC_CR); /* Reset PLLCFGR register to reset default */ @@ -136,7 +136,7 @@ static inline void rcc_enableahb1(void) regval = getreg32(STM32_RCC_AHB1ENR); - /* Enable GPIOA, GPIOB, .... GPIOI*/ + /* Enable GPIOA, GPIOB, .... GPIOI */ #if STM32F7_NGPIO > 0 regval |= (RCC_AHB1ENR_GPIOAEN @@ -757,10 +757,10 @@ static void stm32_stdclockconfig(void) /* Set the PLL dividers and multipliers to configure the main PLL */ #ifdef STM32_BOARD_USEHSI - regval = (STM32_PLLCFG_PLLM | STM32_PLLCFG_PLLN |STM32_PLLCFG_PLLP | + regval = (STM32_PLLCFG_PLLM | STM32_PLLCFG_PLLN | STM32_PLLCFG_PLLP | RCC_PLLCFG_PLLSRC_HSI | STM32_PLLCFG_PLLQ); #else /* if STM32_BOARD_USEHSE */ - regval = (STM32_PLLCFG_PLLM | STM32_PLLCFG_PLLN |STM32_PLLCFG_PLLP | + regval = (STM32_PLLCFG_PLLM | STM32_PLLCFG_PLLN | STM32_PLLCFG_PLLP | RCC_PLLCFG_PLLSRC_HSE | STM32_PLLCFG_PLLQ); #endif putreg32(regval, STM32_RCC_PLLCFG);