From 8811eee0f4e63f2e66188783076f54d548a6aa72 Mon Sep 17 00:00:00 2001 From: Ville Juven Date: Thu, 17 Oct 2024 10:09:30 +0300 Subject: [PATCH] riscv_cpustart.c: Fix reading of interrupt status Let's read the interrupt status correctly, by checking for the interrupt source bit instead of assuming no other status bit is set. --- arch/risc-v/src/common/riscv_cpustart.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/risc-v/src/common/riscv_cpustart.c b/arch/risc-v/src/common/riscv_cpustart.c index d7763c01d9..1b96d4ff4e 100644 --- a/arch/risc-v/src/common/riscv_cpustart.c +++ b/arch/risc-v/src/common/riscv_cpustart.c @@ -81,7 +81,7 @@ void riscv_cpu_boot(int cpu) { asm("WFI"); } - while (READ_CSR(CSR_IP) != IP_SIP); + while (!(READ_CSR(CSR_IP) & IP_SIP)); #ifdef CONFIG_RISCV_PERCPU_SCRATCH /* Initialize the per CPU areas */