arch/avr: save RAMPZ register into thread context
On chips that have it, RAMPZ is part of the thread context and needs to be saved as well.
This commit is contained in:
Kerogit
Xiang Xiao
parent
958b18f25e
commit
88a66f18e6
10 changed files with 96 additions and 10 deletions
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@ -81,7 +81,13 @@
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# define NR_IRQS 34
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# define AVR_PC_SIZE 16
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# define XCPTCONTEXT_REGS 37 /* Size of the register state save array (in bytes) */
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# define XCPTCONTEXT_REGS 38 /* Size of the register state save array (in bytes) */
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# if defined(CONFIG_AVR_HAS_RAMPZ)
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# define AVR_HAS_RAMPZ
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# else
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# error CONFIG_AVR_HAS_RAMPZ is supposed to be set for this chip
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# endif
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#elif defined(CONFIG_ARCH_CHIP_ATMEGA1284P)
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@ -122,7 +128,13 @@
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# define NR_IRQS 34
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# define AVR_PC_SIZE 16
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# define XCPTCONTEXT_REGS 37 /* Size of the register state save array (in bytes) */
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# define XCPTCONTEXT_REGS 38 /* Size of the register state save array (in bytes) */
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# if defined(CONFIG_AVR_HAS_RAMPZ)
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# define AVR_HAS_RAMPZ
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# else
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# error CONFIG_AVR_HAS_RAMPZ is supposed to be set for this chip
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# endif
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#elif defined(CONFIG_ARCH_CHIP_ATMEGA2560)
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@ -185,7 +197,13 @@
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# define NR_IRQS 58
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# define AVR_PC_SIZE 24
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# define XCPTCONTEXT_REGS 38 /* Size of the register state save array (in bytes) */
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# define XCPTCONTEXT_REGS 39 /* Size of the register state save array (in bytes) */
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# if defined(CONFIG_AVR_HAS_RAMPZ)
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# define AVR_HAS_RAMPZ
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# else
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# error CONFIG_AVR_HAS_RAMPZ is supposed to be set for this chip
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# endif
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#else
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#error "Unrecognized chip"
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@ -72,16 +72,24 @@
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#define REG_R2 29
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#define REG_R1 30 /* r1 - the "zero" register */
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#define REG_R0 31 /* r0 */
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#define REG_SREG 32 /* Status register */
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#define REG_R25 33 /* r24-r25 */
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#define REG_R24 34
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#if defined(AVR_HAS_RAMPZ)
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# define REG_RAMPZ 32 /* RAMPZ register for ELPM instruction */
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# define REG_OFFSET_RAMPZ 1
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#else
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# define REG_OFFSET_RAMPZ 0 /* MCU does not have RAMPZ */
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#endif
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#define REG_SREG (32 + REG_OFFSET_RAMPZ) /* Status register */
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#define REG_R25 (33 + REG_OFFSET_RAMPZ) /* r24-r25 */
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#define REG_R24 (34 + REG_OFFSET_RAMPZ)
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/* The program counter is automatically pushed when the interrupt occurs */
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#define REG_PC0 35 /* PC */
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#define REG_PC1 36
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#define REG_PC0 (35 + REG_OFFSET_RAMPZ) /* PC */
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#define REG_PC1 (36 + REG_OFFSET_RAMPZ)
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#if AVR_PC_SIZE > 16
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# define REG_PC2 37
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# define REG_PC2 (37 + REG_OFFSET_RAMPZ)
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#endif
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#define XCPTCONTEXT_SIZE XCPTCONTEXT_REGS
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@ -107,6 +115,9 @@ struct xcptcontext
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uint8_t saved_pc0;
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#if defined(REG_PC2)
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uint8_t saved_pc2;
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#endif
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#if defined(REG_RAMPZ)
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uint8_t saved_rampz;
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#endif
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uint8_t saved_sreg;
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@ -12,16 +12,19 @@ choice
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config ARCH_CHIP_ATMEGA128
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bool "ATMega128"
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select AVR_HAS_RAMPZ
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---help---
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Atmel ATMega128 8-bit AVR.
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config ARCH_CHIP_ATMEGA1284P
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bool "ATMega1284P"
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select AVR_HAS_RAMPZ
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---help---
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Atmel ATMega1284P 8-bit AVR.
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config ARCH_CHIP_ATMEGA2560
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bool "ATMega2560"
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select AVR_HAS_RAMPZ
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---help---
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Atmel ATMega2560 8-bit AVR.
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@ -48,7 +48,9 @@
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* - If RAMPZ is not present, support for LPMX is assumed
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*/
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#define HAVE_RAMPZ 1
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#ifdef AVR_HAS_RAMPZ
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# define HAVE_RAMPZ 1
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#endif
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/****************************************************************************
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* External Symbols
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@ -73,4 +73,8 @@ config AVR_HAS_MEMX_PTR
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of RAM needed to hold this static data.
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endmenu # Atmel AVR Toolchain options
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config AVR_HAS_RAMPZ
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bool
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endif # ARCH_FAMILY_AVR
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@ -107,6 +107,12 @@ void up_initial_state(struct tcb_s *tcb)
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xcp->regs[REG_PC2] = (uint8_t)((uintptr_t)tcb->start & 0xff);
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#endif
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/* Set RAMPZ to zero, the default value (if the MCU has one) */
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#if defined(REG_RAMPZ)
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xcp->regs[REG_RAMPZ] = 0;
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#endif
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/* Enable or disable interrupts, based on user configuration */
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#ifdef CONFIG_SUPPRESS_INTERRUPTS
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@ -91,5 +91,10 @@ void up_dump_register(void *dumpregs)
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regs[REG_PC2], regs[REG_SPH],
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regs[REG_SPL], regs[REG_SREG]);
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#endif
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#if defined(REG_RAMPZ)
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_alert("RAMPZ: %02x\n",
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regs[REG_RAMPZ]);
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#endif
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}
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}
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@ -126,6 +126,9 @@ void up_schedule_sigaction(struct tcb_s *tcb)
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tcb->xcp.saved_pc1 = up_current_regs()[REG_PC1];
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#if defined(REG_PC2)
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tcb->xcp.saved_pc2 = up_current_regs()[REG_PC2];
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#endif
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#if defined(REG_RAMPZ)
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tcb->xcp.saved_rampz = up_current_regs()[REG_RAMPZ];
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#endif
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tcb->xcp.saved_sreg = up_current_regs()[REG_SREG];
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@ -168,6 +171,9 @@ void up_schedule_sigaction(struct tcb_s *tcb)
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tcb->xcp.saved_pc1 = tcb->xcp.regs[REG_PC1];
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#if defined(REG_PC2)
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tcb->xcp.saved_pc2 = tcb->xcp.regs[REG_PC2];
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#endif
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#if defined(REG_RAMPZ)
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tcb->xcp.saved_rampz = tcb->xcp.regs[REG_RAMPZ];
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#endif
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tcb->xcp.saved_sreg = tcb->xcp.regs[REG_SREG];
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@ -103,6 +103,9 @@ void avr_sigdeliver(void)
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regs[REG_PC1] = rtcb->xcp.saved_pc1;
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#if defined(REG_PC2)
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regs[REG_PC2] = rtcb->xcp.saved_pc2;
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#endif
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#if defined(REG_RAMPZ)
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regs[REG_RAMPZ] = rtcb->xcp.saved_rampz;
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#endif
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regs[REG_SREG] = rtcb->xcp.saved_sreg;
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@ -148,6 +148,13 @@
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ori r25, (1 << SREG_I) /* Interrupts re-enabled on restore */
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push r25
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/* Save RAMPZ if the MCU has it */
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#ifdef AVR_HAS_RAMPZ
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in r25, _SFR_IO_ADDR(RAMPZ)
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push r25
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#endif
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/* Save R0 -- the scratch register and the zero register
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* (which may not be zero). R1 must be zero for our purposes
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*/
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@ -296,6 +303,13 @@
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pop r1
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pop r0
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/* Restore RAMPZ if the MCU has it */
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#ifdef AVR_HAS_RAMPZ
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pop r24
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out _SFR_IO_ADDR(RAMPZ), r24
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#endif
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/* Restore the status register (probably enabling interrupts) */
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pop r24 /* Restore the status register */
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@ -392,6 +406,13 @@
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adiw r26, 1
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#ifdef AVR_HAS_RAMPZ
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/* Save RAMPZ if the MCU has it */
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in r0, _SFR_IO_ADDR(RAMPZ)
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st X+, r0
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#endif
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/* Save the status register
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* (probably not necessary since interrupts are disabled)
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*/
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@ -544,6 +565,13 @@
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ld r0, x+
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#ifdef AVR_HAS_RAMPZ
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/* Restore RAMPZ if the MCU has it */
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ld r24, X+
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out _SFR_IO_ADDR(RAMPZ), r24
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#endif
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/* The following control flow split is required to eliminate non-atomic
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* interrupt_enable - return sequence.
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*
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