xtensa/esp32[|s3]: re-enable cache during exception handler
This commit implements re-enabling the cache before the exception handler for ESP32-S3 and removes unnecessary checks (cache should always be re-enabled during an exception handler and disabled again after processed, except for ESP32-S3 that implements no recoverable exceptions). Signed-off-by: Tiago Medicci Serrano <tiago.medicci@espressif.com>
This commit is contained in:
Tiago Medicci Serrano
Alan C. Assis
parent
7ccd6e9041
commit
8956fc440f
5 changed files with 84 additions and 39 deletions
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@ -207,15 +207,6 @@ config ESP32_RUN_IRAM
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This loads all of NuttX inside IRAM. Used to test somewhat small
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images that can fit entirely in IRAM.
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config ESP32_EXCEPTION_ENABLE_CACHE
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bool
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default y
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depends on ESP32_SPIFLASH
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---help---
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When an exception triggers, the panic function reenables the SPI Flash
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cache to allow functions that are located in SPI Flash to run.
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Disable this option to save IRAM space.
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menu "ESP32 Peripheral Selection"
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source "arch/xtensa/src/common/espressif/Kconfig"
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@ -324,16 +324,19 @@ static void advance_pc(uint32_t *regs, int diff)
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uint32_t *xtensa_user(int exccause, uint32_t *regs)
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{
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#ifdef CONFIG_ESP32_EXCEPTION_ENABLE_CACHE
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#ifdef CONFIG_ESP32_SPIFLASH
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bool is_cache_reenabled = false;
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if (!spi_flash_cache_enabled())
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{
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is_cache_reenabled = true;
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spi_enable_cache(0);
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#ifdef CONFIG_SMP
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# ifdef CONFIG_SMP
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spi_enable_cache(1);
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#endif
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_err("\nERROR: Cache was disabled and re-enabled\n");
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# endif
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}
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#endif
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#endif /* CONFIG_ESP32_SPIFLASH */
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#ifdef CONFIG_ARCH_USE_TEXT_HEAP
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/* Emulate byte access for module text.
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@ -375,7 +378,7 @@ uint32_t *xtensa_user(int exccause, uint32_t *regs)
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store_uint8(((uint8_t *)regs[REG_A0 + s]) + imm8,
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regs[REG_A0 + t]);
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advance_pc(regs, 3);
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return regs;
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goto return_with_regs;
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}
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else if (decode_s16i(pc, &imm8, &s, &t))
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{
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@ -391,7 +394,7 @@ uint32_t *xtensa_user(int exccause, uint32_t *regs)
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store_uint8((uint8_t *)va, regs[REG_A0 + t]);
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store_uint8((uint8_t *)va + 1, regs[REG_A0 + t] >> 8);
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advance_pc(regs, 3);
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return regs;
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goto return_with_regs;
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}
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else if (decode_l8ui(pc, &imm8, &s, &t))
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{
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@ -406,7 +409,7 @@ uint32_t *xtensa_user(int exccause, uint32_t *regs)
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regs[REG_A0 + t] = load_uint8(((uint8_t *)regs[REG_A0 + s]) +
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imm8);
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advance_pc(regs, 3);
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return regs;
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goto return_with_regs;
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}
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else if (decode_l16si(pc, &imm8, &s, &t))
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{
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@ -423,7 +426,7 @@ uint32_t *xtensa_user(int exccause, uint32_t *regs)
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uint8_t hi = load_uint8((uint8_t *)va + 1);
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regs[REG_A0 + t] = (int16_t)((hi << 8) | lo);
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advance_pc(regs, 3);
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return regs;
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goto return_with_regs;
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}
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else if (decode_l16ui(pc, &imm8, &s, &t))
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{
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@ -440,11 +443,29 @@ uint32_t *xtensa_user(int exccause, uint32_t *regs)
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uint8_t hi = load_uint8((uint8_t *)va + 1);
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regs[REG_A0 + t] = (hi << 8) | lo;
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advance_pc(regs, 3);
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return regs;
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goto return_with_regs;
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}
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return_with_regs:
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# ifdef CONFIG_ESP32_SPIFLASH
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if (is_cache_reenabled)
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{
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spi_disable_cache(0);
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# ifdef CONFIG_SMP
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spi_disable_cache(1);
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# endif
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}
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# endif /* CONFIG_ESP32_SPIFLASH */
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return regs;
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}
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#else
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# ifdef CONFIG_ESP32_SPIFLASH
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UNUSED(is_cache_reenabled);
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# endif
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#endif
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/* xtensa_user_panic never returns. */
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xtensa_user_panic(exccause, regs);
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@ -251,26 +251,6 @@ static void spiflash_suspend_cache(void)
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g_spi_flash_cache_suspended = true;
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}
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/****************************************************************************
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* Name: spiflash_resume_cache
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*
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* Description:
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* Resume CPU cache.
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*
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****************************************************************************/
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static void spiflash_resume_cache(void)
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{
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int cpu = this_cpu();
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#ifdef CONFIG_SMP
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int other_cpu = cpu ? 0 : 1;
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#endif
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spi_flash_restore_cache();
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g_spi_flash_cache_suspended = false;
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}
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/****************************************************************************
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* Name: spiflash_start
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*
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@ -926,6 +906,32 @@ static int spiflash_init_spi_flash_op_block_task(int cpu)
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* Public Functions
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****************************************************************************/
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/****************************************************************************
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* Name: spiflash_resume_cache
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*
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* Description:
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* Resume CPU cache.
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*
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* Input Parameters:
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* None
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*
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* Returned Value:
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* None
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*
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****************************************************************************/
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void spiflash_resume_cache(void)
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{
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int cpu = this_cpu();
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#ifdef CONFIG_SMP
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int other_cpu = cpu ? 0 : 1;
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#endif
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spi_flash_restore_cache();
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g_spi_flash_cache_suspended = false;
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}
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/****************************************************************************
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* Name: esp32s3_mmap
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*
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@ -75,6 +75,22 @@ struct spiflash_map_req_s
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* Public Function Prototypes
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****************************************************************************/
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/****************************************************************************
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* Name: spiflash_resume_cache
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*
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* Description:
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* Resume CPU cache.
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*
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* Input Parameters:
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* None
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*
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* Returned Value:
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* None
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*
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****************************************************************************/
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void spiflash_resume_cache(void);
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/****************************************************************************
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* Name: esp32s3_mmap
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*
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@ -27,6 +27,10 @@
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#include <stdint.h>
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#include "xtensa.h"
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#ifdef CONFIG_ESP32S3_SPIFLASH
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#include "rom/esp32s3_spiflash.h"
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#include "esp32s3_spiflash.h"
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#endif
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/****************************************************************************
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* Public Data
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@ -61,6 +65,13 @@
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uint32_t *xtensa_user(int exccause, uint32_t *regs)
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{
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#ifdef CONFIG_ESP32S3_SPIFLASH
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if (!spi_flash_cache_enabled())
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{
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spiflash_resume_cache();
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}
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#endif /* CONFIG_ESP32S3_SPIFLASH */
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/* xtensa_user_panic never returns. */
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xtensa_user_panic(exccause, regs);
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