From 8b86fae8d335549670f6045e6cba3c9b2d57875a Mon Sep 17 00:00:00 2001 From: Yang Chung-Fan Date: Tue, 5 May 2020 16:14:00 +0900 Subject: [PATCH] arch: x86_64: Check only XSAVE and rename __eanble_sse3 to __enable_sse_avx --- arch/x86_64/include/intel64/arch.h | 2 +- arch/x86_64/src/intel64/Kconfig | 7 ++++--- arch/x86_64/src/intel64/intel64_check_capability.c | 7 +++---- arch/x86_64/src/intel64/intel64_head.S | 10 +++++----- 4 files changed, 13 insertions(+), 13 deletions(-) diff --git a/arch/x86_64/include/intel64/arch.h b/arch/x86_64/include/intel64/arch.h index 65e204ddbe..0a23f548d1 100644 --- a/arch/x86_64/include/intel64/arch.h +++ b/arch/x86_64/include/intel64/arch.h @@ -580,7 +580,7 @@ extern volatile struct gdt_entry_s *gdt64; int up_map_region(void *base, int size, int flags); void x86_64_check_and_enable_capability(void); -extern void __enable_sse3(void); +extern void __enable_sse_avx(void); extern void __revoke_low_memory(void); extern void __enable_pcid(void); diff --git a/arch/x86_64/src/intel64/Kconfig b/arch/x86_64/src/intel64/Kconfig index 6fc42c2167..d2a99631e9 100644 --- a/arch/x86_64/src/intel64/Kconfig +++ b/arch/x86_64/src/intel64/Kconfig @@ -34,11 +34,12 @@ config ARCH_INTEL64_APIC_FREQ_KHZ endif -config ARCH_INTEL64_HAVE_SSE3 - bool "SSE3 support" +config ARCH_INTEL64_HAVE_XSAVE + bool "XSAVE support" default y ---help--- - Select to enable the use of SSE3 and FPU functions of x86_64 + Select to enable the use of XSAVE and FPU/SSE/AVX functions + of x86_64 config ARCH_INTEL64_HAVE_PCID bool "PCID support" diff --git a/arch/x86_64/src/intel64/intel64_check_capability.c b/arch/x86_64/src/intel64/intel64_check_capability.c index 958839e642..641ab0da0a 100644 --- a/arch/x86_64/src/intel64/intel64_check_capability.c +++ b/arch/x86_64/src/intel64/intel64_check_capability.c @@ -67,8 +67,7 @@ void x86_64_check_and_enable_capability(void) require |= X86_64_CPUID_01_TSCDEA; #endif -#ifdef CONFIG_ARCH_INTEL64_HAVE_SSE3 - require |= X86_64_CPUID_01_SSE3; +#ifdef CONFIG_ARCH_INTEL64_HAVE_XSAVE require |= X86_64_CPUID_01_XSAVE; #endif @@ -90,8 +89,8 @@ void x86_64_check_and_enable_capability(void) goto err; } -#ifdef CONFIG_ARCH_INTEL64_HAVE_SSE3 - __enable_sse3(); +#ifdef CONFIG_ARCH_INTEL64_HAVE_XSAVE + __enable_sse_avx(); #endif #ifdef CONFIG_ARCH_INTEL64_HAVE_PCID diff --git a/arch/x86_64/src/intel64/intel64_head.S b/arch/x86_64/src/intel64/intel64_head.S index d5642456d0..b8d19fbeda 100644 --- a/arch/x86_64/src/intel64/intel64_head.S +++ b/arch/x86_64/src/intel64/intel64_head.S @@ -63,7 +63,7 @@ ****************************************************************************/ .global __pmode_entry /* The 32bit protected mode entry */ .global __nxstart - .global __enable_sse3 + .global __enable_sse_avx .global __enable_pcid .global __revoke_low_memory .global nx_start /* nx_start is defined elsewhere */ @@ -302,16 +302,16 @@ npd_loop: .size __revoke_low_memory, . - __revoke_low_memory /**************************************************************************** - * Name: __enable_sse3 + * Name: __enable_sse_avx * * Description: * Do low-level initialization SSE related processor setting * ****************************************************************************/ - .type __enable_sse3, @function + .type __enable_sse_avx, @function -__enable_sse3: +__enable_sse_avx: // Enable SSE mov %cr0, %rax mov $(X86_CR0_EM), %rbx @@ -330,7 +330,7 @@ __enable_sse3: ret - .size __enable_sse3, . - __enable_sse3 + .size __enable_sse_avx, . - __enable_sse_avx /****************************************************************************