Merged in raiden00/nuttx_lora/lora (pull request #869)
Port STM32F7 I2C to STM32F3 and STM32F0L0 arch/arm/src/stm32: port I2C IPv2 driver from F7 (only F3 chips) arch/arm/src/stm32f0l0: port I2C IPv2 driver from F7 configs/b-l072z-lrwan1: nxlines_oled example (ssd1306) configs/b-l072z-lrwan1: support for the I2C tool configs/nucleo-f303ze: nxlines_oled example (ssd1306) arch/arm/src/stm32h7/chip.h: cosmetics arch/arm/src/stm32/chip/stm32_tim.h: cosmetics Approved-by: Gregory Nutt <gnutt@nuttx.org>
This commit is contained in:
raiden00pl
Gregory Nutt
parent
6c79512b36
commit
8ce1f1a67b
24 changed files with 5315 additions and 3020 deletions
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@ -1325,6 +1325,7 @@ config STM32_STM32L15XX
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select STM32_HAVE_IP_TIMERS_V1
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select STM32_HAVE_IP_ADC_V1
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select STM32_HAVE_IP_DMA_V1
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select STM32_HAVE_IP_I2C_V1
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config STM32_ENERGYLITE
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bool
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@ -1343,6 +1344,7 @@ config STM32_STM32F10XX
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select STM32_HAVE_IP_TIMERS_V1
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select STM32_HAVE_IP_ADC_V1_BASIC
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select STM32_HAVE_IP_DMA_V1
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select STM32_HAVE_IP_I2C_V1
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config STM32_VALUELINE
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bool
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@ -1457,6 +1459,7 @@ config STM32_STM32F20XX
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select STM32_HAVE_IP_TIMERS_V1
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select STM32_HAVE_IP_ADC_V1
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select STM32_HAVE_IP_DMA_V2
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select STM32_HAVE_IP_I2C_V1
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config STM32_STM32F205
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bool
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@ -1541,6 +1544,7 @@ config STM32_STM32F30XX
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select STM32_HAVE_IP_TIMERS_V2
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select STM32_HAVE_IP_ADC_V2
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select STM32_HAVE_IP_DMA_V1
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select STM32_HAVE_IP_I2C_V2
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config STM32_STM32F302
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bool
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@ -1587,6 +1591,7 @@ config STM32_STM32F33XX
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select STM32_HAVE_IP_TIMERS_V2
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select STM32_HAVE_IP_ADC_V2
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select STM32_HAVE_IP_DMA_V1
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select STM32_HAVE_IP_I2C_V2
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config STM32_STM32F37XX
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bool
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@ -1614,6 +1619,7 @@ config STM32_STM32F37XX
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select STM32_HAVE_IP_TIMERS_V1
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select STM32_HAVE_IP_ADC_V1_BASIC
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select STM32_HAVE_IP_DMA_V1
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select STM32_HAVE_IP_I2C_V2
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config STM32_STM32F4XXX
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bool
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@ -1625,6 +1631,7 @@ config STM32_STM32F4XXX
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select STM32_HAVE_IP_TIMERS_V1
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select STM32_HAVE_IP_ADC_V1
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select STM32_HAVE_IP_DMA_V2
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select STM32_HAVE_IP_I2C_V1
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config STM32_STM32F401xBC
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bool
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@ -2214,6 +2221,14 @@ config STM32_HAVE_OPAMP4
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# These are STM32 peripherals IP blocks
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config STM32_HAVE_IP_I2C_V1
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bool
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default n
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config STM32_HAVE_IP_I2C_V2
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bool
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default n
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config STM32_HAVE_IP_DMA_V1
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bool
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default n
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@ -119,17 +119,17 @@ ifeq ($(CONFIG_STM32_CCM_PROCFS),y)
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CHIP_CSRCS += stm32_procfs_ccm.c
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endif
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ifeq ($(CONFIG_STM32_HAVE_IP_I2C_V1),y)
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ifeq ($(CONFIG_STM32_I2C_ALT),y)
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CHIP_CSRCS += stm32_i2c_alt.c
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else ifeq ($(CONFIG_STM32_STM32F30XX),y)
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CHIP_CSRCS += stm32f30xxx_i2c.c
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else ifeq ($(CONFIG_STM32_STM32F37XX),y)
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CHIP_CSRCS += stm32f30xxx_i2c.c
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else ifeq ($(CONFIG_STM32_STM32F4XXX),y)
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CHIP_CSRCS += stm32f40xxx_i2c.c
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else
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CHIP_CSRCS += stm32_i2c.c
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endif
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else ifeq ($(CONFIG_STM32_HAVE_IP_I2C_V2),y)
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CHIP_CSRCS += stm32_i2c_v2.c
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endif
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ifeq ($(CONFIG_USBDEV),y)
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ifeq ($(CONFIG_STM32_USB),y)
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@ -50,104 +50,14 @@
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#include <arch/stm32/irq.h>
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/* Include the chip pin configuration file */
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/* STM32L EnergyLite Line ***********************************************************/
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#if defined(CONFIG_STM32_ENERGYLITE)
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/* STM32L15xx family */
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# if defined(CONFIG_STM32_STM32L15XX)
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# include "chip/stm32l15xxx_pinmap.h"
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# else
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# error "Unsupported EnergyLite chip"
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# endif
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/* STM32 F1 Family ******************************************************************/
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#elif defined(CONFIG_STM32_STM32F10XX)
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/* STM32F100 Value Line */
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# if defined(CONFIG_STM32_VALUELINE)
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# include "chip/stm32f100_pinmap.h"
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/* STM32 F102 USB Access Medium Density Family */
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# elif defined(CONFIG_ARCH_CHIP_STM32F102CB)
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# include "chip/stm32f102_pinmap.h"
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/* STM32 F103 Low / Medium Density Family */
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# elif defined(CONFIG_ARCH_CHIP_STM32F103C4) || \
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defined(CONFIG_ARCH_CHIP_STM32F103C8) || \
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defined(CONFIG_ARCH_CHIP_STM32F103CB)
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# include "chip/stm32f103c_pinmap.h"
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/* STM32 F103 High Density Family */
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/* STM32F103RC, STM32F103RD, and STM32F103RE are all provided in 64 pin packages and differ
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* only in the available FLASH and SRAM.
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*/
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# elif defined(CONFIG_ARCH_CHIP_STM32F103RB) || \
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defined(CONFIG_ARCH_CHIP_STM32F103RC) || \
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defined(CONFIG_ARCH_CHIP_STM32F103RD) || \
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defined(CONFIG_ARCH_CHIP_STM32F103RE) || \
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defined(CONFIG_ARCH_CHIP_STM32F103RG)
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# include "chip/stm32f103r_pinmap.h"
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/* STM32F103VC, STM32F103VD, and STM32F103VE are all provided in 100 pin packages and differ
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* only in the available FLASH and SRAM.
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*/
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# elif defined(CONFIG_ARCH_CHIP_STM32F103VC) || defined(CONFIG_ARCH_CHIP_STM32F103VE)
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# include "chip/stm32f103v_pinmap.h"
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/* STM32F103ZC, STM32F103ZD, and STM32F103ZE are all provided in 144 pin packages and differ
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* only in the available FLASH and SRAM.
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*/
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# elif defined(CONFIG_ARCH_CHIP_STM32F103ZE)
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# include "chip/stm32f103z_pinmap.h"
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/* STM32 F105/F107 Connectivity Line */
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# elif defined(CONFIG_ARCH_CHIP_STM32F105VB)
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# include "chip/stm32f105v_pinmap.h"
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# elif defined(CONFIG_ARCH_CHIP_STM32F105RB)
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# include "chip/stm32f105r_pinmap.h"
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# elif defined(CONFIG_ARCH_CHIP_STM32F107VC)
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# include "chip/stm32f107v_pinmap.h"
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# else
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# error "Unsupported STM32F10XXX chip"
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# endif
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/* STM32 F2 Family ******************************************************************/
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#elif defined(CONFIG_STM32_STM32F20XX)
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# include "chip/stm32f20xxx_pinmap.h"
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/* STM32 F3 Family ******************************************************************/
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#elif defined(CONFIG_STM32_STM32F30XX)
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# include "chip/stm32f30xxx_pinmap.h"
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#elif defined(CONFIG_STM32_STM32F33XX)
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# include "chip/stm32f33xxx_pinmap.h"
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#elif defined(CONFIG_STM32_STM32F37XX)
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# include "chip/stm32f37xxx_pinmap.h"
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/* STM32 F4 Family ******************************************************************/
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#elif defined(CONFIG_STM32_STM32F4XXX)
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# include "chip/stm32f40xxx_pinmap.h"
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#else
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# error "No pinmap file for this STM32 chip"
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#endif
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/* Include the chip memory map. */
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/* Include the chip memory map */
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#include "chip/stm32_memorymap.h"
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/* Include the chip pinmap */
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#include "chip/stm32_pinmap.h"
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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@ -36,177 +36,17 @@
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#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32_I2C_H
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#define __ARCH_ARM_SRC_STM32_CHIP_STM32_I2C_H
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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/* There are 2 main types of I2C IP cores among STM32 chips:
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* 1. STM32 ADC IPv1 - F1, F2, F4 and L1
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* 2. STM32 ADC IPv2 - G0, L0, F0, F3, F7, H7 and L4
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*/
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/* Register Offsets *****************************************************************/
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#define STM32_I2C_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */
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#define STM32_I2C_CR2_OFFSET 0x0004 /* Control register 2 (16-bit) */
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#define STM32_I2C_OAR1_OFFSET 0x0008 /* Own address register 1 (16-bit) */
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#define STM32_I2C_OAR2_OFFSET 0x000c /* Own address register 2 (16-bit) */
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#define STM32_I2C_DR_OFFSET 0x0010 /* Data register (16-bit) */
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#define STM32_I2C_SR1_OFFSET 0x0014 /* Status register 1 (16-bit) */
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#define STM32_I2C_SR2_OFFSET 0x0018 /* Status register 2 (16-bit) */
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#define STM32_I2C_CCR_OFFSET 0x001c /* Clock control register (16-bit) */
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#define STM32_I2C_TRISE_OFFSET 0x0020 /* TRISE Register (16-bit) */
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#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \
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defined(CONFIG_STM32_STM32F446)
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# define STM32_I2C_FLTR_OFFSET 0x0024 /* FLTR Register (16-bit) */
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#endif
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/* Register Addresses ***************************************************************/
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#if STM32_NI2C > 0
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# define STM32_I2C1_CR1 (STM32_I2C1_BASE+STM32_I2C_CR1_OFFSET)
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# define STM32_I2C1_CR2 (STM32_I2C1_BASE+STM32_I2C_CR2_OFFSET)
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# define STM32_I2C1_OAR1 (STM32_I2C1_BASE+STM32_I2C_OAR1_OFFSET)
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# define STM32_I2C1_OAR2 (STM32_I2C1_BASE+STM32_I2C_OAR2_OFFSET)
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# define STM32_I2C1_DR (STM32_I2C1_BASE+STM32_I2C_DR_OFFSET)
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# define STM32_I2C1_SR1 (STM32_I2C1_BASE+STM32_I2C_SR1_OFFSET)
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# define STM32_I2C1_SR2 (STM32_I2C1_BASE+STM32_I2C_SR2_OFFSET)
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# define STM32_I2C1_CCR (STM32_I2C1_BASE+STM32_I2C_CCR_OFFSET)
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# define STM32_I2C1_TRISE (STM32_I2C1_BASE+STM32_I2C_TRISE_OFFSET)
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# ifdef STM32_I2C_FLTR_OFFSET
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# define STM32_I2C1_FLTR (STM32_I2C1_BASE+STM32_I2C_FLTR_OFFSET)
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# endif
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#endif
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#if STM32_NI2C > 1
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# define STM32_I2C2_CR1 (STM32_I2C2_BASE+STM32_I2C_CR1_OFFSET)
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# define STM32_I2C2_CR2 (STM32_I2C2_BASE+STM32_I2C_CR2_OFFSET)
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# define STM32_I2C2_OAR1 (STM32_I2C2_BASE+STM32_I2C_OAR1_OFFSET)
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# define STM32_I2C2_OAR2 (STM32_I2C2_BASE+STM32_I2C_OAR2_OFFSET)
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# define STM32_I2C2_DR (STM32_I2C2_BASE+STM32_I2C_DR_OFFSET)
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# define STM32_I2C2_SR1 (STM32_I2C2_BASE+STM32_I2C_SR1_OFFSET)
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# define STM32_I2C2_SR2 (STM32_I2C2_BASE+STM32_I2C_SR2_OFFSET)
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# define STM32_I2C2_CCR (STM32_I2C2_BASE+STM32_I2C_CCR_OFFSET)
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# define STM32_I2C2_TRISE (STM32_I2C2_BASE+STM32_I2C_TRISE_OFFSET)
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# ifdef STM32_I2C_FLTR_OFFSET
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# define STM32_I2C2_FLTR (STM32_I2C2_BASE+STM32_I2C_FLTR_OFFSET)
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# endif
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#endif
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#if STM32_NI2C > 2
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# define STM32_I2C3_CR1 (STM32_I2C3_BASE+STM32_I2C_CR1_OFFSET)
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# define STM32_I2C3_CR2 (STM32_I2C3_BASE+STM32_I2C_CR2_OFFSET)
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# define STM32_I2C3_OAR1 (STM32_I2C3_BASE+STM32_I2C_OAR1_OFFSET)
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# define STM32_I2C3_OAR2 (STM32_I2C3_BASE+STM32_I2C_OAR2_OFFSET)
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# define STM32_I2C3_DR (STM32_I2C3_BASE+STM32_I2C_DR_OFFSET)
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# define STM32_I2C3_SR1 (STM32_I2C3_BASE+STM32_I2C_SR1_OFFSET)
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# define STM32_I2C3_SR2 (STM32_I2C3_BASE+STM32_I2C_SR2_OFFSET)
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# define STM32_I2C3_CCR (STM32_I2C3_BASE+STM32_I2C_CCR_OFFSET)
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# define STM32_I2C3_TRISE (STM32_I2C3_BASE+STM32_I2C_TRISE_OFFSET)
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# ifdef STM32_I2C_FLTR_OFFSET
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# define STM32_I2C3_FLTR (STM32_I2C3_BASE+STM32_I2C_FLTR_OFFSET)
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# endif
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#endif
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/* Register Bitfield Definitions ****************************************************/
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/* Control register 1 */
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#define I2C_CR1_PE (1 << 0) /* Bit 0: Peripheral Enable */
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#define I2C_CR1_SMBUS (1 << 1) /* Bit 1: SMBus Mode */
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#define I2C_CR1_SMBTYPE (1 << 3) /* Bit 3: SMBus Type */
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#define I2C_CR1_ENARP (1 << 4) /* Bit 4: ARP Enable */
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#define I2C_CR1_ENPEC (1 << 5) /* Bit 5: PEC Enable */
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#define I2C_CR1_ENGC (1 << 6) /* Bit 6: General Call Enable */
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#define I2C_CR1_NOSTRETCH (1 << 7) /* Bit 7: Clock Stretching Disable (Slave mode) */
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#define I2C_CR1_START (1 << 8) /* Bit 8: Start Generation */
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#define I2C_CR1_STOP (1 << 9) /* Bit 9: Stop Generation */
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#define I2C_CR1_ACK (1 << 10) /* Bit 10: Acknowledge Enable */
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#define I2C_CR1_POS (1 << 11) /* Bit 11: Acknowledge/PEC Position (for data reception) */
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#define I2C_CR1_PEC (1 << 12) /* Bit 12: Packet Error Checking */
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#define I2C_CR1_ALERT (1 << 13) /* Bit 13: SMBus Alert */
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#define I2C_CR1_SWRST (1 << 15) /* Bit 15: Software Reset */
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/* Control register 2 */
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#define I2C_CR2_FREQ_SHIFT (0) /* Bits 5-0: Peripheral Clock Frequency */
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#define I2C_CR2_FREQ_MASK (0x3f << I2C_CR2_FREQ_SHIFT)
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#define I2C_CR2_ITERREN (1 << 8) /* Bit 8: Error Interrupt Enable */
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#define I2C_CR2_ITEVFEN (1 << 9) /* Bit 9: Event Interrupt Enable */
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#define I2C_CR2_ITBUFEN (1 << 10) /* Bit 10: Buffer Interrupt Enable */
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#define I2C_CR2_DMAEN (1 << 11) /* Bit 11: DMA Requests Enable */
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#define I2C_CR2_LAST (1 << 12) /* Bit 12: DMA Last Transfer */
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#define I2C_CR2_ALLINTS (I2C_CR2_ITERREN|I2C_CR2_ITEVFEN|I2C_CR2_ITBUFEN)
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/* Own address register 1 */
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#define I2C_OAR1_ADD0 (1 << 0) /* Bit 0: Interface Address */
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#define I2C_OAR1_ADD8_SHIFT (1) /* Bits 7-1: Interface Address */
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#define I2C_OAR1_ADD8_MASK (0x007f << I2C_OAR1_ADD8_SHIFT)
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#define I2C_OAR1_ADD10_SHIFT (1) /* Bits 9-1: Interface Address (10-bit addressing mode)*/
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#define I2C_OAR1_ADD10_MASK (0x01ff << I2C_OAR1_ADD10_SHIFT)
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#define I2C_OAR1_ONE (1 << 14) /* Bit 14: Must be configured and kept at 1 */
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#define I2C_OAR1_ADDMODE (1 << 15) /* Bit 15: Addressing Mode (Slave mode) */
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/* Own address register 2 */
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#define I2C_OAR2_ENDUAL (1 << 0) /* Bit 0: Dual addressing mode enable */
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#define I2C_OAR2_ADD2_SHIFT (1) /* Bits 7-1: Interface address */
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#define I2C_OAR2_ADD2_MASK (0x7f << I2C_OAR2_ADD2_SHIFT)
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/* Data register */
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#define I2C_DR_SHIFT (0) /* Bits 7-0: 8-bit Data Register */
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#define I2C_DR_MASK (0x00ff << I2C_DR_SHIFT)
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/* Status register 1 */
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#define I2C_SR1_SB (1 << 0) /* Bit 0: Start Bit (Master mode) */
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#define I2C_SR1_ADDR (1 << 1) /* Bit 1: Address sent (master mode)/matched (slave mode) */
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#define I2C_SR1_BTF (1 << 2) /* Bit 2: Byte Transfer Finished */
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#define I2C_SR1_ADD10 (1 << 3) /* Bit 3: 10-bit header sent (Master mode) */
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#define I2C_SR1_STOPF (1 << 4) /* Bit 4: Stop detection (Slave mode) */
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/* Bit 5: Reserved */
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#define I2C_SR1_RXNE (1 << 6) /* Bit 6: Data Register not Empty (receivers) */
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#define I2C_SR1_TXE (1 << 7) /* Bit 7: Data Register Empty (transmitters) */
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#define I2C_SR1_BERR (1 << 8) /* Bit 8: Bus Error */
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#define I2C_SR1_ARLO (1 << 9) /* Bit 9: Arbitration Lost (master mode) */
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#define I2C_SR1_AF (1 << 10) /* Bit 10: Acknowledge Failure */
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#define I2C_SR1_OVR (1 << 11) /* Bit 11: Overrun/Underrun */
|
||||
#define I2C_SR1_PECERR (1 << 12) /* Bit 12: PEC Error in reception */
|
||||
/* Bit 13: Reserved */
|
||||
#define I2C_SR1_TIMEOUT (1 << 14) /* Bit 14: Timeout or Tlow Error */
|
||||
#define I2C_SR1_SMBALERT (1 << 15) /* Bit 15: SMBus Alert */
|
||||
|
||||
#define I2C_SR1_ERRORMASK (I2C_SR1_BERR|I2C_SR1_ARLO|I2C_SR1_AF|I2C_SR1_OVR|\
|
||||
I2C_SR1_PECERR|I2C_SR1_TIMEOUT|I2C_SR1_SMBALERT)
|
||||
|
||||
/* Status register 2 */
|
||||
|
||||
#define I2C_SR2_MSL (1 << 0) /* Bit 0: Master/Slave */
|
||||
#define I2C_SR2_BUSY (1 << 1) /* Bit 1: Bus Busy */
|
||||
#define I2C_SR2_TRA (1 << 2) /* Bit 2: Transmitter/Receiver */
|
||||
#define I2C_SR2_GENCALL (1 << 4) /* Bit 4: General Call Address (Slave mode) */
|
||||
#define I2C_SR2_SMBDEFAULT (1 << 5) /* Bit 5: SMBus Device Default Address (Slave mode) */
|
||||
#define I2C_SR2_SMBHOST (1 << 6) /* Bit 6: SMBus Host Header (Slave mode) */
|
||||
#define I2C_SR2_DUALF (1 << 7) /* Bit 7: Dual Flag (Slave mode) */
|
||||
#define I2C_SR2_PEC_SHIFT (8) /* Bits 15-8: Packet Error Checking Register */
|
||||
#define I2C_SR2_PEC_MASK (0xff << I2C_SR2_PEC_SHIFT)
|
||||
|
||||
/* Clock control register */
|
||||
|
||||
#define I2C_CCR_CCR_SHIFT (0) /* Bits 11-0: Clock Control Register in Fast/Standard mode (Master mode) */
|
||||
#define I2C_CCR_CCR_MASK (0x0fff << I2C_CCR_CCR_SHIFT)
|
||||
#define I2C_CCR_DUTY (1 << 14) /* Bit 14: Fast Mode Duty Cycle */
|
||||
#define I2C_CCR_FS (1 << 15) /* Bit 15: Fast Mode Selection */
|
||||
|
||||
/* TRISE Register */
|
||||
|
||||
#define I2C_TRISE_SHIFT (0) /* Bits 5-0: Maximum Rise Time in Fast/Standard mode (Master mode) */
|
||||
#define I2C_TRISE_MASK (0x3f << I2C_TRISE_SHIFT)
|
||||
|
||||
/* FLTR Register */
|
||||
|
||||
#ifdef STM32_I2C_FLTR_OFFSET
|
||||
# define I2C_FLTR_ANOFF (1 << 4) /* Bit 4: Analog noise filter disable */
|
||||
# define I2C_FLTR_DNF_SHIFT 0 /* Bits 0-3: Digital noise filter */
|
||||
# define I2C_FLTR_DNF_MASK (0xf << I2C_FLTR_DNF_SHIFT)
|
||||
#if defined(CONFIG_STM32_HAVE_IP_I2C_V1)
|
||||
# include "stm32_i2c_v1.h"
|
||||
#elif defined(CONFIG_STM32_HAVE_IP_I2C_V2)
|
||||
# include "stm32_i2c_v2.h"
|
||||
#else
|
||||
# error STM32 I2C IP version not specified
|
||||
#endif
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32_I2C_H */
|
||||
|
|
|
|||
214
arch/arm/src/stm32/chip/stm32_i2c_v1.h
Normal file
214
arch/arm/src/stm32/chip/stm32_i2c_v1.h
Normal file
|
|
@ -0,0 +1,214 @@
|
|||
/************************************************************************************
|
||||
* arch/arm/src/stm32/chip/stm32_i2c_v1.h
|
||||
*
|
||||
* Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32_I2C_V1_H
|
||||
#define __ARCH_ARM_SRC_STM32_CHIP_STM32_I2C_V1_H
|
||||
|
||||
/* This file provide definitions for the STM32 I2C IP core 1 (F1, F2, F4 and L1) */
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* Register Offsets *****************************************************************/
|
||||
|
||||
#define STM32_I2C_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */
|
||||
#define STM32_I2C_CR2_OFFSET 0x0004 /* Control register 2 (16-bit) */
|
||||
#define STM32_I2C_OAR1_OFFSET 0x0008 /* Own address register 1 (16-bit) */
|
||||
#define STM32_I2C_OAR2_OFFSET 0x000c /* Own address register 2 (16-bit) */
|
||||
#define STM32_I2C_DR_OFFSET 0x0010 /* Data register (16-bit) */
|
||||
#define STM32_I2C_SR1_OFFSET 0x0014 /* Status register 1 (16-bit) */
|
||||
#define STM32_I2C_SR2_OFFSET 0x0018 /* Status register 2 (16-bit) */
|
||||
#define STM32_I2C_CCR_OFFSET 0x001c /* Clock control register (16-bit) */
|
||||
#define STM32_I2C_TRISE_OFFSET 0x0020 /* TRISE Register (16-bit) */
|
||||
#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \
|
||||
defined(CONFIG_STM32_STM32F446)
|
||||
# define STM32_I2C_FLTR_OFFSET 0x0024 /* FLTR Register (16-bit) */
|
||||
#endif
|
||||
|
||||
/* Register Addresses ***************************************************************/
|
||||
|
||||
#if STM32_NI2C > 0
|
||||
# define STM32_I2C1_CR1 (STM32_I2C1_BASE+STM32_I2C_CR1_OFFSET)
|
||||
# define STM32_I2C1_CR2 (STM32_I2C1_BASE+STM32_I2C_CR2_OFFSET)
|
||||
# define STM32_I2C1_OAR1 (STM32_I2C1_BASE+STM32_I2C_OAR1_OFFSET)
|
||||
# define STM32_I2C1_OAR2 (STM32_I2C1_BASE+STM32_I2C_OAR2_OFFSET)
|
||||
# define STM32_I2C1_DR (STM32_I2C1_BASE+STM32_I2C_DR_OFFSET)
|
||||
# define STM32_I2C1_SR1 (STM32_I2C1_BASE+STM32_I2C_SR1_OFFSET)
|
||||
# define STM32_I2C1_SR2 (STM32_I2C1_BASE+STM32_I2C_SR2_OFFSET)
|
||||
# define STM32_I2C1_CCR (STM32_I2C1_BASE+STM32_I2C_CCR_OFFSET)
|
||||
# define STM32_I2C1_TRISE (STM32_I2C1_BASE+STM32_I2C_TRISE_OFFSET)
|
||||
# ifdef STM32_I2C_FLTR_OFFSET
|
||||
# define STM32_I2C1_FLTR (STM32_I2C1_BASE+STM32_I2C_FLTR_OFFSET)
|
||||
# endif
|
||||
#endif
|
||||
|
||||
#if STM32_NI2C > 1
|
||||
# define STM32_I2C2_CR1 (STM32_I2C2_BASE+STM32_I2C_CR1_OFFSET)
|
||||
# define STM32_I2C2_CR2 (STM32_I2C2_BASE+STM32_I2C_CR2_OFFSET)
|
||||
# define STM32_I2C2_OAR1 (STM32_I2C2_BASE+STM32_I2C_OAR1_OFFSET)
|
||||
# define STM32_I2C2_OAR2 (STM32_I2C2_BASE+STM32_I2C_OAR2_OFFSET)
|
||||
# define STM32_I2C2_DR (STM32_I2C2_BASE+STM32_I2C_DR_OFFSET)
|
||||
# define STM32_I2C2_SR1 (STM32_I2C2_BASE+STM32_I2C_SR1_OFFSET)
|
||||
# define STM32_I2C2_SR2 (STM32_I2C2_BASE+STM32_I2C_SR2_OFFSET)
|
||||
# define STM32_I2C2_CCR (STM32_I2C2_BASE+STM32_I2C_CCR_OFFSET)
|
||||
# define STM32_I2C2_TRISE (STM32_I2C2_BASE+STM32_I2C_TRISE_OFFSET)
|
||||
# ifdef STM32_I2C_FLTR_OFFSET
|
||||
# define STM32_I2C2_FLTR (STM32_I2C2_BASE+STM32_I2C_FLTR_OFFSET)
|
||||
# endif
|
||||
#endif
|
||||
|
||||
#if STM32_NI2C > 2
|
||||
# define STM32_I2C3_CR1 (STM32_I2C3_BASE+STM32_I2C_CR1_OFFSET)
|
||||
# define STM32_I2C3_CR2 (STM32_I2C3_BASE+STM32_I2C_CR2_OFFSET)
|
||||
# define STM32_I2C3_OAR1 (STM32_I2C3_BASE+STM32_I2C_OAR1_OFFSET)
|
||||
# define STM32_I2C3_OAR2 (STM32_I2C3_BASE+STM32_I2C_OAR2_OFFSET)
|
||||
# define STM32_I2C3_DR (STM32_I2C3_BASE+STM32_I2C_DR_OFFSET)
|
||||
# define STM32_I2C3_SR1 (STM32_I2C3_BASE+STM32_I2C_SR1_OFFSET)
|
||||
# define STM32_I2C3_SR2 (STM32_I2C3_BASE+STM32_I2C_SR2_OFFSET)
|
||||
# define STM32_I2C3_CCR (STM32_I2C3_BASE+STM32_I2C_CCR_OFFSET)
|
||||
# define STM32_I2C3_TRISE (STM32_I2C3_BASE+STM32_I2C_TRISE_OFFSET)
|
||||
# ifdef STM32_I2C_FLTR_OFFSET
|
||||
# define STM32_I2C3_FLTR (STM32_I2C3_BASE+STM32_I2C_FLTR_OFFSET)
|
||||
# endif
|
||||
#endif
|
||||
|
||||
/* Register Bitfield Definitions ****************************************************/
|
||||
|
||||
/* Control register 1 */
|
||||
|
||||
#define I2C_CR1_PE (1 << 0) /* Bit 0: Peripheral Enable */
|
||||
#define I2C_CR1_SMBUS (1 << 1) /* Bit 1: SMBus Mode */
|
||||
#define I2C_CR1_SMBTYPE (1 << 3) /* Bit 3: SMBus Type */
|
||||
#define I2C_CR1_ENARP (1 << 4) /* Bit 4: ARP Enable */
|
||||
#define I2C_CR1_ENPEC (1 << 5) /* Bit 5: PEC Enable */
|
||||
#define I2C_CR1_ENGC (1 << 6) /* Bit 6: General Call Enable */
|
||||
#define I2C_CR1_NOSTRETCH (1 << 7) /* Bit 7: Clock Stretching Disable (Slave mode) */
|
||||
#define I2C_CR1_START (1 << 8) /* Bit 8: Start Generation */
|
||||
#define I2C_CR1_STOP (1 << 9) /* Bit 9: Stop Generation */
|
||||
#define I2C_CR1_ACK (1 << 10) /* Bit 10: Acknowledge Enable */
|
||||
#define I2C_CR1_POS (1 << 11) /* Bit 11: Acknowledge/PEC Position (for data reception) */
|
||||
#define I2C_CR1_PEC (1 << 12) /* Bit 12: Packet Error Checking */
|
||||
#define I2C_CR1_ALERT (1 << 13) /* Bit 13: SMBus Alert */
|
||||
#define I2C_CR1_SWRST (1 << 15) /* Bit 15: Software Reset */
|
||||
|
||||
/* Control register 2 */
|
||||
|
||||
#define I2C_CR2_FREQ_SHIFT (0) /* Bits 5-0: Peripheral Clock Frequency */
|
||||
#define I2C_CR2_FREQ_MASK (0x3f << I2C_CR2_FREQ_SHIFT)
|
||||
#define I2C_CR2_ITERREN (1 << 8) /* Bit 8: Error Interrupt Enable */
|
||||
#define I2C_CR2_ITEVFEN (1 << 9) /* Bit 9: Event Interrupt Enable */
|
||||
#define I2C_CR2_ITBUFEN (1 << 10) /* Bit 10: Buffer Interrupt Enable */
|
||||
#define I2C_CR2_DMAEN (1 << 11) /* Bit 11: DMA Requests Enable */
|
||||
#define I2C_CR2_LAST (1 << 12) /* Bit 12: DMA Last Transfer */
|
||||
|
||||
#define I2C_CR2_ALLINTS (I2C_CR2_ITERREN|I2C_CR2_ITEVFEN|I2C_CR2_ITBUFEN)
|
||||
|
||||
/* Own address register 1 */
|
||||
|
||||
#define I2C_OAR1_ADD0 (1 << 0) /* Bit 0: Interface Address */
|
||||
#define I2C_OAR1_ADD8_SHIFT (1) /* Bits 7-1: Interface Address */
|
||||
#define I2C_OAR1_ADD8_MASK (0x007f << I2C_OAR1_ADD8_SHIFT)
|
||||
#define I2C_OAR1_ADD10_SHIFT (1) /* Bits 9-1: Interface Address (10-bit addressing mode)*/
|
||||
#define I2C_OAR1_ADD10_MASK (0x01ff << I2C_OAR1_ADD10_SHIFT)
|
||||
#define I2C_OAR1_ONE (1 << 14) /* Bit 14: Must be configured and kept at 1 */
|
||||
#define I2C_OAR1_ADDMODE (1 << 15) /* Bit 15: Addressing Mode (Slave mode) */
|
||||
|
||||
/* Own address register 2 */
|
||||
|
||||
#define I2C_OAR2_ENDUAL (1 << 0) /* Bit 0: Dual addressing mode enable */
|
||||
#define I2C_OAR2_ADD2_SHIFT (1) /* Bits 7-1: Interface address */
|
||||
#define I2C_OAR2_ADD2_MASK (0x7f << I2C_OAR2_ADD2_SHIFT)
|
||||
|
||||
/* Data register */
|
||||
|
||||
#define I2C_DR_SHIFT (0) /* Bits 7-0: 8-bit Data Register */
|
||||
#define I2C_DR_MASK (0x00ff << I2C_DR_SHIFT)
|
||||
|
||||
/* Status register 1 */
|
||||
|
||||
#define I2C_SR1_SB (1 << 0) /* Bit 0: Start Bit (Master mode) */
|
||||
#define I2C_SR1_ADDR (1 << 1) /* Bit 1: Address sent (master mode)/matched (slave mode) */
|
||||
#define I2C_SR1_BTF (1 << 2) /* Bit 2: Byte Transfer Finished */
|
||||
#define I2C_SR1_ADD10 (1 << 3) /* Bit 3: 10-bit header sent (Master mode) */
|
||||
#define I2C_SR1_STOPF (1 << 4) /* Bit 4: Stop detection (Slave mode) */
|
||||
/* Bit 5: Reserved */
|
||||
#define I2C_SR1_RXNE (1 << 6) /* Bit 6: Data Register not Empty (receivers) */
|
||||
#define I2C_SR1_TXE (1 << 7) /* Bit 7: Data Register Empty (transmitters) */
|
||||
#define I2C_SR1_BERR (1 << 8) /* Bit 8: Bus Error */
|
||||
#define I2C_SR1_ARLO (1 << 9) /* Bit 9: Arbitration Lost (master mode) */
|
||||
#define I2C_SR1_AF (1 << 10) /* Bit 10: Acknowledge Failure */
|
||||
#define I2C_SR1_OVR (1 << 11) /* Bit 11: Overrun/Underrun */
|
||||
#define I2C_SR1_PECERR (1 << 12) /* Bit 12: PEC Error in reception */
|
||||
/* Bit 13: Reserved */
|
||||
#define I2C_SR1_TIMEOUT (1 << 14) /* Bit 14: Timeout or Tlow Error */
|
||||
#define I2C_SR1_SMBALERT (1 << 15) /* Bit 15: SMBus Alert */
|
||||
|
||||
#define I2C_SR1_ERRORMASK (I2C_SR1_BERR|I2C_SR1_ARLO|I2C_SR1_AF|I2C_SR1_OVR|\
|
||||
I2C_SR1_PECERR|I2C_SR1_TIMEOUT|I2C_SR1_SMBALERT)
|
||||
|
||||
/* Status register 2 */
|
||||
|
||||
#define I2C_SR2_MSL (1 << 0) /* Bit 0: Master/Slave */
|
||||
#define I2C_SR2_BUSY (1 << 1) /* Bit 1: Bus Busy */
|
||||
#define I2C_SR2_TRA (1 << 2) /* Bit 2: Transmitter/Receiver */
|
||||
#define I2C_SR2_GENCALL (1 << 4) /* Bit 4: General Call Address (Slave mode) */
|
||||
#define I2C_SR2_SMBDEFAULT (1 << 5) /* Bit 5: SMBus Device Default Address (Slave mode) */
|
||||
#define I2C_SR2_SMBHOST (1 << 6) /* Bit 6: SMBus Host Header (Slave mode) */
|
||||
#define I2C_SR2_DUALF (1 << 7) /* Bit 7: Dual Flag (Slave mode) */
|
||||
#define I2C_SR2_PEC_SHIFT (8) /* Bits 15-8: Packet Error Checking Register */
|
||||
#define I2C_SR2_PEC_MASK (0xff << I2C_SR2_PEC_SHIFT)
|
||||
|
||||
/* Clock control register */
|
||||
|
||||
#define I2C_CCR_CCR_SHIFT (0) /* Bits 11-0: Clock Control Register in Fast/Standard mode (Master mode) */
|
||||
#define I2C_CCR_CCR_MASK (0x0fff << I2C_CCR_CCR_SHIFT)
|
||||
#define I2C_CCR_DUTY (1 << 14) /* Bit 14: Fast Mode Duty Cycle */
|
||||
#define I2C_CCR_FS (1 << 15) /* Bit 15: Fast Mode Selection */
|
||||
|
||||
/* TRISE Register */
|
||||
|
||||
#define I2C_TRISE_SHIFT (0) /* Bits 5-0: Maximum Rise Time in Fast/Standard mode (Master mode) */
|
||||
#define I2C_TRISE_MASK (0x3f << I2C_TRISE_SHIFT)
|
||||
|
||||
/* FLTR Register */
|
||||
|
||||
#ifdef STM32_I2C_FLTR_OFFSET
|
||||
# define I2C_FLTR_ANOFF (1 << 4) /* Bit 4: Analog noise filter disable */
|
||||
# define I2C_FLTR_DNF_SHIFT 0 /* Bits 0-3: Digital noise filter */
|
||||
# define I2C_FLTR_DNF_MASK (0xf << I2C_FLTR_DNF_SHIFT)
|
||||
#endif
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32_I2C_V1_H */
|
||||
|
|
@ -1,5 +1,5 @@
|
|||
/************************************************************************************
|
||||
* arch/arm/src/stm32/chip/stm32f30xxx_i2c.h
|
||||
* arch/arm/src/stm32/chip/stm32_i2c_v2.h
|
||||
*
|
||||
* Copyright (C) 2009, 2011, 2013 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
|
|
@ -33,11 +33,11 @@
|
|||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32F30XXX_I2C_H
|
||||
#define __ARCH_ARM_SRC_STM32_CHIP_STM32F30XXX_I2C_H
|
||||
#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32_I2C_V2_H
|
||||
#define __ARCH_ARM_SRC_STM32_CHIP_STM32_I2C_V2_H
|
||||
|
||||
/* This file provide definitions for the STM32 I2C IP core 2 (F0, F3, F7, H7, and
|
||||
* L4).
|
||||
/* This file provide definitions for the STM32 I2C IP core 2 (G0, L0, F0, F3, F7,
|
||||
* H7, and L4).
|
||||
*/
|
||||
|
||||
/************************************************************************************
|
||||
|
|
@ -250,5 +250,4 @@
|
|||
|
||||
#define I2C_TXDR_MASK (0xff)
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32F30XXX_I2C_H */
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32_I2C_V2_H */
|
||||
137
arch/arm/src/stm32/chip/stm32_pinmap.h
Normal file
137
arch/arm/src/stm32/chip/stm32_pinmap.h
Normal file
|
|
@ -0,0 +1,137 @@
|
|||
/************************************************************************************
|
||||
* arch/arm/src/stm32/chip/stm32_pinmap.h
|
||||
*
|
||||
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32_PINMAP_H
|
||||
#define __ARCH_ARM_SRC_STM32_CHIP_STM32_PINMAP_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
/* STM32L EnergyLite Line ***********************************************************/
|
||||
|
||||
#if defined(CONFIG_STM32_ENERGYLITE)
|
||||
|
||||
/* STM32L15xx family */
|
||||
|
||||
# if defined(CONFIG_STM32_STM32L15XX)
|
||||
# include "chip/stm32l15xxx_pinmap.h"
|
||||
# else
|
||||
# error "Unsupported EnergyLite chip"
|
||||
# endif
|
||||
|
||||
/* STM32 F1 Family ******************************************************************/
|
||||
|
||||
#elif defined(CONFIG_STM32_STM32F10XX)
|
||||
|
||||
/* STM32F100 Value Line */
|
||||
|
||||
# if defined(CONFIG_STM32_VALUELINE)
|
||||
# include "chip/stm32f100_pinmap.h"
|
||||
|
||||
/* STM32 F102 USB Access Medium Density Family */
|
||||
# elif defined(CONFIG_ARCH_CHIP_STM32F102CB)
|
||||
# include "chip/stm32f102_pinmap.h"
|
||||
|
||||
/* STM32 F103 Low / Medium Density Family */
|
||||
# elif defined(CONFIG_ARCH_CHIP_STM32F103C4) || \
|
||||
defined(CONFIG_ARCH_CHIP_STM32F103C8) || \
|
||||
defined(CONFIG_ARCH_CHIP_STM32F103CB)
|
||||
# include "chip/stm32f103c_pinmap.h"
|
||||
|
||||
/* STM32 F103 High Density Family */
|
||||
/* STM32F103RC, STM32F103RD, and STM32F103RE are all provided in 64 pin packages and differ
|
||||
* only in the available FLASH and SRAM.
|
||||
*/
|
||||
|
||||
# elif defined(CONFIG_ARCH_CHIP_STM32F103RB) || \
|
||||
defined(CONFIG_ARCH_CHIP_STM32F103RC) || \
|
||||
defined(CONFIG_ARCH_CHIP_STM32F103RD) || \
|
||||
defined(CONFIG_ARCH_CHIP_STM32F103RE) || \
|
||||
defined(CONFIG_ARCH_CHIP_STM32F103RG)
|
||||
# include "chip/stm32f103r_pinmap.h"
|
||||
|
||||
/* STM32F103VC, STM32F103VD, and STM32F103VE are all provided in 100 pin packages and differ
|
||||
* only in the available FLASH and SRAM.
|
||||
*/
|
||||
|
||||
# elif defined(CONFIG_ARCH_CHIP_STM32F103VC) || defined(CONFIG_ARCH_CHIP_STM32F103VE)
|
||||
# include "chip/stm32f103v_pinmap.h"
|
||||
|
||||
/* STM32F103ZC, STM32F103ZD, and STM32F103ZE are all provided in 144 pin packages and differ
|
||||
* only in the available FLASH and SRAM.
|
||||
*/
|
||||
# elif defined(CONFIG_ARCH_CHIP_STM32F103ZE)
|
||||
# include "chip/stm32f103z_pinmap.h"
|
||||
|
||||
/* STM32 F105/F107 Connectivity Line */
|
||||
|
||||
# elif defined(CONFIG_ARCH_CHIP_STM32F105VB)
|
||||
# include "chip/stm32f105v_pinmap.h"
|
||||
|
||||
# elif defined(CONFIG_ARCH_CHIP_STM32F105RB)
|
||||
# include "chip/stm32f105r_pinmap.h"
|
||||
|
||||
# elif defined(CONFIG_ARCH_CHIP_STM32F107VC)
|
||||
# include "chip/stm32f107v_pinmap.h"
|
||||
# else
|
||||
# error "Unsupported STM32F10XXX chip"
|
||||
# endif
|
||||
|
||||
/* STM32 F2 Family ******************************************************************/
|
||||
|
||||
#elif defined(CONFIG_STM32_STM32F20XX)
|
||||
# include "chip/stm32f20xxx_pinmap.h"
|
||||
|
||||
/* STM32 F3 Family ******************************************************************/
|
||||
|
||||
#elif defined(CONFIG_STM32_STM32F30XX)
|
||||
# include "chip/stm32f30xxx_pinmap.h"
|
||||
#elif defined(CONFIG_STM32_STM32F33XX)
|
||||
# include "chip/stm32f33xxx_pinmap.h"
|
||||
#elif defined(CONFIG_STM32_STM32F37XX)
|
||||
# include "chip/stm32f37xxx_pinmap.h"
|
||||
|
||||
/* STM32 F4 Family ******************************************************************/
|
||||
|
||||
#elif defined(CONFIG_STM32_STM32F4XXX)
|
||||
# include "chip/stm32f40xxx_pinmap.h"
|
||||
#else
|
||||
# error "No pinmap file for this STM32 chip"
|
||||
#endif
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32_PINMAP_H */
|
||||
|
|
@ -47,17 +47,17 @@
|
|||
/* TIM version **************************************************************************************/
|
||||
|
||||
/* Chip has extended version of ADV Timers (F3/F7/H7/L4/L4+):
|
||||
- CCMR3, CCR5 and CCR6 registers
|
||||
- OC5 and OC6
|
||||
- 32-bit CCMR register
|
||||
- UIFREMAP bit in CR1 register
|
||||
- TRGO2 configuration in CR2 register
|
||||
- OCCS bit and 4-bit SMS in SMCR register
|
||||
|
||||
Chip has extended version of General Timers 2-5 (F3/F7/H7/L4/L4+):
|
||||
- UIFREMAP bit in CR1 register
|
||||
- 4-bit SMS in SMCR register
|
||||
*/
|
||||
* - CCMR3, CCR5 and CCR6 registers
|
||||
* - OC5 and OC6
|
||||
* - 32-bit CCMR register
|
||||
* - UIFREMAP bit in CR1 register
|
||||
* - TRGO2 configuration in CR2 register
|
||||
* - OCCS bit and 4-bit SMS in SMCR register
|
||||
*
|
||||
* Chip has extended version of General Timers 2-5 (F3/F7/H7/L4/L4+):
|
||||
* - UIFREMAP bit in CR1 register
|
||||
* - 4-bit SMS in SMCR register
|
||||
*/
|
||||
|
||||
#if defined(CONFIG_STM32_HAVE_IP_TIMERS_V2)
|
||||
# define HAVE_IP_TIMERS_V2
|
||||
|
|
|
|||
|
|
@ -44,12 +44,7 @@
|
|||
#include <nuttx/i2c/i2c_master.h>
|
||||
|
||||
#include "chip.h"
|
||||
#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX) || \
|
||||
defined(CONFIG_STM32_STM32F33XX)
|
||||
# include "chip/stm32f30xxx_i2c.h"
|
||||
#else
|
||||
# include "chip/stm32_i2c.h"
|
||||
#endif
|
||||
#include "chip/stm32_i2c.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
|
|
|
|||
2872
arch/arm/src/stm32/stm32_i2c_v2.c
Normal file
2872
arch/arm/src/stm32/stm32_i2c_v2.c
Normal file
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -51,6 +51,10 @@
|
|||
#include "chip/stm32_pinmap.h"
|
||||
#include "chip/stm32_memorymap.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* If the common ARMv7-M vector handling logic is used, then it expects the
|
||||
* following definition in this file that provides the number of supported external
|
||||
* interrupts which, for this architecture, is provided in the arch/stm32h7/chip.h
|
||||
|
|
@ -64,10 +68,6 @@
|
|||
#define ARMV7M_DCACHE_LINESIZE 32 /* 32 bytes (8 words) */
|
||||
#define ARMV7M_ICACHE_LINESIZE 32 /* 32 bytes (8 words) */
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
|
|
|
|||
|
|
@ -243,7 +243,7 @@
|
|||
/* I2C1 */
|
||||
|
||||
#define GPIO_I2C1_SDA GPIO_I2C1_SDA_2 /* PB9 */
|
||||
#define GPIO_I2C1_SCLK GPIO_I2C1_SCL_2 /* PB8 */
|
||||
#define GPIO_I2C1_SCL GPIO_I2C1_SCL_2 /* PB8 */
|
||||
|
||||
/* DMA channels *************************************************************/
|
||||
/* ADC */
|
||||
|
|
|
|||
73
configs/b-l072z-lrwan1/nxlines_oled/defconfig
Normal file
73
configs/b-l072z-lrwan1/nxlines_oled/defconfig
Normal file
|
|
@ -0,0 +1,73 @@
|
|||
#
|
||||
# This file is autogenerated: PLEASE DO NOT EDIT IT.
|
||||
#
|
||||
# You can use "make menuconfig" to make any modifications to the installed .config file.
|
||||
# You can then do "make savedefconfig" to generate a new defconfig file that includes your
|
||||
# modifications.
|
||||
#
|
||||
# CONFIG_EXAMPLES_NXLINES_DEFAULT_COLORS is not set
|
||||
# CONFIG_LIBC_LONG_LONG is not set
|
||||
# CONFIG_NSH_ARGCAT is not set
|
||||
# CONFIG_NX_DISABLE_1BPP is not set
|
||||
CONFIG_ARCH="arm"
|
||||
CONFIG_ARCH_BOARD="b-l072z-lrwan1"
|
||||
CONFIG_ARCH_BOARD_B_L072Z_LRWAN1=y
|
||||
CONFIG_ARCH_CHIP_STM32L072CZ=y
|
||||
CONFIG_ARCH_CHIP_STM32L072XX=y
|
||||
CONFIG_ARCH_CHIP_STM32L0=y
|
||||
CONFIG_ARCH_STACKDUMP=y
|
||||
CONFIG_BOARD_LOOPSPERMSEC=2796
|
||||
CONFIG_BUILTIN=y
|
||||
CONFIG_DEBUG_FULLOPT=y
|
||||
CONFIG_DISABLE_POLL=y
|
||||
CONFIG_EXAMPLES_NXLINES=y
|
||||
CONFIG_EXAMPLES_NXLINES_BORDERWIDTH=1
|
||||
CONFIG_EXAMPLES_NXLINES_BPP=1
|
||||
CONFIG_EXAMPLES_NXLINES_LINECOLOR=0xff
|
||||
CONFIG_EXAMPLES_NXLINES_LINEWIDTH=1
|
||||
CONFIG_EXPERIMENTAL=y
|
||||
CONFIG_INTELHEX_BINARY=y
|
||||
CONFIG_LCD=y
|
||||
CONFIG_LCD_MAXCONTRAST=255
|
||||
CONFIG_LCD_SH1106_OLED_132=y
|
||||
CONFIG_LCD_SSD1306_I2C=y
|
||||
CONFIG_MAX_TASKS=8
|
||||
CONFIG_MAX_WDOGPARMS=2
|
||||
CONFIG_MQ_MAXMSGSIZE=64
|
||||
CONFIG_NFILE_DESCRIPTORS=6
|
||||
CONFIG_NFILE_STREAMS=6
|
||||
CONFIG_NPTHREAD_KEYS=0
|
||||
CONFIG_NSH_ARCHINIT=y
|
||||
CONFIG_NSH_BUILTIN_APPS=y
|
||||
CONFIG_NSH_FILEIOSIZE=64
|
||||
CONFIG_NSH_LINELEN=64
|
||||
CONFIG_NSH_READLINE=y
|
||||
CONFIG_NUNGET_CHARS=0
|
||||
CONFIG_NX=y
|
||||
CONFIG_NXFONT_MONO5X8=y
|
||||
CONFIG_NX_BLOCKING=y
|
||||
CONFIG_PREALLOC_TIMERS=0
|
||||
CONFIG_PREALLOC_WDOGS=4
|
||||
CONFIG_PTHREAD_MUTEX_UNSAFE=y
|
||||
CONFIG_PTHREAD_STACK_DEFAULT=1536
|
||||
CONFIG_RAM_SIZE=20480
|
||||
CONFIG_RAM_START=0x20000000
|
||||
CONFIG_RAW_BINARY=y
|
||||
CONFIG_RR_INTERVAL=200
|
||||
CONFIG_SCHED_WAITPID=y
|
||||
CONFIG_SDCLONE_DISABLE=y
|
||||
CONFIG_START_DAY=19
|
||||
CONFIG_START_MONTH=5
|
||||
CONFIG_START_YEAR=2013
|
||||
CONFIG_STDIO_DISABLE_BUFFERING=y
|
||||
CONFIG_STM32F0L0_I2C1=y
|
||||
CONFIG_STM32F0L0_PWR=y
|
||||
CONFIG_STM32F0L0_USART2=y
|
||||
CONFIG_SYSTEM_NSH=y
|
||||
CONFIG_SYSTEM_NSH_STACKSIZE=1024
|
||||
CONFIG_TASK_NAME_SIZE=0
|
||||
CONFIG_TASK_SPAWN_DEFAULT_STACKSIZE=1536
|
||||
CONFIG_USART2_SERIAL_CONSOLE=y
|
||||
CONFIG_USERMAIN_STACKSIZE=1536
|
||||
CONFIG_USER_ENTRYPOINT="nsh_main"
|
||||
CONFIG_WDOG_INTRESERVE=0
|
||||
|
|
@ -64,4 +64,8 @@ ifeq ($(CONFIG_ADC),y)
|
|||
CSRCS += stm32_adc.c
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_LCD_SSD1306),y)
|
||||
CSRCS += stm32_ssd1306.c
|
||||
endif
|
||||
|
||||
include $(TOPDIR)/configs/Board.mk
|
||||
|
|
|
|||
|
|
@ -114,6 +114,10 @@
|
|||
#define GPIO_SX127X_CRF2 (GPIO_SPEED_HIGH | GPIO_PORTC | GPIO_PIN2)
|
||||
#define GPIO_SX127X_CRF3 (GPIO_SPEED_HIGH | GPIO_PORTC | GPIO_PIN1)
|
||||
|
||||
/* Oled configuration */
|
||||
|
||||
#define OLED_I2C_PORT 1
|
||||
|
||||
/****************************************************************************
|
||||
* Public Data
|
||||
****************************************************************************/
|
||||
|
|
|
|||
|
|
@ -63,6 +63,65 @@
|
|||
# define HAVE_DAC2 1
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Private Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_i2c_register
|
||||
*
|
||||
* Description:
|
||||
* Register one I2C drivers for the I2C tool.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#if defined(CONFIG_I2C) && defined(CONFIG_SYSTEM_I2CTOOL)
|
||||
static void stm32_i2c_register(int bus)
|
||||
{
|
||||
FAR struct i2c_master_s *i2c;
|
||||
int ret;
|
||||
|
||||
i2c = stm32_i2cbus_initialize(bus);
|
||||
if (i2c == NULL)
|
||||
{
|
||||
syslog(LOG_ERR, "ERROR: Failed to get I2C%d interface\n", bus);
|
||||
}
|
||||
else
|
||||
{
|
||||
ret = i2c_register(i2c, bus);
|
||||
if (ret < 0)
|
||||
{
|
||||
syslog(LOG_ERR, "ERROR: Failed to register I2C%d driver: %d\n",
|
||||
bus, ret);
|
||||
stm32_i2cbus_uninitialize(i2c);
|
||||
}
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_i2ctool
|
||||
*
|
||||
* Description:
|
||||
* Register I2C drivers for the I2C tool.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#if defined(CONFIG_I2C) && defined(CONFIG_SYSTEM_I2CTOOL)
|
||||
static void stm32_i2ctool(void)
|
||||
{
|
||||
#ifdef CONFIG_STM32F0L0_I2C1
|
||||
stm32_i2c_register(1);
|
||||
#endif
|
||||
#ifdef CONFIG_STM32F0L0_I2C2
|
||||
stm32_i2c_register(2);
|
||||
#endif
|
||||
#ifdef CONFIG_STM32F0L0_I2C3
|
||||
stm32_i2c_register(3);
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
|
|
|||
124
configs/b-l072z-lrwan1/src/stm32_ssd1306.c
Normal file
124
configs/b-l072z-lrwan1/src/stm32_ssd1306.c
Normal file
|
|
@ -0,0 +1,124 @@
|
|||
/****************************************************************************
|
||||
* config/b-l072z-lrwan1/src/stm32_ssd1306.c
|
||||
*
|
||||
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
|
||||
* Author: Mateusz Szafoni <raiden00@railab.me>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <debug.h>
|
||||
|
||||
#include <nuttx/board.h>
|
||||
#include <nuttx/lcd/lcd.h>
|
||||
#include <nuttx/lcd/ssd1306.h>
|
||||
#include <nuttx/i2c/i2c_master.h>
|
||||
|
||||
#include "stm32.h"
|
||||
#include "b-l072z-lrwan1.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/* Configuration ************************************************************/
|
||||
|
||||
#ifndef CONFIG_LCD_MAXPOWER
|
||||
# define CONFIG_LCD_MAXPOWER 1
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Private Data
|
||||
****************************************************************************/
|
||||
|
||||
FAR struct i2c_master_s *g_i2c;
|
||||
FAR struct lcd_dev_s *g_lcddev;
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: board_lcd_initialize
|
||||
****************************************************************************/
|
||||
|
||||
int board_lcd_initialize(void)
|
||||
{
|
||||
/* Initialize I2C */
|
||||
|
||||
g_i2c = stm32_i2cbus_initialize(OLED_I2C_PORT);
|
||||
if (!g_i2c)
|
||||
{
|
||||
lcderr("ERROR: Failed to initialize I2C port %d\n", OLED_I2C_PORT);
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
return OK;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: board_lcd_getdev
|
||||
****************************************************************************/
|
||||
|
||||
FAR struct lcd_dev_s *board_lcd_getdev(int devno)
|
||||
{
|
||||
/* Bind the I2C port to the OLED */
|
||||
|
||||
g_lcddev = ssd1306_initialize(g_i2c, NULL, devno);
|
||||
if (!g_lcddev)
|
||||
{
|
||||
lcderr("ERROR: Failed to bind I2C port 1 to OLED %d: %d\n", devno);
|
||||
}
|
||||
else
|
||||
{
|
||||
lcdinfo("Bound I2C port %d to OLED %d\n", OLED_I2C_PORT, devno);
|
||||
|
||||
/* And turn the OLED on */
|
||||
|
||||
(void)g_lcddev->setpower(g_lcddev, CONFIG_LCD_MAXPOWER);
|
||||
return g_lcddev;
|
||||
}
|
||||
|
||||
return NULL;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: board_lcd_uninitialize
|
||||
****************************************************************************/
|
||||
|
||||
void board_lcd_uninitialize(void)
|
||||
{
|
||||
/* TO-FIX */
|
||||
}
|
||||
|
|
@ -199,6 +199,17 @@
|
|||
#define GPIO_USART3_RX GPIO_USART3_RX_3 /* PD9 */
|
||||
#define GPIO_USART3_TX GPIO_USART3_TX_3 /* PD8 */
|
||||
|
||||
/* I2C1 Use Nucleo I2C1 pins */
|
||||
|
||||
#define GPIO_I2C1_SCL GPIO_I2C1_SCL_3 /* PB8 - D15 */
|
||||
#define GPIO_I2C1_SDA GPIO_I2C1_SDA_3 /* PB9 - D14 */
|
||||
|
||||
/* I2C2 Use Nucleo I2C2 pins */
|
||||
|
||||
#define GPIO_I2C2_SCL GPIO_I2C2_SCL_2 /* PF1 - D69 */
|
||||
#define GPIO_I2C2_SDA GPIO_I2C2_SDA_2 /* PF0 - D68 */
|
||||
#define GPIO_I2C2_SMBA GPIO_I2C2_SMBA_2 /* PF2 - D70 */
|
||||
|
||||
/* DMA **********************************************************************/
|
||||
|
||||
#define ADC1_DMA_CHAN DMACHAN_ADC1
|
||||
|
|
|
|||
61
configs/nucleo-f303ze/nxlines_oled/defconfig
Normal file
61
configs/nucleo-f303ze/nxlines_oled/defconfig
Normal file
|
|
@ -0,0 +1,61 @@
|
|||
#
|
||||
# This file is autogenerated: PLEASE DO NOT EDIT IT.
|
||||
#
|
||||
# You can use "make menuconfig" to make any modifications to the installed .config file.
|
||||
# You can then do "make savedefconfig" to generate a new defconfig file that includes your
|
||||
# modifications.
|
||||
#
|
||||
# CONFIG_ARCH_FPU is not set
|
||||
# CONFIG_EXAMPLES_NXLINES_DEFAULT_COLORS is not set
|
||||
# CONFIG_NX_DISABLE_1BPP is not set
|
||||
CONFIG_ARCH="arm"
|
||||
CONFIG_ARCH_BOARD="nucleo-f303ze"
|
||||
CONFIG_ARCH_BOARD_NUCLEO_F303ZE=y
|
||||
CONFIG_ARCH_BUTTONS=y
|
||||
CONFIG_ARCH_CHIP_STM32=y
|
||||
CONFIG_ARCH_CHIP_STM32F303ZE=y
|
||||
CONFIG_ARCH_STACKDUMP=y
|
||||
CONFIG_BOARD_LOOPSPERMSEC=6522
|
||||
CONFIG_BUILTIN=y
|
||||
CONFIG_DISABLE_POLL=y
|
||||
CONFIG_EXAMPLES_NXLINES=y
|
||||
CONFIG_EXAMPLES_NXLINES_BORDERWIDTH=1
|
||||
CONFIG_EXAMPLES_NXLINES_BPP=1
|
||||
CONFIG_EXAMPLES_NXLINES_LINECOLOR=0xff
|
||||
CONFIG_EXAMPLES_NXLINES_LINEWIDTH=1
|
||||
CONFIG_IDLETHREAD_STACKSIZE=2048
|
||||
CONFIG_INTELHEX_BINARY=y
|
||||
CONFIG_LCD=y
|
||||
CONFIG_LCD_MAXCONTRAST=255
|
||||
CONFIG_LCD_SH1106_OLED_132=y
|
||||
CONFIG_LCD_SSD1306_I2C=y
|
||||
CONFIG_MAX_TASKS=16
|
||||
CONFIG_MAX_WDOGPARMS=2
|
||||
CONFIG_MM_REGIONS=2
|
||||
CONFIG_MQ_MAXMSGSIZE=64
|
||||
CONFIG_NFILE_DESCRIPTORS=8
|
||||
CONFIG_NFILE_STREAMS=8
|
||||
CONFIG_NSH_BUILTIN_APPS=y
|
||||
CONFIG_NX=y
|
||||
CONFIG_NXFONT_MONO5X8=y
|
||||
CONFIG_NX_BLOCKING=y
|
||||
CONFIG_PREALLOC_MQ_MSGS=4
|
||||
CONFIG_PREALLOC_TIMERS=4
|
||||
CONFIG_PREALLOC_WDOGS=8
|
||||
CONFIG_RAM_SIZE=65536
|
||||
CONFIG_RAM_START=0x20000000
|
||||
CONFIG_RAW_BINARY=y
|
||||
CONFIG_RR_INTERVAL=200
|
||||
CONFIG_SCHED_WAITPID=y
|
||||
CONFIG_SDCLONE_DISABLE=y
|
||||
CONFIG_START_DAY=27
|
||||
CONFIG_START_YEAR=2013
|
||||
CONFIG_STM32_I2C1=y
|
||||
CONFIG_STM32_JTAG_SW_ENABLE=y
|
||||
CONFIG_STM32_USART3=y
|
||||
CONFIG_SYSLOG_NONE=y
|
||||
CONFIG_SYSTEM_NSH=y
|
||||
CONFIG_TASK_NAME_SIZE=0
|
||||
CONFIG_USART3_SERIAL_CONSOLE=y
|
||||
CONFIG_USER_ENTRYPOINT="nsh_main"
|
||||
CONFIG_WDOG_INTRESERVE=1
|
||||
|
|
@ -56,4 +56,8 @@ ifeq ($(CONFIG_ADC),y)
|
|||
CSRCS += stm32_adc.c
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_LCD_SSD1306),y)
|
||||
CSRCS += stm32_ssd1306.c
|
||||
endif
|
||||
|
||||
include $(TOPDIR)/configs/Board.mk
|
||||
|
|
|
|||
|
|
@ -84,6 +84,10 @@
|
|||
|
||||
#define GPIO_BTN_USER (GPIO_INPUT|GPIO_FLOAT|GPIO_EXTI|GPIO_PORTC|GPIO_PIN13)
|
||||
|
||||
/* Oled configuration */
|
||||
|
||||
#define OLED_I2C_PORT 1
|
||||
|
||||
/****************************************************************************
|
||||
* Public Data
|
||||
****************************************************************************/
|
||||
|
|
|
|||
124
configs/nucleo-f303ze/src/stm32_ssd1306.c
Normal file
124
configs/nucleo-f303ze/src/stm32_ssd1306.c
Normal file
|
|
@ -0,0 +1,124 @@
|
|||
/****************************************************************************
|
||||
* config/nucleo-f303ze/src/stm32_ssd1306.c
|
||||
*
|
||||
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
|
||||
* Author: Mateusz Szafoni <raiden00@railab.me>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <debug.h>
|
||||
|
||||
#include <nuttx/board.h>
|
||||
#include <nuttx/lcd/lcd.h>
|
||||
#include <nuttx/lcd/ssd1306.h>
|
||||
#include <nuttx/i2c/i2c_master.h>
|
||||
|
||||
#include "stm32.h"
|
||||
#include "nucleo-f303ze.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/* Configuration ************************************************************/
|
||||
|
||||
#ifndef CONFIG_LCD_MAXPOWER
|
||||
# define CONFIG_LCD_MAXPOWER 1
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Private Data
|
||||
****************************************************************************/
|
||||
|
||||
FAR struct i2c_master_s *g_i2c;
|
||||
FAR struct lcd_dev_s *g_lcddev;
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: board_lcd_initialize
|
||||
****************************************************************************/
|
||||
|
||||
int board_lcd_initialize(void)
|
||||
{
|
||||
/* Initialize I2C */
|
||||
|
||||
g_i2c = stm32_i2cbus_initialize(OLED_I2C_PORT);
|
||||
if (!g_i2c)
|
||||
{
|
||||
lcderr("ERROR: Failed to initialize I2C port %d\n", OLED_I2C_PORT);
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
return OK;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: board_lcd_getdev
|
||||
****************************************************************************/
|
||||
|
||||
FAR struct lcd_dev_s *board_lcd_getdev(int devno)
|
||||
{
|
||||
/* Bind the I2C port to the OLED */
|
||||
|
||||
g_lcddev = ssd1306_initialize(g_i2c, NULL, devno);
|
||||
if (!g_lcddev)
|
||||
{
|
||||
lcderr("ERROR: Failed to bind I2C port 1 to OLED %d: %d\n", devno);
|
||||
}
|
||||
else
|
||||
{
|
||||
lcdinfo("Bound I2C port %d to OLED %d\n", OLED_I2C_PORT, devno);
|
||||
|
||||
/* And turn the OLED on */
|
||||
|
||||
(void)g_lcddev->setpower(g_lcddev, CONFIG_LCD_MAXPOWER);
|
||||
return g_lcddev;
|
||||
}
|
||||
|
||||
return NULL;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: board_lcd_uninitialize
|
||||
****************************************************************************/
|
||||
|
||||
void board_lcd_uninitialize(void)
|
||||
{
|
||||
/* TO-FIX */
|
||||
}
|
||||
Loading…
Add table
Reference in a new issue