From 8f55ec5c69042fa479a47b2335ecb59772fb5e0e Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sun, 6 Dec 2015 09:29:51 -0600 Subject: [PATCH] SAMV7: Port the WDT driver from the SAMA5 to the SAMV7 --- arch/arm/src/samv7/Kconfig | 10 +- arch/arm/src/samv7/Make.defs | 4 + arch/arm/src/samv7/chip/sam_wdt.h | 30 +- arch/arm/src/samv7/chip/same70_memorymap.h | 4 +- arch/arm/src/samv7/chip/samv71_memorymap.h | 4 +- arch/arm/src/samv7/sam_clockconfig.c | 12 +- arch/arm/src/samv7/sam_wdt.c | 705 +++++++++++++++++++++ arch/arm/src/samv7/sam_wdt.h | 76 +++ 8 files changed, 816 insertions(+), 29 deletions(-) create mode 100644 arch/arm/src/samv7/sam_wdt.c create mode 100644 arch/arm/src/samv7/sam_wdt.h diff --git a/arch/arm/src/samv7/Kconfig b/arch/arm/src/samv7/Kconfig index 0763edb4c1..71cf23effc 100644 --- a/arch/arm/src/samv7/Kconfig +++ b/arch/arm/src/samv7/Kconfig @@ -535,13 +535,15 @@ config SAMV7_USART2 select ARCH_HAVE_USART2 select ARCH_HAVE_SERIAL_TERMIOS -config SAMV7_WDT0 - bool "Watchdog Timer (WDT0)" +config SAMV7_WDT + bool "Watchdog Timer (WDT)" default n + select WATCHDOG -config SAMV7_WDT1 - bool "Watchdog Timer (WDT1)" +config SAMV7_RSWDT + bool "Reinforced Safety Watchdog Timer (RSWDT)" default n + select WATCHDOG endmenu # SAMV7 Peripheral Selection diff --git a/arch/arm/src/samv7/Make.defs b/arch/arm/src/samv7/Make.defs index 0f96bfe0d6..927a135a64 100644 --- a/arch/arm/src/samv7/Make.defs +++ b/arch/arm/src/samv7/Make.defs @@ -136,6 +136,10 @@ ifeq ($(CONFIG_SAMV7_XDMAC),y) CHIP_CSRCS += sam_xdmac.c endif +ifeq ($(CONFIG_SAMV7_WDT),y) +CHIP_CSRCS += sam_wdt.c +endif + ifeq ($(CONFIG_SAMV7_SPI_MASTER),y) CHIP_CSRCS += sam_spi.c endif diff --git a/arch/arm/src/samv7/chip/sam_wdt.h b/arch/arm/src/samv7/chip/sam_wdt.h index 9b298c443e..3a949c3c97 100644 --- a/arch/arm/src/samv7/chip/sam_wdt.h +++ b/arch/arm/src/samv7/chip/sam_wdt.h @@ -58,17 +58,17 @@ /* WDT register addresses ***************************************************************/ -/* WDT0: Legacy Watchdog Timer */ +/* WDT: Legacy Watchdog Timer */ -#define SAM_WDT0_CR (SAM_WDT0_BASE+SAM_WDT_CR_OFFSET) -#define SAM_WDT0_MR (SAM_WDT0_BASE+SAM_WDT_MR_OFFSET) -#define SAM_WDT0_SR (SAM_WDT0_BASE+SAM_WDT_SR_OFFSET) +#define SAM_WDT_CR (SAM_WDT_BASE+SAM_WDT_CR_OFFSET) +#define SAM_WDT_MR (SAM_WDT_BASE+SAM_WDT_MR_OFFSET) +#define SAM_WDT_SR (SAM_WDT_BASE+SAM_WDT_SR_OFFSET) -/* WDT1: Reinforced Safety Watchdog Timer */ +/* RSWDT: Reinforced Safety Watchdog Timer */ -#define SAM_WDT1_CR (SAM_WDT1_BASE+SAM_WDT_CR_OFFSET) -#define SAM_WDT1_MR (SAM_WDT1_BASE+SAM_WDT_MR_OFFSET) -#define SAM_WDT1_SR (SAM_WDT1_BASE+SAM_WDT_SR_OFFSET) +#define SAM_RSWDT_CR (SAM_RSWDT_BASE+SAM_WDT_CR_OFFSET) +#define SAM_RSWDT_MR (SAM_RSWDT_BASE+SAM_WDT_MR_OFFSET) +#define SAM_RSWDT_SR (SAM_RSWDT_BASE+SAM_WDT_SR_OFFSET) /* WDT register bit definitions *********************************************************/ /* Watchdog Timer Control Register */ @@ -76,8 +76,8 @@ #define WDT_CR_WDRSTT (1 << 0) /* Bit 0: Watchdog Rest */ #define WDT_CR_KEY_SHIFT (24) /* Bits 24-31: Password */ #define WDT_CR_KEY_MASK (0xff << WDT_CR_KEY_SHIFT) -# define WDT0_CR_KEY (0xa5 << WDT_CR_KEY_SHIFT) -# define WDT1_CR_KEY (0xc4 << WDT_CR_KEY_SHIFT) +# define WDT_CR_KEY (0xa5 << WDT_CR_KEY_SHIFT) +# define RSWDT_CR_KEY (0xc4 << WDT_CR_KEY_SHIFT) /* Watchdog Timer Mode Register */ @@ -87,20 +87,20 @@ # define WDT_MR_WDV(n) ((uint32_t)(n) << WDT_MR_WDV_SHIFT) #define WDT_MR_WDFIEN (1 << 12) /* Bit 12: Watchdog Fault Interrupt Enable */ #define WDT_MR_WDRSTEN (1 << 13) /* Bit 13: Watchdog Reset Enable */ -#define WDT1_MR_WDRPROC (1 << 14) /* Bit 14: Watchdog Reset Processor (WDT1 only) */ +#define RSWDT_MR_WDRPROC (1 << 14) /* Bit 14: Watchdog Reset Processor (RSWDT only) */ #define WDT_MR_WDDIS (1 << 15) /* Bit 15: Watchdog Disable */ -#define WDT_MR_WDD_SHIFT (16) /* Bits 16-27: Watchdog Delta Value (WDT0 only) */ +#define WDT_MR_WDD_SHIFT (16) /* Bits 16-27: Watchdog Delta Value (WDT only) */ #define WDT_MR_WDD_MAX 0xfff #define WDT_MR_WDD_MASK (WDT_MR_WDD_MAX << WDT_MR_WDD_SHIFT) -# define WDT0_MR_WDD(n) ((uint32_t)(n) << WDT_MR_WDD_SHIFT) -# define WDT1_MR_WDD_ALLONES (0xfff << WDT_MR_WDD_SHIFT) +# define WDT_MR_WDD(n) ((uint32_t)(n) << WDT_MR_WDD_SHIFT) +# define RSWDT_MR_WDD_ALLONES (0xfff << WDT_MR_WDD_SHIFT) #define WDT_MR_WDDBGHLT (1 << 28) /* Bit 28: Watchdog Debug Halt */ #define WDT_MR_WDIDLEHLT (1 << 29) /* Bit 29: Watchdog Idle Halt */ /* Watchdog Timer Status Register */ #define WDT_SR_WDUNF (1 << 0) /* Bit 0: Watchdog Underflow */ -#define WDT0_SR_WDERR (1 << 1) /* Bit 1: Watchdog Error (WDT0 only) */ +#define WDT_SR_WDERR (1 << 1) /* Bit 1: Watchdog Error (WDT only) */ /**************************************************************************************** * Public Types diff --git a/arch/arm/src/samv7/chip/same70_memorymap.h b/arch/arm/src/samv7/chip/same70_memorymap.h index e6a21a3804..8bfa52ecc1 100644 --- a/arch/arm/src/samv7/chip/same70_memorymap.h +++ b/arch/arm/src/samv7/chip/same70_memorymap.h @@ -140,11 +140,11 @@ # define SAM_RSTC_BASE 0x400e1800 /* 0x400e1800-0x400e180f: Reset Controller (RSTC) */ # define SAM_SUPC_BASE 0x400e1810 /* 0x400e1810-0x400e182f: Supply Controller (SUPC) */ # define SAM_RTT_BASE 0x400e1830 /* 0x400e1830-0x400e184f: Real Time Timer (RTT) */ -# define SAM_WDT0_BASE 0x400e1850 /* 0x400e1850-0x400e185f: Watchdog Timer 0 (WDT0) */ +# define SAM_WDT_BASE 0x400e1850 /* 0x400e1850-0x400e185f: Watchdog Timer (WDT) */ # define SAM_RTC_BASE 0x400e1860 /* 0x400e1860-0x400e188f: Real Time Clock (RTC) */ # define SAM_GPBR_BASE 0x400e1890 /* 0x400e1890-0x400e18ff: GPBR */ # define SAM_SYSC_BASE 0x400e18e0 /* 0x400e1890-0x400e18ff: System Controller Common */ -# define SAM_WDT1_BASE 0x400e1900 /* 0x400e1900-0x400e19ff: Watchdog Timer 1 (WDT1) */ +# define SAM_RSWDT_BASE 0x400e1900 /* 0x400e1900-0x400e19ff: Reinforced Safety Watchdog Timer (RSWDT) */ #define SAM_UART2_BASE 0x400e1a00 /* 0x400e1a00-0x400e1bff: UART 2 */ #define SAM_UART3_BASE 0x400e1c00 /* 0x400e1c00-0x400e1dff: UART 3 */ #define SAM_UART4_BASE 0x400e1e00 /* 0x400e1e00-0x400e1fff: UART 4 */ diff --git a/arch/arm/src/samv7/chip/samv71_memorymap.h b/arch/arm/src/samv7/chip/samv71_memorymap.h index b7d55f1031..df8a5a11a8 100644 --- a/arch/arm/src/samv7/chip/samv71_memorymap.h +++ b/arch/arm/src/samv7/chip/samv71_memorymap.h @@ -140,11 +140,11 @@ # define SAM_RSTC_BASE 0x400e1800 /* 0x400e1800-0x400e180f: Reset Controller (RSTC) */ # define SAM_SUPC_BASE 0x400e1810 /* 0x400e1810-0x400e182f: Supply Controller (SUPC) */ # define SAM_RTT_BASE 0x400e1830 /* 0x400e1830-0x400e184f: Real Time Timer (RTT) */ -# define SAM_WDT0_BASE 0x400e1850 /* 0x400e1850-0x400e185f: Watchdog Timer 0 (WDT0) */ +# define SAM_WDT_BASE 0x400e1850 /* 0x400e1850-0x400e185f: Watchdog Timer(WDT) */ # define SAM_RTC_BASE 0x400e1860 /* 0x400e1860-0x400e188f: Real Time Clock (RTC) */ # define SAM_GPBR_BASE 0x400e1890 /* 0x400e1890-0x400e18ff: GPBR */ # define SAM_SYSC_BASE 0x400e18e0 /* 0x400e1890-0x400e18ff: System Controller Common */ -# define SAM_WDT1_BASE 0x400e1900 /* 0x400e1900-0x400e19ff: Watchdog Timer 1 (WDT1) */ +# define SAM_RSWDT_BASE 0x400e1900 /* 0x400e1900-0x400e19ff: Reinforced Safety Watchdog Timer (RSWDT) */ #define SAM_UART2_BASE 0x400e1a00 /* 0x400e1a00-0x400e1bff: UART 2 */ #define SAM_UART3_BASE 0x400e1c00 /* 0x400e1c00-0x400e1dff: UART 3 */ #define SAM_UART4_BASE 0x400e1e00 /* 0x400e1e00-0x400e1fff: UART 4 */ diff --git a/arch/arm/src/samv7/sam_clockconfig.c b/arch/arm/src/samv7/sam_clockconfig.c index f45304ce3e..c7bd6bbc9a 100644 --- a/arch/arm/src/samv7/sam_clockconfig.c +++ b/arch/arm/src/samv7/sam_clockconfig.c @@ -110,14 +110,14 @@ static inline void sam_efcsetup(void) static inline void sam_wdtsetup(void) { -#if !defined(CONFIG_SAMV7_WDT0) || \ - (defined(CONFIG_WDT0_ENABLED_ON_RESET) && defined(CONFIG_WDT0_DISABLE_ON_RESET)) - putreg32(WDT_MR_WDDIS, SAM_WDT0_MR); +#if !defined(CONFIG_SAMV7_WDT) || \ + (defined(CONFIG_WDT_ENABLED_ON_RESET) && defined(CONFIG_WDT_DISABLE_ON_RESET)) + putreg32(WDT_MR_WDDIS, SAM_WDT_MR); #endif -#if !defined(CONFIG_SAMV7_WDT1) || \ - (defined(CONFIG_WDT1_ENABLED_ON_RESET) && defined(CONFIG_WDT1_DISABLE_ON_RESET)) - putreg32(WDT_MR_WDDIS, SAM_WDT1_MR); +#if !defined(CONFIG_SAMV7_RSWDT) || \ + (defined(CONFIG_RSWDT_ENABLED_ON_RESET) && defined(CONFIG_RSWDT_DISABLE_ON_RESET)) + putreg32(WDT_MR_WDDIS, SAM_RSWDT_MR); #endif } diff --git a/arch/arm/src/samv7/sam_wdt.c b/arch/arm/src/samv7/sam_wdt.c new file mode 100644 index 0000000000..e4249f131f --- /dev/null +++ b/arch/arm/src/samv7/sam_wdt.c @@ -0,0 +1,705 @@ +/**************************************************************************** + * arch/arm/src/samv7/sam_wdg.c + * + * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include +#include +#include + +#include +#include + +#include "up_arch.h" +#include "sam_wdt.h" + +#if defined(CONFIG_WATCHDOG) && defined(CONFIG_SAMV7_WDT) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ +/* Configuration ************************************************************/ +/* The Watchdog Timer uses the Slow Clock divided by 128 to establish the + * maximum Watchdog period to be 16 seconds (with a typical Slow Clock of + * 32768 kHz). + */ + +#ifndef BOARD_SCLK_FREQUENCY +# define BOARD_SCLK_FREQUENCY 32768 +#endif + +#define WDT_FREQUENCY (BOARD_SCLK_FREQUENCY / 128) + +/* At 32768Hz, the maximum timeout value will be: + * + * 4096 / WDT_FREQUENCY = 256 seconds or 16,000 milliseconds + * + * And the minimum (non-zero) timeout would be: + * + * 1 / WDT_FREQUENCY = 3.9 milliseconds + */ + +#define WDT_MINTIMEOUT ((1000 + WDT_FREQUENCY - 1) / WDT_FREQUENCY) +#define WDT_MAXTIMEOUT ((4096 * 1000) / WDT_FREQUENCY) + +/* Debug ********************************************************************/ +/* Non-standard debug that may be enabled just for testing the watchdog + * driver. NOTE: that only lldbg types are used so that the output is + * immediately available. + */ + +#ifdef CONFIG_DEBUG_WATCHDOG +# define wddbg lldbg +# define wdvdbg llvdbg +#else +# define wddbg(x...) +# define wdvdbg(x...) +#endif + +/**************************************************************************** + * Private Types + ****************************************************************************/ +/* This structure provides the private representation of the "lower-half" + * driver state structure. This structure must be cast-compatible with the + * well-known watchdog_lowerhalf_s structure. + */ + +struct sam_lowerhalf_s +{ + FAR const struct watchdog_ops_s *ops; /* Lower half operations */ +#ifdef CONFIG_SAMV7_WDT_INTERRUPT + xcpt_t handler; /* Current WDT interrupt handler */ +#endif + uint32_t timeout; /* The actual timeout value (milliseconds) */ + uint16_t reload; /* The 12-bit watchdog reload value */ + bool started; /* The timer has been started */ +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ +/* Register operations ******************************************************/ + +#if defined(CONFIG_SAMV7_WDT_REGDEBUG) && defined(CONFIG_DEBUG) +static uint32_t sam_getreg(uintptr_t regaddr); +static void sam_putreg(uint32_t regval, uintptr_t regaddr); +#else +# define sam_getreg(regaddr) getreg32(regaddr) +# define sam_putreg(regval,regaddr) putreg32(regval,regaddr) +#endif + +/* Interrupt hanlding *******************************************************/ + +#ifdef CONFIG_SAMV7_WDT_INTERRUPT +static int sam_interrupt(int irq, FAR void *context); +#endif + +/* "Lower half" driver methods **********************************************/ + +static int sam_start(FAR struct watchdog_lowerhalf_s *lower); +static int sam_stop(FAR struct watchdog_lowerhalf_s *lower); +static int sam_keepalive(FAR struct watchdog_lowerhalf_s *lower); +static int sam_getstatus(FAR struct watchdog_lowerhalf_s *lower, + FAR struct watchdog_status_s *status); +static int sam_settimeout(FAR struct watchdog_lowerhalf_s *lower, + uint32_t timeout); +static xcpt_t sam_capture(FAR struct watchdog_lowerhalf_s *lower, + xcpt_t handler); +static int sam_ioctl(FAR struct watchdog_lowerhalf_s *lower, int cmd, + unsigned long arg); + +/**************************************************************************** + * Private Data + ****************************************************************************/ +/* "Lower half" driver methods */ + +static const struct watchdog_ops_s g_wdgops = +{ + .start = sam_start, + .stop = sam_stop, + .keepalive = sam_keepalive, + .getstatus = sam_getstatus, + .settimeout = sam_settimeout, + .capture = sam_capture, + .ioctl = sam_ioctl, +}; + +/* "Lower half" driver state */ + +static struct sam_lowerhalf_s g_wdtdev; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: sam_getreg + * + * Description: + * Get the contents of an SAMV7 register + * + ****************************************************************************/ + +#if defined(CONFIG_SAMV7_WDT_REGDEBUG) && defined(CONFIG_DEBUG) +static uint32_t sam_getreg(uintptr_t regaddr) +{ + static uint32_t prevaddr = 0; + static uint32_t count = 0; + static uint32_t preval = 0; + + /* Read the value from the register */ + + uint32_t regval = getreg32(regaddr); + + /* Is this the same value that we read from the same registe last time? Are + * we polling the register? If so, suppress some of the output. + */ + + if (regaddr == prevaddr && regval == preval) + { + if (count == 0xffffffff || ++count > 3) + { + if (count == 4) + { + lldbg("...\n"); + } + + return regval; + } + } + + /* No this is a new address or value */ + + else + { + /* Did we print "..." for the previous value? */ + + if (count > 3) + { + /* Yes.. then show how many times the value repeated */ + + lldbg("[repeats %d more times]\n", count-3); + } + + /* Save the new address, value, and count */ + + prevaddr = regaddr; + preval = regval; + count = 1; + } + + /* Show the register value read */ + + lldbg("%08x->%048\n", regaddr, regval); + return regval; +} +#endif + +/**************************************************************************** + * Name: sam_putreg + * + * Description: + * Set the contents of an SAMV7 register to a value + * + ****************************************************************************/ + +#if defined(CONFIG_SAMV7_WDT_REGDEBUG) && defined(CONFIG_DEBUG) +static void sam_putreg(uint32_t regval, uintptr_t regaddr) +{ + /* Show the register value being written */ + + lldbg("%08x<-%08x\n", regaddr, regval); + + /* Write the value */ + + putreg32(regval, regaddr); +} +#endif + +/**************************************************************************** + * Name: sam_interrupt + * + * Description: + * WDT early warning interrupt + * + * Input Parameters: + * Usual interrupt handler arguments. + * + * Returned Values: + * Always returns OK. + * + ****************************************************************************/ + +#ifdef CONFIG_SAMV7_WDT_INTERRUPT +static int sam_interrupt(int irq, FAR void *context) +{ + FAR struct sam_lowerhalf_s *priv = &g_wdtdev; + + /* Is there a registered handler? */ + + if (priv->handler) + { + /* Yes... NOTE: This interrupt service routine (ISR) must reload + * the WDT counter to prevent the reset. Otherwise, we will reset + * upon return. + */ + + priv->handler(irq, context); + } + + return OK; +} +#endif + +/**************************************************************************** + * Name: sam_start + * + * Description: + * Start the watchdog timer, resetting the time to the current timeout, + * + * Input Parameters: + * lower - A pointer the publicly visible representation of the "lower-half" + * driver state structure. + * + * Returned Values: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int sam_start(FAR struct watchdog_lowerhalf_s *lower) +{ + FAR struct sam_lowerhalf_s *priv = (FAR struct sam_lowerhalf_s *)lower; + + /* The watchdog timer is enabled or disabled by writing to the MR register. + * + * NOTE: The Watchdog Mode Register (WDT_MR) can be written only once. Only + * a processor reset resets it. Writing the WDT_MR register reloads the + * timer with the newly programmed mode parameters. + */ + + wdvdbg("Entry\n"); + return priv->started ? OK : -ENOSYS; +} + +/**************************************************************************** + * Name: sam_stop + * + * Description: + * Stop the watchdog timer + * + * Input Parameters: + * lower - A pointer the publicly visible representation of the "lower-half" + * driver state structure. + * + * Returned Values: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int sam_stop(FAR struct watchdog_lowerhalf_s *lower) +{ + /* The watchdog timer is enabled or disabled by writing to the MR register. + * + * NOTE: The Watchdog Mode Register (WDT_MR) can be written only once. Only + * a processor reset resets it. Writing the WDT_MR register reloads the + * timer with the newly programmed mode parameters. + */ + + wdvdbg("Entry\n"); + return -ENOSYS; +} + +/**************************************************************************** + * Name: sam_keepalive + * + * Description: + * Reset the watchdog timer to the current timeout value, prevent any + * imminent watchdog timeouts. This is sometimes referred as "pinging" + * the atchdog timer or "petting the dog". + * + * Input Parameters: + * lower - A pointer the publicly visible representation of the "lower-half" + * driver state structure. + * + * Returned Values: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int sam_keepalive(FAR struct watchdog_lowerhalf_s *lower) +{ + wdvdbg("Entry\n"); + + /* Write WDT_CR_WDRSTT to the WDT CR regiser (along with the KEY value) + * will restart the watchdog timer. + */ + + sam_putreg(WDT_CR_WDRSTT | WDT_CR_KEY, SAM_WDT_CR); + return OK; +} + +/**************************************************************************** + * Name: sam_getstatus + * + * Description: + * Get the current watchdog timer status + * + * Input Parameters: + * lower - A pointer the publicly visible representation of the "lower-half" + * driver state structure. + * stawtus - The location to return the watchdog status information. + * + * Returned Values: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int sam_getstatus(FAR struct watchdog_lowerhalf_s *lower, + FAR struct watchdog_status_s *status) +{ + FAR struct sam_lowerhalf_s *priv = (FAR struct sam_lowerhalf_s *)lower; + + wdvdbg("Entry\n"); + DEBUGASSERT(priv); + + /* Return the status bit */ + + status->flags = WDFLAGS_RESET; + if (priv->started) + { + status->flags |= WDFLAGS_ACTIVE; + } + +#ifdef CONFIG_SAMV7_WDT_INTERRUPT + if (priv->handler) + { + status->flags |= WDFLAGS_CAPTURE; + } +#endif + + /* Return the actual timeout is milliseconds */ + + status->timeout = priv->timeout; + + /* Get the time remaining until the watchdog expires (in milliseconds) + * + * REVISIT: I think this that this information is available. + */ + + status->timeleft = 0; + + wdvdbg("Status :\n"); + wdvdbg(" flags : %08x\n", status->flags); + wdvdbg(" timeout : %d\n", status->timeout); + wdvdbg(" timeleft : %d\n", status->timeleft); + return OK; +} + +/**************************************************************************** + * Name: sam_settimeout + * + * Description: + * Set a new timeout value (and reset the watchdog timer) + * + * Input Parameters: + * lower - A pointer the publicly visible representation of the "lower-half" + * driver state structure. + * timeout - The new timeout value in millisecnds. + * + * Returned Values: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int sam_settimeout(FAR struct watchdog_lowerhalf_s *lower, + uint32_t timeout) +{ + FAR struct sam_lowerhalf_s *priv = (FAR struct sam_lowerhalf_s *)lower; + uint32_t reload; + uint32_t regval; + + DEBUGASSERT(priv); + wdvdbg("Entry: timeout=%d\n", timeout); + + /* Can this timeout be represented? */ + + if (timeout < WDT_MINTIMEOUT || timeout >= WDT_MAXTIMEOUT) + { + wddbg("Cannot represent timeout: %d < %d > %d\n", + WDT_MINTIMEOUT, timeout, WDT_MAXTIMEOUT); + return -ERANGE; + } + + /* Calculate the reload value to achiee this (appoximate) timeout. + * + * Examples with WDT_FREQUENCY = 32768 / 128 = 256: + * timeout = 4 -> reload = 1 + * timeout = 16000 -> reload = 4096 + */ + + reload = (timeout * WDT_FREQUENCY + 500) / 1000; + if (reload < 1) + { + reload = 1; + } + else if (reload > 4095) + { + reload = 4095; + } + + /* Calculate and save the actual timeout value in milliseconds: + * + * timeout = 1000 * (reload + 1) / Fwwdg + */ + + priv->timeout = (1000 * reload + WDT_FREQUENCY/2) / WDT_FREQUENCY; + + /* Remember the selected values */ + + priv->reload = reload; + + wdvdbg("reload=%d timout: %d->%d\n", + reload, timeout, priv->timeout); + + /* Set the WDT_MR according to calculated value + * + * NOTE: The Watchdog Mode Register (WDT_MR) can be written only once. Only + * a processor reset resets it. Writing the WDT_MR register reloads the + * timer with the newly programmed mode parameters. + */ + + regval = WDT_MR_WDV(reload) | WDT_MR_WDD(reload); + +#ifdef CONFIG_SAMV7_WDT_INTERRUPT + /* Generate an interrupt whent he watchdog timer expires */ + + regval |= WDT_MR_WDFIEN; +#else + /* Reset (everything) if the watchdog timer expires. + * + * REVISIT: Set WDT_MR_WDRPROC so that only the processor is reset? + */ + + regval |= WDT_MR_WDRSTEN; +#endif + +#ifdef CONFIG_SAMV7_WDT_DEBUGHALT + /* Halt the watchdog in the debug state */ + + regval |= WDT_MR_WDDBGHLT; +#endif + +#ifdef CONFIG_SAMV7_WDT_IDLEHALT + /* Halt the watchdog in the IDLE mode */ + + regval |= WDT_MR_WDIDLEHLT; +#endif + + sam_putreg(regval, SAM_WDT_MR); + + /* NOTE: We had to start the watchdog here (because we cannot re-write the + * MR register). So sam_start will not be able to do anything. + */ + + priv->started = true; + + wdvdbg("Setup: CR: %08x MR: %08x SR: %08x\n", + sam_getreg(SAM_WDT_CR), sam_getreg(SAM_WDT_MR), + sam_getreg(SAM_WDT_SR)); + + return OK; +} + +/**************************************************************************** + * Name: sam_capture + * + * Description: + * Don't reset on watchdog timer timeout; instead, call this user provider + * timeout handler. NOTE: Providing handler==NULL will restore the reset + * behavior. + * + * Input Parameters: + * lower - A pointer the publicly visible representation of the "lower-half" + * driver state structure. + * newhandler - The new watchdog expiration function pointer. If this + * function pointer is NULL, then the reset-on-expiration + * behavior is restored, + * + * Returned Values: + * The previous watchdog expiration function pointer or NULL is there was + * no previous function pointer, i.e., if the previous behavior was + * reset-on-expiration (NULL is also returned if an error occurs). + * + ****************************************************************************/ + +static xcpt_t sam_capture(FAR struct watchdog_lowerhalf_s *lower, + xcpt_t handler) +{ +#ifndef CONFIG_SAMV7_WDT_INTERRUPT + wddbg("ERROR: Not configured for this mode\n"); + return NULL; +#else + FAR struct sam_lowerhalf_s *priv = (FAR struct sam_lowerhalf_s *)lower; + irqstate_t flags; + xcpt_t oldhandler; + + DEBUGASSERT(priv); + wdvdbg("Entry: handler=%p\n", handler); + + /* Get the old handler return value */ + + flags = irqsave(); + oldhandler = priv->handler; + + /* Save the new handler */ + + priv->handler = handler; + + /* Are we attaching or detaching the handler? */ + + if (handler) + { + /* Attaching... Enable the WDT interrupt */ + + up_enable_irq(SAM_IRQ_WDT); + } + else + { + /* Detaching... Disable the WDT interrupt */ + + up_disable_irq(SAM_IRQ_WDT); + } + + irqrestore(flags); + return oldhandler; +#endif +} + +/**************************************************************************** + * Name: sam_ioctl + * + * Description: + * Any ioctl commands that are not recognized by the "upper-half" driver + * are forwarded to the lower half driver through this method. + * + * Input Parameters: + * lower - A pointer the publicly visible representation of the "lower-half" + * driver state structure. + * cmd - The ioctol command value + * arg - The optional argument that accompanies the 'cmd'. The + * interpretation of this argument depends on the particular + * command. + * + * Returned Values: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int sam_ioctl(FAR struct watchdog_lowerhalf_s *lower, int cmd, + unsigned long arg) +{ + wdvdbg("cmd=%d arg=%ld\n", cmd, arg); + + /* No ioctls are supported */ + + return -ENOTTY; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_wdginitialize + * + * Description: + * Initialize the WDT watchdog time. The watchdog timer is initialized and + * registered as 'devpath. The initial state of the watchdog time is + * disabled. + * + * Input Parameters: + * None + * + * Returned Values: + * None + * + ****************************************************************************/ + +int up_wdginitialize(void) +{ + FAR struct sam_lowerhalf_s *priv = &g_wdtdev; + + wdvdbg("Entry: CR: %08x MR: %08x SR: %08x\n", + sam_getreg(SAM_WDT_CR), sam_getreg(SAM_WDT_MR), + sam_getreg(SAM_WDT_SR)); + + /* Check if some previous logic was disabled the watchdog timer. Since the + * MR can be written only one time, we are out of business if that is the + * case. + */ + + DEBUGASSERT((sam_getreg(SAM_WDT_MR) & WDT_MR_WDDIS) == 0); + + /* No clock setup is required. The Watchdog Timer uses the Slow Clock + * divided by 128 to establish the maximum Watchdog period to be 16 seconds + * (with a typical Slow Clock of 32768 kHz). + */ + + /* Initialize the driver state structure. Here we assume: (1) the state + * structure lies in .bss and was zeroed at reset time. (2) This function + * is only called once so it is never necessary to re-zero the structure. + */ + + priv->ops = &g_wdgops; + +#ifdef CONFIG_SAMV7_WDT_INTERRUPT + /* Attach our WDT interrupt handler (But don't enable it yet) */ + + (void)irq_attach(SAM_IRQ_WDT, sam_interrupt); +#endif + + /* Register the watchdog driver as /dev/watchdog0 */ + + (void)watchdog_register("/dev/watchdog0", + (FAR struct watchdog_lowerhalf_s *)priv); + return OK; +} + +#endif /* CONFIG_WATCHDOG && CONFIG_SAMV7_WDT */ diff --git a/arch/arm/src/samv7/sam_wdt.h b/arch/arm/src/samv7/sam_wdt.h new file mode 100644 index 0000000000..d5d7c50728 --- /dev/null +++ b/arch/arm/src/samv7/sam_wdt.h @@ -0,0 +1,76 @@ +/**************************************************************************** + * arch/arm/src/samv7/sam_wdt.h + * + * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_SAMV7_SAM_WDT_H +#define __ARCH_ARM_SRC_SAMV7_SAM_WDT_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "chip.h" +#include "chip/sam_wdt.h" + +#ifdef CONFIG_WATCHDOG + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* CONFIG_WATCHDOG */ +#endif /* __ARCH_ARM_SRC_SAMV7_SAM_WDT_H */