SAMA5D3x-EK: At support for the AT25 serial FLASH
This commit is contained in:
Gregory Nutt
parent
1060b232e9
commit
906506c61c
9 changed files with 357 additions and 11 deletions
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@ -5284,4 +5284,6 @@
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and have several limitations: No DMA, no SPI1 support (2013-8-4).
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* arch/arm/src/sama5/sam_spi.c and sam_spi.h: Now supports SPI1
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and a register access debug option (2013-8-4).
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* configs/sama5d3x-ek/src/sam_spi.c: At board support for the
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AT25 serial flash (2013-8-4).
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@ -92,6 +92,7 @@
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#define GPIO_CAN0_RX (GPIO_PERIPHC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOD | GPIO_PIN14) /* Type: GPIO */
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#define GPIO_CAN0_TX (GPIO_PERIPHC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOD | GPIO_PIN15) /* Type: GPIO */
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#define GPIO_CAN1_RX (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN14) /* Type: GMAC */
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#define GPIO_CAN1_TX (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN15) /* Type: GMAC */
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@ -256,12 +257,14 @@
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#define GPIO_MCI0_DA5 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOD | GPIO_PIN6) /* Type: GPIO */
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#define GPIO_MCI0_DA6 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOD | GPIO_PIN7) /* Type: GPIO */
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#define GPIO_MCI0_DA7 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOD | GPIO_PIN8) /* Type: GPIO */
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#define GPIO_MCI1_CDA (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN19) /* Type: GMAC */
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#define GPIO_MCI1_CK (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN24) /* Type: GMAC */
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#define GPIO_MCI1_DA0 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN20) /* Type: GMAC */
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#define GPIO_MCI1_DA1 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN21) /* Type: GMAC */
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#define GPIO_MCI1_DA2 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN22) /* Type: GMAC */
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#define GPIO_MCI1_DA3 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN23) /* Type: GMAC */
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#define GPIO_MCI2_CDA (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN10) /* Type: GPIO */
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#define GPIO_MCI2_CK (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN15) /* Type: MCI_CLK */
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#define GPIO_MCI2_DA0 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN11) /* Type: GPIO */
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@ -282,17 +285,20 @@
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#define GPIO_PWM0_H_2 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN20) /* Type: GPIO */
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#define GPIO_PWM0_L_1 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN1) /* Type: GMAC */
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#define GPIO_PWM0_L_2 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN21) /* Type: GPIO */
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#define GPIO_PWM1_FI (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN31) /* Type: GPIO */
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#define GPIO_PWM1_H_1 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN4) /* Type: GMAC */
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#define GPIO_PWM1_H_2 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN22) /* Type: GPIO */
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#define GPIO_PWM1_L_1 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN5) /* Type: GMAC */
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#define GPIO_PWM1_L_2 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOE | GPIO_PIN31) /* Type: EBI */
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#define GPIO_PWM1_L_3 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN23) /* Type: GPIO */
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#define GPIO_PWM2_FI (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN29) /* Type: GPIO */
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#define GPIO_PWM2_H_1 (GPIO_PERIPHC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOD | GPIO_PIN5) /* Type: GPIO */
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#define GPIO_PWM2_H_2 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN8) /* Type: GMAC */
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#define GPIO_PWM2_L_1 (GPIO_PERIPHC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOD | GPIO_PIN6) /* Type: GPIO */
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#define GPIO_PWM2_L_2 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN9) /* Type: GMAC */
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#define GPIO_PWM3_FI (GPIO_PERIPHC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOD | GPIO_PIN16) /* Type: GPIO */
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#define GPIO_PWM3_H_1 (GPIO_PERIPHC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOD | GPIO_PIN7) /* Type: GPIO */
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#define GPIO_PWM3_H_2 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN12) /* Type: GMAC */
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@ -308,6 +314,7 @@
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#define GPIO_SPI0_NPCS2 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOD | GPIO_PIN15) /* Type: GPIO */
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#define GPIO_SPI0_NPCS3 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOD | GPIO_PIN16) /* Type: GPIO */
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#define GPIO_SPI0_SPCK (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOD | GPIO_PIN12) /* Type: GPIO_CLK */
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#define GPIO_SPI1_MISO (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN22) /* Type: GPIO */
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#define GPIO_SPI1_MOSI (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN23) /* Type: GPIO */
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#define GPIO_SPI1_NPCS0 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN25) /* Type: GPIO */
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@ -324,6 +331,7 @@
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#define GPIO_SSC0_TD (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN18) /* Type: GPIO */
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#define GPIO_SSC0_TF (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN17) /* Type: GPIO */
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#define GPIO_SSC0_TK (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN16) /* Type: GPIO */
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#define GPIO_SSC1_RD (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN11) /* Type: GMAC */
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#define GPIO_SSC1_RF (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN10) /* Type: GMAC */
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#define GPIO_SSC1_RK (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN7) /* Type: GMAC */
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@ -336,18 +344,23 @@
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#define GPIO_TC0_CLK (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOD | GPIO_PIN7) /* Type: GPIO */
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#define GPIO_TC0_IOA (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOD | GPIO_PIN5) /* Type: GPIO */
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#define GPIO_TC0_IOB (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOD | GPIO_PIN6) /* Type: GPIO */
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#define GPIO_TC1_CLK (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN14) /* Type: GPIO */
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#define GPIO_TC1_IOA (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN12) /* Type: GPIO */
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#define GPIO_TC1_IOB (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN13) /* Type: GPIO */
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#define GPIO_TC2_CLK (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOE | GPIO_PIN29) /* Type: EBI */
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#define GPIO_TC2_IOA (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOE | GPIO_PIN27) /* Type: EBI */
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#define GPIO_TC2_IOB (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOE | GPIO_PIN28) /* Type: EBI */
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#define GPIO_TC3_CLK (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN2) /* Type: GPIO */
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#define GPIO_TC3_IOA (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN0) /* Type: GPIO */
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#define GPIO_TC3_IOB (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN1) /* Type: GPIO */
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#define GPIO_TC4_CLK (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN5) /* Type: GPIO */
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#define GPIO_TC4_IOA (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN3) /* Type: GPIO */
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#define GPIO_TC4_IOB (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN4) /* Type: GPIO */
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#define GPIO_TC5_CLK (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN8) /* Type: GPIO */
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#define GPIO_TC5_IOA (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN6) /* Type: GPIO */
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#define GPIO_TC5_IOB (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN7) /* Type: GPIO */
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@ -356,6 +369,7 @@
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#define GPIO_TWI0_CK (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN31) /* Type: GPIO */
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#define GPIO_TWI0_D (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN30) /* Type: GPIO */
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#define GPIO_TWI1_CK (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN27) /* Type: GPIO */
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#define GPIO_TWI1_D (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN26) /* Type: GPIO */
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#define GPIO_TWI2_CK (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN19) /* Type: GPIO */
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@ -365,6 +379,7 @@
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#define GPIO_UART0_RXD (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN29) /* Type: GPIO */
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#define GPIO_UART0_TXD (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN30) /* Type: GPIO */
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#define GPIO_UART1_RXD (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN30) /* Type: GPIO */
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#define GPIO_UART1_TXD (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN31) /* Type: GPIO */
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@ -375,16 +390,19 @@
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#define GPIO_USART0_RXD (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOD | GPIO_PIN17) /* Type: GPIO */
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#define GPIO_USART0_SCK (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOD | GPIO_PIN14) /* Type: GPIO */
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#define GPIO_USART0_TXD (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOD | GPIO_PIN18) /* Type: GPIO */
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#define GPIO_USART1_CTS (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN26) /* Type: GMAC */
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#define GPIO_USART1_RTS (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN27) /* Type: GPIO */
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#define GPIO_USART1_RXD (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN28) /* Type: GPIO */
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#define GPIO_USART1_SCK (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN25) /* Type: GMAC */
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#define GPIO_USART1_TXD (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN29) /* Type: GPIO */
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#define GPIO_USART2_CTS (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOE | GPIO_PIN23) /* Type: EBI */
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#define GPIO_USART2_RTS (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOE | GPIO_PIN24) /* Type: EBI */
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#define GPIO_USART2_RXD (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOE | GPIO_PIN25) /* Type: EBI */
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#define GPIO_USART2_SCK (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOE | GPIO_PIN20) /* Type: EBI */
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#define GPIO_USART2_TXD (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOE | GPIO_PIN26) /* Type: EBI */
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#define GPIO_USART3_CTS (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOE | GPIO_PIN16) /* Type: EBI */
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#define GPIO_USART3_RTS (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOE | GPIO_PIN17) /* Type: EBI */
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#define GPIO_USART3_RXD (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOE | GPIO_PIN18) /* Type: EBI */
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@ -89,7 +89,7 @@
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* Name: sam_spiinitialize
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*
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* Description:
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* Called to configure SPI chip select GPIO pins for the SAM3U10E-EVAL board.
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* Called to configure SPI chip select GPIO pins for the SAM3U-EK board.
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*
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************************************************************************************/
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@ -62,7 +62,6 @@ README
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Contents
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========
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- PIO Muliplexing
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- Development Environment
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- GNU Toolchain Options
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- IDEs
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@ -74,14 +73,10 @@ Contents
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- Creating and Using NORBOOT
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- Buttons and LEDs
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- Serial Consoles
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- Serial FLASH
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- SAMA5D3x-EK Configuration Options
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- Configurations
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PIO Muliplexing
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===============
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To be provided
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Development Environment
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=======================
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@ -513,6 +508,25 @@ Serial Consoles
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- Jumper JP16 not fitted: CDC is enabled
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- Jumper JP16 fitted : CDC is disabled"
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Serial FLASH
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============
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Both the Ronetix and Embest versions of the SAMAD3x CPU modules include an
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Atmel AT25DF321A, 32-megabit, 2.7-volt SPI serial flash. The SPI
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connection is as follows:
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AT25DF321A SAMA5
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--------------- -----------------------------------------------
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SI PD11 SPI0_MOSI
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SO PD10 SPI0_MIS0
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SCK PD12 SPI0_SPCK
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/CS PD13 via NL17SZ126 if JP1 is closed (See below)
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JP1 and JP2 seem to related to /CS on the Ronetix board, but the usage is
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less clear. For the Embest module, JP1 must be closed to connect /CS to
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PD13; on the Ronetix schematic, JP11 seems only to bypass a resistor (may
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not be populated?). I think closing JP1 is correct in either case.
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SAMA5D3x-EK Configuration Options
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=================================
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@ -915,6 +929,24 @@ Configurations
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If the CPU speed changes, then so must the NOR and SDRAM
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initialization!
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7. The Embest or Ronetix CPU module includes an Atmel AT25DF321A,
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32-megabit, 2.7-volt SPI serial flash. Support for that serial
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FLASH can be enabled by modifying the NuttX configuration as
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follows:
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System Type -> SAMA5 Peripheral Support
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CONFIG_SAMA5_SPI0=y : Enable SPI0
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Device Drivers -> Memory Technology Device (MTD) Support
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CONFIG_SPI=y : Enable SPI support
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CONFIG_SPI_EXCHANGE=y : Support the exchange method
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Device Drivers -> SPI Driver Support
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CONFIG_MTD=y : Enable MTD support
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CONFIG_MTD_AT25=y : Enable the AT25 driver
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CONFIG_AT25_SPIMODE=0 : Use SPI mode 0
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CONFIG_AT25_SPIFREQUENCY=20000000 : Use SPI frequency 20MHz
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2013-7-31: I have been unable to execute this configuration from NOR
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FLASH by closing the BMS jumper (J9). As far as I can tell, this
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jumper does nothing on my board??? I have been using the norboot
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@ -46,6 +46,14 @@ ifeq ($(CONFIG_HAVE_CXX),y)
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CSRCS += sam_cxxinitialize.c
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endif
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ifeq ($(CONFIG_SAMA5_SPI0),y)
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CSRCS += sam_spi.c
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else
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ifeq ($(CONFIG_SAMA5_SPI1),y)
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CSRCS += sam_spi.c
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endif
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endif
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ifeq ($(CONFIG_SAMA5_DDRCS),y)
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CSRCS += sam_sdram.c
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endif
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@ -67,6 +67,17 @@
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void sam_boardinitialize(void)
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{
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/* Configure SPI chip selects if 1) SPI is enable, and 2) the weak function
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* sam_spiinitialize() has been brought into the link.
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*/
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#if defined(CONFIG_SAMA5_SPI0) || defined(CONFIG_SAMA5_SPI1)
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if (sam_spiinitialize)
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{
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sam_spiinitialize();
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}
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#endif
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#if defined(CONFIG_SAMA5_DDRCS) && !defined(CONFIG_SAMA5_BOOT_SDRAM)
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/* Configure SDRAM if (1) SDRAM has been enalbled in the NuttX configuration and
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216
configs/sama5d3x-ek/src/sam_spi.c
Normal file
216
configs/sama5d3x-ek/src/sam_spi.c
Normal file
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@ -0,0 +1,216 @@
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/************************************************************************************
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* configs/sama5d3x-ek/src/up_spi.c
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*
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* Copyright (C) 2013 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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#include <stdint.h>
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#include <stdbool.h>
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#include <debug.h>
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#include <errno.h>
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#include <nuttx/spi/spi.h>
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#include <arch/board/board.h>
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#include "up_arch.h"
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#include "chip.h"
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#include "sam_gpio.h"
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#include "sam_spi.h"
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#include "sama5d3x-ek.h"
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#if defined(CONFIG_SAMA5_SPI0) || defined(CONFIG_SAMA5_SPI1)
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/************************************************************************************
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* Definitions
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************************************************************************************/
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/* Enables debug output from this file (needs CONFIG_DEBUG too) */
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#undef SPI_DEBUG /* Define to enable debug */
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||||
#undef SPI_VERBOSE /* Define to enable verbose debug */
|
||||
|
||||
#ifdef SPI_DEBUG
|
||||
# define spidbg lldbg
|
||||
# ifdef SPI_VERBOSE
|
||||
# define spivdbg lldbg
|
||||
# else
|
||||
# define spivdbg(x...)
|
||||
# endif
|
||||
#else
|
||||
# undef SPI_VERBOSE
|
||||
# define spidbg(x...)
|
||||
# define spivdbg(x...)
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
* Private Functions
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Functions
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Name: sam_spiinitialize
|
||||
*
|
||||
* Description:
|
||||
* Called to configure SPI chip select GPIO pins for the SAMA5D3x-EK board.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
void weak_function sam_spiinitialize(void)
|
||||
{
|
||||
#ifdef CONFIG_SAMA5_SPI0
|
||||
#ifdef CONFIG_MTD_AT25
|
||||
/* The AT25 serial FLASH connects using NPCS0 */
|
||||
|
||||
sam_configgpio(GPIO_AT25_NPCS0);
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SAMA5_SPI1
|
||||
#endif
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: sam_spi[0|1]select, sam_spi[0|1]status, and sam_spi[0|1]cmddata
|
||||
*
|
||||
* Description:
|
||||
* These external functions must be provided by board-specific logic. They
|
||||
* include:
|
||||
*
|
||||
* o sam_spi[0|1]select is a functions tomanage the board-specific chip selects
|
||||
* o sam_spi[0|1]status and sam_spi[0|1]cmddata: Implementations of the status
|
||||
* and cmddata methods of the SPI interface defined by struct spi_ops_
|
||||
* (see include/nuttx/spi/spi.h). All other methods including
|
||||
* up_spiinitialize()) are provided by common SAM3/4 logic.
|
||||
*
|
||||
* To use this common SPI logic on your board:
|
||||
*
|
||||
* 1. Provide logic in sam_boardinitialize() to configure SPI chip select
|
||||
* pins.
|
||||
* 2. Provide sam_spi[0|1]select() and sam_spi[0|1]status() functions in your board-
|
||||
* specific logic. These functions will perform chip selection and
|
||||
* status operations using GPIOs in the way your board is configured.
|
||||
* 2. If CONFIG_SPI_CMDDATA is defined in the NuttX configuration, provide
|
||||
* sam_spi[0|1]cmddata() functions in your board-specific logic. This
|
||||
* function will perform cmd/data selection operations using GPIOs in
|
||||
* the way your board is configured.
|
||||
* 3. Add a call to up_spiinitialize() in your low level application
|
||||
* initialization logic
|
||||
* 4. The handle returned by up_spiinitialize() may then be used to bind the
|
||||
* SPI driver to higher level logic (e.g., calling
|
||||
* mmcsd_spislotinitialize(), for example, will bind the SPI driver to
|
||||
* the SPI MMC/SD driver).
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: sam_spi[0|1]select
|
||||
*
|
||||
* Description:
|
||||
* PIO chip select pins may be programmed by the board specific logic in
|
||||
* one of two different ways. First, the pins may be programmed as SPI
|
||||
* peripherals. In that case, the pins are completely controlled by the
|
||||
* SPI driver. This method still needs to be provided, but it may be only
|
||||
* a stub.
|
||||
*
|
||||
* An alternative way to program the PIO chip select pins is as a normal
|
||||
* GPIO output. In that case, the automatic control of the CS pins is
|
||||
* bypassed and this function must provide control of the chip select.
|
||||
* NOTE: In this case, the GPIO output pin does *not* have to be the
|
||||
* same as the NPCS pin normal associated with the chip select number.
|
||||
*
|
||||
* Input Parameters:
|
||||
* devid - Identifies the (logical) device
|
||||
* selected - TRUE:Select the device, FALSE:De-select the device
|
||||
*
|
||||
* Returned Values:
|
||||
* None
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_SAMA5_SPI0
|
||||
void sam_spi0select(enum spi_dev_e devid, bool selected)
|
||||
{
|
||||
#ifdef CONFIG_MTD_AT25
|
||||
/* The AT25 serial FLASH connects using NPCS0 */
|
||||
|
||||
if (devid == SPIDEV_FLASH)
|
||||
{
|
||||
sam_gpiowrite(GPIO_AT25_NPCS0, !selected);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SAMA5_SPI1
|
||||
void sam_spi1select(enum spi_dev_e devid, bool selected)
|
||||
{
|
||||
}
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: sam_spi[0|1]status
|
||||
*
|
||||
* Description:
|
||||
* Return status information associated with the SPI device.
|
||||
*
|
||||
* Input Parameters:
|
||||
* devid - Identifies the (logical) device
|
||||
*
|
||||
* Returned Values:
|
||||
* Bit-encoded SPI status (see include/nuttx/spi/spi.h.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_SAMA5_SPI0
|
||||
uint8_t sam_spi0status(FAR struct spi_dev_s *dev, enum spi_dev_e devid)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SAMA5_SPI0
|
||||
uint8_t sam_spi1status(FAR struct spi_dev_s *dev, enum spi_dev_e devid)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* CONFIG_SAMA5_SPI0 || CONFIG_SAMA5_SPI1 */
|
||||
|
|
@ -94,6 +94,28 @@
|
|||
GPIO_INT_BOTHEDGES | GPIO_PORT_PIOE | GPIO_PIN27)
|
||||
#define IRQ_USER1 SAM_IRQ_PE27
|
||||
|
||||
/* SPI Chip Selects *****************************************************************/
|
||||
/* Both the Ronetix and Embest versions of the SAMAD3x CPU modules include an
|
||||
* Atmel AT25DF321A, 32-megabit, 2.7-volt SPI serial flash. The SPI
|
||||
* connection is as follows:
|
||||
*
|
||||
* AT25DF321A SAMA5
|
||||
* --------------- -----------------------------------------------
|
||||
* SI PD11 SPI0_MOSI
|
||||
* SO PD10 SPI0_MIS0
|
||||
* SCK PD12 SPI0_SPCK
|
||||
* /CS PD13 via NL17SZ126 if JP1 is closed (See below)
|
||||
*
|
||||
* JP1 and JP2 seem to related to /CS on the Ronetix board, but the usage is
|
||||
* less clear. For the Embest module, JP1 must be closed to connect /CS to
|
||||
* PD13; on the Ronetix schematic, JP11 seems only to bypass a resistor (may
|
||||
* not be populated?). I think closing JP1 is correct in either case.
|
||||
*/
|
||||
|
||||
#define GPIO_AT25_NPCS0 (GPIO_OUTPUT | GPIO_CFG_PULLUP | GPIO_OUTPUT_SET | \
|
||||
GPIO_PORT_PIOD | GPIO_PIN13)
|
||||
#define AT25_CSNUM 0
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
|
|
@ -108,6 +130,18 @@
|
|||
* Public Functions
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Name: sam_spiinitialize
|
||||
*
|
||||
* Description:
|
||||
* Called to configure SPI chip select PIO pins for the SAMA4D3x-EK board.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#if defined(CONFIG_SAMA5_SPI0) || defined(CONFIG_SAMA5_SPI1)
|
||||
void weak_function sam_spiinitialize(void);
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
* Name: board_sdram_config
|
||||
*
|
||||
|
|
|
|||
|
|
@ -86,6 +86,31 @@ config AT24XX_ADDR
|
|||
|
||||
endif
|
||||
|
||||
config MTD_AT25
|
||||
bool "SPI-based AT25 FLASH"
|
||||
default n
|
||||
select SPI
|
||||
|
||||
if MTD_AT25
|
||||
|
||||
config AT25_SPIMODE
|
||||
int "AT25 SPI Mode"
|
||||
default 0
|
||||
|
||||
config AT25_SPIFREQUENCY
|
||||
int "AT25 SPI Frequency"
|
||||
default 20000000
|
||||
|
||||
config AT25_READONLY
|
||||
bool "AT25 Read-Only FLASH"
|
||||
default n
|
||||
|
||||
config AT25_SECTOR512
|
||||
bool "Simulate 512 byte Erase Blocks"
|
||||
default n
|
||||
|
||||
endif
|
||||
|
||||
config MTD_AT45DB
|
||||
bool "SPI-based AT45DB flash"
|
||||
default n
|
||||
|
|
@ -94,15 +119,15 @@ config MTD_AT45DB
|
|||
if MTD_AT45DB
|
||||
|
||||
config AT45DB_FREQUENCY
|
||||
int "at45db frequency"
|
||||
int "AT45DB frequency"
|
||||
default 1000000
|
||||
|
||||
config AT45DB_PREWAIT
|
||||
bool "enables higher performance write logic"
|
||||
bool "Enable higher performance write logic"
|
||||
default y
|
||||
|
||||
config AT45DB_PWRSAVE
|
||||
bool "enables power save"
|
||||
bool "Enable power save"
|
||||
default n
|
||||
|
||||
endif
|
||||
|
|
@ -147,7 +172,7 @@ endif
|
|||
|
||||
config MTD_SMART
|
||||
bool "Sector Mapped Allocation for Really Tiny (SMART) Flash support"
|
||||
default y
|
||||
default n
|
||||
---help---
|
||||
The MP25x series of Flash devices are typically very small and have a very large
|
||||
erase block size. This causes issues with the standard Flash Translation Layer
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue